Pileus Git - ~andy/linux/blob - include/linux/mfd/palmas.h

   1 /*
   2  * TI Palmas
   3  *
   4  * Copyright 2011 Texas Instruments Inc.
   5  *
   6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under  the terms of the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the License, or (at your
  11  *  option) any later version.
  12  *
  13  */
  14
  15 #ifndef __LINUX_MFD_PALMAS_H
  16 #define __LINUX_MFD_PALMAS_H
  17
  18 #include <linux/usb/otg.h>
  19 #include <linux/leds.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/driver.h>
  22
  23 #define PALMAS_NUM_CLIENTS              3
  24
  25 struct palmas_pmic;
  26 struct palmas_gpadc;
  27 struct palmas_resource;
  28 struct palmas_usb;
  29
  30 struct palmas {
  31         struct device *dev;
  32
  33         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
  34         struct regmap *regmap[PALMAS_NUM_CLIENTS];
  35
  36         /* Stored chip id */
  37         int id;
  38
  39         /* IRQ Data */
  40         int irq;
  41         u32 irq_mask;
  42         struct mutex irq_lock;
  43         struct regmap_irq_chip_data *irq_data;
  44
  45         /* Child Devices */
  46         struct palmas_pmic *pmic;
  47         struct palmas_gpadc *gpadc;
  48         struct palmas_resource *resource;
  49         struct palmas_usb *usb;
  50
  51         /* GPIO MUXing */
  52         u8 gpio_muxed;
  53         u8 led_muxed;
  54         u8 pwm_muxed;
  55 };
  56
  57 struct palmas_gpadc_platform_data {
  58         /* Channel 3 current source is only enabled during conversion */
  59         int ch3_current;
  60
  61         /* Channel 0 current source can be used for battery detection.
  62          * If used for battery detection this will cause a permanent current
  63          * consumption depending on current level set here.
  64          */
  65         int ch0_current;
  66
  67         /* default BAT_REMOVAL_DAT setting on device probe */
  68         int bat_removal;
  69
  70         /* Sets the START_POLARITY bit in the RT_CTRL register */
  71         int start_polarity;
  72 };
  73
  74 struct palmas_reg_init {
  75         /* warm_rest controls the voltage levels after a warm reset
  76          *
  77          * 0: reload default values from OTP on warm reset
  78          * 1: maintain voltage from VSEL on warm reset
  79          */
  80         int warm_reset;
  81
  82         /* roof_floor controls whether the regulator uses the i2c style
  83          * of DVS or uses the method where a GPIO or other control method is
  84          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
  85          *
  86          * For SMPS
  87          *
  88          * 0: i2c selection of voltage
  89          * 1: pin selection of voltage.
  90          *
  91          * For LDO unused
  92          */
  93         int roof_floor;
  94
  95         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
  96          * the data sheet.
  97          *
  98          * For SMPS
  99          *
 100          * 0: Off
 101          * 1: AUTO
 102          * 2: ECO
 103          * 3: Forced PWM
 104          *
 105          * For LDO
 106          *
 107          * 0: Off
 108          * 1: On
 109          */
 110         int mode_sleep;
 111
 112         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
 113          * register. Set this is the default voltage set in OTP needs
 114          * to be overridden.
 115          */
 116         u8 vsel;
 117
 118 };
 119
 120 enum palmas_regulators {
 121         /* SMPS regulators */
 122         PALMAS_REG_SMPS12,
 123         PALMAS_REG_SMPS123,
 124         PALMAS_REG_SMPS3,
 125         PALMAS_REG_SMPS45,
 126         PALMAS_REG_SMPS457,
 127         PALMAS_REG_SMPS6,
 128         PALMAS_REG_SMPS7,
 129         PALMAS_REG_SMPS8,
 130         PALMAS_REG_SMPS9,
 131         PALMAS_REG_SMPS10,
 132         /* LDO regulators */
 133         PALMAS_REG_LDO1,
 134         PALMAS_REG_LDO2,
 135         PALMAS_REG_LDO3,
 136         PALMAS_REG_LDO4,
 137         PALMAS_REG_LDO5,
 138         PALMAS_REG_LDO6,
 139         PALMAS_REG_LDO7,
 140         PALMAS_REG_LDO8,
 141         PALMAS_REG_LDO9,
 142         PALMAS_REG_LDOLN,
 143         PALMAS_REG_LDOUSB,
 144         /* External regulators */
 145         PALMAS_REG_REGEN1,
 146         PALMAS_REG_REGEN2,
 147         PALMAS_REG_REGEN3,
 148         PALMAS_REG_SYSEN1,
 149         PALMAS_REG_SYSEN2,
 150         /* Total number of regulators */
 151         PALMAS_NUM_REGS,
 152 };
 153
 154 struct palmas_pmic_platform_data {
 155         /* An array of pointers to regulator init data indexed by regulator
 156          * ID
 157          */
 158         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
 159
 160         /* An array of pointers to structures containing sleep mode and DVS
 161          * configuration for regulators indexed by ID
 162          */
 163         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
 164
 165         /* use LDO6 for vibrator control */
 166         int ldo6_vibrator;
 167
 168         /* Enable tracking mode of LDO8 */
 169         bool enable_ldo8_tracking;
 170 };
 171
 172 struct palmas_usb_platform_data {
 173         /* Set this if platform wishes its own vbus control */
 174         int no_control_vbus;
 175
 176         /* Do we enable the wakeup comparator on probe */
 177         int wakeup;
 178 };
 179
 180 struct palmas_resource_platform_data {
 181         int regen1_mode_sleep;
 182         int regen2_mode_sleep;
 183         int sysen1_mode_sleep;
 184         int sysen2_mode_sleep;
 185
 186         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
 187         u8 nsleep_res;
 188         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
 189         u8 nsleep_smps;
 190         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
 191         u8 nsleep_ldo1;
 192         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
 193         u8 nsleep_ldo2;
 194
 195         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
 196         u8 enable1_res;
 197         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
 198         u8 enable1_smps;
 199         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
 200         u8 enable1_ldo1;
 201         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
 202         u8 enable1_ldo2;
 203
 204         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
 205         u8 enable2_res;
 206         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
 207         u8 enable2_smps;
 208         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
 209         u8 enable2_ldo1;
 210         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
 211         u8 enable2_ldo2;
 212 };
 213
 214 struct palmas_clk_platform_data {
 215         int clk32kg_mode_sleep;
 216         int clk32kgaudio_mode_sleep;
 217 };
 218
 219 struct palmas_platform_data {
 220         int irq_flags;
 221         int gpio_base;
 222
 223         /* bit value to be loaded to the POWER_CTRL register */
 224         u8 power_ctrl;
 225
 226         /*
 227          * boolean to select if we want to configure muxing here
 228          * then the two value to load into the registers if true
 229          */
 230         int mux_from_pdata;
 231         u8 pad1, pad2;
 232
 233         struct palmas_pmic_platform_data *pmic_pdata;
 234         struct palmas_gpadc_platform_data *gpadc_pdata;
 235         struct palmas_usb_platform_data *usb_pdata;
 236         struct palmas_resource_platform_data *resource_pdata;
 237         struct palmas_clk_platform_data *clk_pdata;
 238 };
 239
 240 struct palmas_gpadc_calibration {
 241         s32 gain;
 242         s32 gain_error;
 243         s32 offset_error;
 244 };
 245
 246 struct palmas_gpadc {
 247         struct device *dev;
 248         struct palmas *palmas;
 249
 250         int ch3_current;
 251         int ch0_current;
 252
 253         int gpadc_force;
 254
 255         int bat_removal;
 256
 257         struct mutex reading_lock;
 258         struct completion irq_complete;
 259
 260         int eoc_sw_irq;
 261
 262         struct palmas_gpadc_calibration *palmas_cal_tbl;
 263
 264         int conv0_channel;
 265         int conv1_channel;
 266         int rt_channel;
 267 };
 268
 269 struct palmas_gpadc_result {
 270         s32 raw_code;
 271         s32 corrected_code;
 272         s32 result;
 273 };
 274
 275 #define PALMAS_MAX_CHANNELS 16
 276
 277 /* Define the palmas IRQ numbers */
 278 enum palmas_irqs {
 279         /* INT1 registers */
 280         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
 281         PALMAS_PWRON_IRQ,
 282         PALMAS_LONG_PRESS_KEY_IRQ,
 283         PALMAS_RPWRON_IRQ,
 284         PALMAS_PWRDOWN_IRQ,
 285         PALMAS_HOTDIE_IRQ,
 286         PALMAS_VSYS_MON_IRQ,
 287         PALMAS_VBAT_MON_IRQ,
 288         /* INT2 registers */
 289         PALMAS_RTC_ALARM_IRQ,
 290         PALMAS_RTC_TIMER_IRQ,
 291         PALMAS_WDT_IRQ,
 292         PALMAS_BATREMOVAL_IRQ,
 293         PALMAS_RESET_IN_IRQ,
 294         PALMAS_FBI_BB_IRQ,
 295         PALMAS_SHORT_IRQ,
 296         PALMAS_VAC_ACOK_IRQ,
 297         /* INT3 registers */
 298         PALMAS_GPADC_AUTO_0_IRQ,
 299         PALMAS_GPADC_AUTO_1_IRQ,
 300         PALMAS_GPADC_EOC_SW_IRQ,
 301         PALMAS_GPADC_EOC_RT_IRQ,
 302         PALMAS_ID_OTG_IRQ,
 303         PALMAS_ID_IRQ,
 304         PALMAS_VBUS_OTG_IRQ,
 305         PALMAS_VBUS_IRQ,
 306         /* INT4 registers */
 307         PALMAS_GPIO_0_IRQ,
 308         PALMAS_GPIO_1_IRQ,
 309         PALMAS_GPIO_2_IRQ,
 310         PALMAS_GPIO_3_IRQ,
 311         PALMAS_GPIO_4_IRQ,
 312         PALMAS_GPIO_5_IRQ,
 313         PALMAS_GPIO_6_IRQ,
 314         PALMAS_GPIO_7_IRQ,
 315         /* Total Number IRQs */
 316         PALMAS_NUM_IRQ,
 317 };
 318
 319 struct palmas_pmic {
 320         struct palmas *palmas;
 321         struct device *dev;
 322         struct regulator_desc desc[PALMAS_NUM_REGS];
 323         struct regulator_dev *rdev[PALMAS_NUM_REGS];
 324         struct mutex mutex;
 325
 326         int smps123;
 327         int smps457;
 328
 329         int range[PALMAS_REG_SMPS10];
 330         unsigned int ramp_delay[PALMAS_REG_SMPS10];
 331         unsigned int current_reg_mode[PALMAS_REG_SMPS10];
 332 };
 333
 334 struct palmas_resource {
 335         struct palmas *palmas;
 336         struct device *dev;
 337 };
 338
 339 struct palmas_usb {
 340         struct palmas *palmas;
 341         struct device *dev;
 342
 343         /* for vbus reporting with irqs disabled */
 344         spinlock_t lock;
 345
 346         struct regulator *vbus_reg;
 347
 348         /* used to set vbus, in atomic path */
 349         struct work_struct set_vbus_work;
 350
 351         int irq1;
 352         int irq2;
 353         int irq3;
 354         int irq4;
 355
 356         int vbus_enable;
 357
 358         u8 linkstat;
 359 };
 360
 361 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
 362
 363 enum usb_irq_events {
 364         /* Wakeup events from INT3 */
 365         PALMAS_USB_ID_WAKEPUP,
 366         PALMAS_USB_VBUS_WAKEUP,
 367
 368         /* ID_OTG_EVENTS */
 369         PALMAS_USB_ID_GND,
 370         N_PALMAS_USB_ID_GND,
 371         PALMAS_USB_ID_C,
 372         N_PALMAS_USB_ID_C,
 373         PALMAS_USB_ID_B,
 374         N_PALMAS_USB_ID_B,
 375         PALMAS_USB_ID_A,
 376         N_PALMAS_USB_ID_A,
 377         PALMAS_USB_ID_FLOAT,
 378         N_PALMAS_USB_ID_FLOAT,
 379
 380         /* VBUS_OTG_EVENTS */
 381         PALMAS_USB_VB_SESS_END,
 382         N_PALMAS_USB_VB_SESS_END,
 383         PALMAS_USB_VB_SESS_VLD,
 384         N_PALMAS_USB_VB_SESS_VLD,
 385         PALMAS_USB_VA_SESS_VLD,
 386         N_PALMAS_USB_VA_SESS_VLD,
 387         PALMAS_USB_VA_VBUS_VLD,
 388         N_PALMAS_USB_VA_VBUS_VLD,
 389         PALMAS_USB_VADP_SNS,
 390         N_PALMAS_USB_VADP_SNS,
 391         PALMAS_USB_VADP_PRB,
 392         N_PALMAS_USB_VADP_PRB,
 393         PALMAS_USB_VOTG_SESS_VLD,
 394         N_PALMAS_USB_VOTG_SESS_VLD,
 395 };
 396
 397 /* defines so we can store the mux settings */
 398 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
 399 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
 400 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
 401 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
 402 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
 403 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
 404 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
 405 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
 406
 407 #define PALMAS_LED1_MUXED                                       (1 << 0)
 408 #define PALMAS_LED2_MUXED                                       (1 << 1)
 409
 410 #define PALMAS_PWM1_MUXED                                       (1 << 0)
 411 #define PALMAS_PWM2_MUXED                                       (1 << 1)
 412
 413 /* helper macro to get correct slave number */
 414 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
 415 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
 416
 417 /* Base addresses of IP blocks in Palmas */
 418 #define PALMAS_SMPS_DVS_BASE                                    0x20
 419 #define PALMAS_RTC_BASE                                         0x100
 420 #define PALMAS_VALIDITY_BASE                                    0x118
 421 #define PALMAS_SMPS_BASE                                        0x120
 422 #define PALMAS_LDO_BASE                                         0x150
 423 #define PALMAS_DVFS_BASE                                        0x180
 424 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
 425 #define PALMAS_RESOURCE_BASE                                    0x1D4
 426 #define PALMAS_PU_PD_OD_BASE                                    0x1F4
 427 #define PALMAS_LED_BASE                                         0x200
 428 #define PALMAS_INTERRUPT_BASE                                   0x210
 429 #define PALMAS_USB_OTG_BASE                                     0x250
 430 #define PALMAS_VIBRATOR_BASE                                    0x270
 431 #define PALMAS_GPIO_BASE                                        0x280
 432 #define PALMAS_USB_BASE                                         0x290
 433 #define PALMAS_GPADC_BASE                                       0x2C0
 434 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
 435
 436 /* Registers for function RTC */
 437 #define PALMAS_SECONDS_REG                                      0x0
 438 #define PALMAS_MINUTES_REG                                      0x1
 439 #define PALMAS_HOURS_REG                                        0x2
 440 #define PALMAS_DAYS_REG                                         0x3
 441 #define PALMAS_MONTHS_REG                                       0x4
 442 #define PALMAS_YEARS_REG                                        0x5
 443 #define PALMAS_WEEKS_REG                                        0x6
 444 #define PALMAS_ALARM_SECONDS_REG                                0x8
 445 #define PALMAS_ALARM_MINUTES_REG                                0x9
 446 #define PALMAS_ALARM_HOURS_REG                                  0xA
 447 #define PALMAS_ALARM_DAYS_REG                                   0xB
 448 #define PALMAS_ALARM_MONTHS_REG                                 0xC
 449 #define PALMAS_ALARM_YEARS_REG                                  0xD
 450 #define PALMAS_RTC_CTRL_REG                                     0x10
 451 #define PALMAS_RTC_STATUS_REG                                   0x11
 452 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
 453 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
 454 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
 455 #define PALMAS_RTC_RES_PROG_REG                                 0x15
 456 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
 457
 458 /* Bit definitions for SECONDS_REG */
 459 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
 460 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
 461 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
 462 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
 463
 464 /* Bit definitions for MINUTES_REG */
 465 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
 466 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
 467 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
 468 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
 469
 470 /* Bit definitions for HOURS_REG */
 471 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
 472 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
 473 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
 474 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
 475 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
 476 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
 477
 478 /* Bit definitions for DAYS_REG */
 479 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
 480 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
 481 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
 482 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
 483
 484 /* Bit definitions for MONTHS_REG */
 485 #define PALMAS_MONTHS_REG_MONTH1                                0x10
 486 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
 487 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
 488 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
 489
 490 /* Bit definitions for YEARS_REG */
 491 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
 492 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
 493 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
 494 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
 495
 496 /* Bit definitions for WEEKS_REG */
 497 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
 498 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
 499
 500 /* Bit definitions for ALARM_SECONDS_REG */
 501 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
 502 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
 503 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
 504 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
 505
 506 /* Bit definitions for ALARM_MINUTES_REG */
 507 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
 508 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
 509 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
 510 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
 511
 512 /* Bit definitions for ALARM_HOURS_REG */
 513 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
 514 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
 515 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
 516 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
 517 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
 518 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
 519
 520 /* Bit definitions for ALARM_DAYS_REG */
 521 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
 522 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
 523 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
 524 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
 525
 526 /* Bit definitions for ALARM_MONTHS_REG */
 527 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
 528 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
 529 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
 530 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
 531
 532 /* Bit definitions for ALARM_YEARS_REG */
 533 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
 534 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
 535 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
 536 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
 537
 538 /* Bit definitions for RTC_CTRL_REG */
 539 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
 540 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
 541 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
 542 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
 543 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
 544 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
 545 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
 546 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
 547 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
 548 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
 549 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
 550 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
 551 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
 552 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
 553 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
 554 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
 555
 556 /* Bit definitions for RTC_STATUS_REG */
 557 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
 558 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
 559 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
 560 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
 561 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
 562 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
 563 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
 564 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
 565 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
 566 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
 567 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
 568 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
 569 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
 570 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
 571
 572 /* Bit definitions for RTC_INTERRUPTS_REG */
 573 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
 574 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
 575 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
 576 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
 577 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
 578 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
 579 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
 580 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
 581
 582 /* Bit definitions for RTC_COMP_LSB_REG */
 583 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
 584 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
 585
 586 /* Bit definitions for RTC_COMP_MSB_REG */
 587 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
 588 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
 589
 590 /* Bit definitions for RTC_RES_PROG_REG */
 591 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
 592 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
 593
 594 /* Bit definitions for RTC_RESET_STATUS_REG */
 595 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
 596 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
 597
 598 /* Registers for function BACKUP */
 599 #define PALMAS_BACKUP0                                          0x0
 600 #define PALMAS_BACKUP1                                          0x1
 601 #define PALMAS_BACKUP2                                          0x2
 602 #define PALMAS_BACKUP3                                          0x3
 603 #define PALMAS_BACKUP4                                          0x4
 604 #define PALMAS_BACKUP5                                          0x5
 605 #define PALMAS_BACKUP6                                          0x6
 606 #define PALMAS_BACKUP7                                          0x7
 607
 608 /* Bit definitions for BACKUP0 */
 609 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
 610 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
 611
 612 /* Bit definitions for BACKUP1 */
 613 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
 614 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
 615
 616 /* Bit definitions for BACKUP2 */
 617 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
 618 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
 619
 620 /* Bit definitions for BACKUP3 */
 621 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
 622 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
 623
 624 /* Bit definitions for BACKUP4 */
 625 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
 626 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
 627
 628 /* Bit definitions for BACKUP5 */
 629 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
 630 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
 631
 632 /* Bit definitions for BACKUP6 */
 633 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
 634 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
 635
 636 /* Bit definitions for BACKUP7 */
 637 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
 638 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
 639
 640 /* Registers for function SMPS */
 641 #define PALMAS_SMPS12_CTRL                                      0x0
 642 #define PALMAS_SMPS12_TSTEP                                     0x1
 643 #define PALMAS_SMPS12_FORCE                                     0x2
 644 #define PALMAS_SMPS12_VOLTAGE                                   0x3
 645 #define PALMAS_SMPS3_CTRL                                       0x4
 646 #define PALMAS_SMPS3_VOLTAGE                                    0x7
 647 #define PALMAS_SMPS45_CTRL                                      0x8
 648 #define PALMAS_SMPS45_TSTEP                                     0x9
 649 #define PALMAS_SMPS45_FORCE                                     0xA
 650 #define PALMAS_SMPS45_VOLTAGE                                   0xB
 651 #define PALMAS_SMPS6_CTRL                                       0xC
 652 #define PALMAS_SMPS6_TSTEP                                      0xD
 653 #define PALMAS_SMPS6_FORCE                                      0xE
 654 #define PALMAS_SMPS6_VOLTAGE                                    0xF
 655 #define PALMAS_SMPS7_CTRL                                       0x10
 656 #define PALMAS_SMPS7_VOLTAGE                                    0x13
 657 #define PALMAS_SMPS8_CTRL                                       0x14
 658 #define PALMAS_SMPS8_TSTEP                                      0x15
 659 #define PALMAS_SMPS8_FORCE                                      0x16
 660 #define PALMAS_SMPS8_VOLTAGE                                    0x17
 661 #define PALMAS_SMPS9_CTRL                                       0x18
 662 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
 663 #define PALMAS_SMPS10_CTRL                                      0x1C
 664 #define PALMAS_SMPS10_STATUS                                    0x1F
 665 #define PALMAS_SMPS_CTRL                                        0x24
 666 #define PALMAS_SMPS_PD_CTRL                                     0x25
 667 #define PALMAS_SMPS_DITHER_EN                                   0x26
 668 #define PALMAS_SMPS_THERMAL_EN                                  0x27
 669 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
 670 #define PALMAS_SMPS_SHORT_STATUS                                0x29
 671 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
 672 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
 673 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
 674
 675 /* Bit definitions for SMPS12_CTRL */
 676 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
 677 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
 678 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
 679 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 680 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
 681 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
 682 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
 683 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
 684 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
 685 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
 686
 687 /* Bit definitions for SMPS12_TSTEP */
 688 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
 689 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
 690
 691 /* Bit definitions for SMPS12_FORCE */
 692 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
 693 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
 694 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
 695 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
 696
 697 /* Bit definitions for SMPS12_VOLTAGE */
 698 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
 699 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
 700 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
 701 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
 702
 703 /* Bit definitions for SMPS3_CTRL */
 704 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
 705 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
 706 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
 707 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
 708 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
 709 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
 710 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
 711 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
 712
 713 /* Bit definitions for SMPS3_VOLTAGE */
 714 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
 715 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
 716 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
 717 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
 718
 719 /* Bit definitions for SMPS45_CTRL */
 720 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
 721 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
 722 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
 723 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
 724 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
 725 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
 726 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
 727 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
 728 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
 729 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
 730
 731 /* Bit definitions for SMPS45_TSTEP */
 732 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
 733 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
 734
 735 /* Bit definitions for SMPS45_FORCE */
 736 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
 737 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
 738 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
 739 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
 740
 741 /* Bit definitions for SMPS45_VOLTAGE */
 742 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
 743 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
 744 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
 745 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
 746
 747 /* Bit definitions for SMPS6_CTRL */
 748 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
 749 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
 750 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
 751 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 752 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
 753 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
 754 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
 755 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
 756 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
 757 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
 758
 759 /* Bit definitions for SMPS6_TSTEP */
 760 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
 761 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
 762
 763 /* Bit definitions for SMPS6_FORCE */
 764 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
 765 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
 766 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
 767 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
 768
 769 /* Bit definitions for SMPS6_VOLTAGE */
 770 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
 771 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
 772 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
 773 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
 774
 775 /* Bit definitions for SMPS7_CTRL */
 776 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
 777 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
 778 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
 779 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
 780 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
 781 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
 782 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
 783 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
 784
 785 /* Bit definitions for SMPS7_VOLTAGE */
 786 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
 787 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
 788 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
 789 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
 790
 791 /* Bit definitions for SMPS8_CTRL */
 792 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
 793 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
 794 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
 795 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
 796 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
 797 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
 798 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
 799 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
 800 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
 801 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
 802
 803 /* Bit definitions for SMPS8_TSTEP */
 804 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
 805 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
 806
 807 /* Bit definitions for SMPS8_FORCE */
 808 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
 809 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
 810 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
 811 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
 812
 813 /* Bit definitions for SMPS8_VOLTAGE */
 814 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
 815 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
 816 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
 817 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
 818
 819 /* Bit definitions for SMPS9_CTRL */
 820 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
 821 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
 822 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
 823 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
 824 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
 825 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
 826 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
 827 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
 828
 829 /* Bit definitions for SMPS9_VOLTAGE */
 830 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
 831 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
 832 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
 833 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
 834
 835 /* Bit definitions for SMPS10_CTRL */
 836 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
 837 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
 838 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
 839 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
 840
 841 /* Bit definitions for SMPS10_STATUS */
 842 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
 843 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
 844
 845 /* Bit definitions for SMPS_CTRL */
 846 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
 847 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
 848 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
 849 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
 850 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
 851 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
 852 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
 853 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
 854
 855 /* Bit definitions for SMPS_PD_CTRL */
 856 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
 857 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
 858 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
 859 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
 860 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
 861 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
 862 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
 863 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
 864 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
 865 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
 866 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
 867 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
 868 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
 869 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
 870
 871 /* Bit definitions for SMPS_THERMAL_EN */
 872 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
 873 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
 874 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
 875 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
 876 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
 877 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
 878 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
 879 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
 880 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
 881 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
 882
 883 /* Bit definitions for SMPS_THERMAL_STATUS */
 884 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
 885 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
 886 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
 887 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
 888 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
 889 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
 890 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
 891 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
 892 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
 893 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
 894
 895 /* Bit definitions for SMPS_SHORT_STATUS */
 896 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
 897 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
 898 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
 899 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
 900 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
 901 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
 902 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
 903 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
 904 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
 905 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
 906 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
 907 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
 908 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
 909 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
 910 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
 911 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
 912
 913 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
 914 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
 915 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
 916 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
 917 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
 918 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
 919 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
 920 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
 921 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
 922 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
 923 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
 924 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
 925 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
 926 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
 927 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
 928
 929 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
 930 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
 931 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
 932 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
 933 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
 934 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
 935 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
 936 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
 937 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
 938 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
 939 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
 940 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
 941 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
 942 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
 943 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
 944 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
 945 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
 946
 947 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
 948 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
 949 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
 950 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
 951 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
 952 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
 953 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
 954 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
 955 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
 956
 957 /* Registers for function LDO */
 958 #define PALMAS_LDO1_CTRL                                        0x0
 959 #define PALMAS_LDO1_VOLTAGE                                     0x1
 960 #define PALMAS_LDO2_CTRL                                        0x2
 961 #define PALMAS_LDO2_VOLTAGE                                     0x3
 962 #define PALMAS_LDO3_CTRL                                        0x4
 963 #define PALMAS_LDO3_VOLTAGE                                     0x5
 964 #define PALMAS_LDO4_CTRL                                        0x6
 965 #define PALMAS_LDO4_VOLTAGE                                     0x7
 966 #define PALMAS_LDO5_CTRL                                        0x8
 967 #define PALMAS_LDO5_VOLTAGE                                     0x9
 968 #define PALMAS_LDO6_CTRL                                        0xA
 969 #define PALMAS_LDO6_VOLTAGE                                     0xB
 970 #define PALMAS_LDO7_CTRL                                        0xC
 971 #define PALMAS_LDO7_VOLTAGE                                     0xD
 972 #define PALMAS_LDO8_CTRL                                        0xE
 973 #define PALMAS_LDO8_VOLTAGE                                     0xF
 974 #define PALMAS_LDO9_CTRL                                        0x10
 975 #define PALMAS_LDO9_VOLTAGE                                     0x11
 976 #define PALMAS_LDOLN_CTRL                                       0x12
 977 #define PALMAS_LDOLN_VOLTAGE                                    0x13
 978 #define PALMAS_LDOUSB_CTRL                                      0x14
 979 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
 980 #define PALMAS_LDO_CTRL                                         0x1A
 981 #define PALMAS_LDO_PD_CTRL1                                     0x1B
 982 #define PALMAS_LDO_PD_CTRL2                                     0x1C
 983 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
 984 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
 985
 986 /* Bit definitions for LDO1_CTRL */
 987 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
 988 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
 989 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
 990 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
 991 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
 992 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
 993 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
 994 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
 995
 996 /* Bit definitions for LDO1_VOLTAGE */
 997 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
 998 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
 999
1000 /* Bit definitions for LDO2_CTRL */
1001 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1002 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
1003 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1004 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
1005 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1006 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
1007 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1008 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
1009
1010 /* Bit definitions for LDO2_VOLTAGE */
1011 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
1012 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
1013
1014 /* Bit definitions for LDO3_CTRL */
1015 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1016 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
1017 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1018 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
1019 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1020 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
1021 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1022 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
1023
1024 /* Bit definitions for LDO3_VOLTAGE */
1025 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
1026 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
1027
1028 /* Bit definitions for LDO4_CTRL */
1029 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1030 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
1031 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1032 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
1033 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1034 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
1035 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1036 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
1037
1038 /* Bit definitions for LDO4_VOLTAGE */
1039 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
1040 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
1041
1042 /* Bit definitions for LDO5_CTRL */
1043 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1044 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1045 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1046 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1047 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1048 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1049 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1050 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1051
1052 /* Bit definitions for LDO5_VOLTAGE */
1053 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1054 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1055
1056 /* Bit definitions for LDO6_CTRL */
1057 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1058 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1059 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1060 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1061 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1062 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1063 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1064 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1065 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1066 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1067
1068 /* Bit definitions for LDO6_VOLTAGE */
1069 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1070 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1071
1072 /* Bit definitions for LDO7_CTRL */
1073 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1074 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1075 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1076 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1077 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1078 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1079 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1080 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1081
1082 /* Bit definitions for LDO7_VOLTAGE */
1083 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1084 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1085
1086 /* Bit definitions for LDO8_CTRL */
1087 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1088 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1089 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1090 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1091 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1092 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1093 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1094 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1095 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1096 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1097
1098 /* Bit definitions for LDO8_VOLTAGE */
1099 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1100 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1101
1102 /* Bit definitions for LDO9_CTRL */
1103 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1104 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1105 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1106 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1107 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1108 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1109 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1110 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1111 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1112 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1113
1114 /* Bit definitions for LDO9_VOLTAGE */
1115 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1116 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1117
1118 /* Bit definitions for LDOLN_CTRL */
1119 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1120 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1121 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1122 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1123 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1124 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1125 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1126 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1127
1128 /* Bit definitions for LDOLN_VOLTAGE */
1129 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1130 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1131
1132 /* Bit definitions for LDOUSB_CTRL */
1133 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1134 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1135 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1136 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1137 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1138 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1139 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1140 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1141
1142 /* Bit definitions for LDOUSB_VOLTAGE */
1143 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1144 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1145
1146 /* Bit definitions for LDO_CTRL */
1147 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1148 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1149
1150 /* Bit definitions for LDO_PD_CTRL1 */
1151 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1152 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1153 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1154 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1155 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1156 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1157 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1158 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1159 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1160 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1161 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1162 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1163 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1164 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1165 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1166 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1167
1168 /* Bit definitions for LDO_PD_CTRL2 */
1169 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1170 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1171 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1172 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1173 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1174 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1175
1176 /* Bit definitions for LDO_SHORT_STATUS1 */
1177 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1178 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1179 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1180 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1181 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1182 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1183 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1184 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1185 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1186 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1187 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1188 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1189 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1190 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1191 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1192 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1193
1194 /* Bit definitions for LDO_SHORT_STATUS2 */
1195 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1196 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1197 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1198 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1199 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1200 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1201 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1202 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1203
1204 /* Registers for function PMU_CONTROL */
1205 #define PALMAS_DEV_CTRL                                         0x0
1206 #define PALMAS_POWER_CTRL                                       0x1
1207 #define PALMAS_VSYS_LO                                          0x2
1208 #define PALMAS_VSYS_MON                                         0x3
1209 #define PALMAS_VBAT_MON                                         0x4
1210 #define PALMAS_WATCHDOG                                         0x5
1211 #define PALMAS_BOOT_STATUS                                      0x6
1212 #define PALMAS_BATTERY_BOUNCE                                   0x7
1213 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1214 #define PALMAS_LONG_PRESS_KEY                                   0x9
1215 #define PALMAS_OSC_THERM_CTRL                                   0xA
1216 #define PALMAS_BATDEBOUNCING                                    0xB
1217 #define PALMAS_SWOFF_HWRST                                      0xF
1218 #define PALMAS_SWOFF_COLDRST                                    0x10
1219 #define PALMAS_SWOFF_STATUS                                     0x11
1220 #define PALMAS_PMU_CONFIG                                       0x12
1221 #define PALMAS_SPARE                                            0x14
1222 #define PALMAS_PMU_SECONDARY_INT                                0x15
1223 #define PALMAS_SW_REVISION                                      0x17
1224 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1225 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1226
1227 /* Bit definitions for DEV_CTRL */
1228 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1229 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1230 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1231 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1232 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1233 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1234
1235 /* Bit definitions for POWER_CTRL */
1236 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1237 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1238 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1239 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1240 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1241 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1242
1243 /* Bit definitions for VSYS_LO */
1244 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1245 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1246
1247 /* Bit definitions for VSYS_MON */
1248 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1249 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1250 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1251 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1252
1253 /* Bit definitions for VBAT_MON */
1254 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1255 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1256 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1257 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1258
1259 /* Bit definitions for WATCHDOG */
1260 #define PALMAS_WATCHDOG_LOCK                                    0x20
1261 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1262 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1263 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1264 #define PALMAS_WATCHDOG_MODE                                    0x08
1265 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1266 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1267 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1268
1269 /* Bit definitions for BOOT_STATUS */
1270 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1271 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1272 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1273 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1274
1275 /* Bit definitions for BATTERY_BOUNCE */
1276 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1277 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1278
1279 /* Bit definitions for BACKUP_BATTERY_CTRL */
1280 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1281 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1282 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1283 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1284 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1285 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1286 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1287 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1288 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1289 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1290 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1291 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1292 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1293 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1294
1295 /* Bit definitions for LONG_PRESS_KEY */
1296 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1297 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1298 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1299 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1300 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1301 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1302 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1303 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1304
1305 /* Bit definitions for OSC_THERM_CTRL */
1306 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1307 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1308 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1309 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1310 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1311 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1312 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1313 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1314 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1315 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1316 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1317 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1318 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1319 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1320
1321 /* Bit definitions for BATDEBOUNCING */
1322 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1323 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1324 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1325 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1326 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1327 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1328
1329 /* Bit definitions for SWOFF_HWRST */
1330 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1331 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1332 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1333 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1334 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1335 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1336 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1337 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1338 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1339 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1340 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1341 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1342 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1343 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1344 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1345 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1346
1347 /* Bit definitions for SWOFF_COLDRST */
1348 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1349 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1350 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1351 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1352 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1353 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1354 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1355 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1356 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1357 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1358 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1359 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1360 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1361 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1362 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1363 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1364
1365 /* Bit definitions for SWOFF_STATUS */
1366 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1367 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1368 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1369 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1370 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1371 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1372 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1373 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1374 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1375 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1376 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1377 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1378 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1379 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1380 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1381 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1382
1383 /* Bit definitions for PMU_CONFIG */
1384 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1385 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1386 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1387 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1388 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1389 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1390 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1391 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1392 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1393 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1394
1395 /* Bit definitions for SPARE */
1396 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1397 #define PALMAS_SPARE_SPARE_SHIFT                                3
1398 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1399 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1400 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1401 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1402 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1403 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1404
1405 /* Bit definitions for PMU_SECONDARY_INT */
1406 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1407 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1408 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1409 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1410 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1411 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1412 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1413 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
1414 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
1415 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
1416 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
1417 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
1418 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
1419 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
1420 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
1421 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
1422
1423 /* Bit definitions for SW_REVISION */
1424 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
1425 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
1426
1427 /* Bit definitions for EXT_CHRG_CTRL */
1428 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
1429 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
1430 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
1431 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
1432 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
1433 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
1434 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
1435 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
1436 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
1437 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
1438 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
1439 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
1440
1441 /* Bit definitions for PMU_SECONDARY_INT2 */
1442 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
1443 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
1444 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
1445 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
1446 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
1447 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
1448 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
1449 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
1450
1451 /* Registers for function RESOURCE */
1452 #define PALMAS_CLK32KG_CTRL                                     0x0
1453 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
1454 #define PALMAS_REGEN1_CTRL                                      0x2
1455 #define PALMAS_REGEN2_CTRL                                      0x3
1456 #define PALMAS_SYSEN1_CTRL                                      0x4
1457 #define PALMAS_SYSEN2_CTRL                                      0x5
1458 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
1459 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
1460 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
1461 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
1462 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
1463 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
1464 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
1465 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
1466 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
1467 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
1468 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
1469 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
1470 #define PALMAS_REGEN3_CTRL                                      0x12
1471
1472 /* Bit definitions for CLK32KG_CTRL */
1473 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
1474 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
1475 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
1476 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
1477 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
1478 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
1479
1480 /* Bit definitions for CLK32KGAUDIO_CTRL */
1481 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
1482 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
1483 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
1484 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
1485 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
1486 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
1487 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
1488 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
1489
1490 /* Bit definitions for REGEN1_CTRL */
1491 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
1492 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
1493 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
1494 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
1495 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
1496 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1497
1498 /* Bit definitions for REGEN2_CTRL */
1499 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
1500 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
1501 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
1502 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
1503 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
1504 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1505
1506 /* Bit definitions for SYSEN1_CTRL */
1507 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
1508 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
1509 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
1510 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
1511 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
1512 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
1513
1514 /* Bit definitions for SYSEN2_CTRL */
1515 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
1516 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
1517 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
1518 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
1519 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
1520 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
1521
1522 /* Bit definitions for NSLEEP_RES_ASSIGN */
1523 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
1524 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
1525 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
1526 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
1527 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
1528 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
1529 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
1530 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
1531 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
1532 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
1533 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
1534 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
1535 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
1536 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
1537
1538 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1539 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
1540 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
1541 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
1542 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
1543 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
1544 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
1545 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
1546 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
1547 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
1548 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
1549 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
1550 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
1551 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
1552 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
1553 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
1554 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
1555
1556 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1557 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
1558 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
1559 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
1560 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
1561 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
1562 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
1563 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
1564 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
1565 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
1566 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
1567 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
1568 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
1569 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
1570 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
1571 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
1572 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
1573
1574 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1575 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
1576 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
1577 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
1578 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
1579 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
1580 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
1581
1582 /* Bit definitions for ENABLE1_RES_ASSIGN */
1583 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
1584 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
1585 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
1586 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1587 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
1588 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
1589 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
1590 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
1591 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
1592 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
1593 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
1594 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
1595 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
1596 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
1597
1598 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1599 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
1600 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
1601 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
1602 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
1603 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
1604 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
1605 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
1606 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
1607 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
1608 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
1609 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
1610 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
1611 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
1612 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
1613 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
1614 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
1615
1616 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1617 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
1618 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
1619 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
1620 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
1621 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
1622 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
1623 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
1624 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
1625 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
1626 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
1627 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
1628 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
1629 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
1630 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
1631 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
1632 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
1633
1634 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1635 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
1636 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1637 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
1638 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
1639 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
1640 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
1641
1642 /* Bit definitions for ENABLE2_RES_ASSIGN */
1643 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
1644 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
1645 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
1646 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
1647 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
1648 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
1649 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
1650 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
1651 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
1652 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
1653 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
1654 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
1655 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
1656 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
1657
1658 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1659 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
1660 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
1661 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
1662 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
1663 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
1664 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
1665 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
1666 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
1667 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
1668 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
1669 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
1670 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
1671 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
1672 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
1673 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
1674 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
1675
1676 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1677 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
1678 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
1679 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
1680 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
1681 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
1682 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
1683 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
1684 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
1685 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
1686 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
1687 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
1688 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
1689 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
1690 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
1691 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
1692 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
1693
1694 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1695 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
1696 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
1697 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
1698 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
1699 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
1700 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
1701
1702 /* Bit definitions for REGEN3_CTRL */
1703 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
1704 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
1705 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
1706 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
1707 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
1708 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
1709
1710 /* Registers for function PAD_CONTROL */
1711 #define PALMAS_PU_PD_INPUT_CTRL1                                0x0
1712 #define PALMAS_PU_PD_INPUT_CTRL2                                0x1
1713 #define PALMAS_PU_PD_INPUT_CTRL3                                0x2
1714 #define PALMAS_OD_OUTPUT_CTRL                                   0x4
1715 #define PALMAS_POLARITY_CTRL                                    0x5
1716 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0x6
1717 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0x7
1718 #define PALMAS_I2C_SPI                                          0x8
1719 #define PALMAS_PU_PD_INPUT_CTRL4                                0x9
1720 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xA
1721
1722 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1723 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
1724 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
1725 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
1726 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
1727 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
1728 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
1729 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
1730 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
1731 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
1732 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
1733
1734 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1735 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
1736 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
1737 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
1738 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
1739 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
1740 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
1741 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
1742 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
1743 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
1744 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
1745 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
1746 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
1747
1748 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1749 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
1750 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
1751 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
1752 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
1753 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
1754 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
1755 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
1756 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
1757
1758 /* Bit definitions for OD_OUTPUT_CTRL */
1759 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
1760 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
1761 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
1762 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
1763 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
1764 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
1765 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
1766 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
1767
1768 /* Bit definitions for POLARITY_CTRL */
1769 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
1770 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
1771 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
1772 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
1773 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
1774 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
1775 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
1776 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
1777 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
1778 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
1779 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
1780 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
1781 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
1782 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
1783 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
1784 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
1785
1786 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1787 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
1788 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
1789 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
1790 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
1791 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
1792 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
1793 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
1794 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
1795 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
1796 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
1797 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
1798 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
1799
1800 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1801 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
1802 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
1803 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
1804 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
1805 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
1806 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
1807 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
1808 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
1809
1810 /* Bit definitions for I2C_SPI */
1811 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
1812 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
1813 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
1814 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
1815 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
1816 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
1817 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
1818 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
1819 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
1820 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
1821
1822 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1823 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
1824 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
1825 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
1826 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
1827 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
1828 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
1829 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
1830 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
1831
1832 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1833 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
1834 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
1835 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
1836 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
1837
1838 /* Registers for function LED_PWM */
1839 #define PALMAS_LED_PERIOD_CTRL                                  0x0
1840 #define PALMAS_LED_CTRL                                         0x1
1841 #define PALMAS_PWM_CTRL1                                        0x2
1842 #define PALMAS_PWM_CTRL2                                        0x3
1843
1844 /* Bit definitions for LED_PERIOD_CTRL */
1845 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
1846 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
1847 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
1848 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
1849
1850 /* Bit definitions for LED_CTRL */
1851 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
1852 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
1853 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
1854 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
1855 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
1856 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
1857 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
1858 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
1859
1860 /* Bit definitions for PWM_CTRL1 */
1861 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
1862 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
1863 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
1864 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
1865
1866 /* Bit definitions for PWM_CTRL2 */
1867 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
1868 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
1869
1870 /* Registers for function INTERRUPT */
1871 #define PALMAS_INT1_STATUS                                      0x0
1872 #define PALMAS_INT1_MASK                                        0x1
1873 #define PALMAS_INT1_LINE_STATE                                  0x2
1874 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
1875 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
1876 #define PALMAS_INT2_STATUS                                      0x5
1877 #define PALMAS_INT2_MASK                                        0x6
1878 #define PALMAS_INT2_LINE_STATE                                  0x7
1879 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
1880 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
1881 #define PALMAS_INT3_STATUS                                      0xA
1882 #define PALMAS_INT3_MASK                                        0xB
1883 #define PALMAS_INT3_LINE_STATE                                  0xC
1884 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
1885 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
1886 #define PALMAS_INT4_STATUS                                      0xF
1887 #define PALMAS_INT4_MASK                                        0x10
1888 #define PALMAS_INT4_LINE_STATE                                  0x11
1889 #define PALMAS_INT4_EDGE_DETECT1                                0x12
1890 #define PALMAS_INT4_EDGE_DETECT2                                0x13
1891 #define PALMAS_INT_CTRL                                         0x14
1892
1893 /* Bit definitions for INT1_STATUS */
1894 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
1895 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
1896 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
1897 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
1898 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
1899 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
1900 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
1901 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
1902 #define PALMAS_INT1_STATUS_RPWRON                               0x08
1903 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
1904 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
1905 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
1906 #define PALMAS_INT1_STATUS_PWRON                                0x02
1907 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
1908 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
1909 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
1910
1911 /* Bit definitions for INT1_MASK */
1912 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
1913 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
1914 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
1915 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
1916 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
1917 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
1918 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
1919 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
1920 #define PALMAS_INT1_MASK_RPWRON                                 0x08
1921 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
1922 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
1923 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
1924 #define PALMAS_INT1_MASK_PWRON                                  0x02
1925 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
1926 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
1927 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
1928
1929 /* Bit definitions for INT1_LINE_STATE */
1930 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
1931 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
1932 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
1933 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
1934 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
1935 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
1936 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
1937 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
1938 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
1939 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
1940 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
1941 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
1942 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
1943 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
1944 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
1945 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
1946
1947 /* Bit definitions for INT2_STATUS */
1948 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
1949 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
1950 #define PALMAS_INT2_STATUS_SHORT                                0x40
1951 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
1952 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
1953 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
1954 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
1955 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
1956 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
1957 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
1958 #define PALMAS_INT2_STATUS_WDT                                  0x04
1959 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
1960 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
1961 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
1962 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
1963 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
1964
1965 /* Bit definitions for INT2_MASK */
1966 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
1967 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
1968 #define PALMAS_INT2_MASK_SHORT                                  0x40
1969 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
1970 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
1971 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
1972 #define PALMAS_INT2_MASK_RESET_IN                               0x10
1973 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
1974 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
1975 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
1976 #define PALMAS_INT2_MASK_WDT                                    0x04
1977 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
1978 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
1979 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
1980 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
1981 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
1982
1983 /* Bit definitions for INT2_LINE_STATE */
1984 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
1985 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
1986 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
1987 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
1988 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
1989 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
1990 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
1991 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
1992 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
1993 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
1994 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
1995 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
1996 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
1997 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
1998 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
1999 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
2000
2001 /* Bit definitions for INT3_STATUS */
2002 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2003 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
2004 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2005 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
2006 #define PALMAS_INT3_STATUS_ID                                   0x20
2007 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
2008 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2009 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
2010 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2011 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
2012 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2013 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2014 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2015 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2016 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2017 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2018
2019 /* Bit definitions for INT3_MASK */
2020 #define PALMAS_INT3_MASK_VBUS                                   0x80
2021 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2022 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2023 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2024 #define PALMAS_INT3_MASK_ID                                     0x20
2025 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2026 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2027 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2028 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2029 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2030 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2031 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2032 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2033 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2034 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2035 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2036
2037 /* Bit definitions for INT3_LINE_STATE */
2038 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2039 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2040 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2041 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2042 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2043 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2044 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2045 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2046 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2047 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2048 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2049 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2050 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2051 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2052 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2053 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2054
2055 /* Bit definitions for INT4_STATUS */
2056 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2057 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2058 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2059 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2060 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2061 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2062 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2063 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2064 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2065 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2066 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2067 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2068 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2069 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2070 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2071 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2072
2073 /* Bit definitions for INT4_MASK */
2074 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2075 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2076 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2077 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2078 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2079 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2080 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2081 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2082 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2083 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2084 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2085 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2086 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2087 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2088 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2089 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2090
2091 /* Bit definitions for INT4_LINE_STATE */
2092 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2093 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2094 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2095 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2096 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2097 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2098 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2099 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2100 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2101 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2102 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2103 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2104 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2105 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2106 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2107 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2108
2109 /* Bit definitions for INT4_EDGE_DETECT1 */
2110 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2111 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2112 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2113 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2114 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2115 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2116 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2117 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2118 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2119 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2120 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2121 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2122 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2123 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2124 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2125 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2126
2127 /* Bit definitions for INT4_EDGE_DETECT2 */
2128 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2129 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2130 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2131 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2132 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2133 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2134 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2135 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2136 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2137 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2138 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2139 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2140 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2141 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2142 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2143 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2144
2145 /* Bit definitions for INT_CTRL */
2146 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2147 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2148 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2149 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2150
2151 /* Registers for function USB_OTG */
2152 #define PALMAS_USB_WAKEUP                                       0x3
2153 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
2154 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
2155 #define PALMAS_USB_ID_CTRL_SET                                  0x6
2156 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
2157 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
2158 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
2159 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
2160 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
2161 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
2162 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
2163 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
2164 #define PALMAS_USB_ID_INT_SRC                                   0xF
2165 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
2166 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
2167 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
2168 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
2169 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
2170 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
2171 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
2172 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
2173 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
2174 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
2175 #define PALMAS_USB_OTG_REVISION                                 0x1A
2176
2177 /* Bit definitions for USB_WAKEUP */
2178 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
2179 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
2180
2181 /* Bit definitions for USB_VBUS_CTRL_SET */
2182 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
2183 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
2184 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
2185 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
2186 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
2187 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
2188 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
2189 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
2190 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
2191 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
2192
2193 /* Bit definitions for USB_VBUS_CTRL_CLR */
2194 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
2195 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
2196 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
2197 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
2198 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
2199 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
2200 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
2201 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
2202 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
2203 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
2204
2205 /* Bit definitions for USB_ID_CTRL_SET */
2206 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
2207 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
2208 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
2209 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
2210 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
2211 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
2212 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
2213 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
2214 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
2215 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
2216 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
2217 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
2218
2219 /* Bit definitions for USB_ID_CTRL_CLEAR */
2220 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
2221 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
2222 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
2223 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
2224 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
2225 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
2226 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
2227 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
2228 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
2229 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
2230 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
2231 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
2232
2233 /* Bit definitions for USB_VBUS_INT_SRC */
2234 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
2235 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
2236 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
2237 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
2238 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
2239 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
2240 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
2241 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
2242 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
2243 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
2244 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
2245 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
2246 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
2247 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
2248
2249 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2250 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
2251 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
2252 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
2253 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
2254 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
2255 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
2256 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
2257 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
2258 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
2259 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
2260 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
2261 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
2262 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
2263 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
2264 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
2265 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
2266
2267 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2268 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
2269 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
2270 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
2271 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
2272 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
2273 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
2274 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
2275 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
2276 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
2277 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
2278 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
2279 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
2280 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
2281 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
2282 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
2283 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
2284
2285 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2286 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
2287 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
2288 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
2289 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
2290 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
2291 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
2292 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
2293 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
2294 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
2295 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
2296 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
2297 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
2298 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
2299 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
2300
2301 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2302 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
2303 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
2304 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
2305 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
2306 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
2307 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
2308 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
2309 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
2310 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
2311 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
2312 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
2313 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
2314 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
2315 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
2316
2317 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2318 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
2319 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
2320 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
2321 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
2322 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
2323 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
2324 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
2325 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
2326 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
2327 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
2328 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
2329 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
2330 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
2331 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
2332 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
2333 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
2334
2335 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2336 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
2337 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
2338 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
2339 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
2340 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
2341 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
2342 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
2343 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
2344 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
2345 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
2346 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
2347 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
2348 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
2349 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
2350 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
2351 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
2352
2353 /* Bit definitions for USB_ID_INT_SRC */
2354 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
2355 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
2356 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
2357 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
2358 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
2359 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
2360 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
2361 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
2362 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
2363 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
2364
2365 /* Bit definitions for USB_ID_INT_LATCH_SET */
2366 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
2367 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
2368 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
2369 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
2370 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
2371 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
2372 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
2373 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
2374 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
2375 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
2376
2377 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2378 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
2379 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
2380 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
2381 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
2382 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
2383 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
2384 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
2385 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
2386 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
2387 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
2388
2389 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2390 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
2391 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
2392 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
2393 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
2394 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
2395 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
2396 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
2397 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
2398 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
2399 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
2400
2401 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2402 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
2403 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
2404 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
2405 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
2406 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
2407 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
2408 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
2409 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
2410 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
2411 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
2412
2413 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2414 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
2415 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
2416 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
2417 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
2418 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
2419 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
2420 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
2421 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
2422 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
2423 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
2424
2425 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2426 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
2427 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
2428 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
2429 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
2430 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
2431 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
2432 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
2433 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
2434 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
2435 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
2436
2437 /* Bit definitions for USB_OTG_ADP_CTRL */
2438 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
2439 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
2440 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
2441 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
2442
2443 /* Bit definitions for USB_OTG_ADP_HIGH */
2444 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
2445 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
2446
2447 /* Bit definitions for USB_OTG_ADP_LOW */
2448 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
2449 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
2450
2451 /* Bit definitions for USB_OTG_ADP_RISE */
2452 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
2453 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
2454
2455 /* Bit definitions for USB_OTG_REVISION */
2456 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
2457 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
2458
2459 /* Registers for function VIBRATOR */
2460 #define PALMAS_VIBRA_CTRL                                       0x0
2461
2462 /* Bit definitions for VIBRA_CTRL */
2463 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
2464 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
2465 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
2466 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
2467
2468 /* Registers for function GPIO */
2469 #define PALMAS_GPIO_DATA_IN                                     0x0
2470 #define PALMAS_GPIO_DATA_DIR                                    0x1
2471 #define PALMAS_GPIO_DATA_OUT                                    0x2
2472 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
2473 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
2474 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
2475 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
2476 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
2477 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
2478
2479 /* Bit definitions for GPIO_DATA_IN */
2480 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
2481 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
2482 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
2483 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
2484 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
2485 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
2486 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
2487 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
2488 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
2489 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
2490 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
2491 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
2492 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
2493 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
2494 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
2495 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
2496
2497 /* Bit definitions for GPIO_DATA_DIR */
2498 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
2499 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
2500 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
2501 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
2502 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
2503 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
2504 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
2505 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
2506 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
2507 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
2508 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
2509 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
2510 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
2511 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
2512 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
2513 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
2514
2515 /* Bit definitions for GPIO_DATA_OUT */
2516 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
2517 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
2518 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
2519 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
2520 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
2521 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
2522 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
2523 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
2524 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
2525 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
2526 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
2527 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
2528 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
2529 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
2530 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
2531 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
2532
2533 /* Bit definitions for GPIO_DEBOUNCE_EN */
2534 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
2535 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
2536 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
2537 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
2538 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
2539 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
2540 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
2541 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
2542 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
2543 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
2544 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
2545 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
2546 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
2547 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
2548 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
2549 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
2550
2551 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2552 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
2553 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
2554 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
2555 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
2556 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
2557 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
2558 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
2559 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
2560 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
2561 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
2562 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
2563 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
2564 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
2565 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
2566 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
2567 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
2568
2569 /* Bit definitions for GPIO_SET_DATA_OUT */
2570 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
2571 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
2572 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
2573 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
2574 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
2575 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
2576 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
2577 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
2578 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
2579 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
2580 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
2581 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
2582 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
2583 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
2584 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
2585 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
2586
2587 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2588 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
2589 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
2590 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
2591 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
2592 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
2593 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
2594 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
2595 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
2596 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
2597 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
2598 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
2599 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
2600
2601 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2602 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
2603 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
2604 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
2605 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
2606 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
2607 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
2608 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
2609 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
2610 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
2611 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
2612 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
2613 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
2614 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
2615 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
2616
2617 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2618 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
2619 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
2620 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
2621 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
2622 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
2623 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
2624
2625 /* Registers for function GPADC */
2626 #define PALMAS_GPADC_CTRL1                                      0x0
2627 #define PALMAS_GPADC_CTRL2                                      0x1
2628 #define PALMAS_GPADC_RT_CTRL                                    0x2
2629 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
2630 #define PALMAS_GPADC_STATUS                                     0x4
2631 #define PALMAS_GPADC_RT_SELECT                                  0x5
2632 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
2633 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
2634 #define PALMAS_GPADC_AUTO_SELECT                                0x8
2635 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
2636 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
2637 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
2638 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
2639 #define PALMAS_GPADC_SW_SELECT                                  0xD
2640 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
2641 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
2642 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
2643 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
2644 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
2645 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
2646 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
2647 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
2648
2649 /* Bit definitions for GPADC_CTRL1 */
2650 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
2651 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
2652 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
2653 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
2654 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
2655 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
2656 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
2657 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
2658 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
2659 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
2660
2661 /* Bit definitions for GPADC_CTRL2 */
2662 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
2663 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
2664
2665 /* Bit definitions for GPADC_RT_CTRL */
2666 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
2667 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
2668 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
2669 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
2670
2671 /* Bit definitions for GPADC_AUTO_CTRL */
2672 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
2673 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
2674 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
2675 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
2676 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
2677 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
2678 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
2679 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
2680 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
2681 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
2682
2683 /* Bit definitions for GPADC_STATUS */
2684 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
2685 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
2686
2687 /* Bit definitions for GPADC_RT_SELECT */
2688 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
2689 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
2690 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
2691 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
2692
2693 /* Bit definitions for GPADC_RT_CONV0_LSB */
2694 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
2695 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
2696
2697 /* Bit definitions for GPADC_RT_CONV0_MSB */
2698 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
2699 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
2700
2701 /* Bit definitions for GPADC_AUTO_SELECT */
2702 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
2703 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
2704 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
2705 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
2706
2707 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2708 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
2709 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
2710
2711 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2712 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
2713 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
2714
2715 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2716 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
2717 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
2718
2719 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2720 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
2721 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
2722
2723 /* Bit definitions for GPADC_SW_SELECT */
2724 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
2725 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
2726 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
2727 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
2728 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
2729 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
2730
2731 /* Bit definitions for GPADC_SW_CONV0_LSB */
2732 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
2733 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
2734
2735 /* Bit definitions for GPADC_SW_CONV0_MSB */
2736 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
2737 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
2738
2739 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2740 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
2741 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
2742
2743 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2744 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
2745 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
2746 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
2747 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
2748
2749 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2750 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
2751 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
2752
2753 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2754 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
2755 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
2756 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
2757 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
2758
2759 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2760 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
2761 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
2762 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
2763 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
2764 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
2765 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
2766
2767 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2768 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
2769 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
2770 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
2771 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
2772
2773 /* Registers for function GPADC */
2774 #define PALMAS_GPADC_TRIM1                                      0x0
2775 #define PALMAS_GPADC_TRIM2                                      0x1
2776 #define PALMAS_GPADC_TRIM3                                      0x2
2777 #define PALMAS_GPADC_TRIM4                                      0x3
2778 #define PALMAS_GPADC_TRIM5                                      0x4
2779 #define PALMAS_GPADC_TRIM6                                      0x5
2780 #define PALMAS_GPADC_TRIM7                                      0x6
2781 #define PALMAS_GPADC_TRIM8                                      0x7
2782 #define PALMAS_GPADC_TRIM9                                      0x8
2783 #define PALMAS_GPADC_TRIM10                                     0x9
2784 #define PALMAS_GPADC_TRIM11                                     0xA
2785 #define PALMAS_GPADC_TRIM12                                     0xB
2786 #define PALMAS_GPADC_TRIM13                                     0xC
2787 #define PALMAS_GPADC_TRIM14                                     0xD
2788 #define PALMAS_GPADC_TRIM15                                     0xE
2789 #define PALMAS_GPADC_TRIM16                                     0xF
2790
2791 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2792                 unsigned int reg, unsigned int *val)
2793 {
2794         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
2795         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2796
2797         return regmap_read(palmas->regmap[slave_id], addr, val);
2798 }
2799
2800 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2801                 unsigned int reg, unsigned int value)
2802 {
2803         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2804         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2805
2806         return regmap_write(palmas->regmap[slave_id], addr, value);
2807 }
2808
2809 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2810         unsigned int reg, const void *val, size_t val_count)
2811 {
2812         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2813         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2814
2815         return regmap_bulk_write(palmas->regmap[slave_id], addr,
2816                         val, val_count);
2817 }
2818
2819 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2820                 unsigned int reg, void *val, size_t val_count)
2821 {
2822         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2823         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2824
2825         return regmap_bulk_read(palmas->regmap[slave_id], addr,
2826                 val, val_count);
2827 }
2828
2829 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2830         unsigned int reg, unsigned int mask, unsigned int val)
2831 {
2832         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2833         int slave_id = PALMAS_BASE_TO_SLAVE(base);
2834
2835         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2836 }
2837
2838 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2839 {
2840         return regmap_irq_get_virq(palmas->irq_data, irq);
2841 }
2842
2843 #endif /*  __LINUX_MFD_PALMAS_H */