2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
5 * Copyright (C) 2007 Atmel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 #include <linux/dmaengine.h>
17 * struct dw_dma_platform_data - Controller configuration parameters
18 * @nr_channels: Number of channels supported by hardware (max 8)
19 * @is_private: The device channels should be marked as private and not for
20 * by the general purpose DMA channel allocator.
22 struct dw_dma_platform_data {
23 unsigned int nr_channels;
28 * enum dw_dma_slave_width - DMA slave register access width.
29 * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
30 * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
31 * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
33 enum dw_dma_slave_width {
34 DW_DMA_SLAVE_WIDTH_8BIT,
35 DW_DMA_SLAVE_WIDTH_16BIT,
36 DW_DMA_SLAVE_WIDTH_32BIT,
40 * struct dw_dma_slave - Controller-specific information about a slave
42 * @dma_dev: required DMA master device
43 * @tx_reg: physical address of data register used for
44 * memory-to-peripheral transfers
45 * @rx_reg: physical address of data register used for
46 * peripheral-to-memory transfers
47 * @reg_width: peripheral register width
48 * @cfg_hi: Platform-specific initializer for the CFG_HI register
49 * @cfg_lo: Platform-specific initializer for the CFG_LO register
52 struct device *dma_dev;
55 enum dw_dma_slave_width reg_width;
62 /* Platform-configurable bits in CFG_HI */
63 #define DWC_CFGH_FCMODE (1 << 0)
64 #define DWC_CFGH_FIFO_MODE (1 << 1)
65 #define DWC_CFGH_PROTCTL(x) ((x) << 2)
66 #define DWC_CFGH_SRC_PER(x) ((x) << 7)
67 #define DWC_CFGH_DST_PER(x) ((x) << 11)
69 /* Platform-configurable bits in CFG_LO */
70 #define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
71 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
72 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
73 #define DWC_CFGL_LOCK_CH_XACT (2 << 12)
74 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
75 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
76 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
77 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
78 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
79 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
80 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
82 /* DMA API extensions */
83 struct dw_cyclic_desc {
84 struct dw_desc **desc;
85 unsigned long periods;
86 void (*period_callback)(void *param);
87 void *period_callback_param;
90 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
91 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
92 enum dma_data_direction direction);
93 void dw_dma_cyclic_free(struct dma_chan *chan);
94 int dw_dma_cyclic_start(struct dma_chan *chan);
95 void dw_dma_cyclic_stop(struct dma_chan *chan);
97 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
99 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
101 #endif /* DW_DMAC_H */