]> Pileus Git - ~andy/linux/blob - include/asm-x86_64/cache.h
[PATCH] x86_64: Set ____cacheline_maxaligned_in_smp alignment to 128 bytes
[~andy/linux] / include / asm-x86_64 / cache.h
1 /*
2  * include/asm-x8664/cache.h
3  */
4 #ifndef __ARCH_X8664_CACHE_H
5 #define __ARCH_X8664_CACHE_H
6
7 #include <linux/config.h>
8
9 /* L1 cache line size */
10 #define L1_CACHE_SHIFT  (CONFIG_X86_L1_CACHE_SHIFT)
11 #define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
12 #define L1_CACHE_SHIFT_MAX 7    /* largest L1 which this arch supports */
13
14 #endif