2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_X86_64_PROCESSOR_H
6 #define __ASM_X86_64_PROCESSOR_H
8 #include <asm/segment.h>
10 #include <asm/types.h>
11 #include <asm/sigcontext.h>
12 #include <asm/cpufeature.h>
13 #include <linux/threads.h>
15 #include <asm/current.h>
16 #include <asm/system.h>
17 #include <asm/mmsegment.h>
18 #include <asm/percpu.h>
19 #include <linux/personality.h>
20 #include <linux/cpumask.h>
21 #include <asm/desc_defs.h>
24 * CPU type and hardware bug flags. Kept separately for each CPU.
28 __u8 x86; /* CPU family */
29 __u8 x86_vendor; /* CPU vendor */
32 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
33 __u32 x86_capability[NCAPINTS];
34 char x86_vendor_id[16];
35 char x86_model_id[64];
36 int x86_cache_size; /* in KB */
38 int x86_cache_alignment;
39 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
40 __u8 x86_virt_bits, x86_phys_bits;
41 __u8 x86_max_cores; /* cpuid returned max cores value */
42 __u8 x86_coreid_bits; /* cpuid returned core id bits */
44 __u32 extended_cpuid_level; /* Max extended CPUID function supported */
45 unsigned long loops_per_jiffy;
47 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
51 __u8 booted_cores; /* number of cores as seen by OS */
52 __u8 phys_proc_id; /* Physical Processor id. */
53 __u8 cpu_core_id; /* Core id. */
54 __u8 cpu_index; /* index into per_cpu list */
56 } ____cacheline_aligned;
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_TRANSMETA 7
65 #define X86_VENDOR_NUM 8
66 #define X86_VENDOR_UNKNOWN 0xff
69 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
70 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
71 #define current_cpu_data cpu_data(smp_processor_id())
73 #define cpu_data(cpu) boot_cpu_data
74 #define current_cpu_data boot_cpu_data
77 extern char ignore_irq13;
79 extern void identify_cpu(struct cpuinfo_x86 *);
82 * User space process size. 47bits minus one guard page.
84 #define TASK_SIZE64 (0x800000000000UL - 4096)
86 /* This decides where the kernel will search for a free chunk of vm
87 * space during mmap's.
89 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
91 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
92 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
97 #define IO_BITMAP_BITS 65536
98 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
99 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
100 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
101 #define INVALID_IO_BITMAP_OFFSET 0x8000
103 struct i387_fxsave_struct {
112 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
113 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
115 } __attribute__ ((aligned (16)));
118 struct i387_fxsave_struct fxsave;
133 * The extra 1 is there because the CPU will access an
134 * additional byte beyond the end of the IO permission
135 * bitmap. The extra byte must be all 1 bits, and must
136 * be within the limit. Thus we have:
138 * 128 bytes, the bitmap itself, for ports 0..0x3ff
139 * 8 bytes, for an extra "long" of ~0UL
141 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
142 } __attribute__((packed)) ____cacheline_aligned;
145 extern struct cpuinfo_x86 boot_cpu_data;
146 DECLARE_PER_CPU(struct tss_struct,init_tss);
147 /* Save the original ist values for checking stack pointers during debugging */
149 unsigned long ist[7];
151 DECLARE_PER_CPU(struct orig_ist, orig_ist);
153 #ifdef CONFIG_X86_VSMP
154 #define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
155 #define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
157 #define ARCH_MIN_TASKALIGN 16
158 #define ARCH_MIN_MMSTRUCT_ALIGN 0
161 struct thread_struct {
164 unsigned long usersp; /* Copy from PDA */
167 unsigned short es, ds, fsindex, gsindex;
168 /* Hardware debugging registers */
169 unsigned long debugreg0;
170 unsigned long debugreg1;
171 unsigned long debugreg2;
172 unsigned long debugreg3;
173 unsigned long debugreg6;
174 unsigned long debugreg7;
176 unsigned long cr2, trap_no, error_code;
177 /* floating point info */
178 union i387_union i387 __attribute__((aligned(16)));
179 /* IO permissions. the bitmap could be moved into the GDT, that would make
180 switch faster for a limited number of ioperm using tasks. -AK */
182 unsigned long *io_bitmap_ptr;
183 unsigned io_bitmap_max;
184 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
185 unsigned long debugctlmsr;
186 /* Debug Store - if not 0 points to a DS Save Area configuration;
187 * goes into MSR_IA32_DS_AREA */
188 unsigned long ds_area_msr;
189 /* cached TLS descriptors. */
190 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
191 } __attribute__((aligned(16)));
193 #define INIT_THREAD { \
194 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
198 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
202 { &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
204 #define start_thread(regs,new_rip,new_rsp) do { \
205 asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
207 (regs)->ip = (new_rip); \
208 (regs)->sp = (new_rsp); \
209 write_pda(oldrsp, (new_rsp)); \
210 (regs)->cs = __USER_CS; \
211 (regs)->ss = __USER_DS; \
212 (regs)->flags = 0x200; \
217 * Return saved PC of a blocked thread.
218 * What is this good for? it will be always the scheduler or ret_from_fork.
220 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
222 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
223 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
226 #if defined(CONFIG_MPSC) || defined(CONFIG_MCORE2)
227 #define ASM_NOP1 P6_NOP1
228 #define ASM_NOP2 P6_NOP2
229 #define ASM_NOP3 P6_NOP3
230 #define ASM_NOP4 P6_NOP4
231 #define ASM_NOP5 P6_NOP5
232 #define ASM_NOP6 P6_NOP6
233 #define ASM_NOP7 P6_NOP7
234 #define ASM_NOP8 P6_NOP8
236 #define ASM_NOP1 K8_NOP1
237 #define ASM_NOP2 K8_NOP2
238 #define ASM_NOP3 K8_NOP3
239 #define ASM_NOP4 K8_NOP4
240 #define ASM_NOP5 K8_NOP5
241 #define ASM_NOP6 K8_NOP6
242 #define ASM_NOP7 K8_NOP7
243 #define ASM_NOP8 K8_NOP8
247 #define K8_NOP1 ".byte 0x90\n"
248 #define K8_NOP2 ".byte 0x66,0x90\n"
249 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
250 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
251 #define K8_NOP5 K8_NOP3 K8_NOP2
252 #define K8_NOP6 K8_NOP3 K8_NOP3
253 #define K8_NOP7 K8_NOP4 K8_NOP3
254 #define K8_NOP8 K8_NOP4 K8_NOP4
257 /* uses eax dependencies (Intel-recommended choice) */
258 #define P6_NOP1 ".byte 0x90\n"
259 #define P6_NOP2 ".byte 0x66,0x90\n"
260 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
261 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
262 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
263 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
264 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
265 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
267 #define ASM_NOP_MAX 8
269 static inline void prefetchw(void *x)
271 alternative_input("prefetcht0 (%1)",
278 #define stack_current() \
280 struct thread_info *ti; \
281 asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
286 #endif /* __ASM_X86_64_PROCESSOR_H */