2 * Copyright (C) 1994 Linus Torvalds
5 #ifndef __ASM_I386_PROCESSOR_H
6 #define __ASM_I386_PROCESSOR_H
9 #include <asm/math_emu.h>
10 #include <asm/segment.h>
12 #include <asm/types.h>
13 #include <asm/sigcontext.h>
14 #include <asm/cpufeature.h>
16 #include <asm/system.h>
17 #include <linux/cache.h>
18 #include <linux/threads.h>
19 #include <asm/percpu.h>
20 #include <linux/cpumask.h>
21 #include <linux/init.h>
22 #include <asm/desc_defs.h>
25 * CPU type and hardware bug flags. Kept separately for each CPU.
26 * Members of this structure are referenced in head.S, so think twice
27 * before touching them. [mj]
31 __u8 x86; /* CPU family */
32 __u8 x86_vendor; /* CPU vendor */
35 char wp_works_ok; /* It doesn't on 386's */
36 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
39 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
40 unsigned long x86_capability[NCAPINTS];
41 char x86_vendor_id[16];
42 char x86_model_id[64];
43 int x86_cache_size; /* in KB - valid for CPUS which support this
45 int x86_cache_alignment; /* In bytes */
51 unsigned long loops_per_jiffy;
53 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
55 unsigned char x86_max_cores; /* cpuid returned max cores value */
57 unsigned short x86_clflush_size;
59 unsigned char booted_cores; /* number of cores as seen by OS */
60 __u8 phys_proc_id; /* Physical processor id. */
61 __u8 cpu_core_id; /* Core id */
62 __u8 cpu_index; /* index into per_cpu list */
64 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
66 #define X86_VENDOR_INTEL 0
67 #define X86_VENDOR_CYRIX 1
68 #define X86_VENDOR_AMD 2
69 #define X86_VENDOR_UMC 3
70 #define X86_VENDOR_NEXGEN 4
71 #define X86_VENDOR_CENTAUR 5
72 #define X86_VENDOR_TRANSMETA 7
73 #define X86_VENDOR_NSC 8
74 #define X86_VENDOR_NUM 9
75 #define X86_VENDOR_UNKNOWN 0xff
78 * capabilities of CPUs
81 extern struct cpuinfo_x86 boot_cpu_data;
82 extern struct cpuinfo_x86 new_cpu_data;
83 extern struct tss_struct doublefault_tss;
84 DECLARE_PER_CPU(struct tss_struct, init_tss);
87 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
88 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
89 #define current_cpu_data cpu_data(smp_processor_id())
91 #define cpu_data(cpu) boot_cpu_data
92 #define current_cpu_data boot_cpu_data
96 * the following now lives in the per cpu area:
97 * extern int cpu_llc_id[NR_CPUS];
99 DECLARE_PER_CPU(u8, cpu_llc_id);
100 extern char ignore_fpu_irq;
102 void __init cpu_detect(struct cpuinfo_x86 *c);
104 extern void identify_boot_cpu(void);
105 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
108 extern void detect_ht(struct cpuinfo_x86 *c);
110 static inline void detect_ht(struct cpuinfo_x86 *c) {}
113 /* from system description table in BIOS. Mostly for MCA use, but
114 others may find it useful. */
115 extern unsigned int machine_id;
116 extern unsigned int machine_submodel_id;
117 extern unsigned int BIOS_revision;
118 extern unsigned int mca_pentium_flag;
121 * User space process size: 3GB (default).
123 #define TASK_SIZE (PAGE_OFFSET)
129 #define IO_BITMAP_BITS 65536
130 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
131 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
132 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
133 #define INVALID_IO_BITMAP_OFFSET 0x8000
134 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
136 struct i387_fsave_struct {
144 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
145 long status; /* software status information */
148 struct i387_fxsave_struct {
159 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
160 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
162 } __attribute__ ((aligned (16)));
164 struct i387_soft_struct {
172 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
173 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
175 unsigned long entry_eip;
179 struct i387_fsave_struct fsave;
180 struct i387_fxsave_struct fxsave;
181 struct i387_soft_struct soft;
188 struct thread_struct;
190 /* This is the TSS defined by the hardware. */
192 unsigned short back_link,__blh;
194 unsigned short ss0,__ss0h;
196 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
198 unsigned short ss2,__ss2h;
202 unsigned long ax, cx, dx, bx;
203 unsigned long sp, bp, si, di;
204 unsigned short es, __esh;
205 unsigned short cs, __csh;
206 unsigned short ss, __ssh;
207 unsigned short ds, __dsh;
208 unsigned short fs, __fsh;
209 unsigned short gs, __gsh;
210 unsigned short ldt, __ldth;
211 unsigned short trace, io_bitmap_base;
212 } __attribute__((packed));
215 struct i386_hw_tss x86_tss;
218 * The extra 1 is there because the CPU will access an
219 * additional byte beyond the end of the IO permission
220 * bitmap. The extra byte must be all 1 bits, and must
221 * be within the limit.
223 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
225 * Cache the current maximum and the last task that used the bitmap:
227 unsigned long io_bitmap_max;
228 struct thread_struct *io_bitmap_owner;
230 * pads the TSS to be cacheline-aligned (size is 0x100)
232 unsigned long __cacheline_filler[35];
234 * .. and then another 0x100 bytes for emergency kernel stack
236 unsigned long stack[64];
237 } __attribute__((packed));
239 #define ARCH_MIN_TASKALIGN 16
241 struct thread_struct {
242 /* cached TLS descriptors. */
243 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
245 unsigned long sysenter_cs;
250 /* Hardware debugging registers */
251 unsigned long debugreg0;
252 unsigned long debugreg1;
253 unsigned long debugreg2;
254 unsigned long debugreg3;
255 unsigned long debugreg6;
256 unsigned long debugreg7;
258 unsigned long cr2, trap_no, error_code;
259 /* floating point info */
260 union i387_union i387;
261 /* virtual 86 mode info */
262 struct vm86_struct __user * vm86_info;
263 unsigned long screen_bitmap;
264 unsigned long v86flags, v86mask, saved_sp0;
265 unsigned int saved_fs, saved_gs;
267 unsigned long *io_bitmap_ptr;
269 /* max allowed port in the bitmap, in bytes: */
270 unsigned long io_bitmap_max;
271 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
272 unsigned long debugctlmsr;
273 /* Debug Store - if not 0 points to a DS Save Area configuration;
274 * goes into MSR_IA32_DS_AREA */
275 unsigned long ds_area_msr;
278 #define INIT_THREAD { \
279 .sp0 = sizeof(init_stack) + (long)&init_stack, \
281 .sysenter_cs = __KERNEL_CS, \
282 .io_bitmap_ptr = NULL, \
283 .fs = __KERNEL_PERCPU, \
287 * Note that the .io_bitmap member must be extra-big. This is because
288 * the CPU will access an additional byte beyond the end of the IO
289 * permission bitmap. The extra byte must be all 1 bits, and must
290 * be within the limit.
294 .sp0 = sizeof(init_stack) + (long)&init_stack, \
295 .ss0 = __KERNEL_DS, \
296 .ss1 = __KERNEL_CS, \
297 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
299 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
302 #define start_thread(regs, new_eip, new_esp) do { \
303 __asm__("movl %0,%%gs": :"r" (0)); \
306 regs->ds = __USER_DS; \
307 regs->es = __USER_DS; \
308 regs->ss = __USER_DS; \
309 regs->cs = __USER_CS; \
310 regs->ip = new_eip; \
311 regs->sp = new_esp; \
315 extern unsigned long thread_saved_pc(struct task_struct *tsk);
317 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
318 #define KSTK_TOP(info) \
320 unsigned long *__ptr = (unsigned long *)(info); \
321 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
325 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
326 * This is necessary to guarantee that the entire "struct pt_regs"
327 * is accessable even if the CPU haven't stored the SS/ESP registers
328 * on the stack (interrupt gate does not save these registers
329 * when switching to the same priv ring).
330 * Therefore beware: accessing the ss/esp fields of the
331 * "struct pt_regs" is possible, but they may contain the
332 * completely wrong values.
334 #define task_pt_regs(task) \
336 struct pt_regs *__regs__; \
337 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
341 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
343 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
345 tss->x86_tss.sp0 = thread->sp0;
346 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
347 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
348 tss->x86_tss.ss1 = thread->sysenter_cs;
349 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
353 #ifdef CONFIG_PARAVIRT
354 #include <asm/paravirt.h>
357 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
359 native_load_sp0(tss, thread);
361 #endif /* CONFIG_PARAVIRT */
363 /* generic versions from gas */
364 #define GENERIC_NOP1 ".byte 0x90\n"
365 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
366 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
367 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
368 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
369 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
370 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
371 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
374 #define K8_NOP1 GENERIC_NOP1
375 #define K8_NOP2 ".byte 0x66,0x90\n"
376 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
377 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
378 #define K8_NOP5 K8_NOP3 K8_NOP2
379 #define K8_NOP6 K8_NOP3 K8_NOP3
380 #define K8_NOP7 K8_NOP4 K8_NOP3
381 #define K8_NOP8 K8_NOP4 K8_NOP4
384 /* uses eax dependencies (arbitary choice) */
385 #define K7_NOP1 GENERIC_NOP1
386 #define K7_NOP2 ".byte 0x8b,0xc0\n"
387 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
388 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
389 #define K7_NOP5 K7_NOP4 ASM_NOP1
390 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
391 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
392 #define K7_NOP8 K7_NOP7 ASM_NOP1
395 /* uses eax dependencies (Intel-recommended choice) */
396 #define P6_NOP1 GENERIC_NOP1
397 #define P6_NOP2 ".byte 0x66,0x90\n"
398 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
399 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
400 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
401 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
402 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
403 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
406 #define ASM_NOP1 K8_NOP1
407 #define ASM_NOP2 K8_NOP2
408 #define ASM_NOP3 K8_NOP3
409 #define ASM_NOP4 K8_NOP4
410 #define ASM_NOP5 K8_NOP5
411 #define ASM_NOP6 K8_NOP6
412 #define ASM_NOP7 K8_NOP7
413 #define ASM_NOP8 K8_NOP8
414 #elif defined(CONFIG_MK7)
415 #define ASM_NOP1 K7_NOP1
416 #define ASM_NOP2 K7_NOP2
417 #define ASM_NOP3 K7_NOP3
418 #define ASM_NOP4 K7_NOP4
419 #define ASM_NOP5 K7_NOP5
420 #define ASM_NOP6 K7_NOP6
421 #define ASM_NOP7 K7_NOP7
422 #define ASM_NOP8 K7_NOP8
423 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
424 defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
425 defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
426 #define ASM_NOP1 P6_NOP1
427 #define ASM_NOP2 P6_NOP2
428 #define ASM_NOP3 P6_NOP3
429 #define ASM_NOP4 P6_NOP4
430 #define ASM_NOP5 P6_NOP5
431 #define ASM_NOP6 P6_NOP6
432 #define ASM_NOP7 P6_NOP7
433 #define ASM_NOP8 P6_NOP8
435 #define ASM_NOP1 GENERIC_NOP1
436 #define ASM_NOP2 GENERIC_NOP2
437 #define ASM_NOP3 GENERIC_NOP3
438 #define ASM_NOP4 GENERIC_NOP4
439 #define ASM_NOP5 GENERIC_NOP5
440 #define ASM_NOP6 GENERIC_NOP6
441 #define ASM_NOP7 GENERIC_NOP7
442 #define ASM_NOP8 GENERIC_NOP8
445 #define ASM_NOP_MAX 8
447 /* Prefetch instructions for Pentium III and AMD Athlon */
448 /* It's not worth to care about 3dnow! prefetches for the K6
449 because they are microcoded there and very slow.
450 However we don't do prefetches for pre XP Athlons currently
451 That should be fixed. */
452 static inline void prefetch(const void *x)
454 alternative_input(ASM_NOP4,
460 #define ARCH_HAS_PREFETCH
462 /* 3dnow! prefetch to get an exclusive cache line. Useful for
463 spinlocks to avoid one state transition in the cache coherency protocol. */
464 static inline void prefetchw(const void *x)
466 alternative_input(ASM_NOP4,
472 extern void enable_sep_cpu(void);
473 extern int sysenter_setup(void);
475 /* Defined in head.S */
476 extern struct desc_ptr early_gdt_descr;
478 extern void cpu_set_gdt(int);
479 extern void switch_to_new_gdt(void);
480 extern void cpu_init(void);
481 extern void init_gdt(int cpu);
483 #endif /* __ASM_I386_PROCESSOR_H */