1 #ifndef __ASM_X86_PROCESSOR_H
2 #define __ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/percpu.h>
12 #include <asm/system.h>
15 * Default implementation of macro that returns current
16 * instruction pointer ("program counter").
18 static inline void *current_text_addr(void)
21 asm volatile("mov $1f,%0\n1:":"=r" (pc));
25 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
26 unsigned int *ecx, unsigned int *edx)
28 /* ecx is often an input as well as an output. */
34 : "0" (*eax), "2" (*ecx));
37 static inline void load_cr3(pgd_t *pgdir)
39 write_cr3(__pa(pgdir));
43 /* This is the TSS defined by the hardware. */
45 unsigned short back_link, __blh;
47 unsigned short ss0, __ss0h;
49 unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
51 unsigned short ss2, __ss2h;
55 unsigned long ax, cx, dx, bx;
56 unsigned long sp, bp, si, di;
57 unsigned short es, __esh;
58 unsigned short cs, __csh;
59 unsigned short ss, __ssh;
60 unsigned short ds, __dsh;
61 unsigned short fs, __fsh;
62 unsigned short gs, __gsh;
63 unsigned short ldt, __ldth;
64 unsigned short trace, io_bitmap_base;
65 } __attribute__((packed));
78 } __attribute__((packed)) ____cacheline_aligned;
84 #define IO_BITMAP_BITS 65536
85 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
86 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
87 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
88 #define INVALID_IO_BITMAP_OFFSET 0x8000
89 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
92 struct x86_hw_tss x86_tss;
95 * The extra 1 is there because the CPU will access an
96 * additional byte beyond the end of the IO permission
97 * bitmap. The extra byte must be all 1 bits, and must
98 * be within the limit.
100 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
102 * Cache the current maximum and the last task that used the bitmap:
104 unsigned long io_bitmap_max;
105 struct thread_struct *io_bitmap_owner;
107 * pads the TSS to be cacheline-aligned (size is 0x100)
109 unsigned long __cacheline_filler[35];
111 * .. and then another 0x100 bytes for emergency kernel stack
113 unsigned long stack[64];
114 } __attribute__((packed));
116 DECLARE_PER_CPU(struct tss_struct, init_tss);
119 # include "processor_32.h"
121 # include "processor_64.h"
124 extern void print_cpu_info(struct cpuinfo_x86 *);
125 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
126 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
127 extern unsigned short num_cache_leaves;
129 static inline unsigned long native_get_debugreg(int regno)
131 unsigned long val = 0; /* Damn you, gcc! */
135 asm("mov %%db0, %0" :"=r" (val)); break;
137 asm("mov %%db1, %0" :"=r" (val)); break;
139 asm("mov %%db2, %0" :"=r" (val)); break;
141 asm("mov %%db3, %0" :"=r" (val)); break;
143 asm("mov %%db6, %0" :"=r" (val)); break;
145 asm("mov %%db7, %0" :"=r" (val)); break;
152 static inline void native_set_debugreg(int regno, unsigned long value)
156 asm("mov %0,%%db0" : /* no output */ :"r" (value));
159 asm("mov %0,%%db1" : /* no output */ :"r" (value));
162 asm("mov %0,%%db2" : /* no output */ :"r" (value));
165 asm("mov %0,%%db3" : /* no output */ :"r" (value));
168 asm("mov %0,%%db6" : /* no output */ :"r" (value));
171 asm("mov %0,%%db7" : /* no output */ :"r" (value));
179 * Set IOPL bits in EFLAGS from given mask
181 static inline void native_set_iopl_mask(unsigned mask)
185 __asm__ __volatile__ ("pushfl;"
192 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
197 #ifndef CONFIG_PARAVIRT
198 #define __cpuid native_cpuid
199 #define paravirt_enabled() 0
202 * These special macros can be used to get or set a debugging register
204 #define get_debugreg(var, register) \
205 (var) = native_get_debugreg(register)
206 #define set_debugreg(value, register) \
207 native_set_debugreg(register, value)
209 #define set_iopl_mask native_set_iopl_mask
210 #endif /* CONFIG_PARAVIRT */
213 * Save the cr4 feature set we're using (ie
214 * Pentium 4MB enable and PPro Global page
215 * enable), so that any CPU's that boot up
216 * after us can get the correct flags.
218 extern unsigned long mmu_cr4_features;
220 static inline void set_in_cr4(unsigned long mask)
223 mmu_cr4_features |= mask;
229 static inline void clear_in_cr4(unsigned long mask)
232 mmu_cr4_features &= ~mask;
238 struct microcode_header {
246 unsigned int datasize;
247 unsigned int totalsize;
248 unsigned int reserved[3];
252 struct microcode_header hdr;
253 unsigned int bits[0];
256 typedef struct microcode microcode_t;
257 typedef struct microcode_header microcode_header_t;
259 /* microcode format is extended from prescott processors */
260 struct extended_signature {
266 struct extended_sigtable {
269 unsigned int reserved[3];
270 struct extended_signature sigs[0];
274 * create a kernel thread without removing it from tasklists
276 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
278 /* Free all resources held by a thread. */
279 extern void release_thread(struct task_struct *);
281 /* Prepare to copy thread state - unlazy all lazy status */
282 extern void prepare_to_copy(struct task_struct *tsk);
284 unsigned long get_wchan(struct task_struct *p);
287 * Generic CPUID function
288 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
289 * resulting in stale register contents being returned.
291 static inline void cpuid(unsigned int op,
292 unsigned int *eax, unsigned int *ebx,
293 unsigned int *ecx, unsigned int *edx)
297 __cpuid(eax, ebx, ecx, edx);
300 /* Some CPUID calls want 'count' to be placed in ecx */
301 static inline void cpuid_count(unsigned int op, int count,
302 unsigned int *eax, unsigned int *ebx,
303 unsigned int *ecx, unsigned int *edx)
307 __cpuid(eax, ebx, ecx, edx);
311 * CPUID functions returning a single datum
313 static inline unsigned int cpuid_eax(unsigned int op)
315 unsigned int eax, ebx, ecx, edx;
317 cpuid(op, &eax, &ebx, &ecx, &edx);
320 static inline unsigned int cpuid_ebx(unsigned int op)
322 unsigned int eax, ebx, ecx, edx;
324 cpuid(op, &eax, &ebx, &ecx, &edx);
327 static inline unsigned int cpuid_ecx(unsigned int op)
329 unsigned int eax, ebx, ecx, edx;
331 cpuid(op, &eax, &ebx, &ecx, &edx);
334 static inline unsigned int cpuid_edx(unsigned int op)
336 unsigned int eax, ebx, ecx, edx;
338 cpuid(op, &eax, &ebx, &ecx, &edx);
342 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
343 static inline void rep_nop(void)
345 __asm__ __volatile__("rep;nop": : :"memory");
348 /* Stop speculative execution */
349 static inline void sync_core(void)
352 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
353 : "ebx", "ecx", "edx", "memory");
356 #define cpu_relax() rep_nop()
358 static inline void __monitor(const void *eax, unsigned long ecx,
361 /* "monitor %eax,%ecx,%edx;" */
363 ".byte 0x0f,0x01,0xc8;"
364 : :"a" (eax), "c" (ecx), "d"(edx));
367 static inline void __mwait(unsigned long eax, unsigned long ecx)
369 /* "mwait %eax,%ecx;" */
371 ".byte 0x0f,0x01,0xc9;"
372 : :"a" (eax), "c" (ecx));
375 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
377 /* "mwait %eax,%ecx;" */
379 "sti; .byte 0x0f,0x01,0xc9;"
380 : :"a" (eax), "c" (ecx));
383 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
385 extern int force_mwait;
387 extern void select_idle_routine(const struct cpuinfo_x86 *c);
389 extern unsigned long boot_option_idle_override;
391 /* Boot loader type from the setup header */
392 extern int bootloader_type;
393 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
395 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
396 #define ARCH_HAS_PREFETCHW
397 #define ARCH_HAS_SPINLOCK_PREFETCH
399 #define spin_lock_prefetch(x) prefetchw(x)
400 /* This decides where the kernel will search for a free chunk of vm
401 * space during mmap's.
403 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
405 #define KSTK_EIP(task) (task_pt_regs(task)->ip)