2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
31 #define desc_empty(desc) \
32 (!((desc)->a | (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
63 int x86_cache_alignment; /* In bytes */
67 unsigned long loops_per_jiffy;
68 unsigned char x86_num_cores;
69 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
71 #define X86_VENDOR_INTEL 0
72 #define X86_VENDOR_CYRIX 1
73 #define X86_VENDOR_AMD 2
74 #define X86_VENDOR_UMC 3
75 #define X86_VENDOR_NEXGEN 4
76 #define X86_VENDOR_CENTAUR 5
77 #define X86_VENDOR_RISE 6
78 #define X86_VENDOR_TRANSMETA 7
79 #define X86_VENDOR_NSC 8
80 #define X86_VENDOR_NUM 9
81 #define X86_VENDOR_UNKNOWN 0xff
84 * capabilities of CPUs
87 extern struct cpuinfo_x86 boot_cpu_data;
88 extern struct cpuinfo_x86 new_cpu_data;
89 extern struct tss_struct doublefault_tss;
90 DECLARE_PER_CPU(struct tss_struct, init_tss);
93 extern struct cpuinfo_x86 cpu_data[];
94 #define current_cpu_data cpu_data[smp_processor_id()]
96 #define cpu_data (&boot_cpu_data)
97 #define current_cpu_data boot_cpu_data
100 extern int phys_proc_id[NR_CPUS];
101 extern int cpu_core_id[NR_CPUS];
102 extern char ignore_fpu_irq;
104 extern void identify_cpu(struct cpuinfo_x86 *);
105 extern void print_cpu_info(struct cpuinfo_x86 *);
106 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
109 extern void detect_ht(struct cpuinfo_x86 *c);
111 static inline void detect_ht(struct cpuinfo_x86 *c) {}
117 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
118 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
119 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
120 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
121 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
122 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
123 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
124 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
125 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
126 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
127 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
128 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
129 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
130 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
131 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
132 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
133 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
136 * Generic CPUID function
137 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
138 * resulting in stale register contents being returned.
140 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
150 /* Some CPUID calls want 'count' to be placed in ecx */
151 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
159 : "0" (op), "c" (count));
163 * CPUID functions returning a single datum
165 static inline unsigned int cpuid_eax(unsigned int op)
175 static inline unsigned int cpuid_ebx(unsigned int op)
177 unsigned int eax, ebx;
180 : "=a" (eax), "=b" (ebx)
185 static inline unsigned int cpuid_ecx(unsigned int op)
187 unsigned int eax, ecx;
190 : "=a" (eax), "=c" (ecx)
195 static inline unsigned int cpuid_edx(unsigned int op)
197 unsigned int eax, edx;
200 : "=a" (eax), "=d" (edx)
206 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
209 * Intel CPU features in CR4
211 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
212 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
213 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
214 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
215 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
216 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
217 #define X86_CR4_MCE 0x0040 /* Machine check enable */
218 #define X86_CR4_PGE 0x0080 /* enable global pages */
219 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
220 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
221 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
224 * Save the cr4 feature set we're using (ie
225 * Pentium 4MB enable and PPro Global page
226 * enable), so that any CPU's that boot up
227 * after us can get the correct flags.
229 extern unsigned long mmu_cr4_features;
231 static inline void set_in_cr4 (unsigned long mask)
234 mmu_cr4_features |= mask;
240 static inline void clear_in_cr4 (unsigned long mask)
243 mmu_cr4_features &= ~mask;
250 * NSC/Cyrix CPU configuration register indexes
253 #define CX86_PCR0 0x20
254 #define CX86_GCR 0xb8
255 #define CX86_CCR0 0xc0
256 #define CX86_CCR1 0xc1
257 #define CX86_CCR2 0xc2
258 #define CX86_CCR3 0xc3
259 #define CX86_CCR4 0xe8
260 #define CX86_CCR5 0xe9
261 #define CX86_CCR6 0xea
262 #define CX86_CCR7 0xeb
263 #define CX86_PCR1 0xf0
264 #define CX86_DIR0 0xfe
265 #define CX86_DIR1 0xff
266 #define CX86_ARR_BASE 0xc4
267 #define CX86_RCR_BASE 0xdc
270 * NSC/Cyrix CPU indexed register access macros
273 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
275 #define setCx86(reg, data) do { \
277 outb((data), 0x23); \
280 static inline void __monitor(const void *eax, unsigned long ecx,
283 /* "monitor %eax,%ecx,%edx;" */
285 ".byte 0x0f,0x01,0xc8;"
286 : :"a" (eax), "c" (ecx), "d"(edx));
289 static inline void __mwait(unsigned long eax, unsigned long ecx)
291 /* "mwait %eax,%ecx;" */
293 ".byte 0x0f,0x01,0xc9;"
294 : :"a" (eax), "c" (ecx));
297 /* from system description table in BIOS. Mostly for MCA use, but
298 others may find it useful. */
299 extern unsigned int machine_id;
300 extern unsigned int machine_submodel_id;
301 extern unsigned int BIOS_revision;
302 extern unsigned int mca_pentium_flag;
304 /* Boot loader type from the setup header */
305 extern int bootloader_type;
308 * User space process size: 3GB (default).
310 #define TASK_SIZE (PAGE_OFFSET)
312 /* This decides where the kernel will search for a free chunk of vm
313 * space during mmap's.
315 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
317 #define HAVE_ARCH_PICK_MMAP_LAYOUT
322 #define IO_BITMAP_BITS 65536
323 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
324 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
325 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
326 #define INVALID_IO_BITMAP_OFFSET 0x8000
327 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
329 struct i387_fsave_struct {
337 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
338 long status; /* software status information */
341 struct i387_fxsave_struct {
352 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
353 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
355 } __attribute__ ((aligned (16)));
357 struct i387_soft_struct {
365 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
366 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
368 unsigned long entry_eip;
372 struct i387_fsave_struct fsave;
373 struct i387_fxsave_struct fxsave;
374 struct i387_soft_struct soft;
381 struct thread_struct;
384 unsigned short back_link,__blh;
386 unsigned short ss0,__ss0h;
388 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
390 unsigned short ss2,__ss2h;
393 unsigned long eflags;
394 unsigned long eax,ecx,edx,ebx;
399 unsigned short es, __esh;
400 unsigned short cs, __csh;
401 unsigned short ss, __ssh;
402 unsigned short ds, __dsh;
403 unsigned short fs, __fsh;
404 unsigned short gs, __gsh;
405 unsigned short ldt, __ldth;
406 unsigned short trace, io_bitmap_base;
408 * The extra 1 is there because the CPU will access an
409 * additional byte beyond the end of the IO permission
410 * bitmap. The extra byte must be all 1 bits, and must
411 * be within the limit.
413 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
415 * Cache the current maximum and the last task that used the bitmap:
417 unsigned long io_bitmap_max;
418 struct thread_struct *io_bitmap_owner;
420 * pads the TSS to be cacheline-aligned (size is 0x100)
422 unsigned long __cacheline_filler[35];
424 * .. and then another 0x100 bytes for emergency kernel stack
426 unsigned long stack[64];
427 } __attribute__((packed));
429 #define ARCH_MIN_TASKALIGN 16
431 struct thread_struct {
432 /* cached TLS descriptors. */
433 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
435 unsigned long sysenter_cs;
440 /* Hardware debugging registers */
441 unsigned long debugreg[8]; /* %%db0-7 debug registers */
443 unsigned long cr2, trap_no, error_code;
444 /* floating point info */
445 union i387_union i387;
446 /* virtual 86 mode info */
447 struct vm86_struct __user * vm86_info;
448 unsigned long screen_bitmap;
449 unsigned long v86flags, v86mask, saved_esp0;
450 unsigned int saved_fs, saved_gs;
452 unsigned long *io_bitmap_ptr;
453 /* max allowed port in the bitmap, in bytes: */
454 unsigned long io_bitmap_max;
457 #define INIT_THREAD { \
459 .sysenter_cs = __KERNEL_CS, \
460 .io_bitmap_ptr = NULL, \
464 * Note that the .io_bitmap member must be extra-big. This is because
465 * the CPU will access an additional byte beyond the end of the IO
466 * permission bitmap. The extra byte must be all 1 bits, and must
467 * be within the limit.
470 .esp0 = sizeof(init_stack) + (long)&init_stack, \
471 .ss0 = __KERNEL_DS, \
472 .ss1 = __KERNEL_CS, \
473 .ldt = GDT_ENTRY_LDT, \
474 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
475 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
478 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
480 tss->esp0 = thread->esp0;
481 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
482 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
483 tss->ss1 = thread->sysenter_cs;
484 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
488 #define start_thread(regs, new_eip, new_esp) do { \
489 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
491 regs->xds = __USER_DS; \
492 regs->xes = __USER_DS; \
493 regs->xss = __USER_DS; \
494 regs->xcs = __USER_CS; \
495 regs->eip = new_eip; \
496 regs->esp = new_esp; \
500 * These special macros can be used to get or set a debugging register
502 #define get_debugreg(var, register) \
503 __asm__("movl %%db" #register ", %0" \
505 #define set_debugreg(value, register) \
506 __asm__("movl %0,%%db" #register \
511 /* Forward declaration, a strange C thing */
515 /* Free all resources held by a thread. */
516 extern void release_thread(struct task_struct *);
518 /* Prepare to copy thread state - unlazy all lazy status */
519 extern void prepare_to_copy(struct task_struct *tsk);
522 * create a kernel thread without removing it from tasklists
524 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
526 extern unsigned long thread_saved_pc(struct task_struct *tsk);
527 void show_trace(struct task_struct *task, unsigned long *stack);
529 unsigned long get_wchan(struct task_struct *p);
531 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
532 #define KSTK_TOP(info) \
534 unsigned long *__ptr = (unsigned long *)(info); \
535 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
538 #define task_pt_regs(task) \
540 struct pt_regs *__regs__; \
541 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
545 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
546 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
549 struct microcode_header {
557 unsigned int datasize;
558 unsigned int totalsize;
559 unsigned int reserved[3];
563 struct microcode_header hdr;
564 unsigned int bits[0];
567 typedef struct microcode microcode_t;
568 typedef struct microcode_header microcode_header_t;
570 /* microcode format is extended from prescott processors */
571 struct extended_signature {
577 struct extended_sigtable {
580 unsigned int reserved[3];
581 struct extended_signature sigs[0];
583 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
584 #define MICROCODE_IOCFREE _IO('6',0)
586 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
587 static inline void rep_nop(void)
589 __asm__ __volatile__("rep;nop": : :"memory");
592 #define cpu_relax() rep_nop()
594 /* generic versions from gas */
595 #define GENERIC_NOP1 ".byte 0x90\n"
596 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
597 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
598 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
599 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
600 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
601 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
602 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
605 #define K8_NOP1 GENERIC_NOP1
606 #define K8_NOP2 ".byte 0x66,0x90\n"
607 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
608 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
609 #define K8_NOP5 K8_NOP3 K8_NOP2
610 #define K8_NOP6 K8_NOP3 K8_NOP3
611 #define K8_NOP7 K8_NOP4 K8_NOP3
612 #define K8_NOP8 K8_NOP4 K8_NOP4
615 /* uses eax dependencies (arbitary choice) */
616 #define K7_NOP1 GENERIC_NOP1
617 #define K7_NOP2 ".byte 0x8b,0xc0\n"
618 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
619 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
620 #define K7_NOP5 K7_NOP4 ASM_NOP1
621 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
622 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
623 #define K7_NOP8 K7_NOP7 ASM_NOP1
626 #define ASM_NOP1 K8_NOP1
627 #define ASM_NOP2 K8_NOP2
628 #define ASM_NOP3 K8_NOP3
629 #define ASM_NOP4 K8_NOP4
630 #define ASM_NOP5 K8_NOP5
631 #define ASM_NOP6 K8_NOP6
632 #define ASM_NOP7 K8_NOP7
633 #define ASM_NOP8 K8_NOP8
634 #elif defined(CONFIG_MK7)
635 #define ASM_NOP1 K7_NOP1
636 #define ASM_NOP2 K7_NOP2
637 #define ASM_NOP3 K7_NOP3
638 #define ASM_NOP4 K7_NOP4
639 #define ASM_NOP5 K7_NOP5
640 #define ASM_NOP6 K7_NOP6
641 #define ASM_NOP7 K7_NOP7
642 #define ASM_NOP8 K7_NOP8
644 #define ASM_NOP1 GENERIC_NOP1
645 #define ASM_NOP2 GENERIC_NOP2
646 #define ASM_NOP3 GENERIC_NOP3
647 #define ASM_NOP4 GENERIC_NOP4
648 #define ASM_NOP5 GENERIC_NOP5
649 #define ASM_NOP6 GENERIC_NOP6
650 #define ASM_NOP7 GENERIC_NOP7
651 #define ASM_NOP8 GENERIC_NOP8
654 #define ASM_NOP_MAX 8
656 /* Prefetch instructions for Pentium III and AMD Athlon */
657 /* It's not worth to care about 3dnow! prefetches for the K6
658 because they are microcoded there and very slow.
659 However we don't do prefetches for pre XP Athlons currently
660 That should be fixed. */
661 #define ARCH_HAS_PREFETCH
662 extern inline void prefetch(const void *x)
664 alternative_input(ASM_NOP4,
670 #define ARCH_HAS_PREFETCH
671 #define ARCH_HAS_PREFETCHW
672 #define ARCH_HAS_SPINLOCK_PREFETCH
674 /* 3dnow! prefetch to get an exclusive cache line. Useful for
675 spinlocks to avoid one state transition in the cache coherency protocol. */
676 extern inline void prefetchw(const void *x)
678 alternative_input(ASM_NOP4,
683 #define spin_lock_prefetch(x) prefetchw(x)
685 extern void select_idle_routine(const struct cpuinfo_x86 *c);
687 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
689 extern unsigned long boot_option_idle_override;
690 extern void enable_sep_cpu(void);
691 extern int sysenter_setup(void);
694 extern void mtrr_ap_init(void);
695 extern void mtrr_bp_init(void);
697 #define mtrr_ap_init() do {} while (0)
698 #define mtrr_bp_init() do {} while (0)
701 #endif /* __ASM_I386_PROCESSOR_H */