2 * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
3 * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
6 * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
7 * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
9 * Use consistent with the GNU GPL is permitted,
10 * provided that this copyright notice is
11 * preserved in its entirety in all copies and derived works.
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/mfd/core.h>
22 #include <linux/mfd/ds1wm.h>
23 #include <linux/slab.h>
28 #include "../w1_int.h"
31 #define DS1WM_CMD 0x00 /* R/W 4 bits command */
32 #define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */
33 #define DS1WM_INT 0x02 /* R/W interrupt status */
34 #define DS1WM_INT_EN 0x03 /* R/W interrupt enable */
35 #define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */
36 #define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */
38 #define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */
39 #define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */
40 #define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */
41 #define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */
42 #define DS1WM_CMD_RST (1 << 5) /* software reset */
43 #define DS1WM_CMD_OD (1 << 7) /* overdrive */
45 #define DS1WM_INT_PD (1 << 0) /* presence detect */
46 #define DS1WM_INT_PDR (1 << 1) /* presence detect result */
47 #define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */
48 #define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */
49 #define DS1WM_INT_RBF (1 << 4) /* rx buffer full */
50 #define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */
52 #define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */
53 #define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */
54 #define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */
55 #define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */
56 #define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */
57 #define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */
58 #define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */
60 #define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */
62 #define DS1WM_TIMEOUT (HZ * 5)
66 unsigned long divisor;
92 /* you can continue this table, consult the OPERATION - CLOCK DIVISOR
93 section of the ds1wm spec sheet. */
98 int bus_shift; /* # of shifts to calc register offsets */
99 struct platform_device *pdev;
100 const struct mfd_cell *cell;
103 void *reset_complete;
105 void *write_complete;
107 /* last byte received */
109 /* byte to write that makes all intr disabled, */
110 /* considering active_state (IAS) (optimization) */
114 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
117 __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
120 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
122 return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
126 static irqreturn_t ds1wm_isr(int isr, void *data)
128 struct ds1wm_data *ds1wm_data = data;
130 u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
131 /* if no bits are set in int enable register (except the IAS)
132 than go no further, reading the regs below has side effects */
133 if (!(inten & DS1WM_INTEN_NOT_IAS))
136 ds1wm_write_register(ds1wm_data,
137 DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
139 /* this read action clears the INTR and certain flags in ds1wm */
140 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
142 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
144 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
145 inten &= ~DS1WM_INTEN_ETMT;
146 complete(ds1wm_data->write_complete);
148 if (intr & DS1WM_INT_RBF) {
149 /* this read clears the RBF flag */
150 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
152 inten &= ~DS1WM_INTEN_ERBF;
153 if (ds1wm_data->read_complete)
154 complete(ds1wm_data->read_complete);
156 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
157 inten &= ~DS1WM_INTEN_EPD;
158 complete(ds1wm_data->reset_complete);
161 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
165 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
167 unsigned long timeleft;
168 DECLARE_COMPLETION_ONSTACK(reset_done);
170 ds1wm_data->reset_complete = &reset_done;
172 /* enable Presence detect only */
173 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
174 ds1wm_data->int_en_reg_none);
176 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
178 timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
179 ds1wm_data->reset_complete = NULL;
181 dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
185 if (!ds1wm_data->slave_present) {
186 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
193 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
195 unsigned long timeleft;
196 DECLARE_COMPLETION_ONSTACK(write_done);
197 ds1wm_data->write_complete = &write_done;
199 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
200 ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
202 ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
204 timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
206 ds1wm_data->write_complete = NULL;
208 dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
215 static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
217 unsigned long timeleft;
218 u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
219 DECLARE_COMPLETION_ONSTACK(read_done);
221 ds1wm_read_register(ds1wm_data, DS1WM_DATA);
223 ds1wm_data->read_complete = &read_done;
224 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
226 ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
227 timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
229 ds1wm_data->read_complete = NULL;
231 dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
232 ds1wm_data->read_error = -ETIMEDOUT;
235 ds1wm_data->read_error = 0;
236 return ds1wm_data->read_byte;
239 static int ds1wm_find_divisor(int gclk)
243 for (i = ARRAY_SIZE(freq)-1; i >= 0; --i)
244 if (gclk >= freq[i].freq)
245 return freq[i].divisor;
250 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
253 struct ds1wm_driver_data *plat = ds1wm_data->pdev->dev.platform_data;
255 if (ds1wm_data->cell->enable)
256 ds1wm_data->cell->enable(ds1wm_data->pdev);
258 divisor = ds1wm_find_divisor(plat->clock_rate);
259 dev_dbg(&ds1wm_data->pdev->dev,
260 "found divisor 0x%x for clock %d\n", divisor, plat->clock_rate);
262 dev_err(&ds1wm_data->pdev->dev,
263 "no suitable divisor for %dHz clock\n",
267 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
269 /* Let the w1 clock stabilize. */
272 ds1wm_reset(ds1wm_data);
275 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
277 ds1wm_reset(ds1wm_data);
279 /* Disable interrupts. */
280 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
281 ds1wm_data->int_en_reg_none);
283 if (ds1wm_data->cell->disable)
284 ds1wm_data->cell->disable(ds1wm_data->pdev);
287 /* --------------------------------------------------------------------- */
290 static u8 ds1wm_read_byte(void *data)
292 struct ds1wm_data *ds1wm_data = data;
294 return ds1wm_read(ds1wm_data, 0xff);
297 static void ds1wm_write_byte(void *data, u8 byte)
299 struct ds1wm_data *ds1wm_data = data;
301 ds1wm_write(ds1wm_data, byte);
304 static u8 ds1wm_reset_bus(void *data)
306 struct ds1wm_data *ds1wm_data = data;
308 ds1wm_reset(ds1wm_data);
313 static void ds1wm_search(void *data, struct w1_master *master_dev,
314 u8 search_type, w1_slave_found_callback slave_found)
316 struct ds1wm_data *ds1wm_data = data;
318 int ms_discrep_bit = -1;
319 u64 r = 0; /* holds the progress of the search */
321 unsigned slaves_found = 0;
322 unsigned int pass = 0;
324 dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
328 dev_dbg(&ds1wm_data->pdev->dev,
329 "too many attempts (100), search aborted\n");
333 if (ds1wm_reset(ds1wm_data)) {
334 dev_dbg(&ds1wm_data->pdev->dev,
335 "pass: %d reset error (or no slaves)\n", pass);
339 dev_dbg(&ds1wm_data->pdev->dev,
340 "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r);
341 ds1wm_write(ds1wm_data, search_type);
342 dev_dbg(&ds1wm_data->pdev->dev,
343 "pass: %d entering ASM\n", pass);
344 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
345 dev_dbg(&ds1wm_data->pdev->dev,
346 "pass: %d begining nibble loop\n", pass);
350 /* we work one nibble at a time */
351 /* each nibble is interleaved to form a byte */
352 for (i = 0; i < 16; i++) {
354 unsigned char resp, _r, _r_prime, _d;
356 _r = (r >> (4*i)) & 0xf;
357 _r = ((_r & 0x1) << 1) |
362 /* writes _r, then reads back: */
363 resp = ds1wm_read(ds1wm_data, _r);
365 if (ds1wm_data->read_error) {
366 dev_err(&ds1wm_data->pdev->dev,
367 "pass: %d nibble: %d read error\n", pass, i);
371 _r_prime = ((resp & 0x02) >> 1) |
372 ((resp & 0x08) >> 2) |
373 ((resp & 0x20) >> 3) |
374 ((resp & 0x80) >> 4);
376 _d = ((resp & 0x01) >> 0) |
377 ((resp & 0x04) >> 1) |
378 ((resp & 0x10) >> 2) |
379 ((resp & 0x40) >> 3);
381 r_prime |= (unsigned long long) _r_prime << (i * 4);
382 d |= (unsigned long long) _d << (i * 4);
385 if (ds1wm_data->read_error) {
386 dev_err(&ds1wm_data->pdev->dev,
387 "pass: %d read error, retrying\n", pass);
390 dev_dbg(&ds1wm_data->pdev->dev,
391 "pass: %d r\': %0#18llx d:%0#18llx\n",
393 dev_dbg(&ds1wm_data->pdev->dev,
394 "pass: %d nibble loop complete, exiting ASM\n", pass);
395 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
396 dev_dbg(&ds1wm_data->pdev->dev,
397 "pass: %d resetting bus\n", pass);
398 ds1wm_reset(ds1wm_data);
399 if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) {
400 dev_err(&ds1wm_data->pdev->dev,
401 "pass: %d bus error, retrying\n", pass);
402 continue; /* start over */
406 dev_dbg(&ds1wm_data->pdev->dev,
407 "pass: %d found %0#18llx\n", pass, r_prime);
408 slave_found(master_dev, r_prime);
410 dev_dbg(&ds1wm_data->pdev->dev,
411 "pass: %d complete, preparing next pass\n", pass);
413 /* any discrepency found which we already choose the
414 '1' branch is now is now irrelevant we reveal the
415 next branch with this: */
417 /* find last bit set, i.e. the most signif. bit set */
418 ms_discrep_bit = fls64(d) - 1;
419 dev_dbg(&ds1wm_data->pdev->dev,
420 "pass: %d new d:%0#18llx MS discrep bit:%d\n",
421 pass, d, ms_discrep_bit);
423 /* prev_ms_discrep_bit = ms_discrep_bit;
424 prepare for next ROM search: */
425 if (ms_discrep_bit == -1)
428 r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit;
429 } /* end while true */
430 dev_dbg(&ds1wm_data->pdev->dev,
431 "pass: %d total: %d search done ms d bit pos: %d\n", pass,
432 slaves_found, ms_discrep_bit);
435 /* --------------------------------------------------------------------- */
437 static struct w1_bus_master ds1wm_master = {
438 .read_byte = ds1wm_read_byte,
439 .write_byte = ds1wm_write_byte,
440 .reset_bus = ds1wm_reset_bus,
441 .search = ds1wm_search,
444 static int ds1wm_probe(struct platform_device *pdev)
446 struct ds1wm_data *ds1wm_data;
447 struct ds1wm_driver_data *plat;
448 struct resource *res;
454 ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
458 platform_set_drvdata(pdev, ds1wm_data);
460 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465 ds1wm_data->map = ioremap(res->start, resource_size(res));
466 if (!ds1wm_data->map) {
471 /* calculate bus shift from mem resource */
472 ds1wm_data->bus_shift = resource_size(res) >> 3;
474 ds1wm_data->pdev = pdev;
475 ds1wm_data->cell = mfd_get_cell(pdev);
476 if (!ds1wm_data->cell) {
480 plat = pdev->dev.platform_data;
486 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
491 ds1wm_data->irq = res->start;
492 ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
494 if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
495 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
496 if (res->flags & IORESOURCE_IRQ_LOWEDGE)
497 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
499 ret = request_irq(ds1wm_data->irq, ds1wm_isr,
500 IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data);
504 ds1wm_up(ds1wm_data);
506 ds1wm_master.data = (void *)ds1wm_data;
508 ret = w1_add_master_device(&ds1wm_master);
515 ds1wm_down(ds1wm_data);
516 free_irq(ds1wm_data->irq, ds1wm_data);
518 iounmap(ds1wm_data->map);
526 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
528 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
530 ds1wm_down(ds1wm_data);
535 static int ds1wm_resume(struct platform_device *pdev)
537 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
539 ds1wm_up(ds1wm_data);
544 #define ds1wm_suspend NULL
545 #define ds1wm_resume NULL
548 static int ds1wm_remove(struct platform_device *pdev)
550 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
552 w1_remove_master_device(&ds1wm_master);
553 ds1wm_down(ds1wm_data);
554 free_irq(ds1wm_data->irq, ds1wm_data);
555 iounmap(ds1wm_data->map);
561 static struct platform_driver ds1wm_driver = {
565 .probe = ds1wm_probe,
566 .remove = ds1wm_remove,
567 .suspend = ds1wm_suspend,
568 .resume = ds1wm_resume
571 static int __init ds1wm_init(void)
573 printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
574 return platform_driver_register(&ds1wm_driver);
577 static void __exit ds1wm_exit(void)
579 platform_driver_unregister(&ds1wm_driver);
582 module_init(ds1wm_init);
583 module_exit(ds1wm_exit);
585 MODULE_LICENSE("GPL");
586 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
587 "Matt Reimer <mreimer@vpop.net>,"
588 "Jean-Francois Dagenais <dagenaisj@sonatest.com>");
589 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");