2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
28 #define VERSION "0.7.9-NEWAPI"
30 struct tridentfb_par {
31 void __iomem *io_virt; /* iospace virtual memory address */
35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 static unsigned char eng_oper; /* engine operation... */
44 static struct fb_ops tridentfb_ops;
46 static struct fb_fix_screeninfo tridentfb_fix = {
48 .type = FB_TYPE_PACKED_PIXELS,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
54 /* defaults which are normally overriden by user values */
57 static char *mode_option __devinitdata = "640x480";
58 static int bpp __devinitdata = 8;
60 static int noaccel __devinitdata;
65 static int fp __devinitdata;
66 static int crt __devinitdata;
68 static int memsize __devinitdata;
69 static int memdiff __devinitdata;
72 module_param(mode_option, charp, 0);
73 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
74 module_param_named(mode, mode_option, charp, 0);
75 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
76 module_param(bpp, int, 0);
77 module_param(center, int, 0);
78 module_param(stretch, int, 0);
79 module_param(noaccel, int, 0);
80 module_param(memsize, int, 0);
81 module_param(memdiff, int, 0);
82 module_param(nativex, int, 0);
83 module_param(fp, int, 0);
84 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
85 module_param(crt, int, 0);
86 MODULE_PARM_DESC(crt, "Define if CRT is connected");
88 static int is_oldclock(int id)
90 return (id == TGUI9440) ||
95 static int is_oldprotect(int id)
97 return (id == TGUI9440) ||
99 (id == PROVIDIA9685) ||
105 static int is_blade(int id)
107 return (id == BLADE3D) ||
108 (id == CYBERBLADEE4) ||
109 (id == CYBERBLADEi7) ||
110 (id == CYBERBLADEi7D) ||
111 (id == CYBERBLADEi1) ||
112 (id == CYBERBLADEi1D) ||
113 (id == CYBERBLADEAi1) ||
114 (id == CYBERBLADEAi1D);
117 static int is_xp(int id)
119 return (id == CYBERBLADEXPAi1) ||
120 (id == CYBERBLADEXPm8) ||
121 (id == CYBERBLADEXPm16);
124 static int is3Dchip(int id)
126 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
127 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
128 (id == CYBER9397) || (id == CYBER9397DVD) ||
129 (id == CYBER9520) || (id == CYBER9525DVD) ||
130 (id == IMAGE975) || (id == IMAGE985) ||
131 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
132 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
133 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
134 (id == CYBERBLADEXPAi1));
137 static int iscyber(int id)
153 case CYBERBLADEXPAi1:
162 case CYBERBLADEi7: /* VIA MPV4 integrated version */
165 /* case CYBERBLDAEXPm8: Strange */
166 /* case CYBERBLDAEXPm16: Strange */
171 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
173 fb_writeb(val, p->io_virt + reg);
176 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
178 return fb_readb(p->io_virt + reg);
181 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
183 fb_writel(v, par->io_virt + r);
186 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
188 return fb_readl(par->io_virt + r);
192 * Blade specific acceleration.
195 #define point(x, y) ((y) << 16 | (x))
207 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
209 int v1 = (pitch >> 3) << 20;
226 v2 = v1 | (tmp << 29);
227 writemmr(par, 0x21C0, v2);
228 writemmr(par, 0x21C4, v2);
229 writemmr(par, 0x21B8, v2);
230 writemmr(par, 0x21BC, v2);
231 writemmr(par, 0x21D0, v1);
232 writemmr(par, 0x21D4, v1);
233 writemmr(par, 0x21C8, v1);
234 writemmr(par, 0x21CC, v1);
235 writemmr(par, 0x216C, 0);
238 static void blade_wait_engine(struct tridentfb_par *par)
240 while (readmmr(par, STA) & 0xFA800000) ;
243 static void blade_fill_rect(struct tridentfb_par *par,
244 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
246 writemmr(par, CLR, c);
247 writemmr(par, ROP, rop ? 0x66 : ROP_S);
248 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
250 writemmr(par, DR1, point(x, y));
251 writemmr(par, DR2, point(x + w - 1, y + h - 1));
254 static void blade_copy_rect(struct tridentfb_par *par,
255 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
260 s2 = point(x1 + w - 1, y1 + h - 1);
262 d2 = point(x2 + w - 1, y2 + h - 1);
264 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
267 writemmr(par, ROP, ROP_S);
268 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
270 writemmr(par, SR1, direction ? s2 : s1);
271 writemmr(par, SR2, direction ? s1 : s2);
272 writemmr(par, DR1, direction ? d2 : d1);
273 writemmr(par, DR2, direction ? d1 : d2);
277 * BladeXP specific acceleration functions
281 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
283 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
303 switch (pitch << (bpp >> 3)) {
319 t_outb(par, x, 0x2125);
339 writemmr(par, 0x2154, v1);
340 writemmr(par, 0x2150, v1);
341 t_outb(par, 3, 0x2126);
344 static void xp_wait_engine(struct tridentfb_par *par)
352 busy = t_inb(par, STA) & 0x80;
356 if (count == 10000000) {
362 t_outb(par, 0x00, 0x2120);
369 static void xp_fill_rect(struct tridentfb_par *par,
370 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
372 writemmr(par, 0x2127, ROP_P);
373 writemmr(par, 0x2158, c);
374 writemmr(par, 0x2128, 0x4000);
375 writemmr(par, 0x2140, masked_point(h, w));
376 writemmr(par, 0x2138, masked_point(y, x));
377 t_outb(par, 0x01, 0x2124);
378 t_outb(par, eng_oper, 0x2125);
381 static void xp_copy_rect(struct tridentfb_par *par,
382 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
385 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
389 if ((x1 < x2) && (y1 == y2)) {
407 writemmr(par, 0x2128, direction);
408 t_outb(par, ROP_S, 0x2127);
409 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
410 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
411 writemmr(par, 0x2140, masked_point(h, w));
412 t_outb(par, 0x01, 0x2124);
416 * Image specific acceleration functions
418 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
436 writemmr(par, 0x2120, 0xF0000000);
437 writemmr(par, 0x2120, 0x40000000 | tmp);
438 writemmr(par, 0x2120, 0x80000000);
439 writemmr(par, 0x2144, 0x00000000);
440 writemmr(par, 0x2148, 0x00000000);
441 writemmr(par, 0x2150, 0x00000000);
442 writemmr(par, 0x2154, 0x00000000);
443 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
444 writemmr(par, 0x216C, 0x00000000);
445 writemmr(par, 0x2170, 0x00000000);
446 writemmr(par, 0x217C, 0x00000000);
447 writemmr(par, 0x2120, 0x10000000);
448 writemmr(par, 0x2130, (2047 << 16) | 2047);
451 static void image_wait_engine(struct tridentfb_par *par)
453 while (readmmr(par, 0x2164) & 0xF0000000) ;
456 static void image_fill_rect(struct tridentfb_par *par,
457 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
459 writemmr(par, 0x2120, 0x80000000);
460 writemmr(par, 0x2120, 0x90000000 | ROP_S);
462 writemmr(par, 0x2144, c);
464 writemmr(par, DR1, point(x, y));
465 writemmr(par, DR2, point(x + w - 1, y + h - 1));
467 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
470 static void image_copy_rect(struct tridentfb_par *par,
471 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
476 s2 = point(x1 + w - 1, y1 + h - 1);
478 d2 = point(x2 + w - 1, y2 + h - 1);
480 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2120, 0x90000000 | ROP_S);
486 writemmr(par, SR1, direction ? s2 : s1);
487 writemmr(par, SR2, direction ? s1 : s2);
488 writemmr(par, DR1, direction ? d2 : d1);
489 writemmr(par, DR2, direction ? d1 : d2);
490 writemmr(par, 0x2124,
491 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
495 * TGUI 9440/96XX acceleration
498 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
502 /* disable clipping */
503 writemmr(par, 0x2148, 0);
504 writemmr(par, 0x214C, point(4095, 2047));
521 switch ((pitch * bpp) / 8) {
537 fb_writew(x, par->io_virt + 0x2122);
540 static void tgui_fill_rect(struct tridentfb_par *par,
541 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
543 t_outb(par, ROP_P, 0x2127);
544 writemmr(par, 0x212c, c);
545 writemmr(par, 0x2128, 0x4020);
546 writemmr(par, 0x2140, point(w - 1, h - 1));
547 writemmr(par, 0x2138, point(x, y));
548 t_outb(par, 1, 0x2124);
551 static void tgui_copy_rect(struct tridentfb_par *par,
552 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
555 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
557 if ((x1 < x2) && (y1 == y2)) {
575 writemmr(par, 0x2128, 0x4 | flags);
576 t_outb(par, ROP_S, 0x2127);
577 writemmr(par, 0x213C, point(x1_tmp, y1_tmp));
578 writemmr(par, 0x2138, point(x2_tmp, y2_tmp));
579 writemmr(par, 0x2140, point(w - 1, h - 1));
580 t_outb(par, 1, 0x2124);
584 * Accel functions called by the upper layers
586 #ifdef CONFIG_FB_TRIDENT_ACCEL
587 static void tridentfb_fillrect(struct fb_info *info,
588 const struct fb_fillrect *fr)
590 struct tridentfb_par *par = info->par;
591 int bpp = info->var.bits_per_pixel;
602 col = ((u32 *)(info->pseudo_palette))[fr->color];
605 col = ((u32 *)(info->pseudo_palette))[fr->color];
609 par->fill_rect(par, fr->dx, fr->dy, fr->width,
610 fr->height, col, fr->rop);
611 par->wait_engine(par);
613 static void tridentfb_copyarea(struct fb_info *info,
614 const struct fb_copyarea *ca)
616 struct tridentfb_par *par = info->par;
618 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
619 ca->width, ca->height);
620 par->wait_engine(par);
622 #endif /* CONFIG_FB_TRIDENT_ACCEL */
625 * Hardware access functions
628 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
630 return vga_mm_rcrt(par->io_virt, reg);
633 static inline void write3X4(struct tridentfb_par *par, int reg,
636 vga_mm_wcrt(par->io_virt, reg, val);
639 static inline unsigned char read3CE(struct tridentfb_par *par,
642 return vga_mm_rgfx(par->io_virt, reg);
645 static inline void writeAttr(struct tridentfb_par *par, int reg,
648 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
649 vga_mm_wattr(par->io_virt, reg, val);
652 static inline void write3CE(struct tridentfb_par *par, int reg,
655 vga_mm_wgfx(par->io_virt, reg, val);
658 static void enable_mmio(void)
663 /* Unprotect registers */
664 vga_io_wseq(NewMode1, 0x80);
668 outb(inb(0x3D5) | 0x01, 0x3D5);
671 static void disable_mmio(struct tridentfb_par *par)
674 vga_mm_rseq(par->io_virt, 0x0B);
676 /* Unprotect registers */
677 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
680 t_outb(par, PCIReg, 0x3D4);
681 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
684 static void crtc_unlock(struct tridentfb_par *par)
686 write3X4(par, VGA_CRTC_V_SYNC_END,
687 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
690 /* Return flat panel's maximum x resolution */
691 static int __devinit get_nativex(struct tridentfb_par *par)
698 tmp = (read3CE(par, VertStretch) >> 4) & 3;
719 output("%dx%d flat panel found\n", x, y);
724 static void set_lwidth(struct tridentfb_par *par, int width)
726 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
727 write3X4(par, AddColReg,
728 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
731 /* For resolutions smaller than FP resolution stretch */
732 static void screen_stretch(struct tridentfb_par *par)
734 if (par->chip_id != CYBERBLADEXPAi1)
735 write3CE(par, BiosReg, 0);
737 write3CE(par, BiosReg, 8);
738 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
739 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
742 /* For resolutions smaller than FP resolution center */
743 static void screen_center(struct tridentfb_par *par)
745 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
746 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
749 /* Address of first shown pixel in display memory */
750 static void set_screen_start(struct tridentfb_par *par, int base)
753 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
754 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
755 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
756 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
757 tmp = read3X4(par, CRTHiOrd) & 0xF8;
758 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
761 /* Set dotclock frequency */
762 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
765 unsigned long fi, d, di;
766 unsigned char best_m = 0, best_n = 0, best_k = 0;
767 unsigned char hi, lo;
770 for (k = 1; k >= 0; k--)
771 for (m = 0; m < 32; m++)
772 for (n = 0; n < 122; n++) {
773 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
774 if ((di = abs(fi - freq)) < d) {
784 if (is_oldclock(par->chip_id)) {
785 lo = best_n | (best_m << 7);
786 hi = (best_m >> 1) | (best_k << 4);
789 hi = best_m | (best_k << 6);
792 if (is3Dchip(par->chip_id)) {
793 vga_mm_wseq(par->io_virt, ClockHigh, hi);
794 vga_mm_wseq(par->io_virt, ClockLow, lo);
796 t_outb(par, lo, 0x43C8);
797 t_outb(par, hi, 0x43C9);
799 debug("VCLK = %X %X\n", hi, lo);
802 /* Set number of lines for flat panels*/
803 static void set_number_of_lines(struct tridentfb_par *par, int lines)
805 int tmp = read3CE(par, CyberEnhance) & 0x8F;
808 else if (lines > 768)
810 else if (lines > 600)
812 else if (lines > 480)
814 write3CE(par, CyberEnhance, tmp);
818 * If we see that FP is active we assume we have one.
819 * Otherwise we have a CRT display. User can override.
821 static int __devinit is_flatpanel(struct tridentfb_par *par)
825 if (crt || !iscyber(par->chip_id))
827 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
830 /* Try detecting the video memory size */
831 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
833 unsigned char tmp, tmp2;
836 /* If memory size provided by user */
840 switch (par->chip_id) {
845 tmp = read3X4(par, SPR) & 0x0F;
861 k = 10 * Mb; /* XP */
867 k = 12 * Mb; /* XP */
870 k = 14 * Mb; /* XP */
873 k = 16 * Mb; /* XP */
877 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
907 output("framebuffer size = %d Kb\n", k / Kb);
911 /* See if we can handle the video mode described in var */
912 static int tridentfb_check_var(struct fb_var_screeninfo *var,
913 struct fb_info *info)
915 struct tridentfb_par *par = info->par;
916 int bpp = var->bits_per_pixel;
918 int ramdac = 230000; /* 230MHz for most 3D chips */
921 /* check color depth */
923 bpp = var->bits_per_pixel = 32;
924 if (par->chip_id == TGUI9440 && bpp == 32)
926 /* check whether resolution fits on panel and in memory */
927 if (par->flatpanel && nativex && var->xres > nativex)
929 /* various resolution checks */
930 var->xres = (var->xres + 7) & ~0x7;
931 if (var->xres != var->xres_virtual)
932 var->xres_virtual = var->xres;
933 line_length = var->xres_virtual * bpp / 8;
934 #ifdef CONFIG_FB_TRIDENT_ACCEL
935 if (!is3Dchip(par->chip_id)) {
936 /* acceleration requires line length to be power of 2 */
937 if (line_length <= 512)
938 var->xres_virtual = 512 * 8 / bpp;
939 else if (line_length <= 1024)
940 var->xres_virtual = 1024 * 8 / bpp;
941 else if (line_length <= 2048)
942 var->xres_virtual = 2048 * 8 / bpp;
943 else if (line_length <= 4096)
944 var->xres_virtual = 4096 * 8 / bpp;
945 else if (line_length <= 8192)
946 var->xres_virtual = 8192 * 8 / bpp;
948 line_length = var->xres_virtual * bpp / 8;
951 if (var->yres > var->yres_virtual)
952 var->yres_virtual = var->yres;
953 if (line_length * var->yres_virtual > info->fix.smem_len)
959 var->green.offset = 0;
960 var->blue.offset = 0;
962 var->green.length = 6;
963 var->blue.length = 6;
966 var->red.offset = 11;
967 var->green.offset = 5;
968 var->blue.offset = 0;
970 var->green.length = 6;
971 var->blue.length = 5;
974 var->red.offset = 16;
975 var->green.offset = 8;
976 var->blue.offset = 0;
978 var->green.length = 8;
979 var->blue.length = 8;
985 if (is_xp(par->chip_id))
988 switch (par->chip_id) {
990 ramdac = (bpp >= 16) ? 45000 : 90000;
1004 /* The clock is doubled for 32 bpp */
1008 if (PICOS2KHZ(var->pixclock) > ramdac)
1017 /* Pan the display */
1018 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
1019 struct fb_info *info)
1021 struct tridentfb_par *par = info->par;
1022 unsigned int offset;
1025 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
1026 * var->bits_per_pixel / 32;
1027 info->var.xoffset = var->xoffset;
1028 info->var.yoffset = var->yoffset;
1029 set_screen_start(par, offset);
1034 static void shadowmode_on(struct tridentfb_par *par)
1036 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1039 static void shadowmode_off(struct tridentfb_par *par)
1041 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1044 /* Set the hardware to the requested video mode */
1045 static int tridentfb_set_par(struct fb_info *info)
1047 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
1048 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1049 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1050 struct fb_var_screeninfo *var = &info->var;
1051 int bpp = var->bits_per_pixel;
1056 hdispend = var->xres / 8 - 1;
1057 hsyncstart = (var->xres + var->right_margin) / 8 - 1;
1058 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1;
1059 htotal = (var->xres + var->left_margin + var->right_margin +
1060 var->hsync_len) / 8 - 5;
1061 hblankstart = hdispend + 1;
1062 hblankend = htotal + 3;
1064 vdispend = var->yres - 1;
1065 vsyncstart = var->yres + var->lower_margin;
1066 vsyncend = vsyncstart + var->vsync_len;
1067 vtotal = var->upper_margin + vsyncend - 2;
1068 vblankstart = vdispend + 1;
1072 write3CE(par, CyberControl, 8);
1074 if (par->flatpanel && var->xres < nativex) {
1076 * on flat panels with native size larger
1077 * than requested resolution decide whether
1078 * we stretch or center
1080 t_outb(par, 0xEB, VGA_MIS_W);
1087 screen_stretch(par);
1090 t_outb(par, 0x2B, VGA_MIS_W);
1091 write3CE(par, CyberControl, 8);
1094 /* vertical timing values */
1095 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1096 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1097 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1098 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1099 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1100 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1102 /* horizontal timing values */
1103 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1104 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1105 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1106 write3X4(par, VGA_CRTC_H_SYNC_END,
1107 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1108 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1109 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1111 /* higher bits of vertical timing values */
1113 if (vtotal & 0x100) tmp |= 0x01;
1114 if (vdispend & 0x100) tmp |= 0x02;
1115 if (vsyncstart & 0x100) tmp |= 0x04;
1116 if (vblankstart & 0x100) tmp |= 0x08;
1118 if (vtotal & 0x200) tmp |= 0x20;
1119 if (vdispend & 0x200) tmp |= 0x40;
1120 if (vsyncstart & 0x200) tmp |= 0x80;
1121 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1123 tmp = read3X4(par, CRTHiOrd) & 0x07;
1124 tmp |= 0x08; /* line compare bit 10 */
1125 if (vtotal & 0x400) tmp |= 0x80;
1126 if (vblankstart & 0x400) tmp |= 0x40;
1127 if (vsyncstart & 0x400) tmp |= 0x20;
1128 if (vdispend & 0x400) tmp |= 0x10;
1129 write3X4(par, CRTHiOrd, tmp);
1131 tmp = (htotal >> 8) & 0x01;
1132 tmp |= (hdispend >> 7) & 0x02;
1133 tmp |= (hsyncstart >> 5) & 0x08;
1134 tmp |= (hblankstart >> 4) & 0x10;
1135 write3X4(par, HorizOverflow, tmp);
1138 if (vblankstart & 0x200) tmp |= 0x20;
1139 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1140 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1142 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1143 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1144 write3X4(par, VGA_CRTC_MODE, 0xC3);
1146 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1148 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1149 /* enable access extended memory */
1150 write3X4(par, CRTCModuleTest, tmp);
1152 /* enable GE for text acceleration */
1153 write3X4(par, GraphEngReg, 0x80);
1155 #ifdef CONFIG_FB_TRIDENT_ACCEL
1156 par->init_accel(par, info->var.xres_virtual, bpp);
1174 write3X4(par, PixelBusReg, tmp);
1176 tmp = read3X4(par, DRAMControl);
1177 if (!is_oldprotect(par->chip_id))
1179 if (iscyber(par->chip_id))
1181 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1183 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1184 if (!is_xp(par->chip_id))
1185 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1186 /* MMIO & PCI read and write burst enable */
1187 if (par->chip_id != TGUI9440)
1188 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1190 vga_mm_wseq(par->io_virt, 0, 3);
1191 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1192 /* enable 4 maps because needed in chain4 mode */
1193 vga_mm_wseq(par->io_virt, 2, 0x0F);
1194 vga_mm_wseq(par->io_virt, 3, 0);
1195 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1197 /* convert from picoseconds to kHz */
1198 vclk = PICOS2KHZ(info->var.pixclock);
1200 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1201 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1202 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1206 set_vclk(par, vclk);
1207 write3CE(par, MiscExtFunc, tmp | 0x12);
1208 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1209 write3CE(par, 0x6, 0x05); /* graphics mode */
1210 write3CE(par, 0x7, 0x0F); /* planes? */
1212 if (par->chip_id == CYBERBLADEXPAi1) {
1213 /* This fixes snow-effect in 32 bpp */
1214 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1217 /* graphics mode and support 256 color modes */
1218 writeAttr(par, 0x10, 0x41);
1219 writeAttr(par, 0x12, 0x0F); /* planes */
1220 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1223 for (tmp = 0; tmp < 0x10; tmp++)
1224 writeAttr(par, tmp, tmp);
1225 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1226 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1244 t_inb(par, VGA_PEL_IW);
1245 t_inb(par, VGA_PEL_MSK);
1246 t_inb(par, VGA_PEL_MSK);
1247 t_inb(par, VGA_PEL_MSK);
1248 t_inb(par, VGA_PEL_MSK);
1249 t_outb(par, tmp, VGA_PEL_MSK);
1250 t_inb(par, VGA_PEL_IW);
1253 set_number_of_lines(par, info->var.yres);
1254 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1255 set_lwidth(par, info->fix.line_length / 8);
1256 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1257 info->cmap.len = (bpp == 8) ? 256 : 16;
1262 /* Set one color register */
1263 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1264 unsigned blue, unsigned transp,
1265 struct fb_info *info)
1267 int bpp = info->var.bits_per_pixel;
1268 struct tridentfb_par *par = info->par;
1270 if (regno >= info->cmap.len)
1274 t_outb(par, 0xFF, VGA_PEL_MSK);
1275 t_outb(par, regno, VGA_PEL_IW);
1277 t_outb(par, red >> 10, VGA_PEL_D);
1278 t_outb(par, green >> 10, VGA_PEL_D);
1279 t_outb(par, blue >> 10, VGA_PEL_D);
1281 } else if (regno < 16) {
1282 if (bpp == 16) { /* RGB 565 */
1285 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1286 ((blue & 0xF800) >> 11);
1288 ((u32 *)(info->pseudo_palette))[regno] = col;
1289 } else if (bpp == 32) /* ARGB 8888 */
1290 ((u32*)info->pseudo_palette)[regno] =
1291 ((transp & 0xFF00) << 16) |
1292 ((red & 0xFF00) << 8) |
1293 ((green & 0xFF00)) |
1294 ((blue & 0xFF00) >> 8);
1297 /* debug("exit\n"); */
1301 /* Try blanking the screen.For flat panels it does nothing */
1302 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1304 unsigned char PMCont, DPMSCont;
1305 struct tridentfb_par *par = info->par;
1310 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1311 PMCont = t_inb(par, 0x83C6) & 0xFC;
1312 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1313 switch (blank_mode) {
1314 case FB_BLANK_UNBLANK:
1315 /* Screen: On, HSync: On, VSync: On */
1316 case FB_BLANK_NORMAL:
1317 /* Screen: Off, HSync: On, VSync: On */
1321 case FB_BLANK_HSYNC_SUSPEND:
1322 /* Screen: Off, HSync: Off, VSync: On */
1326 case FB_BLANK_VSYNC_SUSPEND:
1327 /* Screen: Off, HSync: On, VSync: Off */
1331 case FB_BLANK_POWERDOWN:
1332 /* Screen: Off, HSync: Off, VSync: Off */
1338 write3CE(par, PowerStatus, DPMSCont);
1339 t_outb(par, 4, 0x83C8);
1340 t_outb(par, PMCont, 0x83C6);
1344 /* let fbcon do a softblank for us */
1345 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1348 static struct fb_ops tridentfb_ops = {
1349 .owner = THIS_MODULE,
1350 .fb_setcolreg = tridentfb_setcolreg,
1351 .fb_pan_display = tridentfb_pan_display,
1352 .fb_blank = tridentfb_blank,
1353 .fb_check_var = tridentfb_check_var,
1354 .fb_set_par = tridentfb_set_par,
1355 #ifdef CONFIG_FB_TRIDENT_ACCEL
1356 .fb_fillrect = tridentfb_fillrect,
1357 .fb_copyarea = tridentfb_copyarea,
1358 .fb_imageblit = cfb_imageblit,
1362 static int __devinit trident_pci_probe(struct pci_dev *dev,
1363 const struct pci_device_id *id)
1366 unsigned char revision;
1367 struct fb_info *info;
1368 struct tridentfb_par *default_par;
1373 err = pci_enable_device(dev);
1377 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1380 default_par = info->par;
1382 chip_id = id->device;
1384 if (chip_id == CYBERBLADEi1)
1385 output("*** Please do use cyblafb, Cyberblade/i1 support "
1386 "will soon be removed from tridentfb!\n");
1389 /* If PCI id is 0x9660 then further detect chip type */
1391 if (chip_id == TGUI9660) {
1392 revision = vga_io_rseq(RevisionID);
1396 chip_id = PROVIDIA9685;
1400 chip_id = CYBER9397;
1403 chip_id = CYBER9397DVD;
1412 chip_id = CYBER9385;
1415 chip_id = CYBER9382;
1418 chip_id = CYBER9388;
1425 chip3D = is3Dchip(chip_id);
1427 if (is_xp(chip_id)) {
1428 default_par->init_accel = xp_init_accel;
1429 default_par->wait_engine = xp_wait_engine;
1430 default_par->fill_rect = xp_fill_rect;
1431 default_par->copy_rect = xp_copy_rect;
1432 } else if (is_blade(chip_id)) {
1433 default_par->init_accel = blade_init_accel;
1434 default_par->wait_engine = blade_wait_engine;
1435 default_par->fill_rect = blade_fill_rect;
1436 default_par->copy_rect = blade_copy_rect;
1437 } else if (chip3D) { /* 3DImage family left */
1438 default_par->init_accel = image_init_accel;
1439 default_par->wait_engine = image_wait_engine;
1440 default_par->fill_rect = image_fill_rect;
1441 default_par->copy_rect = image_copy_rect;
1442 } else { /* TGUI 9440/96XX family */
1443 default_par->init_accel = tgui_init_accel;
1444 default_par->wait_engine = xp_wait_engine;
1445 default_par->fill_rect = tgui_fill_rect;
1446 default_par->copy_rect = tgui_copy_rect;
1449 default_par->chip_id = chip_id;
1451 /* acceleration is on by default for 3D chips */
1452 defaultaccel = chip3D && !noaccel;
1454 /* setup MMIO region */
1455 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1456 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1458 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1459 debug("request_region failed!\n");
1460 framebuffer_release(info);
1464 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1465 tridentfb_fix.mmio_len);
1467 if (!default_par->io_virt) {
1468 debug("ioremap failed\n");
1475 /* setup framebuffer memory */
1476 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1477 tridentfb_fix.smem_len = get_memsize(default_par);
1479 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1480 debug("request_mem_region failed!\n");
1481 disable_mmio(info->par);
1486 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1487 tridentfb_fix.smem_len);
1489 if (!info->screen_base) {
1490 debug("ioremap failed\n");
1495 output("%s board found\n", pci_name(dev));
1496 default_par->flatpanel = is_flatpanel(default_par);
1498 if (default_par->flatpanel)
1499 nativex = get_nativex(default_par);
1501 info->fix = tridentfb_fix;
1502 info->fbops = &tridentfb_ops;
1503 info->pseudo_palette = default_par->pseudo_pal;
1505 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1506 #ifdef CONFIG_FB_TRIDENT_ACCEL
1507 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1509 if (!fb_find_mode(&info->var, info,
1510 mode_option, NULL, 0, NULL, bpp)) {
1514 err = fb_alloc_cmap(&info->cmap, 256, 0);
1518 if (defaultaccel && default_par->init_accel)
1519 info->var.accel_flags |= FB_ACCELF_TEXT;
1521 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1522 info->var.activate |= FB_ACTIVATE_NOW;
1523 info->device = &dev->dev;
1524 if (register_framebuffer(info) < 0) {
1525 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1526 fb_dealloc_cmap(&info->cmap);
1530 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1531 info->node, info->fix.id, info->var.xres,
1532 info->var.yres, info->var.bits_per_pixel);
1534 pci_set_drvdata(dev, info);
1538 if (info->screen_base)
1539 iounmap(info->screen_base);
1540 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1541 disable_mmio(info->par);
1543 if (default_par->io_virt)
1544 iounmap(default_par->io_virt);
1545 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1546 framebuffer_release(info);
1550 static void __devexit trident_pci_remove(struct pci_dev *dev)
1552 struct fb_info *info = pci_get_drvdata(dev);
1553 struct tridentfb_par *par = info->par;
1555 unregister_framebuffer(info);
1556 iounmap(par->io_virt);
1557 iounmap(info->screen_base);
1558 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1559 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1560 pci_set_drvdata(dev, NULL);
1561 framebuffer_release(info);
1564 /* List of boards that we are trying to support */
1565 static struct pci_device_id trident_devices[] = {
1566 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1567 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1568 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1569 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1570 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1571 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1574 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1575 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1576 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1577 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1579 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1580 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1581 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1582 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1584 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1585 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1586 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1590 MODULE_DEVICE_TABLE(pci, trident_devices);
1592 static struct pci_driver tridentfb_pci_driver = {
1593 .name = "tridentfb",
1594 .id_table = trident_devices,
1595 .probe = trident_pci_probe,
1596 .remove = __devexit_p(trident_pci_remove)
1600 * Parse user specified options (`video=trident:')
1602 * video=trident:800x600,bpp=16,noaccel
1605 static int __init tridentfb_setup(char *options)
1608 if (!options || !*options)
1610 while ((opt = strsep(&options, ",")) != NULL) {
1613 if (!strncmp(opt, "noaccel", 7))
1615 else if (!strncmp(opt, "fp", 2))
1617 else if (!strncmp(opt, "crt", 3))
1619 else if (!strncmp(opt, "bpp=", 4))
1620 bpp = simple_strtoul(opt + 4, NULL, 0);
1621 else if (!strncmp(opt, "center", 6))
1623 else if (!strncmp(opt, "stretch", 7))
1625 else if (!strncmp(opt, "memsize=", 8))
1626 memsize = simple_strtoul(opt + 8, NULL, 0);
1627 else if (!strncmp(opt, "memdiff=", 8))
1628 memdiff = simple_strtoul(opt + 8, NULL, 0);
1629 else if (!strncmp(opt, "nativex=", 8))
1630 nativex = simple_strtoul(opt + 8, NULL, 0);
1638 static int __init tridentfb_init(void)
1641 char *option = NULL;
1643 if (fb_get_options("tridentfb", &option))
1645 tridentfb_setup(option);
1647 output("Trident framebuffer %s initializing\n", VERSION);
1648 return pci_register_driver(&tridentfb_pci_driver);
1651 static void __exit tridentfb_exit(void)
1653 pci_unregister_driver(&tridentfb_pci_driver);
1656 module_init(tridentfb_init);
1657 module_exit(tridentfb_exit);
1659 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1660 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1661 MODULE_LICENSE("GPL");