2 * Renesas SH-mobile MIPI DSI support
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 * This is free software; you can redistribute it and/or modify
7 * it under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
11 #include <linux/bitmap.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/types.h>
21 #include <linux/module.h>
23 #include <video/mipi_display.h>
24 #include <video/sh_mipi_dsi.h>
25 #include <video/sh_mobile_lcdc.h>
27 #include "sh_mobile_lcdcfb.h"
29 #define SYSCTRL 0x0000
30 #define SYSCONF 0x0004
32 #define RESREQSET0 0x0018
33 #define RESREQSET1 0x001c
34 #define HSTTOVSET 0x0020
35 #define LPRTOVSET 0x0024
36 #define TATOVSET 0x0028
37 #define PRTOVSET 0x002c
38 #define DSICTRL 0x0030
39 #define DSIINTE 0x0060
40 #define PHYCTRL 0x0070
42 /* relative to linkbase */
48 #define CMTSRTREQ 0x0070
49 #define CMTSRTCTR 0x00d0
51 /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
52 #define MAX_SH_MIPI_DSI 2
55 struct sh_mobile_lcdc_entity entity;
58 void __iomem *linkbase;
60 struct platform_device *pdev;
63 #define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
65 static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
67 /* Protect the above array */
68 static DEFINE_MUTEX(array_lock);
70 static struct sh_mipi *sh_mipi_by_handle(int handle)
72 if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
75 return mipi_dsi[handle];
78 static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
81 u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
84 /* transmit a short packet to LCD panel */
85 iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
86 iowrite32(1, mipi->linkbase + CMTSRTREQ);
88 while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
91 return cnt ? 0 : -ETIMEDOUT;
94 #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
97 static int sh_mipi_dcs(int handle, u8 cmd)
99 struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
102 return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
105 static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
107 struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
110 return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
114 static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
117 * enable LCDC data tx, transition to LPS after completion of each HS
120 iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
123 static void sh_mipi_shutdown(struct platform_device *pdev)
125 struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
127 sh_mipi_dsi_enable(mipi, false);
130 static int sh_mipi_setup(struct sh_mipi *mipi, struct sh_mipi_dsi_info *pdata)
132 void __iomem *base = mipi->base;
133 struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
134 u32 pctype, datatype, pixfmt, linelength, vmctr2;
135 u32 tmp, top, bottom, delay, div;
140 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
141 * the default videomode. If this ever becomes a problem, We'll have to
142 * move this to mipi_display_on() above and use info->var.xres
144 switch (pdata->data_format) {
147 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
148 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
149 linelength = ch->lcd_modes[0].xres * 3;
154 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
155 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
156 linelength = ch->lcd_modes[0].xres * 2;
161 datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
162 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
163 linelength = ch->lcd_modes[0].xres * 3;
168 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
169 pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
170 linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
175 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
176 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
177 linelength = ch->lcd_modes[0].xres * 3;
182 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
183 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
184 linelength = ch->lcd_modes[0].xres * 2;
189 datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
190 pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
191 linelength = ch->lcd_modes[0].xres * 3;
196 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
197 pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
198 linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
203 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
204 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
205 linelength = ch->lcd_modes[0].xres * 2;
210 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
211 pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
212 linelength = ch->lcd_modes[0].xres * 2;
217 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
218 pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
219 linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
224 datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
225 pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
226 /* Length of U/V line */
227 linelength = (ch->lcd_modes[0].xres + 1) / 2;
234 if ((yuv && ch->interface_type != YUV422) ||
235 (!yuv && ch->interface_type != RGB24))
242 iowrite32(0x00000001, base + SYSCTRL);
243 /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
245 iowrite32(0x00000000, base + SYSCTRL);
256 iowrite32(0x70003332, base + TIMSET);
257 /* no responses requested */
258 iowrite32(0x00000000, base + RESREQSET0);
259 /* request response to packets of type 0x28 */
260 iowrite32(0x00000100, base + RESREQSET1);
261 /* High-speed transmission timeout, default 0xffffffff */
262 iowrite32(0x0fffffff, base + HSTTOVSET);
263 /* LP reception timeout, default 0xffffffff */
264 iowrite32(0x0fffffff, base + LPRTOVSET);
265 /* Turn-around timeout, default 0xffffffff */
266 iowrite32(0x0fffffff, base + TATOVSET);
267 /* Peripheral reset timeout, default 0xffffffff */
268 iowrite32(0x0fffffff, base + PRTOVSET);
269 /* Interrupts not used, disable all */
270 iowrite32(0, base + DSIINTE);
272 iowrite32(0x00000001, base + PHYCTRL);
274 /* Deassert resets, power on */
275 iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);
278 * Default = ULPS enable |
279 * Contention detection enabled |
280 * EoT packet transmission enable |
284 bitmap_fill((unsigned long *)&tmp, pdata->lane);
286 iowrite32(tmp, base + SYSCONF);
291 * Enable transmission of all packets,
292 * transmit LPS after each HS packet completion
294 iowrite32(0x00000006, mipi->linkbase + DTCTR);
295 /* VSYNC width = 2 (<< 17) */
296 iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) |
297 (pdata->clksrc << 16) | (pctype << 12) | datatype,
298 mipi->linkbase + VMCTR1);
301 * Non-burst mode with sync pulses: VSE and HSE are output,
302 * HSA period allowed, no commands in LP
305 if (pdata->flags & SH_MIPI_DSI_VSEE)
307 if (pdata->flags & SH_MIPI_DSI_HSEE)
309 if (pdata->flags & SH_MIPI_DSI_HSAE)
311 if (pdata->flags & SH_MIPI_DSI_BL2E)
313 if (pdata->flags & SH_MIPI_DSI_HSABM)
315 if (pdata->flags & SH_MIPI_DSI_HBPBM)
317 if (pdata->flags & SH_MIPI_DSI_HFPBM)
319 iowrite32(vmctr2, mipi->linkbase + VMCTR2);
322 * VMLEN1 = RGBLEN | HSALEN
325 * Video mode - Blanking Packet setting
327 top = linelength << 16; /* RGBLEN */
329 if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
330 bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
331 iowrite32(top | bottom , mipi->linkbase + VMLEN1);
334 * VMLEN2 = HBPLEN | HFPLEN
337 * Video mode - Blanking Packet setting
343 div = 1; /* HSbyteCLK is calculation base
344 * HS4divCLK = HSbyteCLK/2
345 * HS6divCLK is not supported for now */
346 if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
349 if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
350 top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
351 top = ((pdata->lane * top / div) - 10) << 16;
353 if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
354 bottom = ch->lcd_modes[0].right_margin;
355 bottom = (pdata->lane * bottom / div) - 12;
358 bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
359 if ((pdata->lane / div) > bpp) {
360 tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
361 tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
362 delay = (pdata->lane * tmp);
365 iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);
369 /* setup LCD panel */
371 /* cf. drivers/video/omap/lcd_mipid.c */
372 sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
375 * [7] - Page Address Mode
376 * [6] - Column Address Mode
377 * [5] - Page / Column Address Mode
378 * [4] - Display Device Line Refresh Order
379 * [3] - RGB/BGR Order
380 * [2] - Display Data Latch Data Order
381 * [1] - Flip Horizontal
382 * [0] - Flip Vertical
384 sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
385 /* cf. set_data_lines() */
386 sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
388 sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
390 /* Enable timeout counters */
391 iowrite32(0x00000f00, base + DSICTRL);
396 static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
398 struct sh_mipi *mipi = to_sh_mipi(entity);
399 struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
402 pm_runtime_get_sync(&mipi->pdev->dev);
404 ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
406 goto mipi_display_on_fail1;
408 ret = sh_mipi_setup(mipi, pdata);
410 goto mipi_display_on_fail2;
412 sh_mipi_dsi_enable(mipi, true);
414 return SH_MOBILE_LCDC_DISPLAY_CONNECTED;
416 mipi_display_on_fail1:
417 pm_runtime_put_sync(&mipi->pdev->dev);
418 mipi_display_on_fail2:
419 pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
424 static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
426 struct sh_mipi *mipi = to_sh_mipi(entity);
427 struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
429 sh_mipi_dsi_enable(mipi, false);
431 pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
433 pm_runtime_put_sync(&mipi->pdev->dev);
436 static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
437 .display_on = mipi_display_on,
438 .display_off = mipi_display_off,
441 static int __init sh_mipi_probe(struct platform_device *pdev)
443 struct sh_mipi *mipi;
444 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
445 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
447 unsigned long rate, f_current;
448 int idx = pdev->id, ret;
450 if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
453 if (!pdata->set_dot_clock)
456 mutex_lock(&array_lock);
458 for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
461 if (idx == ARRAY_SIZE(mipi_dsi)) {
466 mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
472 mipi->entity.owner = THIS_MODULE;
473 mipi->entity.ops = &mipi_ops;
475 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
476 dev_err(&pdev->dev, "MIPI register region already claimed\n");
481 mipi->base = ioremap(res->start, resource_size(res));
487 if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
488 dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
493 mipi->linkbase = ioremap(res2->start, resource_size(res2));
494 if (!mipi->linkbase) {
501 mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
502 if (IS_ERR(mipi->dsit_clk)) {
503 ret = PTR_ERR(mipi->dsit_clk);
507 f_current = clk_get_rate(mipi->dsit_clk);
508 /* 80MHz required by the datasheet */
509 rate = clk_round_rate(mipi->dsit_clk, 80000000);
510 if (rate > 0 && rate != f_current)
511 ret = clk_set_rate(mipi->dsit_clk, rate);
517 dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
519 ret = clk_enable(mipi->dsit_clk);
523 mipi_dsi[idx] = mipi;
525 pm_runtime_enable(&pdev->dev);
526 pm_runtime_resume(&pdev->dev);
528 mutex_unlock(&array_lock);
529 platform_set_drvdata(pdev, &mipi->entity);
535 clk_put(mipi->dsit_clk);
537 iounmap(mipi->linkbase);
539 release_mem_region(res2->start, resource_size(res2));
543 release_mem_region(res->start, resource_size(res));
548 mutex_unlock(&array_lock);
553 static int __devexit sh_mipi_remove(struct platform_device *pdev)
555 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
556 struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
557 struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
560 mutex_lock(&array_lock);
562 for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
565 if (i == ARRAY_SIZE(mipi_dsi)) {
572 mutex_unlock(&array_lock);
577 pm_runtime_disable(&pdev->dev);
578 clk_disable(mipi->dsit_clk);
579 clk_put(mipi->dsit_clk);
581 iounmap(mipi->linkbase);
583 release_mem_region(res2->start, resource_size(res2));
586 release_mem_region(res->start, resource_size(res));
587 platform_set_drvdata(pdev, NULL);
593 static struct platform_driver sh_mipi_driver = {
594 .remove = __devexit_p(sh_mipi_remove),
595 .shutdown = sh_mipi_shutdown,
597 .name = "sh-mipi-dsi",
601 static int __init sh_mipi_init(void)
603 return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
605 module_init(sh_mipi_init);
607 static void __exit sh_mipi_exit(void)
609 platform_driver_unregister(&sh_mipi_driver);
611 module_exit(sh_mipi_exit);
613 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
614 MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
615 MODULE_LICENSE("GPL v2");