1 /* linux/drivers/video/s3c-fb.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * Samsung SoC Framebuffer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software FoundatIon.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
26 #include <linux/pm_runtime.h>
29 #include <plat/regs-fb-v4.h>
32 /* This driver will export a number of framebuffer interfaces depending
33 * on the configuration passed in via the platform data. Each fb instance
34 * maps to a hardware window. Currently there is no support for runtime
35 * setting of the alpha-blending functions that each window has, so only
36 * window 0 is actually useful.
38 * Window 0 is treated specially, it is used for the basis of the LCD
39 * output timings and as the control for the output power-down state.
42 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
43 * has been replaced by using the platform device name to pick the correct
44 * configuration data for the system.
47 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
49 #define writel(v, r) do { \
50 printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
51 __raw_writel(v, r); } while (0)
52 #endif /* FB_S3C_DEBUG_REGWRITE */
55 #define S3C_FB_VSYNC_IRQ_EN 0
57 #define VSYNC_TIMEOUT_MSEC 50
61 #define VALID_BPP(x) (1 << ((x) - 1))
63 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
64 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
65 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
66 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
67 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
70 * struct s3c_fb_variant - fb variant information
71 * @is_2443: Set if S3C2443/S3C2416 style hardware.
72 * @nr_windows: The number of windows.
73 * @vidtcon: The base for the VIDTCONx registers
74 * @wincon: The base for the WINxCON registers.
75 * @winmap: The base for the WINxMAP registers.
76 * @keycon: The abse for the WxKEYCON registers.
77 * @buf_start: Offset of buffer start registers.
78 * @buf_size: Offset of buffer size registers.
79 * @buf_end: Offset of buffer end registers.
80 * @osd: The base for the OSD registers.
81 * @palette: Address of palette memory, or 0 if none.
82 * @has_prtcon: Set if has PRTCON register.
83 * @has_shadowcon: Set if has SHADOWCON register.
84 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
86 struct s3c_fb_variant {
87 unsigned int is_2443:1;
88 unsigned short nr_windows;
89 unsigned short vidtcon;
90 unsigned short wincon;
91 unsigned short winmap;
92 unsigned short keycon;
93 unsigned short buf_start;
94 unsigned short buf_end;
95 unsigned short buf_size;
97 unsigned short osd_stride;
98 unsigned short palette[S3C_FB_MAX_WIN];
100 unsigned int has_prtcon:1;
101 unsigned int has_shadowcon:1;
102 unsigned int has_clksel:1;
106 * struct s3c_fb_win_variant
107 * @has_osd_c: Set if has OSD C register.
108 * @has_osd_d: Set if has OSD D register.
109 * @has_osd_alpha: Set if can change alpha transparency for a window.
110 * @palette_sz: Size of palette in entries.
111 * @palette_16bpp: Set if palette is 16bits wide.
112 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
113 * register is located at the given offset from OSD_BASE.
114 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
116 * valid_bpp bit x is set if (x+1)BPP is supported.
118 struct s3c_fb_win_variant {
119 unsigned int has_osd_c:1;
120 unsigned int has_osd_d:1;
121 unsigned int has_osd_alpha:1;
122 unsigned int palette_16bpp:1;
123 unsigned short osd_size_off;
124 unsigned short palette_sz;
129 * struct s3c_fb_driverdata - per-device type driver data for init time.
130 * @variant: The variant information for this driver.
131 * @win: The window information for each window.
133 struct s3c_fb_driverdata {
134 struct s3c_fb_variant variant;
135 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
139 * struct s3c_fb_palette - palette information
141 * @g: Green bitfield.
143 * @a: Alpha bitfield.
145 struct s3c_fb_palette {
146 struct fb_bitfield r;
147 struct fb_bitfield g;
148 struct fb_bitfield b;
149 struct fb_bitfield a;
153 * struct s3c_fb_win - per window private data for each framebuffer.
154 * @windata: The platform data supplied for the window configuration.
155 * @parent: The hardware that this window is part of.
156 * @fbinfo: Pointer pack to the framebuffer info for this window.
157 * @varint: The variant information for this window.
158 * @palette_buffer: Buffer/cache to hold palette entries.
159 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
160 * @index: The window number of this window.
161 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
164 struct s3c_fb_pd_win *windata;
165 struct s3c_fb *parent;
166 struct fb_info *fbinfo;
167 struct s3c_fb_palette palette;
168 struct s3c_fb_win_variant variant;
171 u32 pseudo_palette[16];
176 * struct s3c_fb_vsync - vsync information
177 * @wait: a queue for processes waiting for vsync
178 * @count: vsync interrupt count
180 struct s3c_fb_vsync {
181 wait_queue_head_t wait;
186 * struct s3c_fb - overall hardware state of the hardware
187 * @slock: The spinlock protection for this data sturcture.
188 * @dev: The device that we bound to, for printing, etc.
189 * @regs_res: The resource we claimed for the IO registers.
190 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
191 * @lcd_clk: The clk (sclk) feeding pixclk.
192 * @regs: The mapped hardware registers.
193 * @variant: Variant information for this hardware.
194 * @enabled: A bitmask of enabled hardware windows.
195 * @pdata: The platform configuration data passed with the device.
196 * @windows: The hardware windows that have been claimed.
197 * @irq_no: IRQ line number
198 * @irq_flags: irq flags
199 * @vsync_info: VSYNC-related information (count, queues...)
204 struct resource *regs_res;
208 struct s3c_fb_variant variant;
210 unsigned char enabled;
212 struct s3c_fb_platdata *pdata;
213 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
216 unsigned long irq_flags;
217 struct s3c_fb_vsync vsync_info;
221 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
222 * @win: The device window.
223 * @bpp: The bit depth.
225 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
227 return win->variant.valid_bpp & VALID_BPP(bpp);
231 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
232 * @var: The screen information to verify.
233 * @info: The framebuffer device.
235 * Framebuffer layer call to verify the given information and allow us to
236 * update various information depending on the hardware capabilities.
238 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
239 struct fb_info *info)
241 struct s3c_fb_win *win = info->par;
242 struct s3c_fb *sfb = win->parent;
244 dev_dbg(sfb->dev, "checking parameters\n");
246 var->xres_virtual = max(var->xres_virtual, var->xres);
247 var->yres_virtual = max(var->yres_virtual, var->yres);
249 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
250 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
251 win->index, var->bits_per_pixel);
255 /* always ensure these are zero, for drop through cases below */
256 var->transp.offset = 0;
257 var->transp.length = 0;
259 switch (var->bits_per_pixel) {
264 if (sfb->variant.palette[win->index] != 0) {
265 /* non palletised, A:1,R:2,G:3,B:2 mode */
267 var->green.offset = 2;
268 var->blue.offset = 0;
270 var->green.length = 3;
271 var->blue.length = 2;
272 var->transp.offset = 7;
273 var->transp.length = 1;
276 var->red.length = var->bits_per_pixel;
277 var->green = var->red;
278 var->blue = var->red;
283 /* 666 with one bit alpha/transparency */
284 var->transp.offset = 18;
285 var->transp.length = 1;
287 var->bits_per_pixel = 32;
290 var->red.offset = 12;
291 var->green.offset = 6;
292 var->blue.offset = 0;
294 var->green.length = 6;
295 var->blue.length = 6;
299 /* 16 bpp, 565 format */
300 var->red.offset = 11;
301 var->green.offset = 5;
302 var->blue.offset = 0;
304 var->green.length = 6;
305 var->blue.length = 5;
311 var->transp.length = var->bits_per_pixel - 24;
312 var->transp.offset = 24;
315 /* our 24bpp is unpacked, so 32bpp */
316 var->bits_per_pixel = 32;
317 var->red.offset = 16;
319 var->green.offset = 8;
320 var->green.length = 8;
321 var->blue.offset = 0;
322 var->blue.length = 8;
326 dev_err(sfb->dev, "invalid bpp\n");
329 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
334 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
335 * @sfb: The hardware state.
336 * @pixclock: The pixel clock wanted, in picoseconds.
338 * Given the specified pixel clock, work out the necessary divider to get
339 * close to the output frequency.
341 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
344 unsigned long long tmp;
347 if (sfb->variant.has_clksel)
348 clk = clk_get_rate(sfb->bus_clk);
350 clk = clk_get_rate(sfb->lcd_clk);
352 tmp = (unsigned long long)clk;
355 do_div(tmp, 1000000000UL);
356 result = (unsigned int)tmp / 1000;
358 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
359 pixclk, clk, result, clk / result);
365 * s3c_fb_align_word() - align pixel count to word boundary
366 * @bpp: The number of bits per pixel
367 * @pix: The value to be aligned.
369 * Align the given pixel count so that it will start on an 32bit word
372 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
379 pix_per_word = (8 * 32) / bpp;
380 return ALIGN(pix, pix_per_word);
384 * vidosd_set_size() - set OSD size for a window
386 * @win: the window to set OSD size for
387 * @size: OSD size register value
389 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
391 struct s3c_fb *sfb = win->parent;
393 /* OSD can be set up if osd_size_off != 0 for this window */
394 if (win->variant.osd_size_off)
395 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
396 + win->variant.osd_size_off);
400 * vidosd_set_alpha() - set alpha transparency for a window
402 * @win: the window to set OSD size for
403 * @alpha: alpha register value
405 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
407 struct s3c_fb *sfb = win->parent;
409 if (win->variant.has_osd_alpha)
410 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
414 * shadow_protect_win() - disable updating values from shadow registers at vsync
416 * @win: window to protect registers for
417 * @protect: 1 to protect (disable updates)
419 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
421 struct s3c_fb *sfb = win->parent;
425 if (sfb->variant.has_prtcon) {
426 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
427 } else if (sfb->variant.has_shadowcon) {
428 reg = readl(sfb->regs + SHADOWCON);
429 writel(reg | SHADOWCON_WINx_PROTECT(win->index),
430 sfb->regs + SHADOWCON);
433 if (sfb->variant.has_prtcon) {
434 writel(0, sfb->regs + PRTCON);
435 } else if (sfb->variant.has_shadowcon) {
436 reg = readl(sfb->regs + SHADOWCON);
437 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
438 sfb->regs + SHADOWCON);
444 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
445 * @info: The framebuffer to change.
447 * Framebuffer layer request to set a new mode for the specified framebuffer
449 static int s3c_fb_set_par(struct fb_info *info)
451 struct fb_var_screeninfo *var = &info->var;
452 struct s3c_fb_win *win = info->par;
453 struct s3c_fb *sfb = win->parent;
454 void __iomem *regs = sfb->regs;
455 void __iomem *buf = regs;
456 int win_no = win->index;
462 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
464 shadow_protect_win(win, 1);
466 switch (var->bits_per_pixel) {
471 info->fix.visual = FB_VISUAL_TRUECOLOR;
474 if (win->variant.palette_sz >= 256)
475 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
477 info->fix.visual = FB_VISUAL_TRUECOLOR;
480 info->fix.visual = FB_VISUAL_MONO01;
483 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
487 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
489 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
490 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
492 /* disable the window whilst we update it */
493 writel(0, regs + WINCON(win_no));
495 /* use platform specified window as the basis for the lcd timings */
497 if (win_no == sfb->pdata->default_win) {
498 clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
500 data = sfb->pdata->vidcon0;
501 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
504 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
506 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
508 /* write the timing data to the panel */
510 if (sfb->variant.is_2443)
513 data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
514 writel(data, regs + VIDCON0);
516 data = VIDTCON0_VBPD(var->upper_margin - 1) |
517 VIDTCON0_VFPD(var->lower_margin - 1) |
518 VIDTCON0_VSPW(var->vsync_len - 1);
520 writel(data, regs + sfb->variant.vidtcon);
522 data = VIDTCON1_HBPD(var->left_margin - 1) |
523 VIDTCON1_HFPD(var->right_margin - 1) |
524 VIDTCON1_HSPW(var->hsync_len - 1);
527 writel(data, regs + sfb->variant.vidtcon + 4);
529 data = VIDTCON2_LINEVAL(var->yres - 1) |
530 VIDTCON2_HOZVAL(var->xres - 1);
531 writel(data, regs + sfb->variant.vidtcon + 8);
534 /* write the buffer address */
536 /* start and end registers stride is 8 */
537 buf = regs + win_no * 8;
539 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
541 data = info->fix.smem_start + info->fix.line_length * var->yres;
542 writel(data, buf + sfb->variant.buf_end);
544 pagewidth = (var->xres * var->bits_per_pixel) >> 3;
545 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
546 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
547 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
549 /* write 'OSD' registers to control position of framebuffer */
551 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
552 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
554 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
556 VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
558 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
560 data = var->xres * var->yres;
562 alpha = VIDISD14C_ALPHA1_R(0xf) |
563 VIDISD14C_ALPHA1_G(0xf) |
564 VIDISD14C_ALPHA1_B(0xf);
566 vidosd_set_alpha(win, alpha);
567 vidosd_set_size(win, data);
569 /* Enable DMA channel for this window */
570 if (sfb->variant.has_shadowcon) {
571 data = readl(sfb->regs + SHADOWCON);
572 data |= SHADOWCON_CHx_ENABLE(win_no);
573 writel(data, sfb->regs + SHADOWCON);
576 data = WINCONx_ENWIN;
577 sfb->enabled |= (1 << win->index);
579 /* note, since we have to round up the bits-per-pixel, we end up
580 * relying on the bitfield information for r/g/b/a to work out
581 * exactly which mode of operation is intended. */
583 switch (var->bits_per_pixel) {
585 data |= WINCON0_BPPMODE_1BPP;
586 data |= WINCONx_BITSWP;
587 data |= WINCONx_BURSTLEN_4WORD;
590 data |= WINCON0_BPPMODE_2BPP;
591 data |= WINCONx_BITSWP;
592 data |= WINCONx_BURSTLEN_8WORD;
595 data |= WINCON0_BPPMODE_4BPP;
596 data |= WINCONx_BITSWP;
597 data |= WINCONx_BURSTLEN_8WORD;
600 if (var->transp.length != 0)
601 data |= WINCON1_BPPMODE_8BPP_1232;
603 data |= WINCON0_BPPMODE_8BPP_PALETTE;
604 data |= WINCONx_BURSTLEN_8WORD;
605 data |= WINCONx_BYTSWP;
608 if (var->transp.length != 0)
609 data |= WINCON1_BPPMODE_16BPP_A1555;
611 data |= WINCON0_BPPMODE_16BPP_565;
612 data |= WINCONx_HAWSWP;
613 data |= WINCONx_BURSTLEN_16WORD;
617 if (var->red.length == 6) {
618 if (var->transp.length != 0)
619 data |= WINCON1_BPPMODE_19BPP_A1666;
621 data |= WINCON1_BPPMODE_18BPP_666;
622 } else if (var->transp.length == 1)
623 data |= WINCON1_BPPMODE_25BPP_A1888
625 else if ((var->transp.length == 4) ||
626 (var->transp.length == 8))
627 data |= WINCON1_BPPMODE_28BPP_A4888
628 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
630 data |= WINCON0_BPPMODE_24BPP_888;
632 data |= WINCONx_WSWP;
633 data |= WINCONx_BURSTLEN_16WORD;
637 /* Enable the colour keying for the window below this one */
639 u32 keycon0_data = 0, keycon1_data = 0;
640 void __iomem *keycon = regs + sfb->variant.keycon;
642 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
644 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
646 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
648 keycon += (win_no - 1) * 8;
650 writel(keycon0_data, keycon + WKEYCON0);
651 writel(keycon1_data, keycon + WKEYCON1);
654 writel(data, regs + sfb->variant.wincon + (win_no * 4));
655 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
657 shadow_protect_win(win, 0);
663 * s3c_fb_update_palette() - set or schedule a palette update.
664 * @sfb: The hardware information.
665 * @win: The window being updated.
666 * @reg: The palette index being changed.
667 * @value: The computed palette value.
669 * Change the value of a palette register, either by directly writing to
670 * the palette (this requires the palette RAM to be disconnected from the
671 * hardware whilst this is in progress) or schedule the update for later.
673 * At the moment, since we have no VSYNC interrupt support, we simply set
674 * the palette entry directly.
676 static void s3c_fb_update_palette(struct s3c_fb *sfb,
677 struct s3c_fb_win *win,
681 void __iomem *palreg;
684 palreg = sfb->regs + sfb->variant.palette[win->index];
686 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
687 __func__, win->index, reg, palreg, value);
689 win->palette_buffer[reg] = value;
691 palcon = readl(sfb->regs + WPALCON);
692 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
694 if (win->variant.palette_16bpp)
695 writew(value, palreg + (reg * 2));
697 writel(value, palreg + (reg * 4));
699 writel(palcon, sfb->regs + WPALCON);
702 static inline unsigned int chan_to_field(unsigned int chan,
703 struct fb_bitfield *bf)
706 chan >>= 16 - bf->length;
707 return chan << bf->offset;
711 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
712 * @regno: The palette index to change.
713 * @red: The red field for the palette data.
714 * @green: The green field for the palette data.
715 * @blue: The blue field for the palette data.
716 * @trans: The transparency (alpha) field for the palette data.
717 * @info: The framebuffer being changed.
719 static int s3c_fb_setcolreg(unsigned regno,
720 unsigned red, unsigned green, unsigned blue,
721 unsigned transp, struct fb_info *info)
723 struct s3c_fb_win *win = info->par;
724 struct s3c_fb *sfb = win->parent;
727 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
728 __func__, win->index, regno, red, green, blue);
730 switch (info->fix.visual) {
731 case FB_VISUAL_TRUECOLOR:
732 /* true-colour, use pseudo-palette */
735 u32 *pal = info->pseudo_palette;
737 val = chan_to_field(red, &info->var.red);
738 val |= chan_to_field(green, &info->var.green);
739 val |= chan_to_field(blue, &info->var.blue);
745 case FB_VISUAL_PSEUDOCOLOR:
746 if (regno < win->variant.palette_sz) {
747 val = chan_to_field(red, &win->palette.r);
748 val |= chan_to_field(green, &win->palette.g);
749 val |= chan_to_field(blue, &win->palette.b);
751 s3c_fb_update_palette(sfb, win, regno, val);
757 return 1; /* unknown type */
764 * s3c_fb_enable() - Set the state of the main LCD output
765 * @sfb: The main framebuffer state.
766 * @enable: The state to set.
768 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
770 u32 vidcon0 = readl(sfb->regs + VIDCON0);
773 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
775 /* see the note in the framebuffer datasheet about
776 * why you cannot take both of these bits down at the
779 if (!(vidcon0 & VIDCON0_ENVID))
782 vidcon0 |= VIDCON0_ENVID;
783 vidcon0 &= ~VIDCON0_ENVID_F;
786 writel(vidcon0, sfb->regs + VIDCON0);
790 * s3c_fb_blank() - blank or unblank the given window
791 * @blank_mode: The blank state from FB_BLANK_*
792 * @info: The framebuffer to blank.
794 * Framebuffer layer request to change the power state.
796 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
798 struct s3c_fb_win *win = info->par;
799 struct s3c_fb *sfb = win->parent;
800 unsigned int index = win->index;
803 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
805 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
807 switch (blank_mode) {
808 case FB_BLANK_POWERDOWN:
809 wincon &= ~WINCONx_ENWIN;
810 sfb->enabled &= ~(1 << index);
811 /* fall through to FB_BLANK_NORMAL */
813 case FB_BLANK_NORMAL:
814 /* disable the DMA and display 0x0 (black) */
815 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
816 sfb->regs + sfb->variant.winmap + (index * 4));
819 case FB_BLANK_UNBLANK:
820 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
821 wincon |= WINCONx_ENWIN;
822 sfb->enabled |= (1 << index);
825 case FB_BLANK_VSYNC_SUSPEND:
826 case FB_BLANK_HSYNC_SUSPEND:
831 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
833 /* Check the enabled state to see if we need to be running the
834 * main LCD interface, as if there are no active windows then
835 * it is highly likely that we also do not need to output
839 /* We could do something like the following code, but the current
840 * system of using framebuffer events means that we cannot make
841 * the distinction between just window 0 being inactive and all
842 * the windows being down.
844 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
847 /* we're stuck with this until we can do something about overriding
848 * the power control using the blanking event for a single fb.
850 if (index == sfb->pdata->default_win)
851 s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
857 * s3c_fb_pan_display() - Pan the display.
859 * Note that the offsets can be written to the device at any time, as their
860 * values are latched at each vsync automatically. This also means that only
861 * the last call to this function will have any effect on next vsync, but
862 * there is no need to sleep waiting for it to prevent tearing.
864 * @var: The screen information to verify.
865 * @info: The framebuffer device.
867 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
868 struct fb_info *info)
870 struct s3c_fb_win *win = info->par;
871 struct s3c_fb *sfb = win->parent;
872 void __iomem *buf = sfb->regs + win->index * 8;
873 unsigned int start_boff, end_boff;
875 /* Offset in bytes to the start of the displayed area */
876 start_boff = var->yoffset * info->fix.line_length;
877 /* X offset depends on the current bpp */
878 if (info->var.bits_per_pixel >= 8) {
879 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
881 switch (info->var.bits_per_pixel) {
883 start_boff += var->xoffset >> 1;
886 start_boff += var->xoffset >> 2;
889 start_boff += var->xoffset >> 3;
892 dev_err(sfb->dev, "invalid bpp\n");
896 /* Offset in bytes to the end of the displayed area */
897 end_boff = start_boff + info->var.yres * info->fix.line_length;
899 /* Temporarily turn off per-vsync update from shadow registers until
900 * both start and end addresses are updated to prevent corruption */
901 shadow_protect_win(win, 1);
903 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
904 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
906 shadow_protect_win(win, 0);
912 * s3c_fb_enable_irq() - enable framebuffer interrupts
913 * @sfb: main hardware state
915 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
917 void __iomem *regs = sfb->regs;
920 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
921 /* IRQ disabled, enable it */
922 irq_ctrl_reg = readl(regs + VIDINTCON0);
924 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
925 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
927 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
928 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
929 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
930 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
932 writel(irq_ctrl_reg, regs + VIDINTCON0);
937 * s3c_fb_disable_irq() - disable framebuffer interrupts
938 * @sfb: main hardware state
940 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
942 void __iomem *regs = sfb->regs;
945 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
946 /* IRQ enabled, disable it */
947 irq_ctrl_reg = readl(regs + VIDINTCON0);
949 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
950 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
952 writel(irq_ctrl_reg, regs + VIDINTCON0);
956 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
958 struct s3c_fb *sfb = dev_id;
959 void __iomem *regs = sfb->regs;
962 spin_lock(&sfb->slock);
964 irq_sts_reg = readl(regs + VIDINTCON1);
966 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
968 /* VSYNC interrupt, accept it */
969 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
971 sfb->vsync_info.count++;
972 wake_up_interruptible(&sfb->vsync_info.wait);
975 /* We only support waiting for VSYNC for now, so it's safe
976 * to always disable irqs here.
978 s3c_fb_disable_irq(sfb);
980 spin_unlock(&sfb->slock);
985 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
986 * @sfb: main hardware state
989 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
997 count = sfb->vsync_info.count;
998 s3c_fb_enable_irq(sfb);
999 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1000 count != sfb->vsync_info.count,
1001 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1008 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1011 struct s3c_fb_win *win = info->par;
1012 struct s3c_fb *sfb = win->parent;
1017 case FBIO_WAITFORVSYNC:
1018 if (get_user(crtc, (u32 __user *)arg)) {
1023 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1032 static struct fb_ops s3c_fb_ops = {
1033 .owner = THIS_MODULE,
1034 .fb_check_var = s3c_fb_check_var,
1035 .fb_set_par = s3c_fb_set_par,
1036 .fb_blank = s3c_fb_blank,
1037 .fb_setcolreg = s3c_fb_setcolreg,
1038 .fb_fillrect = cfb_fillrect,
1039 .fb_copyarea = cfb_copyarea,
1040 .fb_imageblit = cfb_imageblit,
1041 .fb_pan_display = s3c_fb_pan_display,
1042 .fb_ioctl = s3c_fb_ioctl,
1046 * s3c_fb_missing_pixclock() - calculates pixel clock
1047 * @mode: The video mode to change.
1049 * Calculate the pixel clock when none has been given through platform data.
1051 static void __devinit s3c_fb_missing_pixclock(struct fb_videomode *mode)
1053 u64 pixclk = 1000000000000ULL;
1056 div = mode->left_margin + mode->hsync_len + mode->right_margin +
1058 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1060 div *= mode->refresh ? : 60;
1062 do_div(pixclk, div);
1064 mode->pixclock = pixclk;
1068 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1069 * @sfb: The base resources for the hardware.
1070 * @win: The window to initialise memory for.
1072 * Allocate memory for the given framebuffer.
1074 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1075 struct s3c_fb_win *win)
1077 struct s3c_fb_pd_win *windata = win->windata;
1078 unsigned int real_size, virt_size, size;
1079 struct fb_info *fbi = win->fbinfo;
1082 dev_dbg(sfb->dev, "allocating memory for display\n");
1084 real_size = windata->win_mode.xres * windata->win_mode.yres;
1085 virt_size = windata->virtual_x * windata->virtual_y;
1087 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1088 real_size, windata->win_mode.xres, windata->win_mode.yres,
1089 virt_size, windata->virtual_x, windata->virtual_y);
1091 size = (real_size > virt_size) ? real_size : virt_size;
1092 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1095 fbi->fix.smem_len = size;
1096 size = PAGE_ALIGN(size);
1098 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1100 fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1101 &map_dma, GFP_KERNEL);
1102 if (!fbi->screen_base)
1105 dev_dbg(sfb->dev, "mapped %x to %p\n",
1106 (unsigned int)map_dma, fbi->screen_base);
1108 memset(fbi->screen_base, 0x0, size);
1109 fbi->fix.smem_start = map_dma;
1115 * s3c_fb_free_memory() - free the display memory for the given window
1116 * @sfb: The base resources for the hardware.
1117 * @win: The window to free the display memory for.
1119 * Free the display memory allocated by s3c_fb_alloc_memory().
1121 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1123 struct fb_info *fbi = win->fbinfo;
1125 if (fbi->screen_base)
1126 dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1127 fbi->screen_base, fbi->fix.smem_start);
1131 * s3c_fb_release_win() - release resources for a framebuffer window.
1132 * @win: The window to cleanup the resources for.
1134 * Release the resources that where claimed for the hardware window,
1135 * such as the framebuffer instance and any memory claimed for it.
1137 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1142 if (sfb->variant.has_shadowcon) {
1143 data = readl(sfb->regs + SHADOWCON);
1144 data &= ~SHADOWCON_CHx_ENABLE(win->index);
1145 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1146 writel(data, sfb->regs + SHADOWCON);
1148 unregister_framebuffer(win->fbinfo);
1149 if (win->fbinfo->cmap.len)
1150 fb_dealloc_cmap(&win->fbinfo->cmap);
1151 s3c_fb_free_memory(sfb, win);
1152 framebuffer_release(win->fbinfo);
1157 * s3c_fb_probe_win() - register an hardware window
1158 * @sfb: The base resources for the hardware
1159 * @variant: The variant information for this window.
1160 * @res: Pointer to where to place the resultant window.
1162 * Allocate and do the basic initialisation for one of the hardware's graphics
1165 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1166 struct s3c_fb_win_variant *variant,
1167 struct s3c_fb_win **res)
1169 struct fb_var_screeninfo *var;
1170 struct fb_videomode *initmode;
1171 struct s3c_fb_pd_win *windata;
1172 struct s3c_fb_win *win;
1173 struct fb_info *fbinfo;
1177 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1179 init_waitqueue_head(&sfb->vsync_info.wait);
1181 palette_size = variant->palette_sz * 4;
1183 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1184 palette_size * sizeof(u32), sfb->dev);
1186 dev_err(sfb->dev, "failed to allocate framebuffer\n");
1190 windata = sfb->pdata->win[win_no];
1191 initmode = &windata->win_mode;
1193 WARN_ON(windata->max_bpp == 0);
1194 WARN_ON(windata->win_mode.xres == 0);
1195 WARN_ON(windata->win_mode.yres == 0);
1200 win->variant = *variant;
1201 win->fbinfo = fbinfo;
1203 win->windata = windata;
1204 win->index = win_no;
1205 win->palette_buffer = (u32 *)(win + 1);
1207 ret = s3c_fb_alloc_memory(sfb, win);
1209 dev_err(sfb->dev, "failed to allocate display memory\n");
1213 /* setup the r/b/g positions for the window's palette */
1214 if (win->variant.palette_16bpp) {
1215 /* Set RGB 5:6:5 as default */
1216 win->palette.r.offset = 11;
1217 win->palette.r.length = 5;
1218 win->palette.g.offset = 5;
1219 win->palette.g.length = 6;
1220 win->palette.b.offset = 0;
1221 win->palette.b.length = 5;
1224 /* Set 8bpp or 8bpp and 1bit alpha */
1225 win->palette.r.offset = 16;
1226 win->palette.r.length = 8;
1227 win->palette.g.offset = 8;
1228 win->palette.g.length = 8;
1229 win->palette.b.offset = 0;
1230 win->palette.b.length = 8;
1233 /* setup the initial video mode from the window */
1234 fb_videomode_to_var(&fbinfo->var, initmode);
1236 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1237 fbinfo->fix.accel = FB_ACCEL_NONE;
1238 fbinfo->var.activate = FB_ACTIVATE_NOW;
1239 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1240 fbinfo->var.bits_per_pixel = windata->default_bpp;
1241 fbinfo->fbops = &s3c_fb_ops;
1242 fbinfo->flags = FBINFO_FLAG_DEFAULT;
1243 fbinfo->pseudo_palette = &win->pseudo_palette;
1245 /* prepare to actually start the framebuffer */
1247 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1249 dev_err(sfb->dev, "check_var failed on initial video params\n");
1253 /* create initial colour map */
1255 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1257 fb_set_cmap(&fbinfo->cmap, fbinfo);
1259 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1261 s3c_fb_set_par(fbinfo);
1263 dev_dbg(sfb->dev, "about to register framebuffer\n");
1265 /* run the check_var and set_par on our configuration. */
1267 ret = register_framebuffer(fbinfo);
1269 dev_err(sfb->dev, "failed to register framebuffer\n");
1273 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1279 * s3c_fb_clear_win() - clear hardware window registers.
1280 * @sfb: The base resources for the hardware.
1281 * @win: The window to process.
1283 * Reset the specific window registers to a known state.
1285 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1287 void __iomem *regs = sfb->regs;
1290 writel(0, regs + sfb->variant.wincon + (win * 4));
1291 writel(0, regs + VIDOSD_A(win, sfb->variant));
1292 writel(0, regs + VIDOSD_B(win, sfb->variant));
1293 writel(0, regs + VIDOSD_C(win, sfb->variant));
1294 reg = readl(regs + SHADOWCON);
1295 writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
1298 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1300 const struct platform_device_id *platid;
1301 struct s3c_fb_driverdata *fbdrv;
1302 struct device *dev = &pdev->dev;
1303 struct s3c_fb_platdata *pd;
1305 struct resource *res;
1309 platid = platform_get_device_id(pdev);
1310 fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1312 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1313 dev_err(dev, "too many windows, cannot attach\n");
1317 pd = pdev->dev.platform_data;
1319 dev_err(dev, "no platform data specified\n");
1323 sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
1325 dev_err(dev, "no memory for framebuffers\n");
1329 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1333 sfb->variant = fbdrv->variant;
1335 spin_lock_init(&sfb->slock);
1337 sfb->bus_clk = clk_get(dev, "lcd");
1338 if (IS_ERR(sfb->bus_clk)) {
1339 dev_err(dev, "failed to get bus clock\n");
1340 ret = PTR_ERR(sfb->bus_clk);
1344 clk_enable(sfb->bus_clk);
1346 if (!sfb->variant.has_clksel) {
1347 sfb->lcd_clk = clk_get(dev, "sclk_fimd");
1348 if (IS_ERR(sfb->lcd_clk)) {
1349 dev_err(dev, "failed to get lcd clock\n");
1350 ret = PTR_ERR(sfb->lcd_clk);
1354 clk_enable(sfb->lcd_clk);
1357 pm_runtime_enable(sfb->dev);
1359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361 dev_err(dev, "failed to find registers\n");
1366 sfb->regs_res = request_mem_region(res->start, resource_size(res),
1368 if (!sfb->regs_res) {
1369 dev_err(dev, "failed to claim register region\n");
1374 sfb->regs = ioremap(res->start, resource_size(res));
1376 dev_err(dev, "failed to map registers\n");
1378 goto err_req_region;
1381 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1383 dev_err(dev, "failed to acquire irq resource\n");
1387 sfb->irq_no = res->start;
1388 ret = request_irq(sfb->irq_no, s3c_fb_irq,
1391 dev_err(dev, "irq request failed\n");
1395 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1397 platform_set_drvdata(pdev, sfb);
1398 pm_runtime_get_sync(sfb->dev);
1400 /* setup gpio and output polarity controls */
1404 writel(pd->vidcon1, sfb->regs + VIDCON1);
1406 /* zero all windows before we do anything */
1408 for (win = 0; win < fbdrv->variant.nr_windows; win++)
1409 s3c_fb_clear_win(sfb, win);
1411 /* initialise colour key controls */
1412 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1413 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1416 writel(0xffffff, regs + WKEYCON0);
1417 writel(0xffffff, regs + WKEYCON1);
1420 /* we have the register setup, start allocating framebuffers */
1422 for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1426 if (!pd->win[win]->win_mode.pixclock)
1427 s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
1429 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1430 &sfb->windows[win]);
1432 dev_err(dev, "failed to create window %d\n", win);
1433 for (; win >= 0; win--)
1434 s3c_fb_release_win(sfb, sfb->windows[win]);
1439 platform_set_drvdata(pdev, sfb);
1444 free_irq(sfb->irq_no, sfb);
1450 release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
1453 if (!sfb->variant.has_clksel) {
1454 clk_disable(sfb->lcd_clk);
1455 clk_put(sfb->lcd_clk);
1459 clk_disable(sfb->bus_clk);
1460 clk_put(sfb->bus_clk);
1468 * s3c_fb_remove() - Cleanup on module finalisation
1469 * @pdev: The platform device we are bound to.
1471 * Shutdown and then release all the resources that the driver allocated
1472 * on initialisation.
1474 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1476 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1479 for (win = 0; win < S3C_FB_MAX_WIN; win++)
1480 if (sfb->windows[win])
1481 s3c_fb_release_win(sfb, sfb->windows[win]);
1483 free_irq(sfb->irq_no, sfb);
1487 if (!sfb->variant.has_clksel) {
1488 clk_disable(sfb->lcd_clk);
1489 clk_put(sfb->lcd_clk);
1492 clk_disable(sfb->bus_clk);
1493 clk_put(sfb->bus_clk);
1495 release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
1497 pm_runtime_put_sync(sfb->dev);
1498 pm_runtime_disable(sfb->dev);
1504 #ifdef CONFIG_PM_SLEEP
1505 static int s3c_fb_suspend(struct device *dev)
1507 struct platform_device *pdev = to_platform_device(dev);
1508 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1509 struct s3c_fb_win *win;
1512 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1513 win = sfb->windows[win_no];
1517 /* use the blank function to push into power-down */
1518 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1521 if (!sfb->variant.has_clksel)
1522 clk_disable(sfb->lcd_clk);
1524 clk_disable(sfb->bus_clk);
1525 pm_runtime_put_sync(sfb->dev);
1530 static int s3c_fb_resume(struct device *dev)
1532 struct platform_device *pdev = to_platform_device(dev);
1533 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1534 struct s3c_fb_platdata *pd = sfb->pdata;
1535 struct s3c_fb_win *win;
1538 pm_runtime_get_sync(sfb->dev);
1539 clk_enable(sfb->bus_clk);
1541 if (!sfb->variant.has_clksel)
1542 clk_enable(sfb->lcd_clk);
1544 /* setup gpio and output polarity controls */
1546 writel(pd->vidcon1, sfb->regs + VIDCON1);
1548 /* zero all windows before we do anything */
1549 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1550 s3c_fb_clear_win(sfb, win_no);
1552 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1553 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1555 regs += (win_no * 8);
1556 writel(0xffffff, regs + WKEYCON0);
1557 writel(0xffffff, regs + WKEYCON1);
1560 /* restore framebuffers */
1561 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1562 win = sfb->windows[win_no];
1566 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1567 s3c_fb_set_par(win->fbinfo);
1574 #ifdef CONFIG_PM_RUNTIME
1575 static int s3c_fb_runtime_suspend(struct device *dev)
1580 static int s3c_fb_runtime_resume(struct device *dev)
1586 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1587 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1589 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1592 .osd_size_off = 0x8,
1594 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1595 VALID_BPP(18) | VALID_BPP(24)),
1600 .osd_size_off = 0xc,
1603 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1604 VALID_BPP(18) | VALID_BPP(19) |
1605 VALID_BPP(24) | VALID_BPP(25) |
1611 .osd_size_off = 0xc,
1615 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1616 VALID_BPP(18) | VALID_BPP(19) |
1617 VALID_BPP(24) | VALID_BPP(25) |
1625 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1626 VALID_BPP(18) | VALID_BPP(19) |
1627 VALID_BPP(24) | VALID_BPP(25) |
1635 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1636 VALID_BPP(16) | VALID_BPP(18) |
1637 VALID_BPP(19) | VALID_BPP(24) |
1638 VALID_BPP(25) | VALID_BPP(28)),
1642 static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
1645 .osd_size_off = 0x8,
1647 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1648 VALID_BPP(15) | VALID_BPP(16) |
1649 VALID_BPP(18) | VALID_BPP(19) |
1650 VALID_BPP(24) | VALID_BPP(25) |
1656 .osd_size_off = 0xc,
1659 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1660 VALID_BPP(15) | VALID_BPP(16) |
1661 VALID_BPP(18) | VALID_BPP(19) |
1662 VALID_BPP(24) | VALID_BPP(25) |
1668 .osd_size_off = 0xc,
1671 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1672 VALID_BPP(15) | VALID_BPP(16) |
1673 VALID_BPP(18) | VALID_BPP(19) |
1674 VALID_BPP(24) | VALID_BPP(25) |
1681 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1682 VALID_BPP(15) | VALID_BPP(16) |
1683 VALID_BPP(18) | VALID_BPP(19) |
1684 VALID_BPP(24) | VALID_BPP(25) |
1691 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1692 VALID_BPP(15) | VALID_BPP(16) |
1693 VALID_BPP(18) | VALID_BPP(19) |
1694 VALID_BPP(24) | VALID_BPP(25) |
1699 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1702 .vidtcon = VIDTCON0,
1703 .wincon = WINCON(0),
1704 .winmap = WINxMAP(0),
1708 .buf_start = VIDW_BUF_START(0),
1709 .buf_size = VIDW_BUF_SIZE(0),
1710 .buf_end = VIDW_BUF_END(0),
1723 .win[0] = &s3c_fb_data_64xx_wins[0],
1724 .win[1] = &s3c_fb_data_64xx_wins[1],
1725 .win[2] = &s3c_fb_data_64xx_wins[2],
1726 .win[3] = &s3c_fb_data_64xx_wins[3],
1727 .win[4] = &s3c_fb_data_64xx_wins[4],
1730 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1733 .vidtcon = VIDTCON0,
1734 .wincon = WINCON(0),
1735 .winmap = WINxMAP(0),
1739 .buf_start = VIDW_BUF_START(0),
1740 .buf_size = VIDW_BUF_SIZE(0),
1741 .buf_end = VIDW_BUF_END(0),
1754 .win[0] = &s3c_fb_data_s5p_wins[0],
1755 .win[1] = &s3c_fb_data_s5p_wins[1],
1756 .win[2] = &s3c_fb_data_s5p_wins[2],
1757 .win[3] = &s3c_fb_data_s5p_wins[3],
1758 .win[4] = &s3c_fb_data_s5p_wins[4],
1761 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1764 .vidtcon = VIDTCON0,
1765 .wincon = WINCON(0),
1766 .winmap = WINxMAP(0),
1770 .buf_start = VIDW_BUF_START(0),
1771 .buf_size = VIDW_BUF_SIZE(0),
1772 .buf_end = VIDW_BUF_END(0),
1785 .win[0] = &s3c_fb_data_s5p_wins[0],
1786 .win[1] = &s3c_fb_data_s5p_wins[1],
1787 .win[2] = &s3c_fb_data_s5p_wins[2],
1788 .win[3] = &s3c_fb_data_s5p_wins[3],
1789 .win[4] = &s3c_fb_data_s5p_wins[4],
1792 static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
1795 .vidtcon = VIDTCON0,
1796 .wincon = WINCON(0),
1797 .winmap = WINxMAP(0),
1801 .buf_start = VIDW_BUF_START(0),
1802 .buf_size = VIDW_BUF_SIZE(0),
1803 .buf_end = VIDW_BUF_END(0),
1815 .win[0] = &s3c_fb_data_s5p_wins[0],
1816 .win[1] = &s3c_fb_data_s5p_wins[1],
1817 .win[2] = &s3c_fb_data_s5p_wins[2],
1818 .win[3] = &s3c_fb_data_s5p_wins[3],
1819 .win[4] = &s3c_fb_data_s5p_wins[4],
1822 /* S3C2443/S3C2416 style hardware */
1823 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1844 .win[0] = &(struct s3c_fb_win_variant) {
1846 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1848 .win[1] = &(struct s3c_fb_win_variant) {
1852 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1853 VALID_BPP(18) | VALID_BPP(19) |
1854 VALID_BPP(24) | VALID_BPP(25) |
1859 static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1862 .vidtcon = VIDTCON0,
1863 .wincon = WINCON(0),
1864 .winmap = WINxMAP(0),
1868 .buf_start = VIDW_BUF_START(0),
1869 .buf_size = VIDW_BUF_SIZE(0),
1870 .buf_end = VIDW_BUF_END(0),
1878 .win[0] = &s3c_fb_data_s5p_wins[0],
1879 .win[1] = &s3c_fb_data_s5p_wins[1],
1880 .win[2] = &s3c_fb_data_s5p_wins[2],
1883 static struct platform_device_id s3c_fb_driver_ids[] = {
1886 .driver_data = (unsigned long)&s3c_fb_data_64xx,
1888 .name = "s5pc100-fb",
1889 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
1891 .name = "s5pv210-fb",
1892 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
1894 .name = "exynos4-fb",
1895 .driver_data = (unsigned long)&s3c_fb_data_exynos4,
1897 .name = "s3c2443-fb",
1898 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
1900 .name = "s5p64x0-fb",
1901 .driver_data = (unsigned long)&s3c_fb_data_s5p64x0,
1905 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1907 static const struct dev_pm_ops s3c_fb_pm_ops = {
1908 SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
1909 SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume, NULL)
1912 static struct platform_driver s3c_fb_driver = {
1913 .probe = s3c_fb_probe,
1914 .remove = __devexit_p(s3c_fb_remove),
1915 .id_table = s3c_fb_driver_ids,
1918 .owner = THIS_MODULE,
1919 .pm = &s3c_fb_pm_ops,
1923 module_platform_driver(s3c_fb_driver);
1925 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1926 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1927 MODULE_LICENSE("GPL");
1928 MODULE_ALIAS("platform:s3c-fb");