Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum dss_io_pad_mode {
 101         DSS_IO_PAD_MODE_RESET,
 102         DSS_IO_PAD_MODE_RFBI,
 103         DSS_IO_PAD_MODE_BYPASS,
 104 };
 105
 106 enum dss_hdmi_venc_clk_source_select {
 107         DSS_VENC_TV_CLK = 0,
 108         DSS_HDMI_M_PCLK = 1,
 109 };
 110
 111 enum dss_dsi_content_type {
 112         DSS_DSI_CONTENT_DCS,
 113         DSS_DSI_CONTENT_GENERIC,
 114 };
 115
 116 struct dss_clock_info {
 117         /* rates that we get with dividers below */
 118         unsigned long fck;
 119
 120         /* dividers */
 121         u16 fck_div;
 122 };
 123
 124 struct dispc_clock_info {
 125         /* rates that we get with dividers below */
 126         unsigned long lck;
 127         unsigned long pck;
 128
 129         /* dividers */
 130         u16 lck_div;
 131         u16 pck_div;
 132 };
 133
 134 struct dsi_clock_info {
 135         /* rates that we get with dividers below */
 136         unsigned long fint;
 137         unsigned long clkin4ddr;
 138         unsigned long clkin;
 139         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 140                                                  * OMAP4: PLLx_CLK1 */
 141         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 142                                                  * OMAP4: PLLx_CLK2 */
 143         unsigned long lp_clk;
 144
 145         /* dividers */
 146         u16 regn;
 147         u16 regm;
 148         u16 regm_dispc; /* OMAP3: REGM3
 149                          * OMAP4: REGM4 */
 150         u16 regm_dsi;   /* OMAP3: REGM4
 151                          * OMAP4: REGM5 */
 152         u16 lp_clk_div;
 153
 154         u8 highfreq;
 155         bool use_sys_clk;
 156 };
 157
 158 /* HDMI PLL structure */
 159 struct hdmi_pll_info {
 160         u16 regn;
 161         u16 regm;
 162         u32 regmf;
 163         u16 regm2;
 164         u16 regsd;
 165         u16 dcofreq;
 166 };
 167
 168 struct seq_file;
 169 struct platform_device;
 170
 171 /* core */
 172 struct bus_type *dss_get_bus(void);
 173 struct regulator *dss_get_vdds_dsi(void);
 174 struct regulator *dss_get_vdds_sdi(void);
 175
 176 /* display */
 177 int dss_suspend_all_devices(void);
 178 int dss_resume_all_devices(void);
 179 void dss_disable_all_devices(void);
 180
 181 void dss_init_device(struct platform_device *pdev,
 182                 struct omap_dss_device *dssdev);
 183 void dss_uninit_device(struct platform_device *pdev,
 184                 struct omap_dss_device *dssdev);
 185 bool dss_use_replication(struct omap_dss_device *dssdev,
 186                 enum omap_color_mode mode);
 187 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 188                 u32 fifo_size, u32 burst_size,
 189                 u32 *fifo_low, u32 *fifo_high);
 190
 191 /* manager */
 192 int dss_init_overlay_managers(struct platform_device *pdev);
 193 void dss_uninit_overlay_managers(struct platform_device *pdev);
 194 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 195 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 196                                 u16 *x, u16 *y, u16 *w, u16 *h,
 197                                 bool enlarge_update_area);
 198 void dss_start_update(struct omap_dss_device *dssdev);
 199
 200 /* overlay */
 201 void dss_init_overlays(struct platform_device *pdev);
 202 void dss_uninit_overlays(struct platform_device *pdev);
 203 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 204 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 205 #ifdef L4_EXAMPLE
 206 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 207 #endif
 208 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 209
 210 /* DSS */
 211 int dss_init_platform_driver(void);
 212 void dss_uninit_platform_driver(void);
 213
 214 int dss_runtime_get(void);
 215 void dss_runtime_put(void);
 216
 217 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 218 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 219 void dss_dump_clocks(struct seq_file *s);
 220
 221 void dss_dump_regs(struct seq_file *s);
 222 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 223 void dss_debug_dump_clocks(struct seq_file *s);
 224 #endif
 225
 226 void dss_sdi_init(u8 datapairs);
 227 int dss_sdi_enable(void);
 228 void dss_sdi_disable(void);
 229
 230 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 231 void dss_select_dsi_clk_source(int dsi_module,
 232                 enum omap_dss_clk_source clk_src);
 233 void dss_select_lcd_clk_source(enum omap_channel channel,
 234                 enum omap_dss_clk_source clk_src);
 235 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 236 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
 237 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 238
 239 void dss_set_venc_output(enum omap_dss_venc_type type);
 240 void dss_set_dac_pwrdn_bgz(bool enable);
 241
 242 unsigned long dss_get_dpll4_rate(void);
 243 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 244 int dss_set_clock_div(struct dss_clock_info *cinfo);
 245 int dss_get_clock_div(struct dss_clock_info *cinfo);
 246 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 247                 struct dss_clock_info *dss_cinfo,
 248                 struct dispc_clock_info *dispc_cinfo);
 249
 250 /* SDI */
 251 #ifdef CONFIG_OMAP2_DSS_SDI
 252 int sdi_init(void);
 253 void sdi_exit(void);
 254 int sdi_init_display(struct omap_dss_device *display);
 255 #else
 256 static inline int sdi_init(void)
 257 {
 258         return 0;
 259 }
 260 static inline void sdi_exit(void)
 261 {
 262 }
 263 #endif
 264
 265 /* DSI */
 266 #ifdef CONFIG_OMAP2_DSS_DSI
 267
 268 struct dentry;
 269 struct file_operations;
 270
 271 int dsi_init_platform_driver(void);
 272 void dsi_uninit_platform_driver(void);
 273
 274 int dsi_runtime_get(struct platform_device *dsidev);
 275 void dsi_runtime_put(struct platform_device *dsidev);
 276
 277 void dsi_dump_clocks(struct seq_file *s);
 278 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
 279                 const struct file_operations *debug_fops);
 280 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
 281                 const struct file_operations *debug_fops);
 282
 283 int dsi_init_display(struct omap_dss_device *display);
 284 void dsi_irq_handler(void);
 285 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
 286
 287 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
 288 int dsi_pll_set_clock_div(struct platform_device *dsidev,
 289                 struct dsi_clock_info *cinfo);
 290 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
 291                 unsigned long req_pck, struct dsi_clock_info *cinfo,
 292                 struct dispc_clock_info *dispc_cinfo);
 293 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
 294                 bool enable_hsdiv);
 295 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
 296 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 297                 u32 fifo_size, u32 burst_size,
 298                 u32 *fifo_low, u32 *fifo_high);
 299 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
 300 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
 301 struct platform_device *dsi_get_dsidev_from_id(int module);
 302 #else
 303 static inline int dsi_init_platform_driver(void)
 304 {
 305         return 0;
 306 }
 307 static inline void dsi_uninit_platform_driver(void)
 308 {
 309 }
 310 static inline int dsi_runtime_get(struct platform_device *dsidev)
 311 {
 312         return 0;
 313 }
 314 static inline void dsi_runtime_put(struct platform_device *dsidev)
 315 {
 316 }
 317 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 318 {
 319         WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
 320         return 0;
 321 }
 322 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
 323 {
 324         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 325         return 0;
 326 }
 327 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
 328                 struct dsi_clock_info *cinfo)
 329 {
 330         WARN("%s: DSI not compiled in\n", __func__);
 331         return -ENODEV;
 332 }
 333 static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
 334                 bool is_tft, unsigned long req_pck,
 335                 struct dsi_clock_info *dsi_cinfo,
 336                 struct dispc_clock_info *dispc_cinfo)
 337 {
 338         WARN("%s: DSI not compiled in\n", __func__);
 339         return -ENODEV;
 340 }
 341 static inline int dsi_pll_init(struct platform_device *dsidev,
 342                 bool enable_hsclk, bool enable_hsdiv)
 343 {
 344         WARN("%s: DSI not compiled in\n", __func__);
 345         return -ENODEV;
 346 }
 347 static inline void dsi_pll_uninit(struct platform_device *dsidev,
 348                 bool disconnect_lanes)
 349 {
 350 }
 351 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
 352 {
 353 }
 354 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
 355 {
 356 }
 357 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
 358 {
 359         WARN("%s: DSI not compiled in, returning platform device as NULL\n",
 360                         __func__);
 361         return NULL;
 362 }
 363 #endif
 364
 365 /* DPI */
 366 #ifdef CONFIG_OMAP2_DSS_DPI
 367 int dpi_init(void);
 368 void dpi_exit(void);
 369 int dpi_init_display(struct omap_dss_device *dssdev);
 370 #else
 371 static inline int dpi_init(void)
 372 {
 373         return 0;
 374 }
 375 static inline void dpi_exit(void)
 376 {
 377 }
 378 #endif
 379
 380 /* DISPC */
 381 int dispc_init_platform_driver(void);
 382 void dispc_uninit_platform_driver(void);
 383 void dispc_dump_clocks(struct seq_file *s);
 384 void dispc_dump_irqs(struct seq_file *s);
 385 void dispc_dump_regs(struct seq_file *s);
 386 void dispc_irq_handler(void);
 387 void dispc_fake_vsync_irq(void);
 388
 389 int dispc_runtime_get(void);
 390 void dispc_runtime_put(void);
 391
 392 void dispc_enable_sidle(void);
 393 void dispc_disable_sidle(void);
 394
 395 void dispc_lcd_enable_signal_polarity(bool act_high);
 396 void dispc_lcd_enable_signal(bool enable);
 397 void dispc_pck_free_enable(bool enable);
 398 void dispc_set_digit_size(u16 width, u16 height);
 399 void dispc_enable_fifomerge(bool enable);
 400 void dispc_enable_gamma_table(bool enable);
 401 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 402
 403 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 404 unsigned long dispc_fclk_rate(void);
 405 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 406                 struct dispc_clock_info *cinfo);
 407 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 408                 struct dispc_clock_info *cinfo);
 409
 410
 411 u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
 412 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 413 u32 dispc_ovl_get_burst_size(enum omap_plane plane);
 414 int dispc_ovl_setup(enum omap_plane plane,
 415                       u32 paddr, u16 screen_width,
 416                       u16 pos_x, u16 pos_y,
 417                       u16 width, u16 height,
 418                       u16 out_width, u16 out_height,
 419                       enum omap_color_mode color_mode,
 420                       bool ilace,
 421                       enum omap_dss_rotation_type rotation_type,
 422                       u8 rotation, bool mirror,
 423                       u8 global_alpha, u8 pre_mult_alpha,
 424                       enum omap_channel channel,
 425                       u32 puv_addr);
 426 int dispc_ovl_enable(enum omap_plane plane, bool enable);
 427 void dispc_ovl_enable_replication(enum omap_plane plane, bool enable);
 428
 429
 430 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
 431 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 432 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable);
 433 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 434                 struct omap_dss_cpr_coefs *coefs);
 435 bool dispc_mgr_go_busy(enum omap_channel channel);
 436 void dispc_mgr_go(enum omap_channel channel);
 437 void dispc_mgr_enable(enum omap_channel channel, bool enable);
 438 bool dispc_mgr_is_channel_enabled(enum omap_channel channel);
 439 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode);
 440 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable);
 441 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 442 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
 443                 enum omap_lcd_display_type type);
 444 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color);
 445 u32 dispc_mgr_get_default_color(enum omap_channel channel);
 446 void dispc_mgr_set_trans_key(enum omap_channel ch,
 447                 enum omap_dss_trans_key_type type,
 448                 u32 trans_key);
 449 void dispc_mgr_get_trans_key(enum omap_channel ch,
 450                 enum omap_dss_trans_key_type *type,
 451                 u32 *trans_key);
 452 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable);
 453 void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable);
 454 bool dispc_mgr_trans_key_enabled(enum omap_channel ch);
 455 bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch);
 456 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
 457                 struct omap_video_timings *timings);
 458 void dispc_mgr_set_pol_freq(enum omap_channel channel,
 459                 enum omap_panel_config config, u8 acbi, u8 acb);
 460 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
 461 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
 462 int dispc_mgr_set_clock_div(enum omap_channel channel,
 463                 struct dispc_clock_info *cinfo);
 464 int dispc_mgr_get_clock_div(enum omap_channel channel,
 465                 struct dispc_clock_info *cinfo);
 466
 467 /* VENC */
 468 #ifdef CONFIG_OMAP2_DSS_VENC
 469 int venc_init_platform_driver(void);
 470 void venc_uninit_platform_driver(void);
 471 void venc_dump_regs(struct seq_file *s);
 472 int venc_init_display(struct omap_dss_device *display);
 473 #else
 474 static inline int venc_init_platform_driver(void)
 475 {
 476         return 0;
 477 }
 478 static inline void venc_uninit_platform_driver(void)
 479 {
 480 }
 481 #endif
 482
 483 /* HDMI */
 484 #ifdef CONFIG_OMAP4_DSS_HDMI
 485 int hdmi_init_platform_driver(void);
 486 void hdmi_uninit_platform_driver(void);
 487 int hdmi_init_display(struct omap_dss_device *dssdev);
 488 #else
 489 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 490 {
 491         return 0;
 492 }
 493 static inline int hdmi_init_platform_driver(void)
 494 {
 495         return 0;
 496 }
 497 static inline void hdmi_uninit_platform_driver(void)
 498 {
 499 }
 500 #endif
 501 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 502 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 503 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 504 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 505                                         struct omap_video_timings *timings);
 506 int hdmi_panel_init(void);
 507 void hdmi_panel_exit(void);
 508
 509 /* RFBI */
 510 #ifdef CONFIG_OMAP2_DSS_RFBI
 511 int rfbi_init_platform_driver(void);
 512 void rfbi_uninit_platform_driver(void);
 513 void rfbi_dump_regs(struct seq_file *s);
 514 int rfbi_init_display(struct omap_dss_device *display);
 515 #else
 516 static inline int rfbi_init_platform_driver(void)
 517 {
 518         return 0;
 519 }
 520 static inline void rfbi_uninit_platform_driver(void)
 521 {
 522 }
 523 #endif
 524
 525
 526 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 527 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 528 {
 529         int b;
 530         for (b = 0; b < 32; ++b) {
 531                 if (irqstatus & (1 << b))
 532                         irq_arr[b]++;
 533         }
 534 }
 535 #endif
 536
 537 #endif