Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dss.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.h
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef __OMAP2_DSS_H
  24 #define __OMAP2_DSS_H
  25
  26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
  27 #define DEBUG
  28 #endif
  29
  30 #ifdef DEBUG
  31 extern unsigned int dss_debug;
  32 #ifdef DSS_SUBSYS_NAME
  33 #define DSSDBG(format, ...) \
  34         if (dss_debug) \
  35                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
  36                 ## __VA_ARGS__)
  37 #else
  38 #define DSSDBG(format, ...) \
  39         if (dss_debug) \
  40                 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
  41 #endif
  42
  43 #ifdef DSS_SUBSYS_NAME
  44 #define DSSDBGF(format, ...) \
  45         if (dss_debug) \
  46                 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
  47                                 ": %s(" format ")\n", \
  48                                 __func__, \
  49                                 ## __VA_ARGS__)
  50 #else
  51 #define DSSDBGF(format, ...) \
  52         if (dss_debug) \
  53                 printk(KERN_DEBUG "omapdss: " \
  54                                 ": %s(" format ")\n", \
  55                                 __func__, \
  56                                 ## __VA_ARGS__)
  57 #endif
  58
  59 #else /* DEBUG */
  60 #define DSSDBG(format, ...)
  61 #define DSSDBGF(format, ...)
  62 #endif
  63
  64
  65 #ifdef DSS_SUBSYS_NAME
  66 #define DSSERR(format, ...) \
  67         printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
  68         ## __VA_ARGS__)
  69 #else
  70 #define DSSERR(format, ...) \
  71         printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
  72 #endif
  73
  74 #ifdef DSS_SUBSYS_NAME
  75 #define DSSINFO(format, ...) \
  76         printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
  77         ## __VA_ARGS__)
  78 #else
  79 #define DSSINFO(format, ...) \
  80         printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
  81 #endif
  82
  83 #ifdef DSS_SUBSYS_NAME
  84 #define DSSWARN(format, ...) \
  85         printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
  86         ## __VA_ARGS__)
  87 #else
  88 #define DSSWARN(format, ...) \
  89         printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
  90 #endif
  91
  92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
  93    number. For example 7:0 */
  94 #define FLD_MASK(start, end)    (((1 << ((start) - (end) + 1)) - 1) << (end))
  95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
  96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
  97 #define FLD_MOD(orig, val, start, end) \
  98         (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
  99
 100 enum omap_burst_size {
 101         OMAP_DSS_BURST_4x32 = 0,
 102         OMAP_DSS_BURST_8x32 = 1,
 103         OMAP_DSS_BURST_16x32 = 2,
 104 };
 105
 106 enum omap_parallel_interface_mode {
 107         OMAP_DSS_PARALLELMODE_BYPASS,           /* MIPI DPI */
 108         OMAP_DSS_PARALLELMODE_RFBI,             /* MIPI DBI */
 109         OMAP_DSS_PARALLELMODE_DSI,
 110 };
 111
 112 enum dss_clock {
 113         DSS_CLK_ICK     = 1 << 0,       /* DSS_L3_ICLK and DSS_L4_ICLK */
 114         DSS_CLK_FCK     = 1 << 1,       /* DSS1_ALWON_FCLK */
 115         DSS_CLK_SYSCK   = 1 << 2,       /* DSS2_ALWON_FCLK */
 116         DSS_CLK_TVFCK   = 1 << 3,       /* DSS_TV_FCLK */
 117         DSS_CLK_VIDFCK  = 1 << 4,       /* DSS_96M_FCLK*/
 118 };
 119
 120 enum dss_hdmi_venc_clk_source_select {
 121         DSS_VENC_TV_CLK = 0,
 122         DSS_HDMI_M_PCLK = 1,
 123 };
 124
 125 struct dss_clock_info {
 126         /* rates that we get with dividers below */
 127         unsigned long fck;
 128
 129         /* dividers */
 130         u16 fck_div;
 131 };
 132
 133 struct dispc_clock_info {
 134         /* rates that we get with dividers below */
 135         unsigned long lck;
 136         unsigned long pck;
 137
 138         /* dividers */
 139         u16 lck_div;
 140         u16 pck_div;
 141 };
 142
 143 struct dsi_clock_info {
 144         /* rates that we get with dividers below */
 145         unsigned long fint;
 146         unsigned long clkin4ddr;
 147         unsigned long clkin;
 148         unsigned long dsi_pll_hsdiv_dispc_clk;  /* OMAP3: DSI1_PLL_CLK
 149                                                  * OMAP4: PLLx_CLK1 */
 150         unsigned long dsi_pll_hsdiv_dsi_clk;    /* OMAP3: DSI2_PLL_CLK
 151                                                  * OMAP4: PLLx_CLK2 */
 152         unsigned long lp_clk;
 153
 154         /* dividers */
 155         u16 regn;
 156         u16 regm;
 157         u16 regm_dispc; /* OMAP3: REGM3
 158                          * OMAP4: REGM4 */
 159         u16 regm_dsi;   /* OMAP3: REGM4
 160                          * OMAP4: REGM5 */
 161         u16 lp_clk_div;
 162
 163         u8 highfreq;
 164         bool use_sys_clk;
 165 };
 166
 167 /* HDMI PLL structure */
 168 struct hdmi_pll_info {
 169         u16 regn;
 170         u16 regm;
 171         u32 regmf;
 172         u16 regm2;
 173         u16 regsd;
 174         u16 dcofreq;
 175 };
 176
 177 struct seq_file;
 178 struct platform_device;
 179
 180 /* core */
 181 struct bus_type *dss_get_bus(void);
 182 struct regulator *dss_get_vdds_dsi(void);
 183 struct regulator *dss_get_vdds_sdi(void);
 184
 185 /* display */
 186 int dss_suspend_all_devices(void);
 187 int dss_resume_all_devices(void);
 188 void dss_disable_all_devices(void);
 189
 190 void dss_init_device(struct platform_device *pdev,
 191                 struct omap_dss_device *dssdev);
 192 void dss_uninit_device(struct platform_device *pdev,
 193                 struct omap_dss_device *dssdev);
 194 bool dss_use_replication(struct omap_dss_device *dssdev,
 195                 enum omap_color_mode mode);
 196 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
 197                 u32 fifo_size, enum omap_burst_size *burst_size,
 198                 u32 *fifo_low, u32 *fifo_high);
 199
 200 /* manager */
 201 int dss_init_overlay_managers(struct platform_device *pdev);
 202 void dss_uninit_overlay_managers(struct platform_device *pdev);
 203 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
 204 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
 205                                 u16 *x, u16 *y, u16 *w, u16 *h,
 206                                 bool enlarge_update_area);
 207 void dss_start_update(struct omap_dss_device *dssdev);
 208
 209 /* overlay */
 210 void dss_init_overlays(struct platform_device *pdev);
 211 void dss_uninit_overlays(struct platform_device *pdev);
 212 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
 213 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
 214 #ifdef L4_EXAMPLE
 215 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
 216 #endif
 217 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
 218
 219 /* DSS */
 220 int dss_init_platform_driver(void);
 221 void dss_uninit_platform_driver(void);
 222
 223 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
 224 void dss_save_context(void);
 225 void dss_restore_context(void);
 226 void dss_clk_enable(enum dss_clock clks);
 227 void dss_clk_disable(enum dss_clock clks);
 228 unsigned long dss_clk_get_rate(enum dss_clock clk);
 229 int dss_need_ctx_restore(void);
 230 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
 231 void dss_dump_clocks(struct seq_file *s);
 232
 233 void dss_dump_regs(struct seq_file *s);
 234 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 235 void dss_debug_dump_clocks(struct seq_file *s);
 236 #endif
 237
 238 void dss_sdi_init(u8 datapairs);
 239 int dss_sdi_enable(void);
 240 void dss_sdi_disable(void);
 241
 242 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
 243 void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src);
 244 void dss_select_lcd_clk_source(enum omap_channel channel,
 245                 enum omap_dss_clk_source clk_src);
 246 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
 247 enum omap_dss_clk_source dss_get_dsi_clk_source(void);
 248 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
 249
 250 void dss_set_venc_output(enum omap_dss_venc_type type);
 251 void dss_set_dac_pwrdn_bgz(bool enable);
 252
 253 unsigned long dss_get_dpll4_rate(void);
 254 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
 255 int dss_set_clock_div(struct dss_clock_info *cinfo);
 256 int dss_get_clock_div(struct dss_clock_info *cinfo);
 257 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 258                 struct dss_clock_info *dss_cinfo,
 259                 struct dispc_clock_info *dispc_cinfo);
 260
 261 /* SDI */
 262 #ifdef CONFIG_OMAP2_DSS_SDI
 263 int sdi_init(void);
 264 void sdi_exit(void);
 265 int sdi_init_display(struct omap_dss_device *display);
 266 #else
 267 static inline int sdi_init(void)
 268 {
 269         return 0;
 270 }
 271 static inline void sdi_exit(void)
 272 {
 273 }
 274 #endif
 275
 276 /* DSI */
 277 #ifdef CONFIG_OMAP2_DSS_DSI
 278 int dsi_init_platform_driver(void);
 279 void dsi_uninit_platform_driver(void);
 280
 281 void dsi_dump_clocks(struct seq_file *s);
 282 void dsi_dump_irqs(struct seq_file *s);
 283 void dsi_dump_regs(struct seq_file *s);
 284
 285 void dsi_save_context(void);
 286 void dsi_restore_context(void);
 287
 288 int dsi_init_display(struct omap_dss_device *display);
 289 void dsi_irq_handler(void);
 290 unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
 291 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
 292 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
 293                 struct dsi_clock_info *cinfo,
 294                 struct dispc_clock_info *dispc_cinfo);
 295 int dsi_pll_init(bool enable_hsclk, bool enable_hsdiv);
 296 void dsi_pll_uninit(bool disconnect_lanes);
 297 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
 298                 u32 fifo_size, enum omap_burst_size *burst_size,
 299                 u32 *fifo_low, u32 *fifo_high);
 300 void dsi_wait_pll_hsdiv_dispc_active(void);
 301 void dsi_wait_pll_hsdiv_dsi_active(void);
 302 #else
 303 static inline int dsi_init_platform_driver(void)
 304 {
 305         return 0;
 306 }
 307 static inline void dsi_uninit_platform_driver(void)
 308 {
 309 }
 310 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
 311 {
 312         WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
 313         return 0;
 314 }
 315 static inline void dsi_wait_pll_hsdiv_dispc_active(void)
 316 {
 317 }
 318 static inline void dsi_wait_pll_hsdiv_dsi_active(void)
 319 {
 320 }
 321 #endif
 322
 323 /* DPI */
 324 #ifdef CONFIG_OMAP2_DSS_DPI
 325 int dpi_init(void);
 326 void dpi_exit(void);
 327 int dpi_init_display(struct omap_dss_device *dssdev);
 328 #else
 329 static inline int dpi_init(void)
 330 {
 331         return 0;
 332 }
 333 static inline void dpi_exit(void)
 334 {
 335 }
 336 #endif
 337
 338 /* DISPC */
 339 int dispc_init_platform_driver(void);
 340 void dispc_uninit_platform_driver(void);
 341 void dispc_dump_clocks(struct seq_file *s);
 342 void dispc_dump_irqs(struct seq_file *s);
 343 void dispc_dump_regs(struct seq_file *s);
 344 void dispc_irq_handler(void);
 345 void dispc_fake_vsync_irq(void);
 346
 347 void dispc_save_context(void);
 348 void dispc_restore_context(void);
 349
 350 void dispc_enable_sidle(void);
 351 void dispc_disable_sidle(void);
 352
 353 void dispc_lcd_enable_signal_polarity(bool act_high);
 354 void dispc_lcd_enable_signal(bool enable);
 355 void dispc_pck_free_enable(bool enable);
 356 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
 357
 358 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
 359 void dispc_set_digit_size(u16 width, u16 height);
 360 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
 361 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
 362 void dispc_enable_fifomerge(bool enable);
 363 void dispc_set_burst_size(enum omap_plane plane,
 364                 enum omap_burst_size burst_size);
 365
 366 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
 367 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
 368 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
 369 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
 370 void dispc_set_channel_out(enum omap_plane plane,
 371                 enum omap_channel channel_out);
 372
 373 void dispc_enable_gamma_table(bool enable);
 374 int dispc_setup_plane(enum omap_plane plane,
 375                       u32 paddr, u16 screen_width,
 376                       u16 pos_x, u16 pos_y,
 377                       u16 width, u16 height,
 378                       u16 out_width, u16 out_height,
 379                       enum omap_color_mode color_mode,
 380                       bool ilace,
 381                       enum omap_dss_rotation_type rotation_type,
 382                       u8 rotation, bool mirror,
 383                       u8 global_alpha, u8 pre_mult_alpha,
 384                       enum omap_channel channel);
 385
 386 bool dispc_go_busy(enum omap_channel channel);
 387 void dispc_go(enum omap_channel channel);
 388 void dispc_enable_channel(enum omap_channel channel, bool enable);
 389 bool dispc_is_channel_enabled(enum omap_channel channel);
 390 int dispc_enable_plane(enum omap_plane plane, bool enable);
 391 void dispc_enable_replication(enum omap_plane plane, bool enable);
 392
 393 void dispc_set_parallel_interface_mode(enum omap_channel channel,
 394                 enum omap_parallel_interface_mode mode);
 395 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
 396 void dispc_set_lcd_display_type(enum omap_channel channel,
 397                 enum omap_lcd_display_type type);
 398 void dispc_set_loadmode(enum omap_dss_load_mode mode);
 399
 400 void dispc_set_default_color(enum omap_channel channel, u32 color);
 401 u32 dispc_get_default_color(enum omap_channel channel);
 402 void dispc_set_trans_key(enum omap_channel ch,
 403                 enum omap_dss_trans_key_type type,
 404                 u32 trans_key);
 405 void dispc_get_trans_key(enum omap_channel ch,
 406                 enum omap_dss_trans_key_type *type,
 407                 u32 *trans_key);
 408 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
 409 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
 410 bool dispc_trans_key_enabled(enum omap_channel ch);
 411 bool dispc_alpha_blending_enabled(enum omap_channel ch);
 412
 413 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
 414 void dispc_set_lcd_timings(enum omap_channel channel,
 415                 struct omap_video_timings *timings);
 416 unsigned long dispc_fclk_rate(void);
 417 unsigned long dispc_lclk_rate(enum omap_channel channel);
 418 unsigned long dispc_pclk_rate(enum omap_channel channel);
 419 void dispc_set_pol_freq(enum omap_channel channel,
 420                 enum omap_panel_config config, u8 acbi, u8 acb);
 421 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
 422                 struct dispc_clock_info *cinfo);
 423 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
 424                 struct dispc_clock_info *cinfo);
 425 int dispc_set_clock_div(enum omap_channel channel,
 426                 struct dispc_clock_info *cinfo);
 427 int dispc_get_clock_div(enum omap_channel channel,
 428                 struct dispc_clock_info *cinfo);
 429
 430
 431 /* VENC */
 432 #ifdef CONFIG_OMAP2_DSS_VENC
 433 int venc_init_platform_driver(void);
 434 void venc_uninit_platform_driver(void);
 435 void venc_dump_regs(struct seq_file *s);
 436 int venc_init_display(struct omap_dss_device *display);
 437 #else
 438 static inline int venc_init_platform_driver(void)
 439 {
 440         return 0;
 441 }
 442 static inline void venc_uninit_platform_driver(void)
 443 {
 444 }
 445 #endif
 446
 447 /* HDMI */
 448 #ifdef CONFIG_OMAP4_DSS_HDMI
 449 int hdmi_init_platform_driver(void);
 450 void hdmi_uninit_platform_driver(void);
 451 int hdmi_init_display(struct omap_dss_device *dssdev);
 452 #else
 453 static inline int hdmi_init_display(struct omap_dss_device *dssdev)
 454 {
 455         return 0;
 456 }
 457 static inline int hdmi_init_platform_driver(void)
 458 {
 459         return 0;
 460 }
 461 static inline void hdmi_uninit_platform_driver(void)
 462 {
 463 }
 464 #endif
 465 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
 466 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
 467 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev);
 468 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
 469                                         struct omap_video_timings *timings);
 470 int hdmi_panel_init(void);
 471 void hdmi_panel_exit(void);
 472
 473 /* RFBI */
 474 #ifdef CONFIG_OMAP2_DSS_RFBI
 475 int rfbi_init_platform_driver(void);
 476 void rfbi_uninit_platform_driver(void);
 477 void rfbi_dump_regs(struct seq_file *s);
 478
 479 int rfbi_configure(int rfbi_module, int bpp, int lines);
 480 void rfbi_enable_rfbi(bool enable);
 481 void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
 482                 u16 height, void (callback)(void *data), void *data);
 483 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
 484 unsigned long rfbi_get_max_tx_rate(void);
 485 int rfbi_init_display(struct omap_dss_device *display);
 486 #else
 487 static inline int rfbi_init_platform_driver(void)
 488 {
 489         return 0;
 490 }
 491 static inline void rfbi_uninit_platform_driver(void)
 492 {
 493 }
 494 #endif
 495
 496
 497 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 498 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
 499 {
 500         int b;
 501         for (b = 0; b < 32; ++b) {
 502                 if (irqstatus & (1 << b))
 503                         irq_arr[b]++;
 504         }
 505 }
 506 #endif
 507
 508 #endif