Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/gfp.h>
  35 #include <linux/sizes.h>
  36
  37 #include <video/omapdss.h>
  38
  39 #include "dss.h"
  40 #include "dss_features.h"
  41
  42 #define DSS_SZ_REGS                     SZ_512
  43
  44 struct dss_reg {
  45         u16 idx;
  46 };
  47
  48 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  49
  50 #define DSS_REVISION                    DSS_REG(0x0000)
  51 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  52 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  53 #define DSS_CONTROL                     DSS_REG(0x0040)
  54 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  55 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  56 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dss_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end) \
  62         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  63
  64 static int dss_runtime_get(void);
  65 static void dss_runtime_put(void);
  66
  67 struct dss_features {
  68         u8 fck_div_max;
  69         u8 dss_fck_multiplier;
  70         const char *clk_name;
  71         int (*dpi_select_source)(enum omap_channel channel);
  72 };
  73
  74 static struct {
  75         struct platform_device *pdev;
  76         void __iomem    *base;
  77
  78         struct clk      *dpll4_m4_ck;
  79         struct clk      *dss_clk;
  80
  81         unsigned long   cache_req_pck;
  82         unsigned long   cache_prate;
  83         struct dss_clock_info cache_dss_cinfo;
  84         struct dispc_clock_info cache_dispc_cinfo;
  85
  86         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  87         enum omap_dss_clk_source dispc_clk_source;
  88         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  89
  90         bool            ctx_valid;
  91         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  92
  93         const struct dss_features *feat;
  94 } dss;
  95
  96 static const char * const dss_generic_clk_source_names[] = {
  97         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  98         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  99         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 100         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 101         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 102 };
 103
 104 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 105 {
 106         __raw_writel(val, dss.base + idx.idx);
 107 }
 108
 109 static inline u32 dss_read_reg(const struct dss_reg idx)
 110 {
 111         return __raw_readl(dss.base + idx.idx);
 112 }
 113
 114 #define SR(reg) \
 115         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 116 #define RR(reg) \
 117         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 118
 119 static void dss_save_context(void)
 120 {
 121         DSSDBG("dss_save_context\n");
 122
 123         SR(CONTROL);
 124
 125         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 126                         OMAP_DISPLAY_TYPE_SDI) {
 127                 SR(SDI_CONTROL);
 128                 SR(PLL_CONTROL);
 129         }
 130
 131         dss.ctx_valid = true;
 132
 133         DSSDBG("context saved\n");
 134 }
 135
 136 static void dss_restore_context(void)
 137 {
 138         DSSDBG("dss_restore_context\n");
 139
 140         if (!dss.ctx_valid)
 141                 return;
 142
 143         RR(CONTROL);
 144
 145         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 146                         OMAP_DISPLAY_TYPE_SDI) {
 147                 RR(SDI_CONTROL);
 148                 RR(PLL_CONTROL);
 149         }
 150
 151         DSSDBG("context restored\n");
 152 }
 153
 154 #undef SR
 155 #undef RR
 156
 157 void dss_sdi_init(int datapairs)
 158 {
 159         u32 l;
 160
 161         BUG_ON(datapairs > 3 || datapairs < 1);
 162
 163         l = dss_read_reg(DSS_SDI_CONTROL);
 164         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 165         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 166         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 167         dss_write_reg(DSS_SDI_CONTROL, l);
 168
 169         l = dss_read_reg(DSS_PLL_CONTROL);
 170         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 171         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 172         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 173         dss_write_reg(DSS_PLL_CONTROL, l);
 174 }
 175
 176 int dss_sdi_enable(void)
 177 {
 178         unsigned long timeout;
 179
 180         dispc_pck_free_enable(1);
 181
 182         /* Reset SDI PLL */
 183         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 184         udelay(1);      /* wait 2x PCLK */
 185
 186         /* Lock SDI PLL */
 187         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 188
 189         /* Waiting for PLL lock request to complete */
 190         timeout = jiffies + msecs_to_jiffies(500);
 191         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 192                 if (time_after_eq(jiffies, timeout)) {
 193                         DSSERR("PLL lock request timed out\n");
 194                         goto err1;
 195                 }
 196         }
 197
 198         /* Clearing PLL_GO bit */
 199         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 200
 201         /* Waiting for PLL to lock */
 202         timeout = jiffies + msecs_to_jiffies(500);
 203         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 204                 if (time_after_eq(jiffies, timeout)) {
 205                         DSSERR("PLL lock timed out\n");
 206                         goto err1;
 207                 }
 208         }
 209
 210         dispc_lcd_enable_signal(1);
 211
 212         /* Waiting for SDI reset to complete */
 213         timeout = jiffies + msecs_to_jiffies(500);
 214         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 215                 if (time_after_eq(jiffies, timeout)) {
 216                         DSSERR("SDI reset timed out\n");
 217                         goto err2;
 218                 }
 219         }
 220
 221         return 0;
 222
 223  err2:
 224         dispc_lcd_enable_signal(0);
 225  err1:
 226         /* Reset SDI PLL */
 227         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 228
 229         dispc_pck_free_enable(0);
 230
 231         return -ETIMEDOUT;
 232 }
 233
 234 void dss_sdi_disable(void)
 235 {
 236         dispc_lcd_enable_signal(0);
 237
 238         dispc_pck_free_enable(0);
 239
 240         /* Reset SDI PLL */
 241         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 242 }
 243
 244 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 245 {
 246         return dss_generic_clk_source_names[clk_src];
 247 }
 248
 249 void dss_dump_clocks(struct seq_file *s)
 250 {
 251         unsigned long dpll4_ck_rate;
 252         unsigned long dpll4_m4_ck_rate;
 253         const char *fclk_name, *fclk_real_name;
 254         unsigned long fclk_rate;
 255
 256         if (dss_runtime_get())
 257                 return;
 258
 259         seq_printf(s, "- DSS -\n");
 260
 261         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 262         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 263         fclk_rate = clk_get_rate(dss.dss_clk);
 264
 265         if (dss.dpll4_m4_ck) {
 266                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 267                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 268
 269                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 270
 271                 seq_printf(s, "%s (%s) = %lu / %lu * %d  = %lu\n",
 272                                 fclk_name, fclk_real_name, dpll4_ck_rate,
 273                                 dpll4_ck_rate / dpll4_m4_ck_rate,
 274                                 dss.feat->dss_fck_multiplier, fclk_rate);
 275         } else {
 276                 seq_printf(s, "%s (%s) = %lu\n",
 277                                 fclk_name, fclk_real_name,
 278                                 fclk_rate);
 279         }
 280
 281         dss_runtime_put();
 282 }
 283
 284 static void dss_dump_regs(struct seq_file *s)
 285 {
 286 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 287
 288         if (dss_runtime_get())
 289                 return;
 290
 291         DUMPREG(DSS_REVISION);
 292         DUMPREG(DSS_SYSCONFIG);
 293         DUMPREG(DSS_SYSSTATUS);
 294         DUMPREG(DSS_CONTROL);
 295
 296         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 297                         OMAP_DISPLAY_TYPE_SDI) {
 298                 DUMPREG(DSS_SDI_CONTROL);
 299                 DUMPREG(DSS_PLL_CONTROL);
 300                 DUMPREG(DSS_SDI_STATUS);
 301         }
 302
 303         dss_runtime_put();
 304 #undef DUMPREG
 305 }
 306
 307 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 308 {
 309         struct platform_device *dsidev;
 310         int b;
 311         u8 start, end;
 312
 313         switch (clk_src) {
 314         case OMAP_DSS_CLK_SRC_FCK:
 315                 b = 0;
 316                 break;
 317         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 318                 b = 1;
 319                 dsidev = dsi_get_dsidev_from_id(0);
 320                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 321                 break;
 322         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 323                 b = 2;
 324                 dsidev = dsi_get_dsidev_from_id(1);
 325                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 326                 break;
 327         default:
 328                 BUG();
 329                 return;
 330         }
 331
 332         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 333
 334         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 335
 336         dss.dispc_clk_source = clk_src;
 337 }
 338
 339 void dss_select_dsi_clk_source(int dsi_module,
 340                 enum omap_dss_clk_source clk_src)
 341 {
 342         struct platform_device *dsidev;
 343         int b, pos;
 344
 345         switch (clk_src) {
 346         case OMAP_DSS_CLK_SRC_FCK:
 347                 b = 0;
 348                 break;
 349         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 350                 BUG_ON(dsi_module != 0);
 351                 b = 1;
 352                 dsidev = dsi_get_dsidev_from_id(0);
 353                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 354                 break;
 355         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 356                 BUG_ON(dsi_module != 1);
 357                 b = 1;
 358                 dsidev = dsi_get_dsidev_from_id(1);
 359                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 360                 break;
 361         default:
 362                 BUG();
 363                 return;
 364         }
 365
 366         pos = dsi_module == 0 ? 1 : 10;
 367         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 368
 369         dss.dsi_clk_source[dsi_module] = clk_src;
 370 }
 371
 372 void dss_select_lcd_clk_source(enum omap_channel channel,
 373                 enum omap_dss_clk_source clk_src)
 374 {
 375         struct platform_device *dsidev;
 376         int b, ix, pos;
 377
 378         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 379                 dss_select_dispc_clk_source(clk_src);
 380                 return;
 381         }
 382
 383         switch (clk_src) {
 384         case OMAP_DSS_CLK_SRC_FCK:
 385                 b = 0;
 386                 break;
 387         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 388                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 389                 b = 1;
 390                 dsidev = dsi_get_dsidev_from_id(0);
 391                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 392                 break;
 393         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 394                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 395                        channel != OMAP_DSS_CHANNEL_LCD3);
 396                 b = 1;
 397                 dsidev = dsi_get_dsidev_from_id(1);
 398                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 399                 break;
 400         default:
 401                 BUG();
 402                 return;
 403         }
 404
 405         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 406              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 407         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 408
 409         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 410             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 411         dss.lcd_clk_source[ix] = clk_src;
 412 }
 413
 414 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 415 {
 416         return dss.dispc_clk_source;
 417 }
 418
 419 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 420 {
 421         return dss.dsi_clk_source[dsi_module];
 422 }
 423
 424 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 425 {
 426         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 427                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 428                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 429                 return dss.lcd_clk_source[ix];
 430         } else {
 431                 /* LCD_CLK source is the same as DISPC_FCLK source for
 432                  * OMAP2 and OMAP3 */
 433                 return dss.dispc_clk_source;
 434         }
 435 }
 436
 437 /* calculate clock rates using dividers in cinfo */
 438 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 439 {
 440         if (dss.dpll4_m4_ck) {
 441                 unsigned long prate;
 442
 443                 if (cinfo->fck_div > dss.feat->fck_div_max ||
 444                                 cinfo->fck_div == 0)
 445                         return -EINVAL;
 446
 447                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 448
 449                 cinfo->fck = prate / cinfo->fck_div *
 450                         dss.feat->dss_fck_multiplier;
 451         } else {
 452                 if (cinfo->fck_div != 0)
 453                         return -EINVAL;
 454                 cinfo->fck = clk_get_rate(dss.dss_clk);
 455         }
 456
 457         return 0;
 458 }
 459
 460 int dss_set_clock_div(struct dss_clock_info *cinfo)
 461 {
 462         if (dss.dpll4_m4_ck) {
 463                 unsigned long prate;
 464                 int r;
 465
 466                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 467                 DSSDBG("dpll4_m4 = %ld\n", prate);
 468
 469                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 470                 if (r)
 471                         return r;
 472         } else {
 473                 if (cinfo->fck_div != 0)
 474                         return -EINVAL;
 475         }
 476
 477         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 478
 479         return 0;
 480 }
 481
 482 unsigned long dss_get_dpll4_rate(void)
 483 {
 484         if (dss.dpll4_m4_ck)
 485                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 486         else
 487                 return 0;
 488 }
 489
 490 static int dss_setup_default_clock(void)
 491 {
 492         unsigned long max_dss_fck, prate;
 493         unsigned fck_div;
 494         struct dss_clock_info dss_cinfo = { 0 };
 495         int r;
 496
 497         if (dss.dpll4_m4_ck == NULL)
 498                 return 0;
 499
 500         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 501
 502         prate = dss_get_dpll4_rate();
 503
 504         fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 505                         max_dss_fck);
 506
 507         dss_cinfo.fck_div = fck_div;
 508
 509         r = dss_calc_clock_rates(&dss_cinfo);
 510         if (r)
 511                 return r;
 512
 513         r = dss_set_clock_div(&dss_cinfo);
 514         if (r)
 515                 return r;
 516
 517         return 0;
 518 }
 519
 520 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
 521                 struct dispc_clock_info *dispc_cinfo)
 522 {
 523         unsigned long prate;
 524         struct dss_clock_info best_dss;
 525         struct dispc_clock_info best_dispc;
 526
 527         unsigned long fck, max_dss_fck;
 528
 529         u16 fck_div;
 530
 531         int match = 0;
 532         int min_fck_per_pck;
 533
 534         prate = dss_get_dpll4_rate();
 535
 536         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 537
 538         fck = clk_get_rate(dss.dss_clk);
 539         if (req_pck == dss.cache_req_pck && prate == dss.cache_prate &&
 540                 dss.cache_dss_cinfo.fck == fck) {
 541                 DSSDBG("dispc clock info found from cache.\n");
 542                 *dss_cinfo = dss.cache_dss_cinfo;
 543                 *dispc_cinfo = dss.cache_dispc_cinfo;
 544                 return 0;
 545         }
 546
 547         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 548
 549         if (min_fck_per_pck &&
 550                 req_pck * min_fck_per_pck > max_dss_fck) {
 551                 DSSERR("Requested pixel clock not possible with the current "
 552                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 553                                 "the constraint off.\n");
 554                 min_fck_per_pck = 0;
 555         }
 556
 557 retry:
 558         memset(&best_dss, 0, sizeof(best_dss));
 559         memset(&best_dispc, 0, sizeof(best_dispc));
 560
 561         if (dss.dpll4_m4_ck == NULL) {
 562                 struct dispc_clock_info cur_dispc;
 563                 /* XXX can we change the clock on omap2? */
 564                 fck = clk_get_rate(dss.dss_clk);
 565                 fck_div = 1;
 566
 567                 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
 568                 match = 1;
 569
 570                 best_dss.fck = fck;
 571                 best_dss.fck_div = fck_div;
 572
 573                 best_dispc = cur_dispc;
 574
 575                 goto found;
 576         } else {
 577                 for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) {
 578                         struct dispc_clock_info cur_dispc;
 579
 580                         fck = prate / fck_div * dss.feat->dss_fck_multiplier;
 581
 582                         if (fck > max_dss_fck)
 583                                 continue;
 584
 585                         if (min_fck_per_pck &&
 586                                         fck < req_pck * min_fck_per_pck)
 587                                 continue;
 588
 589                         match = 1;
 590
 591                         dispc_find_clk_divs(req_pck, fck, &cur_dispc);
 592
 593                         if (abs(cur_dispc.pck - req_pck) <
 594                                         abs(best_dispc.pck - req_pck)) {
 595
 596                                 best_dss.fck = fck;
 597                                 best_dss.fck_div = fck_div;
 598
 599                                 best_dispc = cur_dispc;
 600
 601                                 if (cur_dispc.pck == req_pck)
 602                                         goto found;
 603                         }
 604                 }
 605         }
 606
 607 found:
 608         if (!match) {
 609                 if (min_fck_per_pck) {
 610                         DSSERR("Could not find suitable clock settings.\n"
 611                                         "Turning FCK/PCK constraint off and"
 612                                         "trying again.\n");
 613                         min_fck_per_pck = 0;
 614                         goto retry;
 615                 }
 616
 617                 DSSERR("Could not find suitable clock settings.\n");
 618
 619                 return -EINVAL;
 620         }
 621
 622         if (dss_cinfo)
 623                 *dss_cinfo = best_dss;
 624         if (dispc_cinfo)
 625                 *dispc_cinfo = best_dispc;
 626
 627         dss.cache_req_pck = req_pck;
 628         dss.cache_prate = prate;
 629         dss.cache_dss_cinfo = best_dss;
 630         dss.cache_dispc_cinfo = best_dispc;
 631
 632         return 0;
 633 }
 634
 635 void dss_set_venc_output(enum omap_dss_venc_type type)
 636 {
 637         int l = 0;
 638
 639         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 640                 l = 0;
 641         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 642                 l = 1;
 643         else
 644                 BUG();
 645
 646         /* venc out selection. 0 = comp, 1 = svideo */
 647         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 648 }
 649
 650 void dss_set_dac_pwrdn_bgz(bool enable)
 651 {
 652         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 653 }
 654
 655 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 656 {
 657         enum omap_display_type dp;
 658         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 659
 660         /* Complain about invalid selections */
 661         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 662         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 663
 664         /* Select only if we have options */
 665         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 666                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 667 }
 668
 669 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 670 {
 671         enum omap_display_type displays;
 672
 673         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 674         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 675                 return DSS_VENC_TV_CLK;
 676
 677         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 678                 return DSS_HDMI_M_PCLK;
 679
 680         return REG_GET(DSS_CONTROL, 15, 15);
 681 }
 682
 683 static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
 684 {
 685         if (channel != OMAP_DSS_CHANNEL_LCD)
 686                 return -EINVAL;
 687
 688         return 0;
 689 }
 690
 691 static int dss_dpi_select_source_omap4(enum omap_channel channel)
 692 {
 693         int val;
 694
 695         switch (channel) {
 696         case OMAP_DSS_CHANNEL_LCD2:
 697                 val = 0;
 698                 break;
 699         case OMAP_DSS_CHANNEL_DIGIT:
 700                 val = 1;
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705
 706         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 707
 708         return 0;
 709 }
 710
 711 static int dss_dpi_select_source_omap5(enum omap_channel channel)
 712 {
 713         int val;
 714
 715         switch (channel) {
 716         case OMAP_DSS_CHANNEL_LCD:
 717                 val = 1;
 718                 break;
 719         case OMAP_DSS_CHANNEL_LCD2:
 720                 val = 2;
 721                 break;
 722         case OMAP_DSS_CHANNEL_LCD3:
 723                 val = 3;
 724                 break;
 725         case OMAP_DSS_CHANNEL_DIGIT:
 726                 val = 0;
 727                 break;
 728         default:
 729                 return -EINVAL;
 730         }
 731
 732         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 733
 734         return 0;
 735 }
 736
 737 int dss_dpi_select_source(enum omap_channel channel)
 738 {
 739         return dss.feat->dpi_select_source(channel);
 740 }
 741
 742 static int dss_get_clocks(void)
 743 {
 744         struct clk *clk;
 745         int r;
 746
 747         clk = clk_get(&dss.pdev->dev, "fck");
 748         if (IS_ERR(clk)) {
 749                 DSSERR("can't get clock fck\n");
 750                 r = PTR_ERR(clk);
 751                 goto err;
 752         }
 753
 754         dss.dss_clk = clk;
 755
 756         if (dss.feat->clk_name) {
 757                 clk = clk_get(NULL, dss.feat->clk_name);
 758                 if (IS_ERR(clk)) {
 759                         DSSERR("Failed to get %s\n", dss.feat->clk_name);
 760                         r = PTR_ERR(clk);
 761                         goto err;
 762                 }
 763         } else {
 764                 clk = NULL;
 765         }
 766
 767         dss.dpll4_m4_ck = clk;
 768
 769         return 0;
 770
 771 err:
 772         if (dss.dss_clk)
 773                 clk_put(dss.dss_clk);
 774         if (dss.dpll4_m4_ck)
 775                 clk_put(dss.dpll4_m4_ck);
 776
 777         return r;
 778 }
 779
 780 static void dss_put_clocks(void)
 781 {
 782         if (dss.dpll4_m4_ck)
 783                 clk_put(dss.dpll4_m4_ck);
 784         clk_put(dss.dss_clk);
 785 }
 786
 787 static int dss_runtime_get(void)
 788 {
 789         int r;
 790
 791         DSSDBG("dss_runtime_get\n");
 792
 793         r = pm_runtime_get_sync(&dss.pdev->dev);
 794         WARN_ON(r < 0);
 795         return r < 0 ? r : 0;
 796 }
 797
 798 static void dss_runtime_put(void)
 799 {
 800         int r;
 801
 802         DSSDBG("dss_runtime_put\n");
 803
 804         r = pm_runtime_put_sync(&dss.pdev->dev);
 805         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 806 }
 807
 808 /* DEBUGFS */
 809 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 810 void dss_debug_dump_clocks(struct seq_file *s)
 811 {
 812         dss_dump_clocks(s);
 813         dispc_dump_clocks(s);
 814 #ifdef CONFIG_OMAP2_DSS_DSI
 815         dsi_dump_clocks(s);
 816 #endif
 817 }
 818 #endif
 819
 820 static const struct dss_features omap24xx_dss_feats __initconst = {
 821         .fck_div_max            =       16,
 822         .dss_fck_multiplier     =       2,
 823         .clk_name               =       NULL,
 824         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 825 };
 826
 827 static const struct dss_features omap34xx_dss_feats __initconst = {
 828         .fck_div_max            =       16,
 829         .dss_fck_multiplier     =       2,
 830         .clk_name               =       "dpll4_m4_ck",
 831         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 832 };
 833
 834 static const struct dss_features omap3630_dss_feats __initconst = {
 835         .fck_div_max            =       32,
 836         .dss_fck_multiplier     =       1,
 837         .clk_name               =       "dpll4_m4_ck",
 838         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 839 };
 840
 841 static const struct dss_features omap44xx_dss_feats __initconst = {
 842         .fck_div_max            =       32,
 843         .dss_fck_multiplier     =       1,
 844         .clk_name               =       "dpll_per_m5x2_ck",
 845         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 846 };
 847
 848 static const struct dss_features omap54xx_dss_feats __initconst = {
 849         .fck_div_max            =       64,
 850         .dss_fck_multiplier     =       1,
 851         .clk_name               =       "dpll_per_h12x2_ck",
 852         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 853 };
 854
 855 static int __init dss_init_features(struct platform_device *pdev)
 856 {
 857         const struct dss_features *src;
 858         struct dss_features *dst;
 859
 860         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 861         if (!dst) {
 862                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 863                 return -ENOMEM;
 864         }
 865
 866         switch (omapdss_get_version()) {
 867         case OMAPDSS_VER_OMAP24xx:
 868                 src = &omap24xx_dss_feats;
 869                 break;
 870
 871         case OMAPDSS_VER_OMAP34xx_ES1:
 872         case OMAPDSS_VER_OMAP34xx_ES3:
 873         case OMAPDSS_VER_AM35xx:
 874                 src = &omap34xx_dss_feats;
 875                 break;
 876
 877         case OMAPDSS_VER_OMAP3630:
 878                 src = &omap3630_dss_feats;
 879                 break;
 880
 881         case OMAPDSS_VER_OMAP4430_ES1:
 882         case OMAPDSS_VER_OMAP4430_ES2:
 883         case OMAPDSS_VER_OMAP4:
 884                 src = &omap44xx_dss_feats;
 885                 break;
 886
 887         case OMAPDSS_VER_OMAP5:
 888                 src = &omap54xx_dss_feats;
 889                 break;
 890
 891         default:
 892                 return -ENODEV;
 893         }
 894
 895         memcpy(dst, src, sizeof(*dst));
 896         dss.feat = dst;
 897
 898         return 0;
 899 }
 900
 901 /* DSS HW IP initialisation */
 902 static int __init omap_dsshw_probe(struct platform_device *pdev)
 903 {
 904         struct resource *dss_mem;
 905         u32 rev;
 906         int r;
 907
 908         dss.pdev = pdev;
 909
 910         r = dss_init_features(dss.pdev);
 911         if (r)
 912                 return r;
 913
 914         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 915         if (!dss_mem) {
 916                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 917                 return -EINVAL;
 918         }
 919
 920         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
 921                                 resource_size(dss_mem));
 922         if (!dss.base) {
 923                 DSSERR("can't ioremap DSS\n");
 924                 return -ENOMEM;
 925         }
 926
 927         r = dss_get_clocks();
 928         if (r)
 929                 return r;
 930
 931         r = dss_setup_default_clock();
 932         if (r)
 933                 goto err_setup_clocks;
 934
 935         pm_runtime_enable(&pdev->dev);
 936
 937         r = dss_runtime_get();
 938         if (r)
 939                 goto err_runtime_get;
 940
 941         /* Select DPLL */
 942         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 943
 944         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
 945
 946 #ifdef CONFIG_OMAP2_DSS_VENC
 947         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 948         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 949         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 950 #endif
 951         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 952         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 953         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 954         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 955         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 956
 957         rev = dss_read_reg(DSS_REVISION);
 958         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 959                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 960
 961         dss_runtime_put();
 962
 963         dss_debugfs_create_file("dss", dss_dump_regs);
 964
 965         return 0;
 966
 967 err_runtime_get:
 968         pm_runtime_disable(&pdev->dev);
 969 err_setup_clocks:
 970         dss_put_clocks();
 971         return r;
 972 }
 973
 974 static int __exit omap_dsshw_remove(struct platform_device *pdev)
 975 {
 976         pm_runtime_disable(&pdev->dev);
 977
 978         dss_put_clocks();
 979
 980         return 0;
 981 }
 982
 983 static int dss_runtime_suspend(struct device *dev)
 984 {
 985         dss_save_context();
 986         dss_set_min_bus_tput(dev, 0);
 987         return 0;
 988 }
 989
 990 static int dss_runtime_resume(struct device *dev)
 991 {
 992         int r;
 993         /*
 994          * Set an arbitrarily high tput request to ensure OPP100.
 995          * What we should really do is to make a request to stay in OPP100,
 996          * without any tput requirements, but that is not currently possible
 997          * via the PM layer.
 998          */
 999
1000         r = dss_set_min_bus_tput(dev, 1000000000);
1001         if (r)
1002                 return r;
1003
1004         dss_restore_context();
1005         return 0;
1006 }
1007
1008 static const struct dev_pm_ops dss_pm_ops = {
1009         .runtime_suspend = dss_runtime_suspend,
1010         .runtime_resume = dss_runtime_resume,
1011 };
1012
1013 static struct platform_driver omap_dsshw_driver = {
1014         .remove         = __exit_p(omap_dsshw_remove),
1015         .driver         = {
1016                 .name   = "omapdss_dss",
1017                 .owner  = THIS_MODULE,
1018                 .pm     = &dss_pm_ops,
1019         },
1020 };
1021
1022 int __init dss_init_platform_driver(void)
1023 {
1024         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
1025 }
1026
1027 void dss_uninit_platform_driver(void)
1028 {
1029         platform_driver_unregister(&omap_dsshw_driver);
1030 }