Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/gfp.h>
  35
  36 #include <video/omapdss.h>
  37
  38 #include <plat/cpu.h>
  39
  40 #include "dss.h"
  41 #include "dss_features.h"
  42
  43 #define DSS_SZ_REGS                     SZ_512
  44
  45 struct dss_reg {
  46         u16 idx;
  47 };
  48
  49 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  50
  51 #define DSS_REVISION                    DSS_REG(0x0000)
  52 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  53 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  54 #define DSS_CONTROL                     DSS_REG(0x0040)
  55 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  56 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  57 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dss_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end) \
  63         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  64
  65 static int dss_runtime_get(void);
  66 static void dss_runtime_put(void);
  67
  68 struct dss_features {
  69         u8 fck_div_max;
  70         u8 dss_fck_multiplier;
  71         const char *clk_name;
  72 };
  73
  74 static struct {
  75         struct platform_device *pdev;
  76         void __iomem    *base;
  77
  78         struct clk      *dpll4_m4_ck;
  79         struct clk      *dss_clk;
  80
  81         unsigned long   cache_req_pck;
  82         unsigned long   cache_prate;
  83         struct dss_clock_info cache_dss_cinfo;
  84         struct dispc_clock_info cache_dispc_cinfo;
  85
  86         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  87         enum omap_dss_clk_source dispc_clk_source;
  88         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  89
  90         bool            ctx_valid;
  91         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  92
  93         const struct dss_features *feat;
  94 } dss;
  95
  96 static const char * const dss_generic_clk_source_names[] = {
  97         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  98         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  99         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 100 };
 101
 102 static const struct dss_features omap24xx_dss_feats __initconst = {
 103         .fck_div_max            =       16,
 104         .dss_fck_multiplier     =       2,
 105         .clk_name               =       NULL,
 106 };
 107
 108 static const struct dss_features omap34xx_dss_feats __initconst = {
 109         .fck_div_max            =       16,
 110         .dss_fck_multiplier     =       2,
 111         .clk_name               =       "dpll4_m4_ck",
 112 };
 113
 114 static const struct dss_features omap3630_dss_feats __initconst = {
 115         .fck_div_max            =       32,
 116         .dss_fck_multiplier     =       1,
 117         .clk_name               =       "dpll4_m4_ck",
 118 };
 119
 120 static const struct dss_features omap44xx_dss_feats __initconst = {
 121         .fck_div_max            =       32,
 122         .dss_fck_multiplier     =       1,
 123         .clk_name               =       "dpll_per_m5x2_ck",
 124 };
 125
 126 static const struct dss_features omap54xx_dss_feats __initconst = {
 127         .fck_div_max            =       64,
 128         .dss_fck_multiplier     =       1,
 129         .clk_name               =       "dpll_per_h12x2_ck",
 130 };
 131
 132 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 133 {
 134         __raw_writel(val, dss.base + idx.idx);
 135 }
 136
 137 static inline u32 dss_read_reg(const struct dss_reg idx)
 138 {
 139         return __raw_readl(dss.base + idx.idx);
 140 }
 141
 142 #define SR(reg) \
 143         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 144 #define RR(reg) \
 145         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 146
 147 static void dss_save_context(void)
 148 {
 149         DSSDBG("dss_save_context\n");
 150
 151         SR(CONTROL);
 152
 153         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 154                         OMAP_DISPLAY_TYPE_SDI) {
 155                 SR(SDI_CONTROL);
 156                 SR(PLL_CONTROL);
 157         }
 158
 159         dss.ctx_valid = true;
 160
 161         DSSDBG("context saved\n");
 162 }
 163
 164 static void dss_restore_context(void)
 165 {
 166         DSSDBG("dss_restore_context\n");
 167
 168         if (!dss.ctx_valid)
 169                 return;
 170
 171         RR(CONTROL);
 172
 173         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 174                         OMAP_DISPLAY_TYPE_SDI) {
 175                 RR(SDI_CONTROL);
 176                 RR(PLL_CONTROL);
 177         }
 178
 179         DSSDBG("context restored\n");
 180 }
 181
 182 #undef SR
 183 #undef RR
 184
 185 void dss_sdi_init(int datapairs)
 186 {
 187         u32 l;
 188
 189         BUG_ON(datapairs > 3 || datapairs < 1);
 190
 191         l = dss_read_reg(DSS_SDI_CONTROL);
 192         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 193         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 194         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 195         dss_write_reg(DSS_SDI_CONTROL, l);
 196
 197         l = dss_read_reg(DSS_PLL_CONTROL);
 198         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 199         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 200         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 201         dss_write_reg(DSS_PLL_CONTROL, l);
 202 }
 203
 204 int dss_sdi_enable(void)
 205 {
 206         unsigned long timeout;
 207
 208         dispc_pck_free_enable(1);
 209
 210         /* Reset SDI PLL */
 211         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 212         udelay(1);      /* wait 2x PCLK */
 213
 214         /* Lock SDI PLL */
 215         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 216
 217         /* Waiting for PLL lock request to complete */
 218         timeout = jiffies + msecs_to_jiffies(500);
 219         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 220                 if (time_after_eq(jiffies, timeout)) {
 221                         DSSERR("PLL lock request timed out\n");
 222                         goto err1;
 223                 }
 224         }
 225
 226         /* Clearing PLL_GO bit */
 227         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 228
 229         /* Waiting for PLL to lock */
 230         timeout = jiffies + msecs_to_jiffies(500);
 231         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 232                 if (time_after_eq(jiffies, timeout)) {
 233                         DSSERR("PLL lock timed out\n");
 234                         goto err1;
 235                 }
 236         }
 237
 238         dispc_lcd_enable_signal(1);
 239
 240         /* Waiting for SDI reset to complete */
 241         timeout = jiffies + msecs_to_jiffies(500);
 242         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 243                 if (time_after_eq(jiffies, timeout)) {
 244                         DSSERR("SDI reset timed out\n");
 245                         goto err2;
 246                 }
 247         }
 248
 249         return 0;
 250
 251  err2:
 252         dispc_lcd_enable_signal(0);
 253  err1:
 254         /* Reset SDI PLL */
 255         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 256
 257         dispc_pck_free_enable(0);
 258
 259         return -ETIMEDOUT;
 260 }
 261
 262 void dss_sdi_disable(void)
 263 {
 264         dispc_lcd_enable_signal(0);
 265
 266         dispc_pck_free_enable(0);
 267
 268         /* Reset SDI PLL */
 269         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 270 }
 271
 272 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 273 {
 274         return dss_generic_clk_source_names[clk_src];
 275 }
 276
 277 void dss_dump_clocks(struct seq_file *s)
 278 {
 279         unsigned long dpll4_ck_rate;
 280         unsigned long dpll4_m4_ck_rate;
 281         const char *fclk_name, *fclk_real_name;
 282         unsigned long fclk_rate;
 283
 284         if (dss_runtime_get())
 285                 return;
 286
 287         seq_printf(s, "- DSS -\n");
 288
 289         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 290         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 291         fclk_rate = clk_get_rate(dss.dss_clk);
 292
 293         if (dss.dpll4_m4_ck) {
 294                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 295                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 296
 297                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 298
 299                 seq_printf(s, "%s (%s) = %lu / %lu * %d  = %lu\n",
 300                                 fclk_name, fclk_real_name, dpll4_ck_rate,
 301                                 dpll4_ck_rate / dpll4_m4_ck_rate,
 302                                 dss.feat->dss_fck_multiplier, fclk_rate);
 303         } else {
 304                 seq_printf(s, "%s (%s) = %lu\n",
 305                                 fclk_name, fclk_real_name,
 306                                 fclk_rate);
 307         }
 308
 309         dss_runtime_put();
 310 }
 311
 312 static void dss_dump_regs(struct seq_file *s)
 313 {
 314 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 315
 316         if (dss_runtime_get())
 317                 return;
 318
 319         DUMPREG(DSS_REVISION);
 320         DUMPREG(DSS_SYSCONFIG);
 321         DUMPREG(DSS_SYSSTATUS);
 322         DUMPREG(DSS_CONTROL);
 323
 324         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 325                         OMAP_DISPLAY_TYPE_SDI) {
 326                 DUMPREG(DSS_SDI_CONTROL);
 327                 DUMPREG(DSS_PLL_CONTROL);
 328                 DUMPREG(DSS_SDI_STATUS);
 329         }
 330
 331         dss_runtime_put();
 332 #undef DUMPREG
 333 }
 334
 335 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 336 {
 337         struct platform_device *dsidev;
 338         int b;
 339         u8 start, end;
 340
 341         switch (clk_src) {
 342         case OMAP_DSS_CLK_SRC_FCK:
 343                 b = 0;
 344                 break;
 345         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 346                 b = 1;
 347                 dsidev = dsi_get_dsidev_from_id(0);
 348                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 349                 break;
 350         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 351                 b = 2;
 352                 dsidev = dsi_get_dsidev_from_id(1);
 353                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 354                 break;
 355         default:
 356                 BUG();
 357                 return;
 358         }
 359
 360         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 361
 362         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 363
 364         dss.dispc_clk_source = clk_src;
 365 }
 366
 367 void dss_select_dsi_clk_source(int dsi_module,
 368                 enum omap_dss_clk_source clk_src)
 369 {
 370         struct platform_device *dsidev;
 371         int b, pos;
 372
 373         switch (clk_src) {
 374         case OMAP_DSS_CLK_SRC_FCK:
 375                 b = 0;
 376                 break;
 377         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 378                 BUG_ON(dsi_module != 0);
 379                 b = 1;
 380                 dsidev = dsi_get_dsidev_from_id(0);
 381                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 382                 break;
 383         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 384                 BUG_ON(dsi_module != 1);
 385                 b = 1;
 386                 dsidev = dsi_get_dsidev_from_id(1);
 387                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 388                 break;
 389         default:
 390                 BUG();
 391                 return;
 392         }
 393
 394         pos = dsi_module == 0 ? 1 : 10;
 395         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 396
 397         dss.dsi_clk_source[dsi_module] = clk_src;
 398 }
 399
 400 void dss_select_lcd_clk_source(enum omap_channel channel,
 401                 enum omap_dss_clk_source clk_src)
 402 {
 403         struct platform_device *dsidev;
 404         int b, ix, pos;
 405
 406         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 407                 return;
 408
 409         switch (clk_src) {
 410         case OMAP_DSS_CLK_SRC_FCK:
 411                 b = 0;
 412                 break;
 413         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 414                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 415                 b = 1;
 416                 dsidev = dsi_get_dsidev_from_id(0);
 417                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 418                 break;
 419         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 420                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 421                        channel != OMAP_DSS_CHANNEL_LCD3);
 422                 b = 1;
 423                 dsidev = dsi_get_dsidev_from_id(1);
 424                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 425                 break;
 426         default:
 427                 BUG();
 428                 return;
 429         }
 430
 431         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 432              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 433         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 434
 435         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 436             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 437         dss.lcd_clk_source[ix] = clk_src;
 438 }
 439
 440 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 441 {
 442         return dss.dispc_clk_source;
 443 }
 444
 445 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 446 {
 447         return dss.dsi_clk_source[dsi_module];
 448 }
 449
 450 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 451 {
 452         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 453                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 454                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 455                 return dss.lcd_clk_source[ix];
 456         } else {
 457                 /* LCD_CLK source is the same as DISPC_FCLK source for
 458                  * OMAP2 and OMAP3 */
 459                 return dss.dispc_clk_source;
 460         }
 461 }
 462
 463 int dss_set_clock_div(struct dss_clock_info *cinfo)
 464 {
 465         if (dss.dpll4_m4_ck) {
 466                 unsigned long prate;
 467                 int r;
 468
 469                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 470                 DSSDBG("dpll4_m4 = %ld\n", prate);
 471
 472                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 473                 if (r)
 474                         return r;
 475         } else {
 476                 if (cinfo->fck_div != 0)
 477                         return -EINVAL;
 478         }
 479
 480         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 481
 482         return 0;
 483 }
 484
 485 unsigned long dss_get_dpll4_rate(void)
 486 {
 487         if (dss.dpll4_m4_ck)
 488                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 489         else
 490                 return 0;
 491 }
 492
 493 int dss_calc_clock_div(unsigned long req_pck, struct dss_clock_info *dss_cinfo,
 494                 struct dispc_clock_info *dispc_cinfo)
 495 {
 496         unsigned long prate;
 497         struct dss_clock_info best_dss;
 498         struct dispc_clock_info best_dispc;
 499
 500         unsigned long fck, max_dss_fck;
 501
 502         u16 fck_div;
 503
 504         int match = 0;
 505         int min_fck_per_pck;
 506
 507         prate = dss_get_dpll4_rate();
 508
 509         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 510
 511         fck = clk_get_rate(dss.dss_clk);
 512         if (req_pck == dss.cache_req_pck && prate == dss.cache_prate &&
 513                 dss.cache_dss_cinfo.fck == fck) {
 514                 DSSDBG("dispc clock info found from cache.\n");
 515                 *dss_cinfo = dss.cache_dss_cinfo;
 516                 *dispc_cinfo = dss.cache_dispc_cinfo;
 517                 return 0;
 518         }
 519
 520         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 521
 522         if (min_fck_per_pck &&
 523                 req_pck * min_fck_per_pck > max_dss_fck) {
 524                 DSSERR("Requested pixel clock not possible with the current "
 525                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 526                                 "the constraint off.\n");
 527                 min_fck_per_pck = 0;
 528         }
 529
 530 retry:
 531         memset(&best_dss, 0, sizeof(best_dss));
 532         memset(&best_dispc, 0, sizeof(best_dispc));
 533
 534         if (dss.dpll4_m4_ck == NULL) {
 535                 struct dispc_clock_info cur_dispc;
 536                 /* XXX can we change the clock on omap2? */
 537                 fck = clk_get_rate(dss.dss_clk);
 538                 fck_div = 1;
 539
 540                 dispc_find_clk_divs(req_pck, fck, &cur_dispc);
 541                 match = 1;
 542
 543                 best_dss.fck = fck;
 544                 best_dss.fck_div = fck_div;
 545
 546                 best_dispc = cur_dispc;
 547
 548                 goto found;
 549         } else {
 550                 for (fck_div = dss.feat->fck_div_max; fck_div > 0; --fck_div) {
 551                         struct dispc_clock_info cur_dispc;
 552
 553                         fck = prate / fck_div * dss.feat->dss_fck_multiplier;
 554
 555                         if (fck > max_dss_fck)
 556                                 continue;
 557
 558                         if (min_fck_per_pck &&
 559                                         fck < req_pck * min_fck_per_pck)
 560                                 continue;
 561
 562                         match = 1;
 563
 564                         dispc_find_clk_divs(req_pck, fck, &cur_dispc);
 565
 566                         if (abs(cur_dispc.pck - req_pck) <
 567                                         abs(best_dispc.pck - req_pck)) {
 568
 569                                 best_dss.fck = fck;
 570                                 best_dss.fck_div = fck_div;
 571
 572                                 best_dispc = cur_dispc;
 573
 574                                 if (cur_dispc.pck == req_pck)
 575                                         goto found;
 576                         }
 577                 }
 578         }
 579
 580 found:
 581         if (!match) {
 582                 if (min_fck_per_pck) {
 583                         DSSERR("Could not find suitable clock settings.\n"
 584                                         "Turning FCK/PCK constraint off and"
 585                                         "trying again.\n");
 586                         min_fck_per_pck = 0;
 587                         goto retry;
 588                 }
 589
 590                 DSSERR("Could not find suitable clock settings.\n");
 591
 592                 return -EINVAL;
 593         }
 594
 595         if (dss_cinfo)
 596                 *dss_cinfo = best_dss;
 597         if (dispc_cinfo)
 598                 *dispc_cinfo = best_dispc;
 599
 600         dss.cache_req_pck = req_pck;
 601         dss.cache_prate = prate;
 602         dss.cache_dss_cinfo = best_dss;
 603         dss.cache_dispc_cinfo = best_dispc;
 604
 605         return 0;
 606 }
 607
 608 void dss_set_venc_output(enum omap_dss_venc_type type)
 609 {
 610         int l = 0;
 611
 612         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 613                 l = 0;
 614         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 615                 l = 1;
 616         else
 617                 BUG();
 618
 619         /* venc out selection. 0 = comp, 1 = svideo */
 620         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 621 }
 622
 623 void dss_set_dac_pwrdn_bgz(bool enable)
 624 {
 625         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 626 }
 627
 628 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 629 {
 630         enum omap_display_type dp;
 631         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 632
 633         /* Complain about invalid selections */
 634         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 635         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 636
 637         /* Select only if we have options */
 638         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 639                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 640 }
 641
 642 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 643 {
 644         enum omap_display_type displays;
 645
 646         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 647         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 648                 return DSS_VENC_TV_CLK;
 649
 650         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 651                 return DSS_HDMI_M_PCLK;
 652
 653         return REG_GET(DSS_CONTROL, 15, 15);
 654 }
 655
 656 static int dss_get_clocks(void)
 657 {
 658         struct clk *clk;
 659         int r;
 660
 661         clk = clk_get(&dss.pdev->dev, "fck");
 662         if (IS_ERR(clk)) {
 663                 DSSERR("can't get clock fck\n");
 664                 r = PTR_ERR(clk);
 665                 goto err;
 666         }
 667
 668         dss.dss_clk = clk;
 669
 670         clk = clk_get(NULL, dss.feat->clk_name);
 671         if (IS_ERR(clk)) {
 672                 DSSERR("Failed to get %s\n", dss.feat->clk_name);
 673                 r = PTR_ERR(clk);
 674                 goto err;
 675         }
 676
 677         dss.dpll4_m4_ck = clk;
 678
 679         return 0;
 680
 681 err:
 682         if (dss.dss_clk)
 683                 clk_put(dss.dss_clk);
 684         if (dss.dpll4_m4_ck)
 685                 clk_put(dss.dpll4_m4_ck);
 686
 687         return r;
 688 }
 689
 690 static void dss_put_clocks(void)
 691 {
 692         if (dss.dpll4_m4_ck)
 693                 clk_put(dss.dpll4_m4_ck);
 694         clk_put(dss.dss_clk);
 695 }
 696
 697 static int dss_runtime_get(void)
 698 {
 699         int r;
 700
 701         DSSDBG("dss_runtime_get\n");
 702
 703         r = pm_runtime_get_sync(&dss.pdev->dev);
 704         WARN_ON(r < 0);
 705         return r < 0 ? r : 0;
 706 }
 707
 708 static void dss_runtime_put(void)
 709 {
 710         int r;
 711
 712         DSSDBG("dss_runtime_put\n");
 713
 714         r = pm_runtime_put_sync(&dss.pdev->dev);
 715         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 716 }
 717
 718 /* DEBUGFS */
 719 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 720 void dss_debug_dump_clocks(struct seq_file *s)
 721 {
 722         dss_dump_clocks(s);
 723         dispc_dump_clocks(s);
 724 #ifdef CONFIG_OMAP2_DSS_DSI
 725         dsi_dump_clocks(s);
 726 #endif
 727 }
 728 #endif
 729
 730 static int __init dss_init_features(struct device *dev)
 731 {
 732         const struct dss_features *src;
 733         struct dss_features *dst;
 734
 735         dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
 736         if (!dst) {
 737                 dev_err(dev, "Failed to allocate local DSS Features\n");
 738                 return -ENOMEM;
 739         }
 740
 741         if (cpu_is_omap24xx())
 742                 src = &omap24xx_dss_feats;
 743         else if (cpu_is_omap34xx())
 744                 src = &omap34xx_dss_feats;
 745         else if (cpu_is_omap3630())
 746                 src = &omap3630_dss_feats;
 747         else if (cpu_is_omap44xx())
 748                 src = &omap44xx_dss_feats;
 749         else if (soc_is_omap54xx())
 750                 src = &omap54xx_dss_feats;
 751         else
 752                 return -ENODEV;
 753
 754         memcpy(dst, src, sizeof(*dst));
 755         dss.feat = dst;
 756
 757         return 0;
 758 }
 759
 760 /* DSS HW IP initialisation */
 761 static int __init omap_dsshw_probe(struct platform_device *pdev)
 762 {
 763         struct resource *dss_mem;
 764         u32 rev;
 765         int r;
 766
 767         dss.pdev = pdev;
 768
 769         r = dss_init_features(&dss.pdev->dev);
 770         if (r)
 771                 return r;
 772
 773         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 774         if (!dss_mem) {
 775                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 776                 return -EINVAL;
 777         }
 778
 779         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
 780                                 resource_size(dss_mem));
 781         if (!dss.base) {
 782                 DSSERR("can't ioremap DSS\n");
 783                 return -ENOMEM;
 784         }
 785
 786         r = dss_get_clocks();
 787         if (r)
 788                 return r;
 789
 790         pm_runtime_enable(&pdev->dev);
 791
 792         r = dss_runtime_get();
 793         if (r)
 794                 goto err_runtime_get;
 795
 796         /* Select DPLL */
 797         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 798
 799 #ifdef CONFIG_OMAP2_DSS_VENC
 800         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 801         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 802         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 803 #endif
 804         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 805         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 806         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 807         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 808         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 809
 810         rev = dss_read_reg(DSS_REVISION);
 811         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 812                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 813
 814         dss_runtime_put();
 815
 816         dss_debugfs_create_file("dss", dss_dump_regs);
 817
 818         return 0;
 819
 820 err_runtime_get:
 821         pm_runtime_disable(&pdev->dev);
 822         dss_put_clocks();
 823         return r;
 824 }
 825
 826 static int __exit omap_dsshw_remove(struct platform_device *pdev)
 827 {
 828         pm_runtime_disable(&pdev->dev);
 829
 830         dss_put_clocks();
 831
 832         return 0;
 833 }
 834
 835 static int dss_runtime_suspend(struct device *dev)
 836 {
 837         dss_save_context();
 838         dss_set_min_bus_tput(dev, 0);
 839         return 0;
 840 }
 841
 842 static int dss_runtime_resume(struct device *dev)
 843 {
 844         int r;
 845         /*
 846          * Set an arbitrarily high tput request to ensure OPP100.
 847          * What we should really do is to make a request to stay in OPP100,
 848          * without any tput requirements, but that is not currently possible
 849          * via the PM layer.
 850          */
 851
 852         r = dss_set_min_bus_tput(dev, 1000000000);
 853         if (r)
 854                 return r;
 855
 856         dss_restore_context();
 857         return 0;
 858 }
 859
 860 static const struct dev_pm_ops dss_pm_ops = {
 861         .runtime_suspend = dss_runtime_suspend,
 862         .runtime_resume = dss_runtime_resume,
 863 };
 864
 865 static struct platform_driver omap_dsshw_driver = {
 866         .remove         = __exit_p(omap_dsshw_remove),
 867         .driver         = {
 868                 .name   = "omapdss_dss",
 869                 .owner  = THIS_MODULE,
 870                 .pm     = &dss_pm_ops,
 871         },
 872 };
 873
 874 int __init dss_init_platform_driver(void)
 875 {
 876         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
 877 }
 878
 879 void dss_uninit_platform_driver(void)
 880 {
 881         platform_driver_unregister(&omap_dsshw_driver);
 882 }