Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dispc.h

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.h
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  * Author: Archit Taneja <archit@ti.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #ifndef __OMAP2_DISPC_REG_H
  22 #define __OMAP2_DISPC_REG_H
  23
  24 /* DISPC common registers */
  25 #define DISPC_REVISION                  0x0000
  26 #define DISPC_SYSCONFIG                 0x0010
  27 #define DISPC_SYSSTATUS                 0x0014
  28 #define DISPC_IRQSTATUS                 0x0018
  29 #define DISPC_IRQENABLE                 0x001C
  30 #define DISPC_CONTROL                   0x0040
  31 #define DISPC_CONFIG                    0x0044
  32 #define DISPC_CAPABLE                   0x0048
  33 #define DISPC_LINE_STATUS               0x005C
  34 #define DISPC_LINE_NUMBER               0x0060
  35 #define DISPC_GLOBAL_ALPHA              0x0074
  36 #define DISPC_CONTROL2                  0x0238
  37 #define DISPC_CONFIG2                   0x0620
  38 #define DISPC_DIVISOR                   0x0804
  39 #define DISPC_GLOBAL_BUFFER             0x0800
  40 #define DISPC_CONTROL3                  0x0848
  41 #define DISPC_CONFIG3                   0x084C
  42
  43 /* DISPC overlay registers */
  44 #define DISPC_OVL_BA0(n)                (DISPC_OVL_BASE(n) + \
  45                                         DISPC_BA0_OFFSET(n))
  46 #define DISPC_OVL_BA1(n)                (DISPC_OVL_BASE(n) + \
  47                                         DISPC_BA1_OFFSET(n))
  48 #define DISPC_OVL_BA0_UV(n)             (DISPC_OVL_BASE(n) + \
  49                                         DISPC_BA0_UV_OFFSET(n))
  50 #define DISPC_OVL_BA1_UV(n)             (DISPC_OVL_BASE(n) + \
  51                                         DISPC_BA1_UV_OFFSET(n))
  52 #define DISPC_OVL_POSITION(n)           (DISPC_OVL_BASE(n) + \
  53                                         DISPC_POS_OFFSET(n))
  54 #define DISPC_OVL_SIZE(n)               (DISPC_OVL_BASE(n) + \
  55                                         DISPC_SIZE_OFFSET(n))
  56 #define DISPC_OVL_ATTRIBUTES(n)         (DISPC_OVL_BASE(n) + \
  57                                         DISPC_ATTR_OFFSET(n))
  58 #define DISPC_OVL_ATTRIBUTES2(n)        (DISPC_OVL_BASE(n) + \
  59                                         DISPC_ATTR2_OFFSET(n))
  60 #define DISPC_OVL_FIFO_THRESHOLD(n)     (DISPC_OVL_BASE(n) + \
  61                                         DISPC_FIFO_THRESH_OFFSET(n))
  62 #define DISPC_OVL_FIFO_SIZE_STATUS(n)   (DISPC_OVL_BASE(n) + \
  63                                         DISPC_FIFO_SIZE_STATUS_OFFSET(n))
  64 #define DISPC_OVL_ROW_INC(n)            (DISPC_OVL_BASE(n) + \
  65                                         DISPC_ROW_INC_OFFSET(n))
  66 #define DISPC_OVL_PIXEL_INC(n)          (DISPC_OVL_BASE(n) + \
  67                                         DISPC_PIX_INC_OFFSET(n))
  68 #define DISPC_OVL_WINDOW_SKIP(n)        (DISPC_OVL_BASE(n) + \
  69                                         DISPC_WINDOW_SKIP_OFFSET(n))
  70 #define DISPC_OVL_TABLE_BA(n)           (DISPC_OVL_BASE(n) + \
  71                                         DISPC_TABLE_BA_OFFSET(n))
  72 #define DISPC_OVL_FIR(n)                (DISPC_OVL_BASE(n) + \
  73                                         DISPC_FIR_OFFSET(n))
  74 #define DISPC_OVL_FIR2(n)               (DISPC_OVL_BASE(n) + \
  75                                         DISPC_FIR2_OFFSET(n))
  76 #define DISPC_OVL_PICTURE_SIZE(n)       (DISPC_OVL_BASE(n) + \
  77                                         DISPC_PIC_SIZE_OFFSET(n))
  78 #define DISPC_OVL_ACCU0(n)              (DISPC_OVL_BASE(n) + \
  79                                         DISPC_ACCU0_OFFSET(n))
  80 #define DISPC_OVL_ACCU1(n)              (DISPC_OVL_BASE(n) + \
  81                                         DISPC_ACCU1_OFFSET(n))
  82 #define DISPC_OVL_ACCU2_0(n)            (DISPC_OVL_BASE(n) + \
  83                                         DISPC_ACCU2_0_OFFSET(n))
  84 #define DISPC_OVL_ACCU2_1(n)            (DISPC_OVL_BASE(n) + \
  85                                         DISPC_ACCU2_1_OFFSET(n))
  86 #define DISPC_OVL_FIR_COEF_H(n, i)      (DISPC_OVL_BASE(n) + \
  87                                         DISPC_FIR_COEF_H_OFFSET(n, i))
  88 #define DISPC_OVL_FIR_COEF_HV(n, i)     (DISPC_OVL_BASE(n) + \
  89                                         DISPC_FIR_COEF_HV_OFFSET(n, i))
  90 #define DISPC_OVL_FIR_COEF_H2(n, i)     (DISPC_OVL_BASE(n) + \
  91                                         DISPC_FIR_COEF_H2_OFFSET(n, i))
  92 #define DISPC_OVL_FIR_COEF_HV2(n, i)    (DISPC_OVL_BASE(n) + \
  93                                         DISPC_FIR_COEF_HV2_OFFSET(n, i))
  94 #define DISPC_OVL_CONV_COEF(n, i)       (DISPC_OVL_BASE(n) + \
  95                                         DISPC_CONV_COEF_OFFSET(n, i))
  96 #define DISPC_OVL_FIR_COEF_V(n, i)      (DISPC_OVL_BASE(n) + \
  97                                         DISPC_FIR_COEF_V_OFFSET(n, i))
  98 #define DISPC_OVL_FIR_COEF_V2(n, i)     (DISPC_OVL_BASE(n) + \
  99                                         DISPC_FIR_COEF_V2_OFFSET(n, i))
 100 #define DISPC_OVL_PRELOAD(n)            (DISPC_OVL_BASE(n) + \
 101                                         DISPC_PRELOAD_OFFSET(n))
 102
 103 /* DISPC up/downsampling FIR filter coefficient structure */
 104 struct dispc_coef {
 105         s8 hc4_vc22;
 106         s8 hc3_vc2;
 107         u8 hc2_vc1;
 108         s8 hc1_vc0;
 109         s8 hc0_vc00;
 110 };
 111
 112 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
 113
 114 /* DISPC manager/channel specific registers */
 115 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
 116 {
 117         switch (channel) {
 118         case OMAP_DSS_CHANNEL_LCD:
 119                 return 0x004C;
 120         case OMAP_DSS_CHANNEL_DIGIT:
 121                 return 0x0050;
 122         case OMAP_DSS_CHANNEL_LCD2:
 123                 return 0x03AC;
 124         case OMAP_DSS_CHANNEL_LCD3:
 125                 return 0x0814;
 126         default:
 127                 BUG();
 128                 return 0;
 129         }
 130 }
 131
 132 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
 133 {
 134         switch (channel) {
 135         case OMAP_DSS_CHANNEL_LCD:
 136                 return 0x0054;
 137         case OMAP_DSS_CHANNEL_DIGIT:
 138                 return 0x0058;
 139         case OMAP_DSS_CHANNEL_LCD2:
 140                 return 0x03B0;
 141         case OMAP_DSS_CHANNEL_LCD3:
 142                 return 0x0818;
 143         default:
 144                 BUG();
 145                 return 0;
 146         }
 147 }
 148
 149 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
 150 {
 151         switch (channel) {
 152         case OMAP_DSS_CHANNEL_LCD:
 153                 return 0x0064;
 154         case OMAP_DSS_CHANNEL_DIGIT:
 155                 BUG();
 156                 return 0;
 157         case OMAP_DSS_CHANNEL_LCD2:
 158                 return 0x0400;
 159         case OMAP_DSS_CHANNEL_LCD3:
 160                 return 0x0840;
 161         default:
 162                 BUG();
 163                 return 0;
 164         }
 165 }
 166
 167 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
 168 {
 169         switch (channel) {
 170         case OMAP_DSS_CHANNEL_LCD:
 171                 return 0x0068;
 172         case OMAP_DSS_CHANNEL_DIGIT:
 173                 BUG();
 174                 return 0;
 175         case OMAP_DSS_CHANNEL_LCD2:
 176                 return 0x0404;
 177         case OMAP_DSS_CHANNEL_LCD3:
 178                 return 0x0844;
 179         default:
 180                 BUG();
 181                 return 0;
 182         }
 183 }
 184
 185 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
 186 {
 187         switch (channel) {
 188         case OMAP_DSS_CHANNEL_LCD:
 189                 return 0x006C;
 190         case OMAP_DSS_CHANNEL_DIGIT:
 191                 BUG();
 192                 return 0;
 193         case OMAP_DSS_CHANNEL_LCD2:
 194                 return 0x0408;
 195         case OMAP_DSS_CHANNEL_LCD3:
 196                 return 0x083C;
 197         default:
 198                 BUG();
 199                 return 0;
 200         }
 201 }
 202
 203 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
 204 {
 205         switch (channel) {
 206         case OMAP_DSS_CHANNEL_LCD:
 207                 return 0x0070;
 208         case OMAP_DSS_CHANNEL_DIGIT:
 209                 BUG();
 210                 return 0;
 211         case OMAP_DSS_CHANNEL_LCD2:
 212                 return 0x040C;
 213         case OMAP_DSS_CHANNEL_LCD3:
 214                 return 0x0838;
 215         default:
 216                 BUG();
 217                 return 0;
 218         }
 219 }
 220
 221 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
 222 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
 223 {
 224         switch (channel) {
 225         case OMAP_DSS_CHANNEL_LCD:
 226                 return 0x007C;
 227         case OMAP_DSS_CHANNEL_DIGIT:
 228                 return 0x0078;
 229         case OMAP_DSS_CHANNEL_LCD2:
 230                 return 0x03CC;
 231         case OMAP_DSS_CHANNEL_LCD3:
 232                 return 0x0834;
 233         default:
 234                 BUG();
 235                 return 0;
 236         }
 237 }
 238
 239 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
 240 {
 241         switch (channel) {
 242         case OMAP_DSS_CHANNEL_LCD:
 243                 return 0x01D4;
 244         case OMAP_DSS_CHANNEL_DIGIT:
 245                 BUG();
 246                 return 0;
 247         case OMAP_DSS_CHANNEL_LCD2:
 248                 return 0x03C0;
 249         case OMAP_DSS_CHANNEL_LCD3:
 250                 return 0x0828;
 251         default:
 252                 BUG();
 253                 return 0;
 254         }
 255 }
 256
 257 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
 258 {
 259         switch (channel) {
 260         case OMAP_DSS_CHANNEL_LCD:
 261                 return 0x01D8;
 262         case OMAP_DSS_CHANNEL_DIGIT:
 263                 BUG();
 264                 return 0;
 265         case OMAP_DSS_CHANNEL_LCD2:
 266                 return 0x03C4;
 267         case OMAP_DSS_CHANNEL_LCD3:
 268                 return 0x082C;
 269         default:
 270                 BUG();
 271                 return 0;
 272         }
 273 }
 274
 275 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
 276 {
 277         switch (channel) {
 278         case OMAP_DSS_CHANNEL_LCD:
 279                 return 0x01DC;
 280         case OMAP_DSS_CHANNEL_DIGIT:
 281                 BUG();
 282                 return 0;
 283         case OMAP_DSS_CHANNEL_LCD2:
 284                 return 0x03C8;
 285         case OMAP_DSS_CHANNEL_LCD3:
 286                 return 0x0830;
 287         default:
 288                 BUG();
 289                 return 0;
 290         }
 291 }
 292
 293 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
 294 {
 295         switch (channel) {
 296         case OMAP_DSS_CHANNEL_LCD:
 297                 return 0x0220;
 298         case OMAP_DSS_CHANNEL_DIGIT:
 299                 BUG();
 300                 return 0;
 301         case OMAP_DSS_CHANNEL_LCD2:
 302                 return 0x03BC;
 303         case OMAP_DSS_CHANNEL_LCD3:
 304                 return 0x0824;
 305         default:
 306                 BUG();
 307                 return 0;
 308         }
 309 }
 310
 311 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
 312 {
 313         switch (channel) {
 314         case OMAP_DSS_CHANNEL_LCD:
 315                 return 0x0224;
 316         case OMAP_DSS_CHANNEL_DIGIT:
 317                 BUG();
 318                 return 0;
 319         case OMAP_DSS_CHANNEL_LCD2:
 320                 return 0x03B8;
 321         case OMAP_DSS_CHANNEL_LCD3:
 322                 return 0x0820;
 323         default:
 324                 BUG();
 325                 return 0;
 326         }
 327 }
 328
 329 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
 330 {
 331         switch (channel) {
 332         case OMAP_DSS_CHANNEL_LCD:
 333                 return 0x0228;
 334         case OMAP_DSS_CHANNEL_DIGIT:
 335                 BUG();
 336                 return 0;
 337         case OMAP_DSS_CHANNEL_LCD2:
 338                 return 0x03B4;
 339         case OMAP_DSS_CHANNEL_LCD3:
 340                 return 0x081C;
 341         default:
 342                 BUG();
 343                 return 0;
 344         }
 345 }
 346
 347 /* DISPC overlay register base addresses */
 348 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
 349 {
 350         switch (plane) {
 351         case OMAP_DSS_GFX:
 352                 return 0x0080;
 353         case OMAP_DSS_VIDEO1:
 354                 return 0x00BC;
 355         case OMAP_DSS_VIDEO2:
 356                 return 0x014C;
 357         case OMAP_DSS_VIDEO3:
 358                 return 0x0300;
 359         case OMAP_DSS_WB:
 360                 return 0x0500;
 361         default:
 362                 BUG();
 363                 return 0;
 364         }
 365 }
 366
 367 /* DISPC overlay register offsets */
 368 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
 369 {
 370         switch (plane) {
 371         case OMAP_DSS_GFX:
 372         case OMAP_DSS_VIDEO1:
 373         case OMAP_DSS_VIDEO2:
 374                 return 0x0000;
 375         case OMAP_DSS_VIDEO3:
 376                 return 0x0008;
 377         default:
 378                 BUG();
 379                 return 0;
 380         }
 381 }
 382
 383 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
 384 {
 385         switch (plane) {
 386         case OMAP_DSS_GFX:
 387         case OMAP_DSS_VIDEO1:
 388         case OMAP_DSS_VIDEO2:
 389                 return 0x0004;
 390         case OMAP_DSS_VIDEO3:
 391                 return 0x000C;
 392         default:
 393                 BUG();
 394                 return 0;
 395         }
 396 }
 397
 398 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
 399 {
 400         switch (plane) {
 401         case OMAP_DSS_GFX:
 402                 BUG();
 403                 return 0;
 404         case OMAP_DSS_VIDEO1:
 405                 return 0x0544;
 406         case OMAP_DSS_VIDEO2:
 407                 return 0x04BC;
 408         case OMAP_DSS_VIDEO3:
 409                 return 0x0310;
 410         default:
 411                 BUG();
 412                 return 0;
 413         }
 414 }
 415
 416 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
 417 {
 418         switch (plane) {
 419         case OMAP_DSS_GFX:
 420                 BUG();
 421                 return 0;
 422         case OMAP_DSS_VIDEO1:
 423                 return 0x0548;
 424         case OMAP_DSS_VIDEO2:
 425                 return 0x04C0;
 426         case OMAP_DSS_VIDEO3:
 427                 return 0x0314;
 428         default:
 429                 BUG();
 430                 return 0;
 431         }
 432 }
 433
 434 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
 435 {
 436         switch (plane) {
 437         case OMAP_DSS_GFX:
 438         case OMAP_DSS_VIDEO1:
 439         case OMAP_DSS_VIDEO2:
 440                 return 0x0008;
 441         case OMAP_DSS_VIDEO3:
 442                 return 0x009C;
 443         default:
 444                 BUG();
 445                 return 0;
 446         }
 447 }
 448
 449 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
 450 {
 451         switch (plane) {
 452         case OMAP_DSS_GFX:
 453         case OMAP_DSS_VIDEO1:
 454         case OMAP_DSS_VIDEO2:
 455                 return 0x000C;
 456         case OMAP_DSS_VIDEO3:
 457                 return 0x00A8;
 458         default:
 459                 BUG();
 460                 return 0;
 461         }
 462 }
 463
 464 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
 465 {
 466         switch (plane) {
 467         case OMAP_DSS_GFX:
 468                 return 0x0020;
 469         case OMAP_DSS_VIDEO1:
 470         case OMAP_DSS_VIDEO2:
 471                 return 0x0010;
 472         case OMAP_DSS_VIDEO3:
 473                 return 0x0070;
 474         default:
 475                 BUG();
 476                 return 0;
 477         }
 478 }
 479
 480 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
 481 {
 482         switch (plane) {
 483         case OMAP_DSS_GFX:
 484                 BUG();
 485                 return 0;
 486         case OMAP_DSS_VIDEO1:
 487                 return 0x0568;
 488         case OMAP_DSS_VIDEO2:
 489                 return 0x04DC;
 490         case OMAP_DSS_VIDEO3:
 491                 return 0x032C;
 492         default:
 493                 BUG();
 494                 return 0;
 495         }
 496 }
 497
 498 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
 499 {
 500         switch (plane) {
 501         case OMAP_DSS_GFX:
 502                 return 0x0024;
 503         case OMAP_DSS_VIDEO1:
 504         case OMAP_DSS_VIDEO2:
 505                 return 0x0014;
 506         case OMAP_DSS_VIDEO3:
 507                 return 0x008C;
 508         default:
 509                 BUG();
 510                 return 0;
 511         }
 512 }
 513
 514 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
 515 {
 516         switch (plane) {
 517         case OMAP_DSS_GFX:
 518                 return 0x0028;
 519         case OMAP_DSS_VIDEO1:
 520         case OMAP_DSS_VIDEO2:
 521                 return 0x0018;
 522         case OMAP_DSS_VIDEO3:
 523         case OMAP_DSS_WB:
 524                 return 0x0088;
 525         default:
 526                 BUG();
 527                 return 0;
 528         }
 529 }
 530
 531 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
 532 {
 533         switch (plane) {
 534         case OMAP_DSS_GFX:
 535                 return 0x002C;
 536         case OMAP_DSS_VIDEO1:
 537         case OMAP_DSS_VIDEO2:
 538                 return 0x001C;
 539         case OMAP_DSS_VIDEO3:
 540                 return 0x00A4;
 541         default:
 542                 BUG();
 543                 return 0;
 544         }
 545 }
 546
 547 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
 548 {
 549         switch (plane) {
 550         case OMAP_DSS_GFX:
 551                 return 0x0030;
 552         case OMAP_DSS_VIDEO1:
 553         case OMAP_DSS_VIDEO2:
 554                 return 0x0020;
 555         case OMAP_DSS_VIDEO3:
 556                 return 0x0098;
 557         default:
 558                 BUG();
 559                 return 0;
 560         }
 561 }
 562
 563 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
 564 {
 565         switch (plane) {
 566         case OMAP_DSS_GFX:
 567                 return 0x0034;
 568         case OMAP_DSS_VIDEO1:
 569         case OMAP_DSS_VIDEO2:
 570         case OMAP_DSS_VIDEO3:
 571                 BUG();
 572                 return 0;
 573         default:
 574                 BUG();
 575                 return 0;
 576         }
 577 }
 578
 579 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
 580 {
 581         switch (plane) {
 582         case OMAP_DSS_GFX:
 583                 return 0x0038;
 584         case OMAP_DSS_VIDEO1:
 585         case OMAP_DSS_VIDEO2:
 586         case OMAP_DSS_VIDEO3:
 587                 BUG();
 588                 return 0;
 589         default:
 590                 BUG();
 591                 return 0;
 592         }
 593 }
 594
 595 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
 596 {
 597         switch (plane) {
 598         case OMAP_DSS_GFX:
 599                 BUG();
 600                 return 0;
 601         case OMAP_DSS_VIDEO1:
 602         case OMAP_DSS_VIDEO2:
 603                 return 0x0024;
 604         case OMAP_DSS_VIDEO3:
 605                 return 0x0090;
 606         default:
 607                 BUG();
 608                 return 0;
 609         }
 610 }
 611
 612 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
 613 {
 614         switch (plane) {
 615         case OMAP_DSS_GFX:
 616                 BUG();
 617                 return 0;
 618         case OMAP_DSS_VIDEO1:
 619                 return 0x0580;
 620         case OMAP_DSS_VIDEO2:
 621                 return 0x055C;
 622         case OMAP_DSS_VIDEO3:
 623                 return 0x0424;
 624         default:
 625                 BUG();
 626                 return 0;
 627         }
 628 }
 629
 630 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
 631 {
 632         switch (plane) {
 633         case OMAP_DSS_GFX:
 634                 BUG();
 635                 return 0;
 636         case OMAP_DSS_VIDEO1:
 637         case OMAP_DSS_VIDEO2:
 638                 return 0x0028;
 639         case OMAP_DSS_VIDEO3:
 640                 return 0x0094;
 641         default:
 642                 BUG();
 643                 return 0;
 644         }
 645 }
 646
 647
 648 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
 649 {
 650         switch (plane) {
 651         case OMAP_DSS_GFX:
 652                 BUG();
 653                 return 0;
 654         case OMAP_DSS_VIDEO1:
 655         case OMAP_DSS_VIDEO2:
 656                 return 0x002C;
 657         case OMAP_DSS_VIDEO3:
 658                 return 0x0000;
 659         default:
 660                 BUG();
 661                 return 0;
 662         }
 663 }
 664
 665 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
 666 {
 667         switch (plane) {
 668         case OMAP_DSS_GFX:
 669                 BUG();
 670                 return 0;
 671         case OMAP_DSS_VIDEO1:
 672                 return 0x0584;
 673         case OMAP_DSS_VIDEO2:
 674                 return 0x0560;
 675         case OMAP_DSS_VIDEO3:
 676                 return 0x0428;
 677         default:
 678                 BUG();
 679                 return 0;
 680         }
 681 }
 682
 683 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
 684 {
 685         switch (plane) {
 686         case OMAP_DSS_GFX:
 687                 BUG();
 688                 return 0;
 689         case OMAP_DSS_VIDEO1:
 690         case OMAP_DSS_VIDEO2:
 691                 return 0x0030;
 692         case OMAP_DSS_VIDEO3:
 693                 return 0x0004;
 694         default:
 695                 BUG();
 696                 return 0;
 697         }
 698 }
 699
 700 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
 701 {
 702         switch (plane) {
 703         case OMAP_DSS_GFX:
 704                 BUG();
 705                 return 0;
 706         case OMAP_DSS_VIDEO1:
 707                 return 0x0588;
 708         case OMAP_DSS_VIDEO2:
 709                 return 0x0564;
 710         case OMAP_DSS_VIDEO3:
 711                 return 0x042C;
 712         default:
 713                 BUG();
 714                 return 0;
 715         }
 716 }
 717
 718 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 719 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
 720 {
 721         switch (plane) {
 722         case OMAP_DSS_GFX:
 723                 BUG();
 724                 return 0;
 725         case OMAP_DSS_VIDEO1:
 726         case OMAP_DSS_VIDEO2:
 727                 return 0x0034 + i * 0x8;
 728         case OMAP_DSS_VIDEO3:
 729                 return 0x0010 + i * 0x8;
 730         default:
 731                 BUG();
 732                 return 0;
 733         }
 734 }
 735
 736 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 737 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
 738 {
 739         switch (plane) {
 740         case OMAP_DSS_GFX:
 741                 BUG();
 742                 return 0;
 743         case OMAP_DSS_VIDEO1:
 744                 return 0x058C + i * 0x8;
 745         case OMAP_DSS_VIDEO2:
 746                 return 0x0568 + i * 0x8;
 747         case OMAP_DSS_VIDEO3:
 748                 return 0x0430 + i * 0x8;
 749         default:
 750                 BUG();
 751                 return 0;
 752         }
 753 }
 754
 755 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 756 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
 757 {
 758         switch (plane) {
 759         case OMAP_DSS_GFX:
 760                 BUG();
 761                 return 0;
 762         case OMAP_DSS_VIDEO1:
 763         case OMAP_DSS_VIDEO2:
 764                 return 0x0038 + i * 0x8;
 765         case OMAP_DSS_VIDEO3:
 766                 return 0x0014 + i * 0x8;
 767         default:
 768                 BUG();
 769                 return 0;
 770         }
 771 }
 772
 773 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 774 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
 775 {
 776         switch (plane) {
 777         case OMAP_DSS_GFX:
 778                 BUG();
 779                 return 0;
 780         case OMAP_DSS_VIDEO1:
 781                 return 0x0590 + i * 8;
 782         case OMAP_DSS_VIDEO2:
 783                 return 0x056C + i * 0x8;
 784         case OMAP_DSS_VIDEO3:
 785                 return 0x0434 + i * 0x8;
 786         default:
 787                 BUG();
 788                 return 0;
 789         }
 790 }
 791
 792 /* coef index i = {0, 1, 2, 3, 4,} */
 793 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
 794 {
 795         switch (plane) {
 796         case OMAP_DSS_GFX:
 797                 BUG();
 798                 return 0;
 799         case OMAP_DSS_VIDEO1:
 800         case OMAP_DSS_VIDEO2:
 801         case OMAP_DSS_VIDEO3:
 802                 return 0x0074 + i * 0x4;
 803         default:
 804                 BUG();
 805                 return 0;
 806         }
 807 }
 808
 809 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 810 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
 811 {
 812         switch (plane) {
 813         case OMAP_DSS_GFX:
 814                 BUG();
 815                 return 0;
 816         case OMAP_DSS_VIDEO1:
 817                 return 0x0124 + i * 0x4;
 818         case OMAP_DSS_VIDEO2:
 819                 return 0x00B4 + i * 0x4;
 820         case OMAP_DSS_VIDEO3:
 821                 return 0x0050 + i * 0x4;
 822         default:
 823                 BUG();
 824                 return 0;
 825         }
 826 }
 827
 828 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 829 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
 830 {
 831         switch (plane) {
 832         case OMAP_DSS_GFX:
 833                 BUG();
 834                 return 0;
 835         case OMAP_DSS_VIDEO1:
 836                 return 0x05CC + i * 0x4;
 837         case OMAP_DSS_VIDEO2:
 838                 return 0x05A8 + i * 0x4;
 839         case OMAP_DSS_VIDEO3:
 840                 return 0x0470 + i * 0x4;
 841         default:
 842                 BUG();
 843                 return 0;
 844         }
 845 }
 846
 847 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
 848 {
 849         switch (plane) {
 850         case OMAP_DSS_GFX:
 851                 return 0x01AC;
 852         case OMAP_DSS_VIDEO1:
 853                 return 0x0174;
 854         case OMAP_DSS_VIDEO2:
 855                 return 0x00E8;
 856         case OMAP_DSS_VIDEO3:
 857                 return 0x00A0;
 858         default:
 859                 BUG();
 860                 return 0;
 861         }
 862 }
 863 #endif