Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <video/omapdss.h>
  41
  42 #include "dss.h"
  43 #include "dss_features.h"
  44 #include "dispc.h"
  45
  46 /* DISPC */
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  50                                          DISPC_IRQ_OCP_ERR | \
  51                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  53                                          DISPC_IRQ_SYNC_LOST | \
  54                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  55
  56 #define DISPC_MAX_NR_ISRS               8
  57
  58 struct omap_dispc_isr_data {
  59         omap_dispc_isr_t        isr;
  60         void                    *arg;
  61         u32                     mask;
  62 };
  63
  64 enum omap_burst_size {
  65         BURST_SIZE_X2 = 0,
  66         BURST_SIZE_X4 = 1,
  67         BURST_SIZE_X8 = 2,
  68 };
  69
  70 #define REG_GET(idx, start, end) \
  71         FLD_GET(dispc_read_reg(idx), start, end)
  72
  73 #define REG_FLD_MOD(idx, val, start, end)                               \
  74         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  75
  76 struct dispc_irq_stats {
  77         unsigned long last_reset;
  78         unsigned irq_count;
  79         unsigned irqs[32];
  80 };
  81
  82 struct dispc_features {
  83         u8 sw_start;
  84         u8 fp_start;
  85         u8 bp_start;
  86         u16 sw_max;
  87         u16 vp_max;
  88         u16 hp_max;
  89         int (*calc_scaling) (enum omap_channel channel,
  90                 const struct omap_video_timings *mgr_timings,
  91                 u16 width, u16 height, u16 out_width, u16 out_height,
  92                 enum omap_color_mode color_mode, bool *five_taps,
  93                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
  94                 u16 pos_x, unsigned long *core_clk);
  95         unsigned long (*calc_core_clk) (enum omap_channel channel,
  96                 u16 width, u16 height, u16 out_width, u16 out_height);
  97         u8 num_fifos;
  98
  99         /* swap GFX & WB fifos */
 100         bool gfx_fifo_workaround:1;
 101 };
 102
 103 #define DISPC_MAX_NR_FIFOS 5
 104
 105 static struct {
 106         struct platform_device *pdev;
 107         void __iomem    *base;
 108
 109         int             ctx_loss_cnt;
 110
 111         int irq;
 112         struct clk *dss_clk;
 113
 114         u32 fifo_size[DISPC_MAX_NR_FIFOS];
 115         /* maps which plane is using a fifo. fifo-id -> plane-id */
 116         int fifo_assignment[DISPC_MAX_NR_FIFOS];
 117
 118         spinlock_t irq_lock;
 119         u32 irq_error_mask;
 120         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 121         u32 error_irqs;
 122         struct work_struct error_work;
 123
 124         bool            ctx_valid;
 125         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 126
 127         const struct dispc_features *feat;
 128
 129 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 130         spinlock_t irq_stats_lock;
 131         struct dispc_irq_stats irq_stats;
 132 #endif
 133 } dispc;
 134
 135 enum omap_color_component {
 136         /* used for all color formats for OMAP3 and earlier
 137          * and for RGB and Y color component on OMAP4
 138          */
 139         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 140         /* used for UV component for
 141          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 142          * color formats on OMAP4
 143          */
 144         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 145 };
 146
 147 enum mgr_reg_fields {
 148         DISPC_MGR_FLD_ENABLE,
 149         DISPC_MGR_FLD_STNTFT,
 150         DISPC_MGR_FLD_GO,
 151         DISPC_MGR_FLD_TFTDATALINES,
 152         DISPC_MGR_FLD_STALLMODE,
 153         DISPC_MGR_FLD_TCKENABLE,
 154         DISPC_MGR_FLD_TCKSELECTION,
 155         DISPC_MGR_FLD_CPR,
 156         DISPC_MGR_FLD_FIFOHANDCHECK,
 157         /* used to maintain a count of the above fields */
 158         DISPC_MGR_FLD_NUM,
 159 };
 160
 161 static const struct {
 162         const char *name;
 163         u32 vsync_irq;
 164         u32 framedone_irq;
 165         u32 sync_lost_irq;
 166         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
 167 } mgr_desc[] = {
 168         [OMAP_DSS_CHANNEL_LCD] = {
 169                 .name           = "LCD",
 170                 .vsync_irq      = DISPC_IRQ_VSYNC,
 171                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
 172                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
 173                 .reg_desc       = {
 174                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
 175                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
 176                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
 177                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
 178                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
 179                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
 180                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
 181                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
 182                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 183                 },
 184         },
 185         [OMAP_DSS_CHANNEL_DIGIT] = {
 186                 .name           = "DIGIT",
 187                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
 188                 .framedone_irq  = 0,
 189                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
 190                 .reg_desc       = {
 191                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
 192                         [DISPC_MGR_FLD_STNTFT]          = { },
 193                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
 194                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
 195                         [DISPC_MGR_FLD_STALLMODE]       = { },
 196                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
 197                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
 198                         [DISPC_MGR_FLD_CPR]             = { },
 199                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
 200                 },
 201         },
 202         [OMAP_DSS_CHANNEL_LCD2] = {
 203                 .name           = "LCD2",
 204                 .vsync_irq      = DISPC_IRQ_VSYNC2,
 205                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
 206                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
 207                 .reg_desc       = {
 208                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
 209                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
 210                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
 211                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
 212                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
 213                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
 214                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
 215                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
 216                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
 217                 },
 218         },
 219         [OMAP_DSS_CHANNEL_LCD3] = {
 220                 .name           = "LCD3",
 221                 .vsync_irq      = DISPC_IRQ_VSYNC3,
 222                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
 223                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
 224                 .reg_desc       = {
 225                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
 226                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
 227                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
 228                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
 229                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
 230                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
 231                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
 232                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
 233                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
 234                 },
 235         },
 236 };
 237
 238 static void _omap_dispc_set_irqs(void);
 239
 240 static inline void dispc_write_reg(const u16 idx, u32 val)
 241 {
 242         __raw_writel(val, dispc.base + idx);
 243 }
 244
 245 static inline u32 dispc_read_reg(const u16 idx)
 246 {
 247         return __raw_readl(dispc.base + idx);
 248 }
 249
 250 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
 251 {
 252         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 253         return REG_GET(rfld.reg, rfld.high, rfld.low);
 254 }
 255
 256 static void mgr_fld_write(enum omap_channel channel,
 257                                         enum mgr_reg_fields regfld, int val) {
 258         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
 259         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
 260 }
 261
 262 #define SR(reg) \
 263         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 264 #define RR(reg) \
 265         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 266
 267 static void dispc_save_context(void)
 268 {
 269         int i, j;
 270
 271         DSSDBG("dispc_save_context\n");
 272
 273         SR(IRQENABLE);
 274         SR(CONTROL);
 275         SR(CONFIG);
 276         SR(LINE_NUMBER);
 277         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 278                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 279                 SR(GLOBAL_ALPHA);
 280         if (dss_has_feature(FEAT_MGR_LCD2)) {
 281                 SR(CONTROL2);
 282                 SR(CONFIG2);
 283         }
 284         if (dss_has_feature(FEAT_MGR_LCD3)) {
 285                 SR(CONTROL3);
 286                 SR(CONFIG3);
 287         }
 288
 289         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 290                 SR(DEFAULT_COLOR(i));
 291                 SR(TRANS_COLOR(i));
 292                 SR(SIZE_MGR(i));
 293                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 294                         continue;
 295                 SR(TIMING_H(i));
 296                 SR(TIMING_V(i));
 297                 SR(POL_FREQ(i));
 298                 SR(DIVISORo(i));
 299
 300                 SR(DATA_CYCLE1(i));
 301                 SR(DATA_CYCLE2(i));
 302                 SR(DATA_CYCLE3(i));
 303
 304                 if (dss_has_feature(FEAT_CPR)) {
 305                         SR(CPR_COEF_R(i));
 306                         SR(CPR_COEF_G(i));
 307                         SR(CPR_COEF_B(i));
 308                 }
 309         }
 310
 311         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 312                 SR(OVL_BA0(i));
 313                 SR(OVL_BA1(i));
 314                 SR(OVL_POSITION(i));
 315                 SR(OVL_SIZE(i));
 316                 SR(OVL_ATTRIBUTES(i));
 317                 SR(OVL_FIFO_THRESHOLD(i));
 318                 SR(OVL_ROW_INC(i));
 319                 SR(OVL_PIXEL_INC(i));
 320                 if (dss_has_feature(FEAT_PRELOAD))
 321                         SR(OVL_PRELOAD(i));
 322                 if (i == OMAP_DSS_GFX) {
 323                         SR(OVL_WINDOW_SKIP(i));
 324                         SR(OVL_TABLE_BA(i));
 325                         continue;
 326                 }
 327                 SR(OVL_FIR(i));
 328                 SR(OVL_PICTURE_SIZE(i));
 329                 SR(OVL_ACCU0(i));
 330                 SR(OVL_ACCU1(i));
 331
 332                 for (j = 0; j < 8; j++)
 333                         SR(OVL_FIR_COEF_H(i, j));
 334
 335                 for (j = 0; j < 8; j++)
 336                         SR(OVL_FIR_COEF_HV(i, j));
 337
 338                 for (j = 0; j < 5; j++)
 339                         SR(OVL_CONV_COEF(i, j));
 340
 341                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 342                         for (j = 0; j < 8; j++)
 343                                 SR(OVL_FIR_COEF_V(i, j));
 344                 }
 345
 346                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 347                         SR(OVL_BA0_UV(i));
 348                         SR(OVL_BA1_UV(i));
 349                         SR(OVL_FIR2(i));
 350                         SR(OVL_ACCU2_0(i));
 351                         SR(OVL_ACCU2_1(i));
 352
 353                         for (j = 0; j < 8; j++)
 354                                 SR(OVL_FIR_COEF_H2(i, j));
 355
 356                         for (j = 0; j < 8; j++)
 357                                 SR(OVL_FIR_COEF_HV2(i, j));
 358
 359                         for (j = 0; j < 8; j++)
 360                                 SR(OVL_FIR_COEF_V2(i, j));
 361                 }
 362                 if (dss_has_feature(FEAT_ATTR2))
 363                         SR(OVL_ATTRIBUTES2(i));
 364         }
 365
 366         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 367                 SR(DIVISOR);
 368
 369         dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
 370         dispc.ctx_valid = true;
 371
 372         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 373 }
 374
 375 static void dispc_restore_context(void)
 376 {
 377         int i, j, ctx;
 378
 379         DSSDBG("dispc_restore_context\n");
 380
 381         if (!dispc.ctx_valid)
 382                 return;
 383
 384         ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
 385
 386         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 387                 return;
 388
 389         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 390                         dispc.ctx_loss_cnt, ctx);
 391
 392         /*RR(IRQENABLE);*/
 393         /*RR(CONTROL);*/
 394         RR(CONFIG);
 395         RR(LINE_NUMBER);
 396         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 397                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 398                 RR(GLOBAL_ALPHA);
 399         if (dss_has_feature(FEAT_MGR_LCD2))
 400                 RR(CONFIG2);
 401         if (dss_has_feature(FEAT_MGR_LCD3))
 402                 RR(CONFIG3);
 403
 404         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 405                 RR(DEFAULT_COLOR(i));
 406                 RR(TRANS_COLOR(i));
 407                 RR(SIZE_MGR(i));
 408                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 409                         continue;
 410                 RR(TIMING_H(i));
 411                 RR(TIMING_V(i));
 412                 RR(POL_FREQ(i));
 413                 RR(DIVISORo(i));
 414
 415                 RR(DATA_CYCLE1(i));
 416                 RR(DATA_CYCLE2(i));
 417                 RR(DATA_CYCLE3(i));
 418
 419                 if (dss_has_feature(FEAT_CPR)) {
 420                         RR(CPR_COEF_R(i));
 421                         RR(CPR_COEF_G(i));
 422                         RR(CPR_COEF_B(i));
 423                 }
 424         }
 425
 426         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 427                 RR(OVL_BA0(i));
 428                 RR(OVL_BA1(i));
 429                 RR(OVL_POSITION(i));
 430                 RR(OVL_SIZE(i));
 431                 RR(OVL_ATTRIBUTES(i));
 432                 RR(OVL_FIFO_THRESHOLD(i));
 433                 RR(OVL_ROW_INC(i));
 434                 RR(OVL_PIXEL_INC(i));
 435                 if (dss_has_feature(FEAT_PRELOAD))
 436                         RR(OVL_PRELOAD(i));
 437                 if (i == OMAP_DSS_GFX) {
 438                         RR(OVL_WINDOW_SKIP(i));
 439                         RR(OVL_TABLE_BA(i));
 440                         continue;
 441                 }
 442                 RR(OVL_FIR(i));
 443                 RR(OVL_PICTURE_SIZE(i));
 444                 RR(OVL_ACCU0(i));
 445                 RR(OVL_ACCU1(i));
 446
 447                 for (j = 0; j < 8; j++)
 448                         RR(OVL_FIR_COEF_H(i, j));
 449
 450                 for (j = 0; j < 8; j++)
 451                         RR(OVL_FIR_COEF_HV(i, j));
 452
 453                 for (j = 0; j < 5; j++)
 454                         RR(OVL_CONV_COEF(i, j));
 455
 456                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 457                         for (j = 0; j < 8; j++)
 458                                 RR(OVL_FIR_COEF_V(i, j));
 459                 }
 460
 461                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 462                         RR(OVL_BA0_UV(i));
 463                         RR(OVL_BA1_UV(i));
 464                         RR(OVL_FIR2(i));
 465                         RR(OVL_ACCU2_0(i));
 466                         RR(OVL_ACCU2_1(i));
 467
 468                         for (j = 0; j < 8; j++)
 469                                 RR(OVL_FIR_COEF_H2(i, j));
 470
 471                         for (j = 0; j < 8; j++)
 472                                 RR(OVL_FIR_COEF_HV2(i, j));
 473
 474                         for (j = 0; j < 8; j++)
 475                                 RR(OVL_FIR_COEF_V2(i, j));
 476                 }
 477                 if (dss_has_feature(FEAT_ATTR2))
 478                         RR(OVL_ATTRIBUTES2(i));
 479         }
 480
 481         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 482                 RR(DIVISOR);
 483
 484         /* enable last, because LCD & DIGIT enable are here */
 485         RR(CONTROL);
 486         if (dss_has_feature(FEAT_MGR_LCD2))
 487                 RR(CONTROL2);
 488         if (dss_has_feature(FEAT_MGR_LCD3))
 489                 RR(CONTROL3);
 490         /* clear spurious SYNC_LOST_DIGIT interrupts */
 491         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 492
 493         /*
 494          * enable last so IRQs won't trigger before
 495          * the context is fully restored
 496          */
 497         RR(IRQENABLE);
 498
 499         DSSDBG("context restored\n");
 500 }
 501
 502 #undef SR
 503 #undef RR
 504
 505 int dispc_runtime_get(void)
 506 {
 507         int r;
 508
 509         DSSDBG("dispc_runtime_get\n");
 510
 511         r = pm_runtime_get_sync(&dispc.pdev->dev);
 512         WARN_ON(r < 0);
 513         return r < 0 ? r : 0;
 514 }
 515
 516 void dispc_runtime_put(void)
 517 {
 518         int r;
 519
 520         DSSDBG("dispc_runtime_put\n");
 521
 522         r = pm_runtime_put_sync(&dispc.pdev->dev);
 523         WARN_ON(r < 0 && r != -ENOSYS);
 524 }
 525
 526 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 527 {
 528         return mgr_desc[channel].vsync_irq;
 529 }
 530
 531 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 532 {
 533         return mgr_desc[channel].framedone_irq;
 534 }
 535
 536 bool dispc_mgr_go_busy(enum omap_channel channel)
 537 {
 538         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 539 }
 540
 541 void dispc_mgr_go(enum omap_channel channel)
 542 {
 543         bool enable_bit, go_bit;
 544
 545         /* if the channel is not enabled, we don't need GO */
 546         enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
 547
 548         if (!enable_bit)
 549                 return;
 550
 551         go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
 552
 553         if (go_bit) {
 554                 DSSERR("GO bit not down for channel %d\n", channel);
 555                 return;
 556         }
 557
 558         DSSDBG("GO %s\n", mgr_desc[channel].name);
 559
 560         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
 561 }
 562
 563 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 564 {
 565         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 566 }
 567
 568 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 569 {
 570         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 571 }
 572
 573 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 574 {
 575         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 576 }
 577
 578 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 579 {
 580         BUG_ON(plane == OMAP_DSS_GFX);
 581
 582         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 583 }
 584
 585 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 586                 u32 value)
 587 {
 588         BUG_ON(plane == OMAP_DSS_GFX);
 589
 590         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 591 }
 592
 593 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 594 {
 595         BUG_ON(plane == OMAP_DSS_GFX);
 596
 597         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 598 }
 599
 600 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 601                                 int fir_vinc, int five_taps,
 602                                 enum omap_color_component color_comp)
 603 {
 604         const struct dispc_coef *h_coef, *v_coef;
 605         int i;
 606
 607         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 608         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 609
 610         for (i = 0; i < 8; i++) {
 611                 u32 h, hv;
 612
 613                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 614                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 615                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 616                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 617                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 618                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 619                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 620                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 621
 622                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 623                         dispc_ovl_write_firh_reg(plane, i, h);
 624                         dispc_ovl_write_firhv_reg(plane, i, hv);
 625                 } else {
 626                         dispc_ovl_write_firh2_reg(plane, i, h);
 627                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 628                 }
 629
 630         }
 631
 632         if (five_taps) {
 633                 for (i = 0; i < 8; i++) {
 634                         u32 v;
 635                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 636                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 637                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 638                                 dispc_ovl_write_firv_reg(plane, i, v);
 639                         else
 640                                 dispc_ovl_write_firv2_reg(plane, i, v);
 641                 }
 642         }
 643 }
 644
 645 static void _dispc_setup_color_conv_coef(void)
 646 {
 647         int i;
 648         const struct color_conv_coef {
 649                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 650                 int  full_range;
 651         }  ctbl_bt601_5 = {
 652                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 653         };
 654
 655         const struct color_conv_coef *ct;
 656
 657 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 658
 659         ct = &ctbl_bt601_5;
 660
 661         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 662                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 663                         CVAL(ct->rcr, ct->ry));
 664                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 665                         CVAL(ct->gy,  ct->rcb));
 666                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 667                         CVAL(ct->gcb, ct->gcr));
 668                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 669                         CVAL(ct->bcr, ct->by));
 670                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 671                         CVAL(0, ct->bcb));
 672
 673                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 674                         11, 11);
 675         }
 676
 677 #undef CVAL
 678 }
 679
 680
 681 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 682 {
 683         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 684 }
 685
 686 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 687 {
 688         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 689 }
 690
 691 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 692 {
 693         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 694 }
 695
 696 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 697 {
 698         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 699 }
 700
 701 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 702 {
 703         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 704
 705         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 706 }
 707
 708 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 709 {
 710         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 711
 712         if (plane == OMAP_DSS_GFX)
 713                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 714         else
 715                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 716 }
 717
 718 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 719 {
 720         u32 val;
 721
 722         BUG_ON(plane == OMAP_DSS_GFX);
 723
 724         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 725
 726         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 727 }
 728
 729 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
 730 {
 731         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 732
 733         if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 734                 return;
 735
 736         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 737 }
 738
 739 static void dispc_ovl_enable_zorder_planes(void)
 740 {
 741         int i;
 742
 743         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 744                 return;
 745
 746         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 747                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 748 }
 749
 750 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 751 {
 752         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 753
 754         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 755                 return;
 756
 757         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 758 }
 759
 760 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 761 {
 762         static const unsigned shifts[] = { 0, 8, 16, 24, };
 763         int shift;
 764         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 765
 766         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 767                 return;
 768
 769         shift = shifts[plane];
 770         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 771 }
 772
 773 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 774 {
 775         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 776 }
 777
 778 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 779 {
 780         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 781 }
 782
 783 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 784                 enum omap_color_mode color_mode)
 785 {
 786         u32 m = 0;
 787         if (plane != OMAP_DSS_GFX) {
 788                 switch (color_mode) {
 789                 case OMAP_DSS_COLOR_NV12:
 790                         m = 0x0; break;
 791                 case OMAP_DSS_COLOR_RGBX16:
 792                         m = 0x1; break;
 793                 case OMAP_DSS_COLOR_RGBA16:
 794                         m = 0x2; break;
 795                 case OMAP_DSS_COLOR_RGB12U:
 796                         m = 0x4; break;
 797                 case OMAP_DSS_COLOR_ARGB16:
 798                         m = 0x5; break;
 799                 case OMAP_DSS_COLOR_RGB16:
 800                         m = 0x6; break;
 801                 case OMAP_DSS_COLOR_ARGB16_1555:
 802                         m = 0x7; break;
 803                 case OMAP_DSS_COLOR_RGB24U:
 804                         m = 0x8; break;
 805                 case OMAP_DSS_COLOR_RGB24P:
 806                         m = 0x9; break;
 807                 case OMAP_DSS_COLOR_YUV2:
 808                         m = 0xa; break;
 809                 case OMAP_DSS_COLOR_UYVY:
 810                         m = 0xb; break;
 811                 case OMAP_DSS_COLOR_ARGB32:
 812                         m = 0xc; break;
 813                 case OMAP_DSS_COLOR_RGBA32:
 814                         m = 0xd; break;
 815                 case OMAP_DSS_COLOR_RGBX32:
 816                         m = 0xe; break;
 817                 case OMAP_DSS_COLOR_XRGB16_1555:
 818                         m = 0xf; break;
 819                 default:
 820                         BUG(); return;
 821                 }
 822         } else {
 823                 switch (color_mode) {
 824                 case OMAP_DSS_COLOR_CLUT1:
 825                         m = 0x0; break;
 826                 case OMAP_DSS_COLOR_CLUT2:
 827                         m = 0x1; break;
 828                 case OMAP_DSS_COLOR_CLUT4:
 829                         m = 0x2; break;
 830                 case OMAP_DSS_COLOR_CLUT8:
 831                         m = 0x3; break;
 832                 case OMAP_DSS_COLOR_RGB12U:
 833                         m = 0x4; break;
 834                 case OMAP_DSS_COLOR_ARGB16:
 835                         m = 0x5; break;
 836                 case OMAP_DSS_COLOR_RGB16:
 837                         m = 0x6; break;
 838                 case OMAP_DSS_COLOR_ARGB16_1555:
 839                         m = 0x7; break;
 840                 case OMAP_DSS_COLOR_RGB24U:
 841                         m = 0x8; break;
 842                 case OMAP_DSS_COLOR_RGB24P:
 843                         m = 0x9; break;
 844                 case OMAP_DSS_COLOR_RGBX16:
 845                         m = 0xa; break;
 846                 case OMAP_DSS_COLOR_RGBA16:
 847                         m = 0xb; break;
 848                 case OMAP_DSS_COLOR_ARGB32:
 849                         m = 0xc; break;
 850                 case OMAP_DSS_COLOR_RGBA32:
 851                         m = 0xd; break;
 852                 case OMAP_DSS_COLOR_RGBX32:
 853                         m = 0xe; break;
 854                 case OMAP_DSS_COLOR_XRGB16_1555:
 855                         m = 0xf; break;
 856                 default:
 857                         BUG(); return;
 858                 }
 859         }
 860
 861         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 862 }
 863
 864 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
 865                 enum omap_dss_rotation_type rotation_type)
 866 {
 867         if (dss_has_feature(FEAT_BURST_2D) == 0)
 868                 return;
 869
 870         if (rotation_type == OMAP_DSS_ROT_TILER)
 871                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
 872         else
 873                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
 874 }
 875
 876 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 877 {
 878         int shift;
 879         u32 val;
 880         int chan = 0, chan2 = 0;
 881
 882         switch (plane) {
 883         case OMAP_DSS_GFX:
 884                 shift = 8;
 885                 break;
 886         case OMAP_DSS_VIDEO1:
 887         case OMAP_DSS_VIDEO2:
 888         case OMAP_DSS_VIDEO3:
 889                 shift = 16;
 890                 break;
 891         default:
 892                 BUG();
 893                 return;
 894         }
 895
 896         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 897         if (dss_has_feature(FEAT_MGR_LCD2)) {
 898                 switch (channel) {
 899                 case OMAP_DSS_CHANNEL_LCD:
 900                         chan = 0;
 901                         chan2 = 0;
 902                         break;
 903                 case OMAP_DSS_CHANNEL_DIGIT:
 904                         chan = 1;
 905                         chan2 = 0;
 906                         break;
 907                 case OMAP_DSS_CHANNEL_LCD2:
 908                         chan = 0;
 909                         chan2 = 1;
 910                         break;
 911                 case OMAP_DSS_CHANNEL_LCD3:
 912                         if (dss_has_feature(FEAT_MGR_LCD3)) {
 913                                 chan = 0;
 914                                 chan2 = 2;
 915                         } else {
 916                                 BUG();
 917                                 return;
 918                         }
 919                         break;
 920                 default:
 921                         BUG();
 922                         return;
 923                 }
 924
 925                 val = FLD_MOD(val, chan, shift, shift);
 926                 val = FLD_MOD(val, chan2, 31, 30);
 927         } else {
 928                 val = FLD_MOD(val, channel, shift, shift);
 929         }
 930         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 931 }
 932
 933 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 934 {
 935         int shift;
 936         u32 val;
 937         enum omap_channel channel;
 938
 939         switch (plane) {
 940         case OMAP_DSS_GFX:
 941                 shift = 8;
 942                 break;
 943         case OMAP_DSS_VIDEO1:
 944         case OMAP_DSS_VIDEO2:
 945         case OMAP_DSS_VIDEO3:
 946                 shift = 16;
 947                 break;
 948         default:
 949                 BUG();
 950                 return 0;
 951         }
 952
 953         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 954
 955         if (dss_has_feature(FEAT_MGR_LCD3)) {
 956                 if (FLD_GET(val, 31, 30) == 0)
 957                         channel = FLD_GET(val, shift, shift);
 958                 else if (FLD_GET(val, 31, 30) == 1)
 959                         channel = OMAP_DSS_CHANNEL_LCD2;
 960                 else
 961                         channel = OMAP_DSS_CHANNEL_LCD3;
 962         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
 963                 if (FLD_GET(val, 31, 30) == 0)
 964                         channel = FLD_GET(val, shift, shift);
 965                 else
 966                         channel = OMAP_DSS_CHANNEL_LCD2;
 967         } else {
 968                 channel = FLD_GET(val, shift, shift);
 969         }
 970
 971         return channel;
 972 }
 973
 974 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 975                 enum omap_burst_size burst_size)
 976 {
 977         static const unsigned shifts[] = { 6, 14, 14, 14, };
 978         int shift;
 979
 980         shift = shifts[plane];
 981         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 982 }
 983
 984 static void dispc_configure_burst_sizes(void)
 985 {
 986         int i;
 987         const int burst_size = BURST_SIZE_X8;
 988
 989         /* Configure burst size always to maximum size */
 990         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 991                 dispc_ovl_set_burst_size(i, burst_size);
 992 }
 993
 994 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
 995 {
 996         unsigned unit = dss_feat_get_burst_size_unit();
 997         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 998         return unit * 8;
 999 }
1000
1001 void dispc_enable_gamma_table(bool enable)
1002 {
1003         /*
1004          * This is partially implemented to support only disabling of
1005          * the gamma table.
1006          */
1007         if (enable) {
1008                 DSSWARN("Gamma table enabling for TV not yet supported");
1009                 return;
1010         }
1011
1012         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1013 }
1014
1015 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1016 {
1017         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1018                 return;
1019
1020         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1021 }
1022
1023 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1024                 struct omap_dss_cpr_coefs *coefs)
1025 {
1026         u32 coef_r, coef_g, coef_b;
1027
1028         if (!dss_mgr_is_lcd(channel))
1029                 return;
1030
1031         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1032                 FLD_VAL(coefs->rb, 9, 0);
1033         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1034                 FLD_VAL(coefs->gb, 9, 0);
1035         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1036                 FLD_VAL(coefs->bb, 9, 0);
1037
1038         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1039         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1040         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1041 }
1042
1043 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1044 {
1045         u32 val;
1046
1047         BUG_ON(plane == OMAP_DSS_GFX);
1048
1049         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1050         val = FLD_MOD(val, enable, 9, 9);
1051         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1052 }
1053
1054 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1055 {
1056         static const unsigned shifts[] = { 5, 10, 10, 10 };
1057         int shift;
1058
1059         shift = shifts[plane];
1060         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1061 }
1062
1063 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1064                 u16 height)
1065 {
1066         u32 val;
1067
1068         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1069         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1070 }
1071
1072 static void dispc_init_fifos(void)
1073 {
1074         u32 size;
1075         int fifo;
1076         u8 start, end;
1077         u32 unit;
1078
1079         unit = dss_feat_get_buffer_size_unit();
1080
1081         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1082
1083         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1084                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1085                 size *= unit;
1086                 dispc.fifo_size[fifo] = size;
1087
1088                 /*
1089                  * By default fifos are mapped directly to overlays, fifo 0 to
1090                  * ovl 0, fifo 1 to ovl 1, etc.
1091                  */
1092                 dispc.fifo_assignment[fifo] = fifo;
1093         }
1094
1095         /*
1096          * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1097          * causes problems with certain use cases, like using the tiler in 2D
1098          * mode. The below hack swaps the fifos of GFX and WB planes, thus
1099          * giving GFX plane a larger fifo. WB but should work fine with a
1100          * smaller fifo.
1101          */
1102         if (dispc.feat->gfx_fifo_workaround) {
1103                 u32 v;
1104
1105                 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1106
1107                 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1108                 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1109                 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1110                 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1111
1112                 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1113
1114                 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1115                 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1116         }
1117 }
1118
1119 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1120 {
1121         int fifo;
1122         u32 size = 0;
1123
1124         for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1125                 if (dispc.fifo_assignment[fifo] == plane)
1126                         size += dispc.fifo_size[fifo];
1127         }
1128
1129         return size;
1130 }
1131
1132 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1133 {
1134         u8 hi_start, hi_end, lo_start, lo_end;
1135         u32 unit;
1136
1137         unit = dss_feat_get_buffer_size_unit();
1138
1139         WARN_ON(low % unit != 0);
1140         WARN_ON(high % unit != 0);
1141
1142         low /= unit;
1143         high /= unit;
1144
1145         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1146         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1147
1148         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1149                         plane,
1150                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1151                                 lo_start, lo_end) * unit,
1152                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1153                                 hi_start, hi_end) * unit,
1154                         low * unit, high * unit);
1155
1156         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1157                         FLD_VAL(high, hi_start, hi_end) |
1158                         FLD_VAL(low, lo_start, lo_end));
1159 }
1160
1161 void dispc_enable_fifomerge(bool enable)
1162 {
1163         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1164                 WARN_ON(enable);
1165                 return;
1166         }
1167
1168         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1169         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1170 }
1171
1172 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1173                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1174                 bool manual_update)
1175 {
1176         /*
1177          * All sizes are in bytes. Both the buffer and burst are made of
1178          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1179          */
1180
1181         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1182         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1183         int i;
1184
1185         burst_size = dispc_ovl_get_burst_size(plane);
1186         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1187
1188         if (use_fifomerge) {
1189                 total_fifo_size = 0;
1190                 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1191                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1192         } else {
1193                 total_fifo_size = ovl_fifo_size;
1194         }
1195
1196         /*
1197          * We use the same low threshold for both fifomerge and non-fifomerge
1198          * cases, but for fifomerge we calculate the high threshold using the
1199          * combined fifo size
1200          */
1201
1202         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1203                 *fifo_low = ovl_fifo_size - burst_size * 2;
1204                 *fifo_high = total_fifo_size - burst_size;
1205         } else {
1206                 *fifo_low = ovl_fifo_size - burst_size;
1207                 *fifo_high = total_fifo_size - buf_unit;
1208         }
1209 }
1210
1211 static void dispc_ovl_set_fir(enum omap_plane plane,
1212                                 int hinc, int vinc,
1213                                 enum omap_color_component color_comp)
1214 {
1215         u32 val;
1216
1217         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1218                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1219
1220                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1221                                         &hinc_start, &hinc_end);
1222                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1223                                         &vinc_start, &vinc_end);
1224                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1225                                 FLD_VAL(hinc, hinc_start, hinc_end);
1226
1227                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1228         } else {
1229                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1230                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1231         }
1232 }
1233
1234 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1235 {
1236         u32 val;
1237         u8 hor_start, hor_end, vert_start, vert_end;
1238
1239         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1240         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1241
1242         val = FLD_VAL(vaccu, vert_start, vert_end) |
1243                         FLD_VAL(haccu, hor_start, hor_end);
1244
1245         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1246 }
1247
1248 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1249 {
1250         u32 val;
1251         u8 hor_start, hor_end, vert_start, vert_end;
1252
1253         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1254         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1255
1256         val = FLD_VAL(vaccu, vert_start, vert_end) |
1257                         FLD_VAL(haccu, hor_start, hor_end);
1258
1259         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1260 }
1261
1262 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1263                 int vaccu)
1264 {
1265         u32 val;
1266
1267         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1268         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1269 }
1270
1271 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1272                 int vaccu)
1273 {
1274         u32 val;
1275
1276         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1277         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1278 }
1279
1280 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1281                 u16 orig_width, u16 orig_height,
1282                 u16 out_width, u16 out_height,
1283                 bool five_taps, u8 rotation,
1284                 enum omap_color_component color_comp)
1285 {
1286         int fir_hinc, fir_vinc;
1287
1288         fir_hinc = 1024 * orig_width / out_width;
1289         fir_vinc = 1024 * orig_height / out_height;
1290
1291         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1292                                 color_comp);
1293         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1294 }
1295
1296 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1297                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1298                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1299 {
1300         int h_accu2_0, h_accu2_1;
1301         int v_accu2_0, v_accu2_1;
1302         int chroma_hinc, chroma_vinc;
1303         int idx;
1304
1305         struct accu {
1306                 s8 h0_m, h0_n;
1307                 s8 h1_m, h1_n;
1308                 s8 v0_m, v0_n;
1309                 s8 v1_m, v1_n;
1310         };
1311
1312         const struct accu *accu_table;
1313         const struct accu *accu_val;
1314
1315         static const struct accu accu_nv12[4] = {
1316                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1317                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1318                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1319                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1320         };
1321
1322         static const struct accu accu_nv12_ilace[4] = {
1323                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1324                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1325                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1326                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1327         };
1328
1329         static const struct accu accu_yuv[4] = {
1330                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1331                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1332                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1333                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1334         };
1335
1336         switch (rotation) {
1337         case OMAP_DSS_ROT_0:
1338                 idx = 0;
1339                 break;
1340         case OMAP_DSS_ROT_90:
1341                 idx = 1;
1342                 break;
1343         case OMAP_DSS_ROT_180:
1344                 idx = 2;
1345                 break;
1346         case OMAP_DSS_ROT_270:
1347                 idx = 3;
1348                 break;
1349         default:
1350                 BUG();
1351                 return;
1352         }
1353
1354         switch (color_mode) {
1355         case OMAP_DSS_COLOR_NV12:
1356                 if (ilace)
1357                         accu_table = accu_nv12_ilace;
1358                 else
1359                         accu_table = accu_nv12;
1360                 break;
1361         case OMAP_DSS_COLOR_YUV2:
1362         case OMAP_DSS_COLOR_UYVY:
1363                 accu_table = accu_yuv;
1364                 break;
1365         default:
1366                 BUG();
1367                 return;
1368         }
1369
1370         accu_val = &accu_table[idx];
1371
1372         chroma_hinc = 1024 * orig_width / out_width;
1373         chroma_vinc = 1024 * orig_height / out_height;
1374
1375         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1376         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1377         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1378         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1379
1380         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1381         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1382 }
1383
1384 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1385                 u16 orig_width, u16 orig_height,
1386                 u16 out_width, u16 out_height,
1387                 bool ilace, bool five_taps,
1388                 bool fieldmode, enum omap_color_mode color_mode,
1389                 u8 rotation)
1390 {
1391         int accu0 = 0;
1392         int accu1 = 0;
1393         u32 l;
1394
1395         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1396                                 out_width, out_height, five_taps,
1397                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1398         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1399
1400         /* RESIZEENABLE and VERTICALTAPS */
1401         l &= ~((0x3 << 5) | (0x1 << 21));
1402         l |= (orig_width != out_width) ? (1 << 5) : 0;
1403         l |= (orig_height != out_height) ? (1 << 6) : 0;
1404         l |= five_taps ? (1 << 21) : 0;
1405
1406         /* VRESIZECONF and HRESIZECONF */
1407         if (dss_has_feature(FEAT_RESIZECONF)) {
1408                 l &= ~(0x3 << 7);
1409                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1410                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1411         }
1412
1413         /* LINEBUFFERSPLIT */
1414         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1415                 l &= ~(0x1 << 22);
1416                 l |= five_taps ? (1 << 22) : 0;
1417         }
1418
1419         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1420
1421         /*
1422          * field 0 = even field = bottom field
1423          * field 1 = odd field = top field
1424          */
1425         if (ilace && !fieldmode) {
1426                 accu1 = 0;
1427                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1428                 if (accu0 >= 1024/2) {
1429                         accu1 = 1024/2;
1430                         accu0 -= accu1;
1431                 }
1432         }
1433
1434         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1435         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1436 }
1437
1438 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1439                 u16 orig_width, u16 orig_height,
1440                 u16 out_width, u16 out_height,
1441                 bool ilace, bool five_taps,
1442                 bool fieldmode, enum omap_color_mode color_mode,
1443                 u8 rotation)
1444 {
1445         int scale_x = out_width != orig_width;
1446         int scale_y = out_height != orig_height;
1447
1448         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1449                 return;
1450         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1451                         color_mode != OMAP_DSS_COLOR_UYVY &&
1452                         color_mode != OMAP_DSS_COLOR_NV12)) {
1453                 /* reset chroma resampling for RGB formats  */
1454                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1455                 return;
1456         }
1457
1458         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1459                         out_height, ilace, color_mode, rotation);
1460
1461         switch (color_mode) {
1462         case OMAP_DSS_COLOR_NV12:
1463                 /* UV is subsampled by 2 vertically*/
1464                 orig_height >>= 1;
1465                 /* UV is subsampled by 2 horz.*/
1466                 orig_width >>= 1;
1467                 break;
1468         case OMAP_DSS_COLOR_YUV2:
1469         case OMAP_DSS_COLOR_UYVY:
1470                 /*For YUV422 with 90/270 rotation,
1471                  *we don't upsample chroma
1472                  */
1473                 if (rotation == OMAP_DSS_ROT_0 ||
1474                         rotation == OMAP_DSS_ROT_180)
1475                         /* UV is subsampled by 2 hrz*/
1476                         orig_width >>= 1;
1477                 /* must use FIR for YUV422 if rotated */
1478                 if (rotation != OMAP_DSS_ROT_0)
1479                         scale_x = scale_y = true;
1480                 break;
1481         default:
1482                 BUG();
1483                 return;
1484         }
1485
1486         if (out_width != orig_width)
1487                 scale_x = true;
1488         if (out_height != orig_height)
1489                 scale_y = true;
1490
1491         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1492                         out_width, out_height, five_taps,
1493                                 rotation, DISPC_COLOR_COMPONENT_UV);
1494
1495         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1496                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1497         /* set H scaling */
1498         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1499         /* set V scaling */
1500         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1501 }
1502
1503 static void dispc_ovl_set_scaling(enum omap_plane plane,
1504                 u16 orig_width, u16 orig_height,
1505                 u16 out_width, u16 out_height,
1506                 bool ilace, bool five_taps,
1507                 bool fieldmode, enum omap_color_mode color_mode,
1508                 u8 rotation)
1509 {
1510         BUG_ON(plane == OMAP_DSS_GFX);
1511
1512         dispc_ovl_set_scaling_common(plane,
1513                         orig_width, orig_height,
1514                         out_width, out_height,
1515                         ilace, five_taps,
1516                         fieldmode, color_mode,
1517                         rotation);
1518
1519         dispc_ovl_set_scaling_uv(plane,
1520                 orig_width, orig_height,
1521                 out_width, out_height,
1522                 ilace, five_taps,
1523                 fieldmode, color_mode,
1524                 rotation);
1525 }
1526
1527 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1528                 bool mirroring, enum omap_color_mode color_mode)
1529 {
1530         bool row_repeat = false;
1531         int vidrot = 0;
1532
1533         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1534                         color_mode == OMAP_DSS_COLOR_UYVY) {
1535
1536                 if (mirroring) {
1537                         switch (rotation) {
1538                         case OMAP_DSS_ROT_0:
1539                                 vidrot = 2;
1540                                 break;
1541                         case OMAP_DSS_ROT_90:
1542                                 vidrot = 1;
1543                                 break;
1544                         case OMAP_DSS_ROT_180:
1545                                 vidrot = 0;
1546                                 break;
1547                         case OMAP_DSS_ROT_270:
1548                                 vidrot = 3;
1549                                 break;
1550                         }
1551                 } else {
1552                         switch (rotation) {
1553                         case OMAP_DSS_ROT_0:
1554                                 vidrot = 0;
1555                                 break;
1556                         case OMAP_DSS_ROT_90:
1557                                 vidrot = 1;
1558                                 break;
1559                         case OMAP_DSS_ROT_180:
1560                                 vidrot = 2;
1561                                 break;
1562                         case OMAP_DSS_ROT_270:
1563                                 vidrot = 3;
1564                                 break;
1565                         }
1566                 }
1567
1568                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1569                         row_repeat = true;
1570                 else
1571                         row_repeat = false;
1572         }
1573
1574         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1575         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1576                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1577                         row_repeat ? 1 : 0, 18, 18);
1578 }
1579
1580 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1581 {
1582         switch (color_mode) {
1583         case OMAP_DSS_COLOR_CLUT1:
1584                 return 1;
1585         case OMAP_DSS_COLOR_CLUT2:
1586                 return 2;
1587         case OMAP_DSS_COLOR_CLUT4:
1588                 return 4;
1589         case OMAP_DSS_COLOR_CLUT8:
1590         case OMAP_DSS_COLOR_NV12:
1591                 return 8;
1592         case OMAP_DSS_COLOR_RGB12U:
1593         case OMAP_DSS_COLOR_RGB16:
1594         case OMAP_DSS_COLOR_ARGB16:
1595         case OMAP_DSS_COLOR_YUV2:
1596         case OMAP_DSS_COLOR_UYVY:
1597         case OMAP_DSS_COLOR_RGBA16:
1598         case OMAP_DSS_COLOR_RGBX16:
1599         case OMAP_DSS_COLOR_ARGB16_1555:
1600         case OMAP_DSS_COLOR_XRGB16_1555:
1601                 return 16;
1602         case OMAP_DSS_COLOR_RGB24P:
1603                 return 24;
1604         case OMAP_DSS_COLOR_RGB24U:
1605         case OMAP_DSS_COLOR_ARGB32:
1606         case OMAP_DSS_COLOR_RGBA32:
1607         case OMAP_DSS_COLOR_RGBX32:
1608                 return 32;
1609         default:
1610                 BUG();
1611                 return 0;
1612         }
1613 }
1614
1615 static s32 pixinc(int pixels, u8 ps)
1616 {
1617         if (pixels == 1)
1618                 return 1;
1619         else if (pixels > 1)
1620                 return 1 + (pixels - 1) * ps;
1621         else if (pixels < 0)
1622                 return 1 - (-pixels + 1) * ps;
1623         else
1624                 BUG();
1625                 return 0;
1626 }
1627
1628 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1629                 u16 screen_width,
1630                 u16 width, u16 height,
1631                 enum omap_color_mode color_mode, bool fieldmode,
1632                 unsigned int field_offset,
1633                 unsigned *offset0, unsigned *offset1,
1634                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1635 {
1636         u8 ps;
1637
1638         /* FIXME CLUT formats */
1639         switch (color_mode) {
1640         case OMAP_DSS_COLOR_CLUT1:
1641         case OMAP_DSS_COLOR_CLUT2:
1642         case OMAP_DSS_COLOR_CLUT4:
1643         case OMAP_DSS_COLOR_CLUT8:
1644                 BUG();
1645                 return;
1646         case OMAP_DSS_COLOR_YUV2:
1647         case OMAP_DSS_COLOR_UYVY:
1648                 ps = 4;
1649                 break;
1650         default:
1651                 ps = color_mode_to_bpp(color_mode) / 8;
1652                 break;
1653         }
1654
1655         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1656                         width, height);
1657
1658         /*
1659          * field 0 = even field = bottom field
1660          * field 1 = odd field = top field
1661          */
1662         switch (rotation + mirror * 4) {
1663         case OMAP_DSS_ROT_0:
1664         case OMAP_DSS_ROT_180:
1665                 /*
1666                  * If the pixel format is YUV or UYVY divide the width
1667                  * of the image by 2 for 0 and 180 degree rotation.
1668                  */
1669                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1670                         color_mode == OMAP_DSS_COLOR_UYVY)
1671                         width = width >> 1;
1672         case OMAP_DSS_ROT_90:
1673         case OMAP_DSS_ROT_270:
1674                 *offset1 = 0;
1675                 if (field_offset)
1676                         *offset0 = field_offset * screen_width * ps;
1677                 else
1678                         *offset0 = 0;
1679
1680                 *row_inc = pixinc(1 +
1681                         (y_predecim * screen_width - x_predecim * width) +
1682                         (fieldmode ? screen_width : 0), ps);
1683                 *pix_inc = pixinc(x_predecim, ps);
1684                 break;
1685
1686         case OMAP_DSS_ROT_0 + 4:
1687         case OMAP_DSS_ROT_180 + 4:
1688                 /* If the pixel format is YUV or UYVY divide the width
1689                  * of the image by 2  for 0 degree and 180 degree
1690                  */
1691                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1692                         color_mode == OMAP_DSS_COLOR_UYVY)
1693                         width = width >> 1;
1694         case OMAP_DSS_ROT_90 + 4:
1695         case OMAP_DSS_ROT_270 + 4:
1696                 *offset1 = 0;
1697                 if (field_offset)
1698                         *offset0 = field_offset * screen_width * ps;
1699                 else
1700                         *offset0 = 0;
1701                 *row_inc = pixinc(1 -
1702                         (y_predecim * screen_width + x_predecim * width) -
1703                         (fieldmode ? screen_width : 0), ps);
1704                 *pix_inc = pixinc(x_predecim, ps);
1705                 break;
1706
1707         default:
1708                 BUG();
1709                 return;
1710         }
1711 }
1712
1713 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1714                 u16 screen_width,
1715                 u16 width, u16 height,
1716                 enum omap_color_mode color_mode, bool fieldmode,
1717                 unsigned int field_offset,
1718                 unsigned *offset0, unsigned *offset1,
1719                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1720 {
1721         u8 ps;
1722         u16 fbw, fbh;
1723
1724         /* FIXME CLUT formats */
1725         switch (color_mode) {
1726         case OMAP_DSS_COLOR_CLUT1:
1727         case OMAP_DSS_COLOR_CLUT2:
1728         case OMAP_DSS_COLOR_CLUT4:
1729         case OMAP_DSS_COLOR_CLUT8:
1730                 BUG();
1731                 return;
1732         default:
1733                 ps = color_mode_to_bpp(color_mode) / 8;
1734                 break;
1735         }
1736
1737         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1738                         width, height);
1739
1740         /* width & height are overlay sizes, convert to fb sizes */
1741
1742         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1743                 fbw = width;
1744                 fbh = height;
1745         } else {
1746                 fbw = height;
1747                 fbh = width;
1748         }
1749
1750         /*
1751          * field 0 = even field = bottom field
1752          * field 1 = odd field = top field
1753          */
1754         switch (rotation + mirror * 4) {
1755         case OMAP_DSS_ROT_0:
1756                 *offset1 = 0;
1757                 if (field_offset)
1758                         *offset0 = *offset1 + field_offset * screen_width * ps;
1759                 else
1760                         *offset0 = *offset1;
1761                 *row_inc = pixinc(1 +
1762                         (y_predecim * screen_width - fbw * x_predecim) +
1763                         (fieldmode ? screen_width : 0), ps);
1764                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1765                         color_mode == OMAP_DSS_COLOR_UYVY)
1766                         *pix_inc = pixinc(x_predecim, 2 * ps);
1767                 else
1768                         *pix_inc = pixinc(x_predecim, ps);
1769                 break;
1770         case OMAP_DSS_ROT_90:
1771                 *offset1 = screen_width * (fbh - 1) * ps;
1772                 if (field_offset)
1773                         *offset0 = *offset1 + field_offset * ps;
1774                 else
1775                         *offset0 = *offset1;
1776                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1777                                 y_predecim + (fieldmode ? 1 : 0), ps);
1778                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1779                 break;
1780         case OMAP_DSS_ROT_180:
1781                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1782                 if (field_offset)
1783                         *offset0 = *offset1 - field_offset * screen_width * ps;
1784                 else
1785                         *offset0 = *offset1;
1786                 *row_inc = pixinc(-1 -
1787                         (y_predecim * screen_width - fbw * x_predecim) -
1788                         (fieldmode ? screen_width : 0), ps);
1789                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1790                         color_mode == OMAP_DSS_COLOR_UYVY)
1791                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1792                 else
1793                         *pix_inc = pixinc(-x_predecim, ps);
1794                 break;
1795         case OMAP_DSS_ROT_270:
1796                 *offset1 = (fbw - 1) * ps;
1797                 if (field_offset)
1798                         *offset0 = *offset1 - field_offset * ps;
1799                 else
1800                         *offset0 = *offset1;
1801                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1802                                 y_predecim - (fieldmode ? 1 : 0), ps);
1803                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1804                 break;
1805
1806         /* mirroring */
1807         case OMAP_DSS_ROT_0 + 4:
1808                 *offset1 = (fbw - 1) * ps;
1809                 if (field_offset)
1810                         *offset0 = *offset1 + field_offset * screen_width * ps;
1811                 else
1812                         *offset0 = *offset1;
1813                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1814                                 (fieldmode ? screen_width : 0),
1815                                 ps);
1816                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1817                         color_mode == OMAP_DSS_COLOR_UYVY)
1818                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1819                 else
1820                         *pix_inc = pixinc(-x_predecim, ps);
1821                 break;
1822
1823         case OMAP_DSS_ROT_90 + 4:
1824                 *offset1 = 0;
1825                 if (field_offset)
1826                         *offset0 = *offset1 + field_offset * ps;
1827                 else
1828                         *offset0 = *offset1;
1829                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1830                                 y_predecim + (fieldmode ? 1 : 0),
1831                                 ps);
1832                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1833                 break;
1834
1835         case OMAP_DSS_ROT_180 + 4:
1836                 *offset1 = screen_width * (fbh - 1) * ps;
1837                 if (field_offset)
1838                         *offset0 = *offset1 - field_offset * screen_width * ps;
1839                 else
1840                         *offset0 = *offset1;
1841                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1842                                 (fieldmode ? screen_width : 0),
1843                                 ps);
1844                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1845                         color_mode == OMAP_DSS_COLOR_UYVY)
1846                         *pix_inc = pixinc(x_predecim, 2 * ps);
1847                 else
1848                         *pix_inc = pixinc(x_predecim, ps);
1849                 break;
1850
1851         case OMAP_DSS_ROT_270 + 4:
1852                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1853                 if (field_offset)
1854                         *offset0 = *offset1 - field_offset * ps;
1855                 else
1856                         *offset0 = *offset1;
1857                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1858                                 y_predecim - (fieldmode ? 1 : 0),
1859                                 ps);
1860                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1861                 break;
1862
1863         default:
1864                 BUG();
1865                 return;
1866         }
1867 }
1868
1869 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1870                 enum omap_color_mode color_mode, bool fieldmode,
1871                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1872                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1873 {
1874         u8 ps;
1875
1876         switch (color_mode) {
1877         case OMAP_DSS_COLOR_CLUT1:
1878         case OMAP_DSS_COLOR_CLUT2:
1879         case OMAP_DSS_COLOR_CLUT4:
1880         case OMAP_DSS_COLOR_CLUT8:
1881                 BUG();
1882                 return;
1883         default:
1884                 ps = color_mode_to_bpp(color_mode) / 8;
1885                 break;
1886         }
1887
1888         DSSDBG("scrw %d, width %d\n", screen_width, width);
1889
1890         /*
1891          * field 0 = even field = bottom field
1892          * field 1 = odd field = top field
1893          */
1894         *offset1 = 0;
1895         if (field_offset)
1896                 *offset0 = *offset1 + field_offset * screen_width * ps;
1897         else
1898                 *offset0 = *offset1;
1899         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1900                         (fieldmode ? screen_width : 0), ps);
1901         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1902                 color_mode == OMAP_DSS_COLOR_UYVY)
1903                 *pix_inc = pixinc(x_predecim, 2 * ps);
1904         else
1905                 *pix_inc = pixinc(x_predecim, ps);
1906 }
1907
1908 /*
1909  * This function is used to avoid synclosts in OMAP3, because of some
1910  * undocumented horizontal position and timing related limitations.
1911  */
1912 static int check_horiz_timing_omap3(enum omap_channel channel,
1913                 const struct omap_video_timings *t, u16 pos_x,
1914                 u16 width, u16 height, u16 out_width, u16 out_height)
1915 {
1916         int DS = DIV_ROUND_UP(height, out_height);
1917         unsigned long nonactive, lclk, pclk;
1918         static const u8 limits[3] = { 8, 10, 20 };
1919         u64 val, blank;
1920         int i;
1921
1922         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
1923         pclk = dispc_mgr_pclk_rate(channel);
1924         if (dss_mgr_is_lcd(channel))
1925                 lclk = dispc_mgr_lclk_rate(channel);
1926         else
1927                 lclk = dispc_fclk_rate();
1928
1929         i = 0;
1930         if (out_height < height)
1931                 i++;
1932         if (out_width < width)
1933                 i++;
1934         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
1935         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1936         if (blank <= limits[i])
1937                 return -EINVAL;
1938
1939         /*
1940          * Pixel data should be prepared before visible display point starts.
1941          * So, atleast DS-2 lines must have already been fetched by DISPC
1942          * during nonactive - pos_x period.
1943          */
1944         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1945         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1946                 val, max(0, DS - 2) * width);
1947         if (val < max(0, DS - 2) * width)
1948                 return -EINVAL;
1949
1950         /*
1951          * All lines need to be refilled during the nonactive period of which
1952          * only one line can be loaded during the active period. So, atleast
1953          * DS - 1 lines should be loaded during nonactive period.
1954          */
1955         val =  div_u64((u64)nonactive * lclk, pclk);
1956         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
1957                 val, max(0, DS - 1) * width);
1958         if (val < max(0, DS - 1) * width)
1959                 return -EINVAL;
1960
1961         return 0;
1962 }
1963
1964 static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
1965                 const struct omap_video_timings *mgr_timings, u16 width,
1966                 u16 height, u16 out_width, u16 out_height,
1967                 enum omap_color_mode color_mode)
1968 {
1969         u32 core_clk = 0;
1970         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1971
1972         if (height <= out_height && width <= out_width)
1973                 return (unsigned long) pclk;
1974
1975         if (height > out_height) {
1976                 unsigned int ppl = mgr_timings->x_res;
1977
1978                 tmp = pclk * height * out_width;
1979                 do_div(tmp, 2 * out_height * ppl);
1980                 core_clk = tmp;
1981
1982                 if (height > 2 * out_height) {
1983                         if (ppl == out_width)
1984                                 return 0;
1985
1986                         tmp = pclk * (height - 2 * out_height) * out_width;
1987                         do_div(tmp, 2 * out_height * (ppl - out_width));
1988                         core_clk = max_t(u32, core_clk, tmp);
1989                 }
1990         }
1991
1992         if (width > out_width) {
1993                 tmp = pclk * width;
1994                 do_div(tmp, out_width);
1995                 core_clk = max_t(u32, core_clk, tmp);
1996
1997                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1998                         core_clk <<= 1;
1999         }
2000
2001         return core_clk;
2002 }
2003
2004 static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width,
2005                 u16 height, u16 out_width, u16 out_height)
2006 {
2007         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2008
2009         if (height > out_height && width > out_width)
2010                 return pclk * 4;
2011         else
2012                 return pclk * 2;
2013 }
2014
2015 static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width,
2016                 u16 height, u16 out_width, u16 out_height)
2017 {
2018         unsigned int hf, vf;
2019         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2020
2021         /*
2022          * FIXME how to determine the 'A' factor
2023          * for the no downscaling case ?
2024          */
2025
2026         if (width > 3 * out_width)
2027                 hf = 4;
2028         else if (width > 2 * out_width)
2029                 hf = 3;
2030         else if (width > out_width)
2031                 hf = 2;
2032         else
2033                 hf = 1;
2034         if (height > out_height)
2035                 vf = 2;
2036         else
2037                 vf = 1;
2038
2039         return pclk * vf * hf;
2040 }
2041
2042 static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width,
2043                 u16 height, u16 out_width, u16 out_height)
2044 {
2045         unsigned long pclk = dispc_mgr_pclk_rate(channel);
2046
2047         if (width > out_width)
2048                 return DIV_ROUND_UP(pclk, out_width) * width;
2049         else
2050                 return pclk;
2051 }
2052
2053 static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel,
2054                 const struct omap_video_timings *mgr_timings,
2055                 u16 width, u16 height, u16 out_width, u16 out_height,
2056                 enum omap_color_mode color_mode, bool *five_taps,
2057                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2058                 u16 pos_x, unsigned long *core_clk)
2059 {
2060         int error;
2061         u16 in_width, in_height;
2062         int min_factor = min(*decim_x, *decim_y);
2063         const int maxsinglelinewidth =
2064                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2065         *five_taps = false;
2066
2067         do {
2068                 in_height = DIV_ROUND_UP(height, *decim_y);
2069                 in_width = DIV_ROUND_UP(width, *decim_x);
2070                 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2071                                 in_height, out_width, out_height);
2072                 error = (in_width > maxsinglelinewidth || !*core_clk ||
2073                         *core_clk > dispc_core_clk_rate());
2074                 if (error) {
2075                         if (*decim_x == *decim_y) {
2076                                 *decim_x = min_factor;
2077                                 ++*decim_y;
2078                         } else {
2079                                 swap(*decim_x, *decim_y);
2080                                 if (*decim_x < *decim_y)
2081                                         ++*decim_x;
2082                         }
2083                 }
2084         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2085
2086         if (in_width > maxsinglelinewidth) {
2087                 DSSERR("Cannot scale max input width exceeded");
2088                 return -EINVAL;
2089         }
2090         return 0;
2091 }
2092
2093 static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel,
2094                 const struct omap_video_timings *mgr_timings,
2095                 u16 width, u16 height, u16 out_width, u16 out_height,
2096                 enum omap_color_mode color_mode, bool *five_taps,
2097                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2098                 u16 pos_x, unsigned long *core_clk)
2099 {
2100         int error;
2101         u16 in_width, in_height;
2102         int min_factor = min(*decim_x, *decim_y);
2103         const int maxsinglelinewidth =
2104                         dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2105
2106         do {
2107                 in_height = DIV_ROUND_UP(height, *decim_y);
2108                 in_width = DIV_ROUND_UP(width, *decim_x);
2109                 *core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2110                         in_width, in_height, out_width, out_height, color_mode);
2111
2112                 error = check_horiz_timing_omap3(channel, mgr_timings, pos_x,
2113                         in_width, in_height, out_width, out_height);
2114
2115                 if (in_width > maxsinglelinewidth)
2116                         if (in_height > out_height &&
2117                                                 in_height < out_height * 2)
2118                                 *five_taps = false;
2119                 if (!*five_taps)
2120                         *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2121                                         in_height, out_width, out_height);
2122
2123                 error = (error || in_width > maxsinglelinewidth * 2 ||
2124                         (in_width > maxsinglelinewidth && *five_taps) ||
2125                         !*core_clk || *core_clk > dispc_core_clk_rate());
2126                 if (error) {
2127                         if (*decim_x == *decim_y) {
2128                                 *decim_x = min_factor;
2129                                 ++*decim_y;
2130                         } else {
2131                                 swap(*decim_x, *decim_y);
2132                                 if (*decim_x < *decim_y)
2133                                         ++*decim_x;
2134                         }
2135                 }
2136         } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2137
2138         if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height,
2139                 out_width, out_height)){
2140                         DSSERR("horizontal timing too tight\n");
2141                         return -EINVAL;
2142         }
2143
2144         if (in_width > (maxsinglelinewidth * 2)) {
2145                 DSSERR("Cannot setup scaling");
2146                 DSSERR("width exceeds maximum width possible");
2147                 return -EINVAL;
2148         }
2149
2150         if (in_width > maxsinglelinewidth && *five_taps) {
2151                 DSSERR("cannot setup scaling with five taps");
2152                 return -EINVAL;
2153         }
2154         return 0;
2155 }
2156
2157 static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel,
2158                 const struct omap_video_timings *mgr_timings,
2159                 u16 width, u16 height, u16 out_width, u16 out_height,
2160                 enum omap_color_mode color_mode, bool *five_taps,
2161                 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2162                 u16 pos_x, unsigned long *core_clk)
2163 {
2164         u16 in_width, in_width_max;
2165         int decim_x_min = *decim_x;
2166         u16 in_height = DIV_ROUND_UP(height, *decim_y);
2167         const int maxsinglelinewidth =
2168                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2169
2170         in_width_max = dispc_core_clk_rate() /
2171                         DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width);
2172         *decim_x = DIV_ROUND_UP(width, in_width_max);
2173
2174         *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2175         if (*decim_x > *x_predecim)
2176                 return -EINVAL;
2177
2178         do {
2179                 in_width = DIV_ROUND_UP(width, *decim_x);
2180         } while (*decim_x <= *x_predecim &&
2181                         in_width > maxsinglelinewidth && ++*decim_x);
2182
2183         if (in_width > maxsinglelinewidth) {
2184                 DSSERR("Cannot scale width exceeds max line width");
2185                 return -EINVAL;
2186         }
2187
2188         *core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height,
2189                                 out_width, out_height);
2190         return 0;
2191 }
2192
2193 static int dispc_ovl_calc_scaling(enum omap_plane plane,
2194                 enum omap_channel channel,
2195                 const struct omap_video_timings *mgr_timings,
2196                 u16 width, u16 height, u16 out_width, u16 out_height,
2197                 enum omap_color_mode color_mode, bool *five_taps,
2198                 int *x_predecim, int *y_predecim, u16 pos_x)
2199 {
2200         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2201         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2202         const int max_decim_limit = 16;
2203         unsigned long core_clk = 0;
2204         int decim_x, decim_y, ret;
2205
2206         if (width == out_width && height == out_height)
2207                 return 0;
2208
2209         if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2210                 return -EINVAL;
2211
2212         *x_predecim = max_decim_limit;
2213         *y_predecim = max_decim_limit;
2214
2215         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2216             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2217             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2218             color_mode == OMAP_DSS_COLOR_CLUT8) {
2219                 *x_predecim = 1;
2220                 *y_predecim = 1;
2221                 *five_taps = false;
2222                 return 0;
2223         }
2224
2225         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2226         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2227
2228         if (decim_x > *x_predecim || out_width > width * 8)
2229                 return -EINVAL;
2230
2231         if (decim_y > *y_predecim || out_height > height * 8)
2232                 return -EINVAL;
2233
2234         ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height,
2235                 out_width, out_height, color_mode, five_taps, x_predecim,
2236                 y_predecim, &decim_x, &decim_y, pos_x, &core_clk);
2237         if (ret)
2238                 return ret;
2239
2240         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2241         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2242
2243         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2244                 DSSERR("failed to set up scaling, "
2245                         "required core clk rate = %lu Hz, "
2246                         "current core clk rate = %lu Hz\n",
2247                         core_clk, dispc_core_clk_rate());
2248                 return -EINVAL;
2249         }
2250
2251         *x_predecim = decim_x;
2252         *y_predecim = decim_y;
2253         return 0;
2254 }
2255
2256 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2257                 bool replication, const struct omap_video_timings *mgr_timings)
2258 {
2259         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2260         bool five_taps = true;
2261         bool fieldmode = 0;
2262         int r, cconv = 0;
2263         unsigned offset0, offset1;
2264         s32 row_inc;
2265         s32 pix_inc;
2266         u16 frame_height = oi->height;
2267         unsigned int field_offset = 0;
2268         u16 in_height = oi->height;
2269         u16 in_width = oi->width;
2270         u16 out_width, out_height;
2271         enum omap_channel channel;
2272         int x_predecim = 1, y_predecim = 1;
2273         bool ilace = mgr_timings->interlace;
2274
2275         channel = dispc_ovl_get_channel_out(plane);
2276
2277         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2278                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2279                 plane, oi->paddr, oi->p_uv_addr,
2280                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2281                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2282                 oi->mirror, ilace, channel, replication);
2283
2284         if (oi->paddr == 0)
2285                 return -EINVAL;
2286
2287         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2288         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2289
2290         if (ilace && oi->height == out_height)
2291                 fieldmode = 1;
2292
2293         if (ilace) {
2294                 if (fieldmode)
2295                         in_height /= 2;
2296                 oi->pos_y /= 2;
2297                 out_height /= 2;
2298
2299                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2300                                 "out_height %d\n",
2301                                 in_height, oi->pos_y, out_height);
2302         }
2303
2304         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2305                 return -EINVAL;
2306
2307         r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2308                         in_height, out_width, out_height, oi->color_mode,
2309                         &five_taps, &x_predecim, &y_predecim, oi->pos_x);
2310         if (r)
2311                 return r;
2312
2313         in_width = DIV_ROUND_UP(in_width, x_predecim);
2314         in_height = DIV_ROUND_UP(in_height, y_predecim);
2315
2316         if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2317                         oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2318                         oi->color_mode == OMAP_DSS_COLOR_NV12)
2319                 cconv = 1;
2320
2321         if (ilace && !fieldmode) {
2322                 /*
2323                  * when downscaling the bottom field may have to start several
2324                  * source lines below the top field. Unfortunately ACCUI
2325                  * registers will only hold the fractional part of the offset
2326                  * so the integer part must be added to the base address of the
2327                  * bottom field.
2328                  */
2329                 if (!in_height || in_height == out_height)
2330                         field_offset = 0;
2331                 else
2332                         field_offset = in_height / out_height / 2;
2333         }
2334
2335         /* Fields are independent but interleaved in memory. */
2336         if (fieldmode)
2337                 field_offset = 1;
2338
2339         offset0 = 0;
2340         offset1 = 0;
2341         row_inc = 0;
2342         pix_inc = 0;
2343
2344         if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2345                 calc_tiler_rotation_offset(oi->screen_width, in_width,
2346                                 oi->color_mode, fieldmode, field_offset,
2347                                 &offset0, &offset1, &row_inc, &pix_inc,
2348                                 x_predecim, y_predecim);
2349         else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2350                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
2351                                 oi->screen_width, in_width, frame_height,
2352                                 oi->color_mode, fieldmode, field_offset,
2353                                 &offset0, &offset1, &row_inc, &pix_inc,
2354                                 x_predecim, y_predecim);
2355         else
2356                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
2357                                 oi->screen_width, in_width, frame_height,
2358                                 oi->color_mode, fieldmode, field_offset,
2359                                 &offset0, &offset1, &row_inc, &pix_inc,
2360                                 x_predecim, y_predecim);
2361
2362         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2363                         offset0, offset1, row_inc, pix_inc);
2364
2365         dispc_ovl_set_color_mode(plane, oi->color_mode);
2366
2367         dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2368
2369         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2370         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
2371
2372         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2373                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2374                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
2375         }
2376
2377
2378         dispc_ovl_set_row_inc(plane, row_inc);
2379         dispc_ovl_set_pix_inc(plane, pix_inc);
2380
2381         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2382                         in_height, out_width, out_height);
2383
2384         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
2385
2386         dispc_ovl_set_pic_size(plane, in_width, in_height);
2387
2388         if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
2389                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2390                                    out_height, ilace, five_taps, fieldmode,
2391                                    oi->color_mode, oi->rotation);
2392                 dispc_ovl_set_vid_size(plane, out_width, out_height);
2393                 dispc_ovl_set_vid_color_conv(plane, cconv);
2394         }
2395
2396         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2397                         oi->color_mode);
2398
2399         dispc_ovl_set_zorder(plane, oi->zorder);
2400         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2401         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
2402
2403         dispc_ovl_enable_replication(plane, replication);
2404
2405         return 0;
2406 }
2407
2408 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2409 {
2410         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2411
2412         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2413
2414         return 0;
2415 }
2416
2417 static void dispc_disable_isr(void *data, u32 mask)
2418 {
2419         struct completion *compl = data;
2420         complete(compl);
2421 }
2422
2423 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2424 {
2425         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2426         /* flush posted write */
2427         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2428 }
2429
2430 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2431 {
2432         struct completion frame_done_completion;
2433         bool is_on;
2434         int r;
2435         u32 irq;
2436
2437         /* When we disable LCD output, we need to wait until frame is done.
2438          * Otherwise the DSS is still working, and turning off the clocks
2439          * prevents DSS from going to OFF mode */
2440         is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2441
2442         irq = mgr_desc[channel].framedone_irq;
2443
2444         if (!enable && is_on) {
2445                 init_completion(&frame_done_completion);
2446
2447                 r = omap_dispc_register_isr(dispc_disable_isr,
2448                                 &frame_done_completion, irq);
2449
2450                 if (r)
2451                         DSSERR("failed to register FRAMEDONE isr\n");
2452         }
2453
2454         _enable_lcd_out(channel, enable);
2455
2456         if (!enable && is_on) {
2457                 if (!wait_for_completion_timeout(&frame_done_completion,
2458                                         msecs_to_jiffies(100)))
2459                         DSSERR("timeout waiting for FRAME DONE\n");
2460
2461                 r = omap_dispc_unregister_isr(dispc_disable_isr,
2462                                 &frame_done_completion, irq);
2463
2464                 if (r)
2465                         DSSERR("failed to unregister FRAMEDONE isr\n");
2466         }
2467 }
2468
2469 static void _enable_digit_out(bool enable)
2470 {
2471         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2472         /* flush posted write */
2473         dispc_read_reg(DISPC_CONTROL);
2474 }
2475
2476 static void dispc_mgr_enable_digit_out(bool enable)
2477 {
2478         struct completion frame_done_completion;
2479         enum dss_hdmi_venc_clk_source_select src;
2480         int r, i;
2481         u32 irq_mask;
2482         int num_irqs;
2483
2484         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2485                 return;
2486
2487         src = dss_get_hdmi_venc_clk_source();
2488
2489         if (enable) {
2490                 unsigned long flags;
2491                 /* When we enable digit output, we'll get an extra digit
2492                  * sync lost interrupt, that we need to ignore */
2493                 spin_lock_irqsave(&dispc.irq_lock, flags);
2494                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2495                 _omap_dispc_set_irqs();
2496                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2497         }
2498
2499         /* When we disable digit output, we need to wait until fields are done.
2500          * Otherwise the DSS is still working, and turning off the clocks
2501          * prevents DSS from going to OFF mode. And when enabling, we need to
2502          * wait for the extra sync losts */
2503         init_completion(&frame_done_completion);
2504
2505         if (src == DSS_HDMI_M_PCLK && enable == false) {
2506                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2507                 num_irqs = 1;
2508         } else {
2509                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2510                 /* XXX I understand from TRM that we should only wait for the
2511                  * current field to complete. But it seems we have to wait for
2512                  * both fields */
2513                 num_irqs = 2;
2514         }
2515
2516         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2517                         irq_mask);
2518         if (r)
2519                 DSSERR("failed to register %x isr\n", irq_mask);
2520
2521         _enable_digit_out(enable);
2522
2523         for (i = 0; i < num_irqs; ++i) {
2524                 if (!wait_for_completion_timeout(&frame_done_completion,
2525                                         msecs_to_jiffies(100)))
2526                         DSSERR("timeout waiting for digit out to %s\n",
2527                                         enable ? "start" : "stop");
2528         }
2529
2530         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2531                         irq_mask);
2532         if (r)
2533                 DSSERR("failed to unregister %x isr\n", irq_mask);
2534
2535         if (enable) {
2536                 unsigned long flags;
2537                 spin_lock_irqsave(&dispc.irq_lock, flags);
2538                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2539                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2540                 _omap_dispc_set_irqs();
2541                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2542         }
2543 }
2544
2545 bool dispc_mgr_is_enabled(enum omap_channel channel)
2546 {
2547         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2548 }
2549
2550 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2551 {
2552         if (dss_mgr_is_lcd(channel))
2553                 dispc_mgr_enable_lcd_out(channel, enable);
2554         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2555                 dispc_mgr_enable_digit_out(enable);
2556         else
2557                 BUG();
2558 }
2559
2560 void dispc_lcd_enable_signal_polarity(bool act_high)
2561 {
2562         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2563                 return;
2564
2565         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2566 }
2567
2568 void dispc_lcd_enable_signal(bool enable)
2569 {
2570         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2571                 return;
2572
2573         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2574 }
2575
2576 void dispc_pck_free_enable(bool enable)
2577 {
2578         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2579                 return;
2580
2581         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2582 }
2583
2584 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2585 {
2586         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2587 }
2588
2589
2590 void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2591 {
2592         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2593 }
2594
2595 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2596 {
2597         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2598 }
2599
2600
2601 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2602 {
2603         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2604 }
2605
2606 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2607                 enum omap_dss_trans_key_type type,
2608                 u32 trans_key)
2609 {
2610         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2611
2612         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2613 }
2614
2615 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2616 {
2617         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2618 }
2619
2620 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2621                 bool enable)
2622 {
2623         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2624                 return;
2625
2626         if (ch == OMAP_DSS_CHANNEL_LCD)
2627                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2628         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2629                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2630 }
2631
2632 void dispc_mgr_setup(enum omap_channel channel,
2633                 struct omap_overlay_manager_info *info)
2634 {
2635         dispc_mgr_set_default_color(channel, info->default_color);
2636         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2637         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2638         dispc_mgr_enable_alpha_fixed_zorder(channel,
2639                         info->partial_alpha_enabled);
2640         if (dss_has_feature(FEAT_CPR)) {
2641                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2642                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2643         }
2644 }
2645
2646 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2647 {
2648         int code;
2649
2650         switch (data_lines) {
2651         case 12:
2652                 code = 0;
2653                 break;
2654         case 16:
2655                 code = 1;
2656                 break;
2657         case 18:
2658                 code = 2;
2659                 break;
2660         case 24:
2661                 code = 3;
2662                 break;
2663         default:
2664                 BUG();
2665                 return;
2666         }
2667
2668         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2669 }
2670
2671 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2672 {
2673         u32 l;
2674         int gpout0, gpout1;
2675
2676         switch (mode) {
2677         case DSS_IO_PAD_MODE_RESET:
2678                 gpout0 = 0;
2679                 gpout1 = 0;
2680                 break;
2681         case DSS_IO_PAD_MODE_RFBI:
2682                 gpout0 = 1;
2683                 gpout1 = 0;
2684                 break;
2685         case DSS_IO_PAD_MODE_BYPASS:
2686                 gpout0 = 1;
2687                 gpout1 = 1;
2688                 break;
2689         default:
2690                 BUG();
2691                 return;
2692         }
2693
2694         l = dispc_read_reg(DISPC_CONTROL);
2695         l = FLD_MOD(l, gpout0, 15, 15);
2696         l = FLD_MOD(l, gpout1, 16, 16);
2697         dispc_write_reg(DISPC_CONTROL, l);
2698 }
2699
2700 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2701 {
2702         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2703 }
2704
2705 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2706 {
2707         return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2708                 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2709 }
2710
2711 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2712                 int vsw, int vfp, int vbp)
2713 {
2714         if (hsw < 1 || hsw > dispc.feat->sw_max ||
2715                         hfp < 1 || hfp > dispc.feat->hp_max ||
2716                         hbp < 1 || hbp > dispc.feat->hp_max ||
2717                         vsw < 1 || vsw > dispc.feat->sw_max ||
2718                         vfp < 0 || vfp > dispc.feat->vp_max ||
2719                         vbp < 0 || vbp > dispc.feat->vp_max)
2720                 return false;
2721         return true;
2722 }
2723
2724 bool dispc_mgr_timings_ok(enum omap_channel channel,
2725                 const struct omap_video_timings *timings)
2726 {
2727         bool timings_ok;
2728
2729         timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2730
2731         if (dss_mgr_is_lcd(channel))
2732                 timings_ok =  timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2733                                                 timings->hfp, timings->hbp,
2734                                                 timings->vsw, timings->vfp,
2735                                                 timings->vbp);
2736
2737         return timings_ok;
2738 }
2739
2740 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2741                 int hfp, int hbp, int vsw, int vfp, int vbp,
2742                 enum omap_dss_signal_level vsync_level,
2743                 enum omap_dss_signal_level hsync_level,
2744                 enum omap_dss_signal_edge data_pclk_edge,
2745                 enum omap_dss_signal_level de_level,
2746                 enum omap_dss_signal_edge sync_pclk_edge)
2747
2748 {
2749         u32 timing_h, timing_v, l;
2750         bool onoff, rf, ipc;
2751
2752         timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2753                         FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2754                         FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2755         timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2756                         FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2757                         FLD_VAL(vbp, dispc.feat->bp_start, 20);
2758
2759         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2760         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2761
2762         switch (data_pclk_edge) {
2763         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2764                 ipc = false;
2765                 break;
2766         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2767                 ipc = true;
2768                 break;
2769         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2770         default:
2771                 BUG();
2772         }
2773
2774         switch (sync_pclk_edge) {
2775         case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2776                 onoff = false;
2777                 rf = false;
2778                 break;
2779         case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2780                 onoff = true;
2781                 rf = false;
2782                 break;
2783         case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2784                 onoff = true;
2785                 rf = true;
2786                 break;
2787         default:
2788                 BUG();
2789         };
2790
2791         l = dispc_read_reg(DISPC_POL_FREQ(channel));
2792         l |= FLD_VAL(onoff, 17, 17);
2793         l |= FLD_VAL(rf, 16, 16);
2794         l |= FLD_VAL(de_level, 15, 15);
2795         l |= FLD_VAL(ipc, 14, 14);
2796         l |= FLD_VAL(hsync_level, 13, 13);
2797         l |= FLD_VAL(vsync_level, 12, 12);
2798         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2799 }
2800
2801 /* change name to mode? */
2802 void dispc_mgr_set_timings(enum omap_channel channel,
2803                 struct omap_video_timings *timings)
2804 {
2805         unsigned xtot, ytot;
2806         unsigned long ht, vt;
2807         struct omap_video_timings t = *timings;
2808
2809         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2810
2811         if (!dispc_mgr_timings_ok(channel, &t)) {
2812                 BUG();
2813                 return;
2814         }
2815
2816         if (dss_mgr_is_lcd(channel)) {
2817                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2818                                 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2819                                 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
2820
2821                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2822                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2823
2824                 ht = (timings->pixel_clock * 1000) / xtot;
2825                 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2826
2827                 DSSDBG("pck %u\n", timings->pixel_clock);
2828                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2829                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2830                 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2831                         t.vsync_level, t.hsync_level, t.data_pclk_edge,
2832                         t.de_level, t.sync_pclk_edge);
2833
2834                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2835         } else {
2836                 if (t.interlace == true)
2837                         t.y_res /= 2;
2838         }
2839
2840         dispc_mgr_set_size(channel, t.x_res, t.y_res);
2841 }
2842
2843 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2844                 u16 pck_div)
2845 {
2846         BUG_ON(lck_div < 1);
2847         BUG_ON(pck_div < 1);
2848
2849         dispc_write_reg(DISPC_DIVISORo(channel),
2850                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2851 }
2852
2853 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2854                 int *pck_div)
2855 {
2856         u32 l;
2857         l = dispc_read_reg(DISPC_DIVISORo(channel));
2858         *lck_div = FLD_GET(l, 23, 16);
2859         *pck_div = FLD_GET(l, 7, 0);
2860 }
2861
2862 unsigned long dispc_fclk_rate(void)
2863 {
2864         struct platform_device *dsidev;
2865         unsigned long r = 0;
2866
2867         switch (dss_get_dispc_clk_source()) {
2868         case OMAP_DSS_CLK_SRC_FCK:
2869                 r = clk_get_rate(dispc.dss_clk);
2870                 break;
2871         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2872                 dsidev = dsi_get_dsidev_from_id(0);
2873                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2874                 break;
2875         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2876                 dsidev = dsi_get_dsidev_from_id(1);
2877                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2878                 break;
2879         default:
2880                 BUG();
2881                 return 0;
2882         }
2883
2884         return r;
2885 }
2886
2887 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2888 {
2889         struct platform_device *dsidev;
2890         int lcd;
2891         unsigned long r;
2892         u32 l;
2893
2894         l = dispc_read_reg(DISPC_DIVISORo(channel));
2895
2896         lcd = FLD_GET(l, 23, 16);
2897
2898         switch (dss_get_lcd_clk_source(channel)) {
2899         case OMAP_DSS_CLK_SRC_FCK:
2900                 r = clk_get_rate(dispc.dss_clk);
2901                 break;
2902         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2903                 dsidev = dsi_get_dsidev_from_id(0);
2904                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2905                 break;
2906         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2907                 dsidev = dsi_get_dsidev_from_id(1);
2908                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2909                 break;
2910         default:
2911                 BUG();
2912                 return 0;
2913         }
2914
2915         return r / lcd;
2916 }
2917
2918 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2919 {
2920         unsigned long r;
2921
2922         if (dss_mgr_is_lcd(channel)) {
2923                 int pcd;
2924                 u32 l;
2925
2926                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2927
2928                 pcd = FLD_GET(l, 7, 0);
2929
2930                 r = dispc_mgr_lclk_rate(channel);
2931
2932                 return r / pcd;
2933         } else {
2934                 enum dss_hdmi_venc_clk_source_select source;
2935
2936                 source = dss_get_hdmi_venc_clk_source();
2937
2938                 switch (source) {
2939                 case DSS_VENC_TV_CLK:
2940                         return venc_get_pixel_clock();
2941                 case DSS_HDMI_M_PCLK:
2942                         return hdmi_get_pixel_clock();
2943                 default:
2944                         BUG();
2945                         return 0;
2946                 }
2947         }
2948 }
2949
2950 unsigned long dispc_core_clk_rate(void)
2951 {
2952         int lcd;
2953         unsigned long fclk = dispc_fclk_rate();
2954
2955         if (dss_has_feature(FEAT_CORE_CLK_DIV))
2956                 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2957         else
2958                 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2959
2960         return fclk / lcd;
2961 }
2962
2963 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
2964 {
2965         int lcd, pcd;
2966         enum omap_dss_clk_source lcd_clk_src;
2967
2968         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
2969
2970         lcd_clk_src = dss_get_lcd_clk_source(channel);
2971
2972         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
2973                 dss_get_generic_clk_source_name(lcd_clk_src),
2974                 dss_feat_get_clk_source_name(lcd_clk_src));
2975
2976         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
2977
2978         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2979                 dispc_mgr_lclk_rate(channel), lcd);
2980         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2981                 dispc_mgr_pclk_rate(channel), pcd);
2982 }
2983
2984 void dispc_dump_clocks(struct seq_file *s)
2985 {
2986         int lcd;
2987         u32 l;
2988         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2989
2990         if (dispc_runtime_get())
2991                 return;
2992
2993         seq_printf(s, "- DISPC -\n");
2994
2995         seq_printf(s, "dispc fclk source = %s (%s)\n",
2996                         dss_get_generic_clk_source_name(dispc_clk_src),
2997                         dss_feat_get_clk_source_name(dispc_clk_src));
2998
2999         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3000
3001         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3002                 seq_printf(s, "- DISPC-CORE-CLK -\n");
3003                 l = dispc_read_reg(DISPC_DIVISOR);
3004                 lcd = FLD_GET(l, 23, 16);
3005
3006                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3007                                 (dispc_fclk_rate()/lcd), lcd);
3008         }
3009
3010         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3011
3012         if (dss_has_feature(FEAT_MGR_LCD2))
3013                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3014         if (dss_has_feature(FEAT_MGR_LCD3))
3015                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3016
3017         dispc_runtime_put();
3018 }
3019
3020 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3021 void dispc_dump_irqs(struct seq_file *s)
3022 {
3023         unsigned long flags;
3024         struct dispc_irq_stats stats;
3025
3026         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3027
3028         stats = dispc.irq_stats;
3029         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3030         dispc.irq_stats.last_reset = jiffies;
3031
3032         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3033
3034         seq_printf(s, "period %u ms\n",
3035                         jiffies_to_msecs(jiffies - stats.last_reset));
3036
3037         seq_printf(s, "irqs %d\n", stats.irq_count);
3038 #define PIS(x) \
3039         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3040
3041         PIS(FRAMEDONE);
3042         PIS(VSYNC);
3043         PIS(EVSYNC_EVEN);
3044         PIS(EVSYNC_ODD);
3045         PIS(ACBIAS_COUNT_STAT);
3046         PIS(PROG_LINE_NUM);
3047         PIS(GFX_FIFO_UNDERFLOW);
3048         PIS(GFX_END_WIN);
3049         PIS(PAL_GAMMA_MASK);
3050         PIS(OCP_ERR);
3051         PIS(VID1_FIFO_UNDERFLOW);
3052         PIS(VID1_END_WIN);
3053         PIS(VID2_FIFO_UNDERFLOW);
3054         PIS(VID2_END_WIN);
3055         if (dss_feat_get_num_ovls() > 3) {
3056                 PIS(VID3_FIFO_UNDERFLOW);
3057                 PIS(VID3_END_WIN);
3058         }
3059         PIS(SYNC_LOST);
3060         PIS(SYNC_LOST_DIGIT);
3061         PIS(WAKEUP);
3062         if (dss_has_feature(FEAT_MGR_LCD2)) {
3063                 PIS(FRAMEDONE2);
3064                 PIS(VSYNC2);
3065                 PIS(ACBIAS_COUNT_STAT2);
3066                 PIS(SYNC_LOST2);
3067         }
3068         if (dss_has_feature(FEAT_MGR_LCD3)) {
3069                 PIS(FRAMEDONE3);
3070                 PIS(VSYNC3);
3071                 PIS(ACBIAS_COUNT_STAT3);
3072                 PIS(SYNC_LOST3);
3073         }
3074 #undef PIS
3075 }
3076 #endif
3077
3078 static void dispc_dump_regs(struct seq_file *s)
3079 {
3080         int i, j;
3081         const char *mgr_names[] = {
3082                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
3083                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
3084                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
3085                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
3086         };
3087         const char *ovl_names[] = {
3088                 [OMAP_DSS_GFX]          = "GFX",
3089                 [OMAP_DSS_VIDEO1]       = "VID1",
3090                 [OMAP_DSS_VIDEO2]       = "VID2",
3091                 [OMAP_DSS_VIDEO3]       = "VID3",
3092         };
3093         const char **p_names;
3094
3095 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3096
3097         if (dispc_runtime_get())
3098                 return;
3099
3100         /* DISPC common registers */
3101         DUMPREG(DISPC_REVISION);
3102         DUMPREG(DISPC_SYSCONFIG);
3103         DUMPREG(DISPC_SYSSTATUS);
3104         DUMPREG(DISPC_IRQSTATUS);
3105         DUMPREG(DISPC_IRQENABLE);
3106         DUMPREG(DISPC_CONTROL);
3107         DUMPREG(DISPC_CONFIG);
3108         DUMPREG(DISPC_CAPABLE);
3109         DUMPREG(DISPC_LINE_STATUS);
3110         DUMPREG(DISPC_LINE_NUMBER);
3111         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3112                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3113                 DUMPREG(DISPC_GLOBAL_ALPHA);
3114         if (dss_has_feature(FEAT_MGR_LCD2)) {
3115                 DUMPREG(DISPC_CONTROL2);
3116                 DUMPREG(DISPC_CONFIG2);
3117         }
3118         if (dss_has_feature(FEAT_MGR_LCD3)) {
3119                 DUMPREG(DISPC_CONTROL3);
3120                 DUMPREG(DISPC_CONFIG3);
3121         }
3122
3123 #undef DUMPREG
3124
3125 #define DISPC_REG(i, name) name(i)
3126 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3127         48 - strlen(#r) - strlen(p_names[i]), " ", \
3128         dispc_read_reg(DISPC_REG(i, r)))
3129
3130         p_names = mgr_names;
3131
3132         /* DISPC channel specific registers */
3133         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3134                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3135                 DUMPREG(i, DISPC_TRANS_COLOR);
3136                 DUMPREG(i, DISPC_SIZE_MGR);
3137
3138                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3139                         continue;
3140
3141                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3142                 DUMPREG(i, DISPC_TRANS_COLOR);
3143                 DUMPREG(i, DISPC_TIMING_H);
3144                 DUMPREG(i, DISPC_TIMING_V);
3145                 DUMPREG(i, DISPC_POL_FREQ);
3146                 DUMPREG(i, DISPC_DIVISORo);
3147                 DUMPREG(i, DISPC_SIZE_MGR);
3148
3149                 DUMPREG(i, DISPC_DATA_CYCLE1);
3150                 DUMPREG(i, DISPC_DATA_CYCLE2);
3151                 DUMPREG(i, DISPC_DATA_CYCLE3);
3152
3153                 if (dss_has_feature(FEAT_CPR)) {
3154                         DUMPREG(i, DISPC_CPR_COEF_R);
3155                         DUMPREG(i, DISPC_CPR_COEF_G);
3156                         DUMPREG(i, DISPC_CPR_COEF_B);
3157                 }
3158         }
3159
3160         p_names = ovl_names;
3161
3162         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3163                 DUMPREG(i, DISPC_OVL_BA0);
3164                 DUMPREG(i, DISPC_OVL_BA1);
3165                 DUMPREG(i, DISPC_OVL_POSITION);
3166                 DUMPREG(i, DISPC_OVL_SIZE);
3167                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3168                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3169                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3170                 DUMPREG(i, DISPC_OVL_ROW_INC);
3171                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3172                 if (dss_has_feature(FEAT_PRELOAD))
3173                         DUMPREG(i, DISPC_OVL_PRELOAD);
3174
3175                 if (i == OMAP_DSS_GFX) {
3176                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3177                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3178                         continue;
3179                 }
3180
3181                 DUMPREG(i, DISPC_OVL_FIR);
3182                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3183                 DUMPREG(i, DISPC_OVL_ACCU0);
3184                 DUMPREG(i, DISPC_OVL_ACCU1);
3185                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3186                         DUMPREG(i, DISPC_OVL_BA0_UV);
3187                         DUMPREG(i, DISPC_OVL_BA1_UV);
3188                         DUMPREG(i, DISPC_OVL_FIR2);
3189                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3190                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3191                 }
3192                 if (dss_has_feature(FEAT_ATTR2))
3193                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3194                 if (dss_has_feature(FEAT_PRELOAD))
3195                         DUMPREG(i, DISPC_OVL_PRELOAD);
3196         }
3197
3198 #undef DISPC_REG
3199 #undef DUMPREG
3200
3201 #define DISPC_REG(plane, name, i) name(plane, i)
3202 #define DUMPREG(plane, name, i) \
3203         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3204         46 - strlen(#name) - strlen(p_names[plane]), " ", \
3205         dispc_read_reg(DISPC_REG(plane, name, i)))
3206
3207         /* Video pipeline coefficient registers */
3208
3209         /* start from OMAP_DSS_VIDEO1 */
3210         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3211                 for (j = 0; j < 8; j++)
3212                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3213
3214                 for (j = 0; j < 8; j++)
3215                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3216
3217                 for (j = 0; j < 5; j++)
3218                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3219
3220                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3221                         for (j = 0; j < 8; j++)
3222                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3223                 }
3224
3225                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3226                         for (j = 0; j < 8; j++)
3227                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3228
3229                         for (j = 0; j < 8; j++)
3230                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3231
3232                         for (j = 0; j < 8; j++)
3233                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3234                 }
3235         }
3236
3237         dispc_runtime_put();
3238
3239 #undef DISPC_REG
3240 #undef DUMPREG
3241 }
3242
3243 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3244 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3245                 struct dispc_clock_info *cinfo)
3246 {
3247         u16 pcd_min, pcd_max;
3248         unsigned long best_pck;
3249         u16 best_ld, cur_ld;
3250         u16 best_pd, cur_pd;
3251
3252         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3253         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3254
3255         best_pck = 0;
3256         best_ld = 0;
3257         best_pd = 0;
3258
3259         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3260                 unsigned long lck = fck / cur_ld;
3261
3262                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3263                         unsigned long pck = lck / cur_pd;
3264                         long old_delta = abs(best_pck - req_pck);
3265                         long new_delta = abs(pck - req_pck);
3266
3267                         if (best_pck == 0 || new_delta < old_delta) {
3268                                 best_pck = pck;
3269                                 best_ld = cur_ld;
3270                                 best_pd = cur_pd;
3271
3272                                 if (pck == req_pck)
3273                                         goto found;
3274                         }
3275
3276                         if (pck < req_pck)
3277                                 break;
3278                 }
3279
3280                 if (lck / pcd_min < req_pck)
3281                         break;
3282         }
3283
3284 found:
3285         cinfo->lck_div = best_ld;
3286         cinfo->pck_div = best_pd;
3287         cinfo->lck = fck / cinfo->lck_div;
3288         cinfo->pck = cinfo->lck / cinfo->pck_div;
3289 }
3290
3291 /* calculate clock rates using dividers in cinfo */
3292 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3293                 struct dispc_clock_info *cinfo)
3294 {
3295         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3296                 return -EINVAL;
3297         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3298                 return -EINVAL;
3299
3300         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3301         cinfo->pck = cinfo->lck / cinfo->pck_div;
3302
3303         return 0;
3304 }
3305
3306 void dispc_mgr_set_clock_div(enum omap_channel channel,
3307                 struct dispc_clock_info *cinfo)
3308 {
3309         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3310         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3311
3312         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3313 }
3314
3315 int dispc_mgr_get_clock_div(enum omap_channel channel,
3316                 struct dispc_clock_info *cinfo)
3317 {
3318         unsigned long fck;
3319
3320         fck = dispc_fclk_rate();
3321
3322         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3323         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3324
3325         cinfo->lck = fck / cinfo->lck_div;
3326         cinfo->pck = cinfo->lck / cinfo->pck_div;
3327
3328         return 0;
3329 }
3330
3331 /* dispc.irq_lock has to be locked by the caller */
3332 static void _omap_dispc_set_irqs(void)
3333 {
3334         u32 mask;
3335         u32 old_mask;
3336         int i;
3337         struct omap_dispc_isr_data *isr_data;
3338
3339         mask = dispc.irq_error_mask;
3340
3341         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3342                 isr_data = &dispc.registered_isr[i];
3343
3344                 if (isr_data->isr == NULL)
3345                         continue;
3346
3347                 mask |= isr_data->mask;
3348         }
3349
3350         old_mask = dispc_read_reg(DISPC_IRQENABLE);
3351         /* clear the irqstatus for newly enabled irqs */
3352         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3353
3354         dispc_write_reg(DISPC_IRQENABLE, mask);
3355 }
3356
3357 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3358 {
3359         int i;
3360         int ret;
3361         unsigned long flags;
3362         struct omap_dispc_isr_data *isr_data;
3363
3364         if (isr == NULL)
3365                 return -EINVAL;
3366
3367         spin_lock_irqsave(&dispc.irq_lock, flags);
3368
3369         /* check for duplicate entry */
3370         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3371                 isr_data = &dispc.registered_isr[i];
3372                 if (isr_data->isr == isr && isr_data->arg == arg &&
3373                                 isr_data->mask == mask) {
3374                         ret = -EINVAL;
3375                         goto err;
3376                 }
3377         }
3378
3379         isr_data = NULL;
3380         ret = -EBUSY;
3381
3382         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3383                 isr_data = &dispc.registered_isr[i];
3384
3385                 if (isr_data->isr != NULL)
3386                         continue;
3387
3388                 isr_data->isr = isr;
3389                 isr_data->arg = arg;
3390                 isr_data->mask = mask;
3391                 ret = 0;
3392
3393                 break;
3394         }
3395
3396         if (ret)
3397                 goto err;
3398
3399         _omap_dispc_set_irqs();
3400
3401         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3402
3403         return 0;
3404 err:
3405         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3406
3407         return ret;
3408 }
3409 EXPORT_SYMBOL(omap_dispc_register_isr);
3410
3411 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3412 {
3413         int i;
3414         unsigned long flags;
3415         int ret = -EINVAL;
3416         struct omap_dispc_isr_data *isr_data;
3417
3418         spin_lock_irqsave(&dispc.irq_lock, flags);
3419
3420         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3421                 isr_data = &dispc.registered_isr[i];
3422                 if (isr_data->isr != isr || isr_data->arg != arg ||
3423                                 isr_data->mask != mask)
3424                         continue;
3425
3426                 /* found the correct isr */
3427
3428                 isr_data->isr = NULL;
3429                 isr_data->arg = NULL;
3430                 isr_data->mask = 0;
3431
3432                 ret = 0;
3433                 break;
3434         }
3435
3436         if (ret == 0)
3437                 _omap_dispc_set_irqs();
3438
3439         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3440
3441         return ret;
3442 }
3443 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3444
3445 #ifdef DEBUG
3446 static void print_irq_status(u32 status)
3447 {
3448         if ((status & dispc.irq_error_mask) == 0)
3449                 return;
3450
3451         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3452
3453 #define PIS(x) \
3454         if (status & DISPC_IRQ_##x) \
3455                 printk(#x " ");
3456         PIS(GFX_FIFO_UNDERFLOW);
3457         PIS(OCP_ERR);
3458         PIS(VID1_FIFO_UNDERFLOW);
3459         PIS(VID2_FIFO_UNDERFLOW);
3460         if (dss_feat_get_num_ovls() > 3)
3461                 PIS(VID3_FIFO_UNDERFLOW);
3462         PIS(SYNC_LOST);
3463         PIS(SYNC_LOST_DIGIT);
3464         if (dss_has_feature(FEAT_MGR_LCD2))
3465                 PIS(SYNC_LOST2);
3466         if (dss_has_feature(FEAT_MGR_LCD3))
3467                 PIS(SYNC_LOST3);
3468 #undef PIS
3469
3470         printk("\n");
3471 }
3472 #endif
3473
3474 /* Called from dss.c. Note that we don't touch clocks here,
3475  * but we presume they are on because we got an IRQ. However,
3476  * an irq handler may turn the clocks off, so we may not have
3477  * clock later in the function. */
3478 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3479 {
3480         int i;
3481         u32 irqstatus, irqenable;
3482         u32 handledirqs = 0;
3483         u32 unhandled_errors;
3484         struct omap_dispc_isr_data *isr_data;
3485         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3486
3487         spin_lock(&dispc.irq_lock);
3488
3489         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3490         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3491
3492         /* IRQ is not for us */
3493         if (!(irqstatus & irqenable)) {
3494                 spin_unlock(&dispc.irq_lock);
3495                 return IRQ_NONE;
3496         }
3497
3498 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3499         spin_lock(&dispc.irq_stats_lock);
3500         dispc.irq_stats.irq_count++;
3501         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3502         spin_unlock(&dispc.irq_stats_lock);
3503 #endif
3504
3505 #ifdef DEBUG
3506         if (dss_debug)
3507                 print_irq_status(irqstatus);
3508 #endif
3509         /* Ack the interrupt. Do it here before clocks are possibly turned
3510          * off */
3511         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3512         /* flush posted write */
3513         dispc_read_reg(DISPC_IRQSTATUS);
3514
3515         /* make a copy and unlock, so that isrs can unregister
3516          * themselves */
3517         memcpy(registered_isr, dispc.registered_isr,
3518                         sizeof(registered_isr));
3519
3520         spin_unlock(&dispc.irq_lock);
3521
3522         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3523                 isr_data = &registered_isr[i];
3524
3525                 if (!isr_data->isr)
3526                         continue;
3527
3528                 if (isr_data->mask & irqstatus) {
3529                         isr_data->isr(isr_data->arg, irqstatus);
3530                         handledirqs |= isr_data->mask;
3531                 }
3532         }
3533
3534         spin_lock(&dispc.irq_lock);
3535
3536         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3537
3538         if (unhandled_errors) {
3539                 dispc.error_irqs |= unhandled_errors;
3540
3541                 dispc.irq_error_mask &= ~unhandled_errors;
3542                 _omap_dispc_set_irqs();
3543
3544                 schedule_work(&dispc.error_work);
3545         }
3546
3547         spin_unlock(&dispc.irq_lock);
3548
3549         return IRQ_HANDLED;
3550 }
3551
3552 static void dispc_error_worker(struct work_struct *work)
3553 {
3554         int i;
3555         u32 errors;
3556         unsigned long flags;
3557         static const unsigned fifo_underflow_bits[] = {
3558                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3559                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3560                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3561                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3562         };
3563
3564         spin_lock_irqsave(&dispc.irq_lock, flags);
3565         errors = dispc.error_irqs;
3566         dispc.error_irqs = 0;
3567         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3568
3569         dispc_runtime_get();
3570
3571         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3572                 struct omap_overlay *ovl;
3573                 unsigned bit;
3574
3575                 ovl = omap_dss_get_overlay(i);
3576                 bit = fifo_underflow_bits[i];
3577
3578                 if (bit & errors) {
3579                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3580                                         ovl->name);
3581                         dispc_ovl_enable(ovl->id, false);
3582                         dispc_mgr_go(ovl->manager->id);
3583                         msleep(50);
3584                 }
3585         }
3586
3587         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3588                 struct omap_overlay_manager *mgr;
3589                 unsigned bit;
3590
3591                 mgr = omap_dss_get_overlay_manager(i);
3592                 bit = mgr_desc[i].sync_lost_irq;
3593
3594                 if (bit & errors) {
3595                         struct omap_dss_device *dssdev = mgr->device;
3596                         bool enable;
3597
3598                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3599                                         "with video overlays disabled\n",
3600                                         mgr->name);
3601
3602                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3603                         dssdev->driver->disable(dssdev);
3604
3605                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3606                                 struct omap_overlay *ovl;
3607                                 ovl = omap_dss_get_overlay(i);
3608
3609                                 if (ovl->id != OMAP_DSS_GFX &&
3610                                                 ovl->manager == mgr)
3611                                         dispc_ovl_enable(ovl->id, false);
3612                         }
3613
3614                         dispc_mgr_go(mgr->id);
3615                         msleep(50);
3616
3617                         if (enable)
3618                                 dssdev->driver->enable(dssdev);
3619                 }
3620         }
3621
3622         if (errors & DISPC_IRQ_OCP_ERR) {
3623                 DSSERR("OCP_ERR\n");
3624                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3625                         struct omap_overlay_manager *mgr;
3626                         mgr = omap_dss_get_overlay_manager(i);
3627                         if (mgr->device && mgr->device->driver)
3628                                 mgr->device->driver->disable(mgr->device);
3629                 }
3630         }
3631
3632         spin_lock_irqsave(&dispc.irq_lock, flags);
3633         dispc.irq_error_mask |= errors;
3634         _omap_dispc_set_irqs();
3635         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3636
3637         dispc_runtime_put();
3638 }
3639
3640 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3641 {
3642         void dispc_irq_wait_handler(void *data, u32 mask)
3643         {
3644                 complete((struct completion *)data);
3645         }
3646
3647         int r;
3648         DECLARE_COMPLETION_ONSTACK(completion);
3649
3650         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3651                         irqmask);
3652
3653         if (r)
3654                 return r;
3655
3656         timeout = wait_for_completion_timeout(&completion, timeout);
3657
3658         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3659
3660         if (timeout == 0)
3661                 return -ETIMEDOUT;
3662
3663         if (timeout == -ERESTARTSYS)
3664                 return -ERESTARTSYS;
3665
3666         return 0;
3667 }
3668
3669 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3670                 unsigned long timeout)
3671 {
3672         void dispc_irq_wait_handler(void *data, u32 mask)
3673         {
3674                 complete((struct completion *)data);
3675         }
3676
3677         int r;
3678         DECLARE_COMPLETION_ONSTACK(completion);
3679
3680         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3681                         irqmask);
3682
3683         if (r)
3684                 return r;
3685
3686         timeout = wait_for_completion_interruptible_timeout(&completion,
3687                         timeout);
3688
3689         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3690
3691         if (timeout == 0)
3692                 return -ETIMEDOUT;
3693
3694         if (timeout == -ERESTARTSYS)
3695                 return -ERESTARTSYS;
3696
3697         return 0;
3698 }
3699
3700 static void _omap_dispc_initialize_irq(void)
3701 {
3702         unsigned long flags;
3703
3704         spin_lock_irqsave(&dispc.irq_lock, flags);
3705
3706         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3707
3708         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3709         if (dss_has_feature(FEAT_MGR_LCD2))
3710                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3711         if (dss_has_feature(FEAT_MGR_LCD3))
3712                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
3713         if (dss_feat_get_num_ovls() > 3)
3714                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3715
3716         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3717          * so clear it */
3718         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3719
3720         _omap_dispc_set_irqs();
3721
3722         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3723 }
3724
3725 void dispc_enable_sidle(void)
3726 {
3727         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3728 }
3729
3730 void dispc_disable_sidle(void)
3731 {
3732         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3733 }
3734
3735 static void _omap_dispc_initial_config(void)
3736 {
3737         u32 l;
3738
3739         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3740         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3741                 l = dispc_read_reg(DISPC_DIVISOR);
3742                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3743                 l = FLD_MOD(l, 1, 0, 0);
3744                 l = FLD_MOD(l, 1, 23, 16);
3745                 dispc_write_reg(DISPC_DIVISOR, l);
3746         }
3747
3748         /* FUNCGATED */
3749         if (dss_has_feature(FEAT_FUNCGATED))
3750                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3751
3752         _dispc_setup_color_conv_coef();
3753
3754         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3755
3756         dispc_init_fifos();
3757
3758         dispc_configure_burst_sizes();
3759
3760         dispc_ovl_enable_zorder_planes();
3761 }
3762
3763 static const struct dispc_features omap24xx_dispc_feats __initconst = {
3764         .sw_start               =       5,
3765         .fp_start               =       15,
3766         .bp_start               =       27,
3767         .sw_max                 =       64,
3768         .vp_max                 =       255,
3769         .hp_max                 =       256,
3770         .calc_scaling           =       dispc_ovl_calc_scaling_24xx,
3771         .calc_core_clk          =       calc_core_clk_24xx,
3772         .num_fifos              =       3,
3773 };
3774
3775 static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3776         .sw_start               =       5,
3777         .fp_start               =       15,
3778         .bp_start               =       27,
3779         .sw_max                 =       64,
3780         .vp_max                 =       255,
3781         .hp_max                 =       256,
3782         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3783         .calc_core_clk          =       calc_core_clk_34xx,
3784         .num_fifos              =       3,
3785 };
3786
3787 static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3788         .sw_start               =       7,
3789         .fp_start               =       19,
3790         .bp_start               =       31,
3791         .sw_max                 =       256,
3792         .vp_max                 =       4095,
3793         .hp_max                 =       4096,
3794         .calc_scaling           =       dispc_ovl_calc_scaling_34xx,
3795         .calc_core_clk          =       calc_core_clk_34xx,
3796         .num_fifos              =       3,
3797 };
3798
3799 static const struct dispc_features omap44xx_dispc_feats __initconst = {
3800         .sw_start               =       7,
3801         .fp_start               =       19,
3802         .bp_start               =       31,
3803         .sw_max                 =       256,
3804         .vp_max                 =       4095,
3805         .hp_max                 =       4096,
3806         .calc_scaling           =       dispc_ovl_calc_scaling_44xx,
3807         .calc_core_clk          =       calc_core_clk_44xx,
3808         .num_fifos              =       5,
3809         .gfx_fifo_workaround    =       true,
3810 };
3811
3812 static int __init dispc_init_features(struct device *dev)
3813 {
3814         const struct dispc_features *src;
3815         struct dispc_features *dst;
3816
3817         dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3818         if (!dst) {
3819                 dev_err(dev, "Failed to allocate DISPC Features\n");
3820                 return -ENOMEM;
3821         }
3822
3823         if (cpu_is_omap24xx()) {
3824                 src = &omap24xx_dispc_feats;
3825         } else if (cpu_is_omap34xx()) {
3826                 if (omap_rev() < OMAP3430_REV_ES3_0)
3827                         src = &omap34xx_rev1_0_dispc_feats;
3828                 else
3829                         src = &omap34xx_rev3_0_dispc_feats;
3830         } else if (cpu_is_omap44xx()) {
3831                 src = &omap44xx_dispc_feats;
3832         } else {
3833                 return -ENODEV;
3834         }
3835
3836         memcpy(dst, src, sizeof(*dst));
3837         dispc.feat = dst;
3838
3839         return 0;
3840 }
3841
3842 /* DISPC HW IP initialisation */
3843 static int __init omap_dispchw_probe(struct platform_device *pdev)
3844 {
3845         u32 rev;
3846         int r = 0;
3847         struct resource *dispc_mem;
3848         struct clk *clk;
3849
3850         dispc.pdev = pdev;
3851
3852         r = dispc_init_features(&dispc.pdev->dev);
3853         if (r)
3854                 return r;
3855
3856         spin_lock_init(&dispc.irq_lock);
3857
3858 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3859         spin_lock_init(&dispc.irq_stats_lock);
3860         dispc.irq_stats.last_reset = jiffies;
3861 #endif
3862
3863         INIT_WORK(&dispc.error_work, dispc_error_worker);
3864
3865         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3866         if (!dispc_mem) {
3867                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3868                 return -EINVAL;
3869         }
3870
3871         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3872                                   resource_size(dispc_mem));
3873         if (!dispc.base) {
3874                 DSSERR("can't ioremap DISPC\n");
3875                 return -ENOMEM;
3876         }
3877
3878         dispc.irq = platform_get_irq(dispc.pdev, 0);
3879         if (dispc.irq < 0) {
3880                 DSSERR("platform_get_irq failed\n");
3881                 return -ENODEV;
3882         }
3883
3884         r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3885                              IRQF_SHARED, "OMAP DISPC", dispc.pdev);
3886         if (r < 0) {
3887                 DSSERR("request_irq failed\n");
3888                 return r;
3889         }
3890
3891         clk = clk_get(&pdev->dev, "fck");
3892         if (IS_ERR(clk)) {
3893                 DSSERR("can't get fck\n");
3894                 r = PTR_ERR(clk);
3895                 return r;
3896         }
3897
3898         dispc.dss_clk = clk;
3899
3900         pm_runtime_enable(&pdev->dev);
3901
3902         r = dispc_runtime_get();
3903         if (r)
3904                 goto err_runtime_get;
3905
3906         _omap_dispc_initial_config();
3907
3908         _omap_dispc_initialize_irq();
3909
3910         rev = dispc_read_reg(DISPC_REVISION);
3911         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3912                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3913
3914         dispc_runtime_put();
3915
3916         dss_debugfs_create_file("dispc", dispc_dump_regs);
3917
3918 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3919         dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3920 #endif
3921         return 0;
3922
3923 err_runtime_get:
3924         pm_runtime_disable(&pdev->dev);
3925         clk_put(dispc.dss_clk);
3926         return r;
3927 }
3928
3929 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3930 {
3931         pm_runtime_disable(&pdev->dev);
3932
3933         clk_put(dispc.dss_clk);
3934
3935         return 0;
3936 }
3937
3938 static int dispc_runtime_suspend(struct device *dev)
3939 {
3940         dispc_save_context();
3941
3942         return 0;
3943 }
3944
3945 static int dispc_runtime_resume(struct device *dev)
3946 {
3947         dispc_restore_context();
3948
3949         return 0;
3950 }
3951
3952 static const struct dev_pm_ops dispc_pm_ops = {
3953         .runtime_suspend = dispc_runtime_suspend,
3954         .runtime_resume = dispc_runtime_resume,
3955 };
3956
3957 static struct platform_driver omap_dispchw_driver = {
3958         .remove         = __exit_p(omap_dispchw_remove),
3959         .driver         = {
3960                 .name   = "omapdss_dispc",
3961                 .owner  = THIS_MODULE,
3962                 .pm     = &dispc_pm_ops,
3963         },
3964 };
3965
3966 int __init dispc_init_platform_driver(void)
3967 {
3968         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3969 }
3970
3971 void __exit dispc_uninit_platform_driver(void)
3972 {
3973         platform_driver_unregister(&omap_dispchw_driver);
3974 }