Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/export.h>
  29 #include <linux/clk.h>
  30 #include <linux/io.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/delay.h>
  34 #include <linux/workqueue.h>
  35 #include <linux/hardirq.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 enum omap_burst_size {
  67         BURST_SIZE_X2 = 0,
  68         BURST_SIZE_X4 = 1,
  69         BURST_SIZE_X8 = 2,
  70 };
  71
  72 #define REG_GET(idx, start, end) \
  73         FLD_GET(dispc_read_reg(idx), start, end)
  74
  75 #define REG_FLD_MOD(idx, val, start, end)                               \
  76         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  77
  78 struct dispc_irq_stats {
  79         unsigned long last_reset;
  80         unsigned irq_count;
  81         unsigned irqs[32];
  82 };
  83
  84 static struct {
  85         struct platform_device *pdev;
  86         void __iomem    *base;
  87
  88         int             ctx_loss_cnt;
  89
  90         int irq;
  91         struct clk *dss_clk;
  92
  93         u32     fifo_size[MAX_DSS_OVERLAYS];
  94
  95         spinlock_t irq_lock;
  96         u32 irq_error_mask;
  97         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
  98         u32 error_irqs;
  99         struct work_struct error_work;
 100
 101         bool            ctx_valid;
 102         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 103
 104 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 105         spinlock_t irq_stats_lock;
 106         struct dispc_irq_stats irq_stats;
 107 #endif
 108 } dispc;
 109
 110 enum omap_color_component {
 111         /* used for all color formats for OMAP3 and earlier
 112          * and for RGB and Y color component on OMAP4
 113          */
 114         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 115         /* used for UV component for
 116          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 117          * color formats on OMAP4
 118          */
 119         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 120 };
 121
 122 static void _omap_dispc_set_irqs(void);
 123
 124 static inline void dispc_write_reg(const u16 idx, u32 val)
 125 {
 126         __raw_writel(val, dispc.base + idx);
 127 }
 128
 129 static inline u32 dispc_read_reg(const u16 idx)
 130 {
 131         return __raw_readl(dispc.base + idx);
 132 }
 133
 134 static int dispc_get_ctx_loss_count(void)
 135 {
 136         struct device *dev = &dispc.pdev->dev;
 137         struct omap_display_platform_data *pdata = dev->platform_data;
 138         struct omap_dss_board_info *board_data = pdata->board_data;
 139         int cnt;
 140
 141         if (!board_data->get_context_loss_count)
 142                 return -ENOENT;
 143
 144         cnt = board_data->get_context_loss_count(dev);
 145
 146         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 147
 148         return cnt;
 149 }
 150
 151 #define SR(reg) \
 152         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 153 #define RR(reg) \
 154         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 155
 156 static void dispc_save_context(void)
 157 {
 158         int i, j;
 159
 160         DSSDBG("dispc_save_context\n");
 161
 162         SR(IRQENABLE);
 163         SR(CONTROL);
 164         SR(CONFIG);
 165         SR(LINE_NUMBER);
 166         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 167                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 168                 SR(GLOBAL_ALPHA);
 169         if (dss_has_feature(FEAT_MGR_LCD2)) {
 170                 SR(CONTROL2);
 171                 SR(CONFIG2);
 172         }
 173
 174         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 175                 SR(DEFAULT_COLOR(i));
 176                 SR(TRANS_COLOR(i));
 177                 SR(SIZE_MGR(i));
 178                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 179                         continue;
 180                 SR(TIMING_H(i));
 181                 SR(TIMING_V(i));
 182                 SR(POL_FREQ(i));
 183                 SR(DIVISORo(i));
 184
 185                 SR(DATA_CYCLE1(i));
 186                 SR(DATA_CYCLE2(i));
 187                 SR(DATA_CYCLE3(i));
 188
 189                 if (dss_has_feature(FEAT_CPR)) {
 190                         SR(CPR_COEF_R(i));
 191                         SR(CPR_COEF_G(i));
 192                         SR(CPR_COEF_B(i));
 193                 }
 194         }
 195
 196         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 197                 SR(OVL_BA0(i));
 198                 SR(OVL_BA1(i));
 199                 SR(OVL_POSITION(i));
 200                 SR(OVL_SIZE(i));
 201                 SR(OVL_ATTRIBUTES(i));
 202                 SR(OVL_FIFO_THRESHOLD(i));
 203                 SR(OVL_ROW_INC(i));
 204                 SR(OVL_PIXEL_INC(i));
 205                 if (dss_has_feature(FEAT_PRELOAD))
 206                         SR(OVL_PRELOAD(i));
 207                 if (i == OMAP_DSS_GFX) {
 208                         SR(OVL_WINDOW_SKIP(i));
 209                         SR(OVL_TABLE_BA(i));
 210                         continue;
 211                 }
 212                 SR(OVL_FIR(i));
 213                 SR(OVL_PICTURE_SIZE(i));
 214                 SR(OVL_ACCU0(i));
 215                 SR(OVL_ACCU1(i));
 216
 217                 for (j = 0; j < 8; j++)
 218                         SR(OVL_FIR_COEF_H(i, j));
 219
 220                 for (j = 0; j < 8; j++)
 221                         SR(OVL_FIR_COEF_HV(i, j));
 222
 223                 for (j = 0; j < 5; j++)
 224                         SR(OVL_CONV_COEF(i, j));
 225
 226                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 227                         for (j = 0; j < 8; j++)
 228                                 SR(OVL_FIR_COEF_V(i, j));
 229                 }
 230
 231                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 232                         SR(OVL_BA0_UV(i));
 233                         SR(OVL_BA1_UV(i));
 234                         SR(OVL_FIR2(i));
 235                         SR(OVL_ACCU2_0(i));
 236                         SR(OVL_ACCU2_1(i));
 237
 238                         for (j = 0; j < 8; j++)
 239                                 SR(OVL_FIR_COEF_H2(i, j));
 240
 241                         for (j = 0; j < 8; j++)
 242                                 SR(OVL_FIR_COEF_HV2(i, j));
 243
 244                         for (j = 0; j < 8; j++)
 245                                 SR(OVL_FIR_COEF_V2(i, j));
 246                 }
 247                 if (dss_has_feature(FEAT_ATTR2))
 248                         SR(OVL_ATTRIBUTES2(i));
 249         }
 250
 251         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 252                 SR(DIVISOR);
 253
 254         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 255         dispc.ctx_valid = true;
 256
 257         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 258 }
 259
 260 static void dispc_restore_context(void)
 261 {
 262         int i, j, ctx;
 263
 264         DSSDBG("dispc_restore_context\n");
 265
 266         if (!dispc.ctx_valid)
 267                 return;
 268
 269         ctx = dispc_get_ctx_loss_count();
 270
 271         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 272                 return;
 273
 274         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 275                         dispc.ctx_loss_cnt, ctx);
 276
 277         /*RR(IRQENABLE);*/
 278         /*RR(CONTROL);*/
 279         RR(CONFIG);
 280         RR(LINE_NUMBER);
 281         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
 282                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 283                 RR(GLOBAL_ALPHA);
 284         if (dss_has_feature(FEAT_MGR_LCD2))
 285                 RR(CONFIG2);
 286
 287         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 288                 RR(DEFAULT_COLOR(i));
 289                 RR(TRANS_COLOR(i));
 290                 RR(SIZE_MGR(i));
 291                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 292                         continue;
 293                 RR(TIMING_H(i));
 294                 RR(TIMING_V(i));
 295                 RR(POL_FREQ(i));
 296                 RR(DIVISORo(i));
 297
 298                 RR(DATA_CYCLE1(i));
 299                 RR(DATA_CYCLE2(i));
 300                 RR(DATA_CYCLE3(i));
 301
 302                 if (dss_has_feature(FEAT_CPR)) {
 303                         RR(CPR_COEF_R(i));
 304                         RR(CPR_COEF_G(i));
 305                         RR(CPR_COEF_B(i));
 306                 }
 307         }
 308
 309         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 310                 RR(OVL_BA0(i));
 311                 RR(OVL_BA1(i));
 312                 RR(OVL_POSITION(i));
 313                 RR(OVL_SIZE(i));
 314                 RR(OVL_ATTRIBUTES(i));
 315                 RR(OVL_FIFO_THRESHOLD(i));
 316                 RR(OVL_ROW_INC(i));
 317                 RR(OVL_PIXEL_INC(i));
 318                 if (dss_has_feature(FEAT_PRELOAD))
 319                         RR(OVL_PRELOAD(i));
 320                 if (i == OMAP_DSS_GFX) {
 321                         RR(OVL_WINDOW_SKIP(i));
 322                         RR(OVL_TABLE_BA(i));
 323                         continue;
 324                 }
 325                 RR(OVL_FIR(i));
 326                 RR(OVL_PICTURE_SIZE(i));
 327                 RR(OVL_ACCU0(i));
 328                 RR(OVL_ACCU1(i));
 329
 330                 for (j = 0; j < 8; j++)
 331                         RR(OVL_FIR_COEF_H(i, j));
 332
 333                 for (j = 0; j < 8; j++)
 334                         RR(OVL_FIR_COEF_HV(i, j));
 335
 336                 for (j = 0; j < 5; j++)
 337                         RR(OVL_CONV_COEF(i, j));
 338
 339                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 340                         for (j = 0; j < 8; j++)
 341                                 RR(OVL_FIR_COEF_V(i, j));
 342                 }
 343
 344                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 345                         RR(OVL_BA0_UV(i));
 346                         RR(OVL_BA1_UV(i));
 347                         RR(OVL_FIR2(i));
 348                         RR(OVL_ACCU2_0(i));
 349                         RR(OVL_ACCU2_1(i));
 350
 351                         for (j = 0; j < 8; j++)
 352                                 RR(OVL_FIR_COEF_H2(i, j));
 353
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_HV2(i, j));
 356
 357                         for (j = 0; j < 8; j++)
 358                                 RR(OVL_FIR_COEF_V2(i, j));
 359                 }
 360                 if (dss_has_feature(FEAT_ATTR2))
 361                         RR(OVL_ATTRIBUTES2(i));
 362         }
 363
 364         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 365                 RR(DIVISOR);
 366
 367         /* enable last, because LCD & DIGIT enable are here */
 368         RR(CONTROL);
 369         if (dss_has_feature(FEAT_MGR_LCD2))
 370                 RR(CONTROL2);
 371         /* clear spurious SYNC_LOST_DIGIT interrupts */
 372         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 373
 374         /*
 375          * enable last so IRQs won't trigger before
 376          * the context is fully restored
 377          */
 378         RR(IRQENABLE);
 379
 380         DSSDBG("context restored\n");
 381 }
 382
 383 #undef SR
 384 #undef RR
 385
 386 int dispc_runtime_get(void)
 387 {
 388         int r;
 389
 390         DSSDBG("dispc_runtime_get\n");
 391
 392         r = pm_runtime_get_sync(&dispc.pdev->dev);
 393         WARN_ON(r < 0);
 394         return r < 0 ? r : 0;
 395 }
 396
 397 void dispc_runtime_put(void)
 398 {
 399         int r;
 400
 401         DSSDBG("dispc_runtime_put\n");
 402
 403         r = pm_runtime_put_sync(&dispc.pdev->dev);
 404         WARN_ON(r < 0);
 405 }
 406
 407 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
 408 {
 409         if (channel == OMAP_DSS_CHANNEL_LCD ||
 410                         channel == OMAP_DSS_CHANNEL_LCD2)
 411                 return true;
 412         else
 413                 return false;
 414 }
 415
 416 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
 417 {
 418         struct omap_overlay_manager *mgr =
 419                 omap_dss_get_overlay_manager(channel);
 420
 421         return mgr ? mgr->device : NULL;
 422 }
 423
 424 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
 425 {
 426         switch (channel) {
 427         case OMAP_DSS_CHANNEL_LCD:
 428                 return DISPC_IRQ_VSYNC;
 429         case OMAP_DSS_CHANNEL_LCD2:
 430                 return DISPC_IRQ_VSYNC2;
 431         case OMAP_DSS_CHANNEL_DIGIT:
 432                 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
 433         default:
 434                 BUG();
 435         }
 436 }
 437
 438 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
 439 {
 440         switch (channel) {
 441         case OMAP_DSS_CHANNEL_LCD:
 442                 return DISPC_IRQ_FRAMEDONE;
 443         case OMAP_DSS_CHANNEL_LCD2:
 444                 return DISPC_IRQ_FRAMEDONE2;
 445         case OMAP_DSS_CHANNEL_DIGIT:
 446                 return 0;
 447         default:
 448                 BUG();
 449         }
 450 }
 451
 452 bool dispc_mgr_go_busy(enum omap_channel channel)
 453 {
 454         int bit;
 455
 456         if (dispc_mgr_is_lcd(channel))
 457                 bit = 5; /* GOLCD */
 458         else
 459                 bit = 6; /* GODIGIT */
 460
 461         if (channel == OMAP_DSS_CHANNEL_LCD2)
 462                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 463         else
 464                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 465 }
 466
 467 void dispc_mgr_go(enum omap_channel channel)
 468 {
 469         int bit;
 470         bool enable_bit, go_bit;
 471
 472         if (dispc_mgr_is_lcd(channel))
 473                 bit = 0; /* LCDENABLE */
 474         else
 475                 bit = 1; /* DIGITALENABLE */
 476
 477         /* if the channel is not enabled, we don't need GO */
 478         if (channel == OMAP_DSS_CHANNEL_LCD2)
 479                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 480         else
 481                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 482
 483         if (!enable_bit)
 484                 return;
 485
 486         if (dispc_mgr_is_lcd(channel))
 487                 bit = 5; /* GOLCD */
 488         else
 489                 bit = 6; /* GODIGIT */
 490
 491         if (channel == OMAP_DSS_CHANNEL_LCD2)
 492                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 493         else
 494                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 495
 496         if (go_bit) {
 497                 DSSERR("GO bit not down for channel %d\n", channel);
 498                 return;
 499         }
 500
 501         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 502                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 503
 504         if (channel == OMAP_DSS_CHANNEL_LCD2)
 505                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 506         else
 507                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 508 }
 509
 510 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 511 {
 512         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 513 }
 514
 515 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 516 {
 517         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 518 }
 519
 520 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 521 {
 522         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 523 }
 524
 525 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 526 {
 527         BUG_ON(plane == OMAP_DSS_GFX);
 528
 529         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 530 }
 531
 532 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 533                 u32 value)
 534 {
 535         BUG_ON(plane == OMAP_DSS_GFX);
 536
 537         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 538 }
 539
 540 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 541 {
 542         BUG_ON(plane == OMAP_DSS_GFX);
 543
 544         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 545 }
 546
 547 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
 548                                 int fir_vinc, int five_taps,
 549                                 enum omap_color_component color_comp)
 550 {
 551         const struct dispc_coef *h_coef, *v_coef;
 552         int i;
 553
 554         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
 555         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
 556
 557         for (i = 0; i < 8; i++) {
 558                 u32 h, hv;
 559
 560                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
 561                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
 562                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
 563                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
 564                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
 565                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
 566                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
 567                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
 568
 569                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 570                         dispc_ovl_write_firh_reg(plane, i, h);
 571                         dispc_ovl_write_firhv_reg(plane, i, hv);
 572                 } else {
 573                         dispc_ovl_write_firh2_reg(plane, i, h);
 574                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 575                 }
 576
 577         }
 578
 579         if (five_taps) {
 580                 for (i = 0; i < 8; i++) {
 581                         u32 v;
 582                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
 583                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
 584                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 585                                 dispc_ovl_write_firv_reg(plane, i, v);
 586                         else
 587                                 dispc_ovl_write_firv2_reg(plane, i, v);
 588                 }
 589         }
 590 }
 591
 592 static void _dispc_setup_color_conv_coef(void)
 593 {
 594         int i;
 595         const struct color_conv_coef {
 596                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 597                 int  full_range;
 598         }  ctbl_bt601_5 = {
 599                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 600         };
 601
 602         const struct color_conv_coef *ct;
 603
 604 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 605
 606         ct = &ctbl_bt601_5;
 607
 608         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 609                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 610                         CVAL(ct->rcr, ct->ry));
 611                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 612                         CVAL(ct->gy,  ct->rcb));
 613                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 614                         CVAL(ct->gcb, ct->gcr));
 615                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 616                         CVAL(ct->bcr, ct->by));
 617                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 618                         CVAL(0, ct->bcb));
 619
 620                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 621                         11, 11);
 622         }
 623
 624 #undef CVAL
 625 }
 626
 627
 628 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 629 {
 630         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 631 }
 632
 633 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 634 {
 635         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 636 }
 637
 638 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 639 {
 640         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 641 }
 642
 643 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 644 {
 645         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 646 }
 647
 648 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 649 {
 650         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 651
 652         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 653 }
 654
 655 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 656 {
 657         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 658
 659         if (plane == OMAP_DSS_GFX)
 660                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 661         else
 662                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 663 }
 664
 665 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 666 {
 667         u32 val;
 668
 669         BUG_ON(plane == OMAP_DSS_GFX);
 670
 671         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 672
 673         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 674 }
 675
 676 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
 677 {
 678         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 679
 680         if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
 681                 return;
 682
 683         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
 684 }
 685
 686 static void dispc_ovl_enable_zorder_planes(void)
 687 {
 688         int i;
 689
 690         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
 691                 return;
 692
 693         for (i = 0; i < dss_feat_get_num_ovls(); i++)
 694                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
 695 }
 696
 697 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 698 {
 699         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 700
 701         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 702                 return;
 703
 704         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 705 }
 706
 707 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 708 {
 709         static const unsigned shifts[] = { 0, 8, 16, 24, };
 710         int shift;
 711         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 712
 713         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 714                 return;
 715
 716         shift = shifts[plane];
 717         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 718 }
 719
 720 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 721 {
 722         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 723 }
 724
 725 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 726 {
 727         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 728 }
 729
 730 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 731                 enum omap_color_mode color_mode)
 732 {
 733         u32 m = 0;
 734         if (plane != OMAP_DSS_GFX) {
 735                 switch (color_mode) {
 736                 case OMAP_DSS_COLOR_NV12:
 737                         m = 0x0; break;
 738                 case OMAP_DSS_COLOR_RGB12U:
 739                         m = 0x1; break;
 740                 case OMAP_DSS_COLOR_RGBA16:
 741                         m = 0x2; break;
 742                 case OMAP_DSS_COLOR_RGBX16:
 743                         m = 0x4; break;
 744                 case OMAP_DSS_COLOR_ARGB16:
 745                         m = 0x5; break;
 746                 case OMAP_DSS_COLOR_RGB16:
 747                         m = 0x6; break;
 748                 case OMAP_DSS_COLOR_ARGB16_1555:
 749                         m = 0x7; break;
 750                 case OMAP_DSS_COLOR_RGB24U:
 751                         m = 0x8; break;
 752                 case OMAP_DSS_COLOR_RGB24P:
 753                         m = 0x9; break;
 754                 case OMAP_DSS_COLOR_YUV2:
 755                         m = 0xa; break;
 756                 case OMAP_DSS_COLOR_UYVY:
 757                         m = 0xb; break;
 758                 case OMAP_DSS_COLOR_ARGB32:
 759                         m = 0xc; break;
 760                 case OMAP_DSS_COLOR_RGBA32:
 761                         m = 0xd; break;
 762                 case OMAP_DSS_COLOR_RGBX32:
 763                         m = 0xe; break;
 764                 case OMAP_DSS_COLOR_XRGB16_1555:
 765                         m = 0xf; break;
 766                 default:
 767                         BUG(); break;
 768                 }
 769         } else {
 770                 switch (color_mode) {
 771                 case OMAP_DSS_COLOR_CLUT1:
 772                         m = 0x0; break;
 773                 case OMAP_DSS_COLOR_CLUT2:
 774                         m = 0x1; break;
 775                 case OMAP_DSS_COLOR_CLUT4:
 776                         m = 0x2; break;
 777                 case OMAP_DSS_COLOR_CLUT8:
 778                         m = 0x3; break;
 779                 case OMAP_DSS_COLOR_RGB12U:
 780                         m = 0x4; break;
 781                 case OMAP_DSS_COLOR_ARGB16:
 782                         m = 0x5; break;
 783                 case OMAP_DSS_COLOR_RGB16:
 784                         m = 0x6; break;
 785                 case OMAP_DSS_COLOR_ARGB16_1555:
 786                         m = 0x7; break;
 787                 case OMAP_DSS_COLOR_RGB24U:
 788                         m = 0x8; break;
 789                 case OMAP_DSS_COLOR_RGB24P:
 790                         m = 0x9; break;
 791                 case OMAP_DSS_COLOR_YUV2:
 792                         m = 0xa; break;
 793                 case OMAP_DSS_COLOR_UYVY:
 794                         m = 0xb; break;
 795                 case OMAP_DSS_COLOR_ARGB32:
 796                         m = 0xc; break;
 797                 case OMAP_DSS_COLOR_RGBA32:
 798                         m = 0xd; break;
 799                 case OMAP_DSS_COLOR_RGBX32:
 800                         m = 0xe; break;
 801                 case OMAP_DSS_COLOR_XRGB16_1555:
 802                         m = 0xf; break;
 803                 default:
 804                         BUG(); break;
 805                 }
 806         }
 807
 808         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 809 }
 810
 811 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
 812 {
 813         int shift;
 814         u32 val;
 815         int chan = 0, chan2 = 0;
 816
 817         switch (plane) {
 818         case OMAP_DSS_GFX:
 819                 shift = 8;
 820                 break;
 821         case OMAP_DSS_VIDEO1:
 822         case OMAP_DSS_VIDEO2:
 823         case OMAP_DSS_VIDEO3:
 824                 shift = 16;
 825                 break;
 826         default:
 827                 BUG();
 828                 return;
 829         }
 830
 831         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 832         if (dss_has_feature(FEAT_MGR_LCD2)) {
 833                 switch (channel) {
 834                 case OMAP_DSS_CHANNEL_LCD:
 835                         chan = 0;
 836                         chan2 = 0;
 837                         break;
 838                 case OMAP_DSS_CHANNEL_DIGIT:
 839                         chan = 1;
 840                         chan2 = 0;
 841                         break;
 842                 case OMAP_DSS_CHANNEL_LCD2:
 843                         chan = 0;
 844                         chan2 = 1;
 845                         break;
 846                 default:
 847                         BUG();
 848                 }
 849
 850                 val = FLD_MOD(val, chan, shift, shift);
 851                 val = FLD_MOD(val, chan2, 31, 30);
 852         } else {
 853                 val = FLD_MOD(val, channel, shift, shift);
 854         }
 855         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 856 }
 857
 858 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
 859 {
 860         int shift;
 861         u32 val;
 862         enum omap_channel channel;
 863
 864         switch (plane) {
 865         case OMAP_DSS_GFX:
 866                 shift = 8;
 867                 break;
 868         case OMAP_DSS_VIDEO1:
 869         case OMAP_DSS_VIDEO2:
 870         case OMAP_DSS_VIDEO3:
 871                 shift = 16;
 872                 break;
 873         default:
 874                 BUG();
 875         }
 876
 877         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 878
 879         if (dss_has_feature(FEAT_MGR_LCD2)) {
 880                 if (FLD_GET(val, 31, 30) == 0)
 881                         channel = FLD_GET(val, shift, shift);
 882                 else
 883                         channel = OMAP_DSS_CHANNEL_LCD2;
 884         } else {
 885                 channel = FLD_GET(val, shift, shift);
 886         }
 887
 888         return channel;
 889 }
 890
 891 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 892                 enum omap_burst_size burst_size)
 893 {
 894         static const unsigned shifts[] = { 6, 14, 14, 14, };
 895         int shift;
 896
 897         shift = shifts[plane];
 898         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 899 }
 900
 901 static void dispc_configure_burst_sizes(void)
 902 {
 903         int i;
 904         const int burst_size = BURST_SIZE_X8;
 905
 906         /* Configure burst size always to maximum size */
 907         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 908                 dispc_ovl_set_burst_size(i, burst_size);
 909 }
 910
 911 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
 912 {
 913         unsigned unit = dss_feat_get_burst_size_unit();
 914         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 915         return unit * 8;
 916 }
 917
 918 void dispc_enable_gamma_table(bool enable)
 919 {
 920         /*
 921          * This is partially implemented to support only disabling of
 922          * the gamma table.
 923          */
 924         if (enable) {
 925                 DSSWARN("Gamma table enabling for TV not yet supported");
 926                 return;
 927         }
 928
 929         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 930 }
 931
 932 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
 933 {
 934         u16 reg;
 935
 936         if (channel == OMAP_DSS_CHANNEL_LCD)
 937                 reg = DISPC_CONFIG;
 938         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 939                 reg = DISPC_CONFIG2;
 940         else
 941                 return;
 942
 943         REG_FLD_MOD(reg, enable, 15, 15);
 944 }
 945
 946 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 947                 struct omap_dss_cpr_coefs *coefs)
 948 {
 949         u32 coef_r, coef_g, coef_b;
 950
 951         if (!dispc_mgr_is_lcd(channel))
 952                 return;
 953
 954         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 955                 FLD_VAL(coefs->rb, 9, 0);
 956         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 957                 FLD_VAL(coefs->gb, 9, 0);
 958         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 959                 FLD_VAL(coefs->bb, 9, 0);
 960
 961         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 962         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 963         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 964 }
 965
 966 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
 967 {
 968         u32 val;
 969
 970         BUG_ON(plane == OMAP_DSS_GFX);
 971
 972         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 973         val = FLD_MOD(val, enable, 9, 9);
 974         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 975 }
 976
 977 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
 978 {
 979         static const unsigned shifts[] = { 5, 10, 10, 10 };
 980         int shift;
 981
 982         shift = shifts[plane];
 983         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
 984 }
 985
 986 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 987 {
 988         u32 val;
 989         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 990         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 991         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
 992 }
 993
 994 void dispc_set_digit_size(u16 width, u16 height)
 995 {
 996         u32 val;
 997         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 998         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 999         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1000 }
1001
1002 static void dispc_read_plane_fifo_sizes(void)
1003 {
1004         u32 size;
1005         int plane;
1006         u8 start, end;
1007         u32 unit;
1008
1009         unit = dss_feat_get_buffer_size_unit();
1010
1011         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1012
1013         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1014                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1015                 size *= unit;
1016                 dispc.fifo_size[plane] = size;
1017         }
1018 }
1019
1020 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1021 {
1022         return dispc.fifo_size[plane];
1023 }
1024
1025 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1026 {
1027         u8 hi_start, hi_end, lo_start, lo_end;
1028         u32 unit;
1029
1030         unit = dss_feat_get_buffer_size_unit();
1031
1032         WARN_ON(low % unit != 0);
1033         WARN_ON(high % unit != 0);
1034
1035         low /= unit;
1036         high /= unit;
1037
1038         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1039         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1040
1041         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1042                         plane,
1043                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1044                                 lo_start, lo_end) * unit,
1045                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1046                                 hi_start, hi_end) * unit,
1047                         low * unit, high * unit);
1048
1049         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1050                         FLD_VAL(high, hi_start, hi_end) |
1051                         FLD_VAL(low, lo_start, lo_end));
1052 }
1053
1054 void dispc_enable_fifomerge(bool enable)
1055 {
1056         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1057                 WARN_ON(enable);
1058                 return;
1059         }
1060
1061         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1062         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1063 }
1064
1065 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1066                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1067 {
1068         /*
1069          * All sizes are in bytes. Both the buffer and burst are made of
1070          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1071          */
1072
1073         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1074         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1075         int i;
1076
1077         burst_size = dispc_ovl_get_burst_size(plane);
1078         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1079
1080         if (use_fifomerge) {
1081                 total_fifo_size = 0;
1082                 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1083                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1084         } else {
1085                 total_fifo_size = ovl_fifo_size;
1086         }
1087
1088         /*
1089          * We use the same low threshold for both fifomerge and non-fifomerge
1090          * cases, but for fifomerge we calculate the high threshold using the
1091          * combined fifo size
1092          */
1093
1094         if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1095                 *fifo_low = ovl_fifo_size - burst_size * 2;
1096                 *fifo_high = total_fifo_size - burst_size;
1097         } else {
1098                 *fifo_low = ovl_fifo_size - burst_size;
1099                 *fifo_high = total_fifo_size - buf_unit;
1100         }
1101 }
1102
1103 static void dispc_ovl_set_fir(enum omap_plane plane,
1104                                 int hinc, int vinc,
1105                                 enum omap_color_component color_comp)
1106 {
1107         u32 val;
1108
1109         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1110                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1111
1112                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1113                                         &hinc_start, &hinc_end);
1114                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1115                                         &vinc_start, &vinc_end);
1116                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1117                                 FLD_VAL(hinc, hinc_start, hinc_end);
1118
1119                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1120         } else {
1121                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1122                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1123         }
1124 }
1125
1126 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1127 {
1128         u32 val;
1129         u8 hor_start, hor_end, vert_start, vert_end;
1130
1131         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1132         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1133
1134         val = FLD_VAL(vaccu, vert_start, vert_end) |
1135                         FLD_VAL(haccu, hor_start, hor_end);
1136
1137         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1138 }
1139
1140 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1141 {
1142         u32 val;
1143         u8 hor_start, hor_end, vert_start, vert_end;
1144
1145         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1146         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1147
1148         val = FLD_VAL(vaccu, vert_start, vert_end) |
1149                         FLD_VAL(haccu, hor_start, hor_end);
1150
1151         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1152 }
1153
1154 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1155                 int vaccu)
1156 {
1157         u32 val;
1158
1159         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1160         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1161 }
1162
1163 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1164                 int vaccu)
1165 {
1166         u32 val;
1167
1168         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1169         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1170 }
1171
1172 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1173                 u16 orig_width, u16 orig_height,
1174                 u16 out_width, u16 out_height,
1175                 bool five_taps, u8 rotation,
1176                 enum omap_color_component color_comp)
1177 {
1178         int fir_hinc, fir_vinc;
1179
1180         fir_hinc = 1024 * orig_width / out_width;
1181         fir_vinc = 1024 * orig_height / out_height;
1182
1183         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1184                                 color_comp);
1185         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1186 }
1187
1188 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1189                 u16 orig_width, u16 orig_height,
1190                 u16 out_width, u16 out_height,
1191                 bool ilace, bool five_taps,
1192                 bool fieldmode, enum omap_color_mode color_mode,
1193                 u8 rotation)
1194 {
1195         int accu0 = 0;
1196         int accu1 = 0;
1197         u32 l;
1198
1199         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1200                                 out_width, out_height, five_taps,
1201                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1202         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1203
1204         /* RESIZEENABLE and VERTICALTAPS */
1205         l &= ~((0x3 << 5) | (0x1 << 21));
1206         l |= (orig_width != out_width) ? (1 << 5) : 0;
1207         l |= (orig_height != out_height) ? (1 << 6) : 0;
1208         l |= five_taps ? (1 << 21) : 0;
1209
1210         /* VRESIZECONF and HRESIZECONF */
1211         if (dss_has_feature(FEAT_RESIZECONF)) {
1212                 l &= ~(0x3 << 7);
1213                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1214                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1215         }
1216
1217         /* LINEBUFFERSPLIT */
1218         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1219                 l &= ~(0x1 << 22);
1220                 l |= five_taps ? (1 << 22) : 0;
1221         }
1222
1223         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1224
1225         /*
1226          * field 0 = even field = bottom field
1227          * field 1 = odd field = top field
1228          */
1229         if (ilace && !fieldmode) {
1230                 accu1 = 0;
1231                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1232                 if (accu0 >= 1024/2) {
1233                         accu1 = 1024/2;
1234                         accu0 -= accu1;
1235                 }
1236         }
1237
1238         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1239         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1240 }
1241
1242 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1243                 u16 orig_width, u16 orig_height,
1244                 u16 out_width, u16 out_height,
1245                 bool ilace, bool five_taps,
1246                 bool fieldmode, enum omap_color_mode color_mode,
1247                 u8 rotation)
1248 {
1249         int scale_x = out_width != orig_width;
1250         int scale_y = out_height != orig_height;
1251
1252         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1253                 return;
1254         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1255                         color_mode != OMAP_DSS_COLOR_UYVY &&
1256                         color_mode != OMAP_DSS_COLOR_NV12)) {
1257                 /* reset chroma resampling for RGB formats  */
1258                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1259                 return;
1260         }
1261         switch (color_mode) {
1262         case OMAP_DSS_COLOR_NV12:
1263                 /* UV is subsampled by 2 vertically*/
1264                 orig_height >>= 1;
1265                 /* UV is subsampled by 2 horz.*/
1266                 orig_width >>= 1;
1267                 break;
1268         case OMAP_DSS_COLOR_YUV2:
1269         case OMAP_DSS_COLOR_UYVY:
1270                 /*For YUV422 with 90/270 rotation,
1271                  *we don't upsample chroma
1272                  */
1273                 if (rotation == OMAP_DSS_ROT_0 ||
1274                         rotation == OMAP_DSS_ROT_180)
1275                         /* UV is subsampled by 2 hrz*/
1276                         orig_width >>= 1;
1277                 /* must use FIR for YUV422 if rotated */
1278                 if (rotation != OMAP_DSS_ROT_0)
1279                         scale_x = scale_y = true;
1280                 break;
1281         default:
1282                 BUG();
1283         }
1284
1285         if (out_width != orig_width)
1286                 scale_x = true;
1287         if (out_height != orig_height)
1288                 scale_y = true;
1289
1290         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1291                         out_width, out_height, five_taps,
1292                                 rotation, DISPC_COLOR_COMPONENT_UV);
1293
1294         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1295                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1296         /* set H scaling */
1297         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1298         /* set V scaling */
1299         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1300
1301         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1302         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1303 }
1304
1305 static void dispc_ovl_set_scaling(enum omap_plane plane,
1306                 u16 orig_width, u16 orig_height,
1307                 u16 out_width, u16 out_height,
1308                 bool ilace, bool five_taps,
1309                 bool fieldmode, enum omap_color_mode color_mode,
1310                 u8 rotation)
1311 {
1312         BUG_ON(plane == OMAP_DSS_GFX);
1313
1314         dispc_ovl_set_scaling_common(plane,
1315                         orig_width, orig_height,
1316                         out_width, out_height,
1317                         ilace, five_taps,
1318                         fieldmode, color_mode,
1319                         rotation);
1320
1321         dispc_ovl_set_scaling_uv(plane,
1322                 orig_width, orig_height,
1323                 out_width, out_height,
1324                 ilace, five_taps,
1325                 fieldmode, color_mode,
1326                 rotation);
1327 }
1328
1329 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1330                 bool mirroring, enum omap_color_mode color_mode)
1331 {
1332         bool row_repeat = false;
1333         int vidrot = 0;
1334
1335         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1336                         color_mode == OMAP_DSS_COLOR_UYVY) {
1337
1338                 if (mirroring) {
1339                         switch (rotation) {
1340                         case OMAP_DSS_ROT_0:
1341                                 vidrot = 2;
1342                                 break;
1343                         case OMAP_DSS_ROT_90:
1344                                 vidrot = 1;
1345                                 break;
1346                         case OMAP_DSS_ROT_180:
1347                                 vidrot = 0;
1348                                 break;
1349                         case OMAP_DSS_ROT_270:
1350                                 vidrot = 3;
1351                                 break;
1352                         }
1353                 } else {
1354                         switch (rotation) {
1355                         case OMAP_DSS_ROT_0:
1356                                 vidrot = 0;
1357                                 break;
1358                         case OMAP_DSS_ROT_90:
1359                                 vidrot = 1;
1360                                 break;
1361                         case OMAP_DSS_ROT_180:
1362                                 vidrot = 2;
1363                                 break;
1364                         case OMAP_DSS_ROT_270:
1365                                 vidrot = 3;
1366                                 break;
1367                         }
1368                 }
1369
1370                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1371                         row_repeat = true;
1372                 else
1373                         row_repeat = false;
1374         }
1375
1376         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1377         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1378                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1379                         row_repeat ? 1 : 0, 18, 18);
1380 }
1381
1382 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1383 {
1384         switch (color_mode) {
1385         case OMAP_DSS_COLOR_CLUT1:
1386                 return 1;
1387         case OMAP_DSS_COLOR_CLUT2:
1388                 return 2;
1389         case OMAP_DSS_COLOR_CLUT4:
1390                 return 4;
1391         case OMAP_DSS_COLOR_CLUT8:
1392         case OMAP_DSS_COLOR_NV12:
1393                 return 8;
1394         case OMAP_DSS_COLOR_RGB12U:
1395         case OMAP_DSS_COLOR_RGB16:
1396         case OMAP_DSS_COLOR_ARGB16:
1397         case OMAP_DSS_COLOR_YUV2:
1398         case OMAP_DSS_COLOR_UYVY:
1399         case OMAP_DSS_COLOR_RGBA16:
1400         case OMAP_DSS_COLOR_RGBX16:
1401         case OMAP_DSS_COLOR_ARGB16_1555:
1402         case OMAP_DSS_COLOR_XRGB16_1555:
1403                 return 16;
1404         case OMAP_DSS_COLOR_RGB24P:
1405                 return 24;
1406         case OMAP_DSS_COLOR_RGB24U:
1407         case OMAP_DSS_COLOR_ARGB32:
1408         case OMAP_DSS_COLOR_RGBA32:
1409         case OMAP_DSS_COLOR_RGBX32:
1410                 return 32;
1411         default:
1412                 BUG();
1413         }
1414 }
1415
1416 static s32 pixinc(int pixels, u8 ps)
1417 {
1418         if (pixels == 1)
1419                 return 1;
1420         else if (pixels > 1)
1421                 return 1 + (pixels - 1) * ps;
1422         else if (pixels < 0)
1423                 return 1 - (-pixels + 1) * ps;
1424         else
1425                 BUG();
1426 }
1427
1428 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1429                 u16 screen_width,
1430                 u16 width, u16 height,
1431                 enum omap_color_mode color_mode, bool fieldmode,
1432                 unsigned int field_offset,
1433                 unsigned *offset0, unsigned *offset1,
1434                 s32 *row_inc, s32 *pix_inc)
1435 {
1436         u8 ps;
1437
1438         /* FIXME CLUT formats */
1439         switch (color_mode) {
1440         case OMAP_DSS_COLOR_CLUT1:
1441         case OMAP_DSS_COLOR_CLUT2:
1442         case OMAP_DSS_COLOR_CLUT4:
1443         case OMAP_DSS_COLOR_CLUT8:
1444                 BUG();
1445                 return;
1446         case OMAP_DSS_COLOR_YUV2:
1447         case OMAP_DSS_COLOR_UYVY:
1448                 ps = 4;
1449                 break;
1450         default:
1451                 ps = color_mode_to_bpp(color_mode) / 8;
1452                 break;
1453         }
1454
1455         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1456                         width, height);
1457
1458         /*
1459          * field 0 = even field = bottom field
1460          * field 1 = odd field = top field
1461          */
1462         switch (rotation + mirror * 4) {
1463         case OMAP_DSS_ROT_0:
1464         case OMAP_DSS_ROT_180:
1465                 /*
1466                  * If the pixel format is YUV or UYVY divide the width
1467                  * of the image by 2 for 0 and 180 degree rotation.
1468                  */
1469                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1470                         color_mode == OMAP_DSS_COLOR_UYVY)
1471                         width = width >> 1;
1472         case OMAP_DSS_ROT_90:
1473         case OMAP_DSS_ROT_270:
1474                 *offset1 = 0;
1475                 if (field_offset)
1476                         *offset0 = field_offset * screen_width * ps;
1477                 else
1478                         *offset0 = 0;
1479
1480                 *row_inc = pixinc(1 + (screen_width - width) +
1481                                 (fieldmode ? screen_width : 0),
1482                                 ps);
1483                 *pix_inc = pixinc(1, ps);
1484                 break;
1485
1486         case OMAP_DSS_ROT_0 + 4:
1487         case OMAP_DSS_ROT_180 + 4:
1488                 /* If the pixel format is YUV or UYVY divide the width
1489                  * of the image by 2  for 0 degree and 180 degree
1490                  */
1491                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1492                         color_mode == OMAP_DSS_COLOR_UYVY)
1493                         width = width >> 1;
1494         case OMAP_DSS_ROT_90 + 4:
1495         case OMAP_DSS_ROT_270 + 4:
1496                 *offset1 = 0;
1497                 if (field_offset)
1498                         *offset0 = field_offset * screen_width * ps;
1499                 else
1500                         *offset0 = 0;
1501                 *row_inc = pixinc(1 - (screen_width + width) -
1502                                 (fieldmode ? screen_width : 0),
1503                                 ps);
1504                 *pix_inc = pixinc(1, ps);
1505                 break;
1506
1507         default:
1508                 BUG();
1509         }
1510 }
1511
1512 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1513                 u16 screen_width,
1514                 u16 width, u16 height,
1515                 enum omap_color_mode color_mode, bool fieldmode,
1516                 unsigned int field_offset,
1517                 unsigned *offset0, unsigned *offset1,
1518                 s32 *row_inc, s32 *pix_inc)
1519 {
1520         u8 ps;
1521         u16 fbw, fbh;
1522
1523         /* FIXME CLUT formats */
1524         switch (color_mode) {
1525         case OMAP_DSS_COLOR_CLUT1:
1526         case OMAP_DSS_COLOR_CLUT2:
1527         case OMAP_DSS_COLOR_CLUT4:
1528         case OMAP_DSS_COLOR_CLUT8:
1529                 BUG();
1530                 return;
1531         default:
1532                 ps = color_mode_to_bpp(color_mode) / 8;
1533                 break;
1534         }
1535
1536         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1537                         width, height);
1538
1539         /* width & height are overlay sizes, convert to fb sizes */
1540
1541         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1542                 fbw = width;
1543                 fbh = height;
1544         } else {
1545                 fbw = height;
1546                 fbh = width;
1547         }
1548
1549         /*
1550          * field 0 = even field = bottom field
1551          * field 1 = odd field = top field
1552          */
1553         switch (rotation + mirror * 4) {
1554         case OMAP_DSS_ROT_0:
1555                 *offset1 = 0;
1556                 if (field_offset)
1557                         *offset0 = *offset1 + field_offset * screen_width * ps;
1558                 else
1559                         *offset0 = *offset1;
1560                 *row_inc = pixinc(1 + (screen_width - fbw) +
1561                                 (fieldmode ? screen_width : 0),
1562                                 ps);
1563                 *pix_inc = pixinc(1, ps);
1564                 break;
1565         case OMAP_DSS_ROT_90:
1566                 *offset1 = screen_width * (fbh - 1) * ps;
1567                 if (field_offset)
1568                         *offset0 = *offset1 + field_offset * ps;
1569                 else
1570                         *offset0 = *offset1;
1571                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1572                                 (fieldmode ? 1 : 0), ps);
1573                 *pix_inc = pixinc(-screen_width, ps);
1574                 break;
1575         case OMAP_DSS_ROT_180:
1576                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1577                 if (field_offset)
1578                         *offset0 = *offset1 - field_offset * screen_width * ps;
1579                 else
1580                         *offset0 = *offset1;
1581                 *row_inc = pixinc(-1 -
1582                                 (screen_width - fbw) -
1583                                 (fieldmode ? screen_width : 0),
1584                                 ps);
1585                 *pix_inc = pixinc(-1, ps);
1586                 break;
1587         case OMAP_DSS_ROT_270:
1588                 *offset1 = (fbw - 1) * ps;
1589                 if (field_offset)
1590                         *offset0 = *offset1 - field_offset * ps;
1591                 else
1592                         *offset0 = *offset1;
1593                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1594                                 (fieldmode ? 1 : 0), ps);
1595                 *pix_inc = pixinc(screen_width, ps);
1596                 break;
1597
1598         /* mirroring */
1599         case OMAP_DSS_ROT_0 + 4:
1600                 *offset1 = (fbw - 1) * ps;
1601                 if (field_offset)
1602                         *offset0 = *offset1 + field_offset * screen_width * ps;
1603                 else
1604                         *offset0 = *offset1;
1605                 *row_inc = pixinc(screen_width * 2 - 1 +
1606                                 (fieldmode ? screen_width : 0),
1607                                 ps);
1608                 *pix_inc = pixinc(-1, ps);
1609                 break;
1610
1611         case OMAP_DSS_ROT_90 + 4:
1612                 *offset1 = 0;
1613                 if (field_offset)
1614                         *offset0 = *offset1 + field_offset * ps;
1615                 else
1616                         *offset0 = *offset1;
1617                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1618                                 (fieldmode ? 1 : 0),
1619                                 ps);
1620                 *pix_inc = pixinc(screen_width, ps);
1621                 break;
1622
1623         case OMAP_DSS_ROT_180 + 4:
1624                 *offset1 = screen_width * (fbh - 1) * ps;
1625                 if (field_offset)
1626                         *offset0 = *offset1 - field_offset * screen_width * ps;
1627                 else
1628                         *offset0 = *offset1;
1629                 *row_inc = pixinc(1 - screen_width * 2 -
1630                                 (fieldmode ? screen_width : 0),
1631                                 ps);
1632                 *pix_inc = pixinc(1, ps);
1633                 break;
1634
1635         case OMAP_DSS_ROT_270 + 4:
1636                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1637                 if (field_offset)
1638                         *offset0 = *offset1 - field_offset * ps;
1639                 else
1640                         *offset0 = *offset1;
1641                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1642                                 (fieldmode ? 1 : 0),
1643                                 ps);
1644                 *pix_inc = pixinc(-screen_width, ps);
1645                 break;
1646
1647         default:
1648                 BUG();
1649         }
1650 }
1651
1652 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1653                 u16 height, u16 out_width, u16 out_height,
1654                 enum omap_color_mode color_mode)
1655 {
1656         u32 fclk = 0;
1657         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1658
1659         if (height <= out_height && width <= out_width)
1660                 return (unsigned long) pclk;
1661
1662         if (height > out_height) {
1663                 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1664                 unsigned int ppl = dssdev->panel.timings.x_res;
1665
1666                 tmp = pclk * height * out_width;
1667                 do_div(tmp, 2 * out_height * ppl);
1668                 fclk = tmp;
1669
1670                 if (height > 2 * out_height) {
1671                         if (ppl == out_width)
1672                                 return 0;
1673
1674                         tmp = pclk * (height - 2 * out_height) * out_width;
1675                         do_div(tmp, 2 * out_height * (ppl - out_width));
1676                         fclk = max(fclk, (u32) tmp);
1677                 }
1678         }
1679
1680         if (width > out_width) {
1681                 tmp = pclk * width;
1682                 do_div(tmp, out_width);
1683                 fclk = max(fclk, (u32) tmp);
1684
1685                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1686                         fclk <<= 1;
1687         }
1688
1689         return fclk;
1690 }
1691
1692 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1693                 u16 height, u16 out_width, u16 out_height)
1694 {
1695         unsigned int hf, vf;
1696         unsigned long pclk = dispc_mgr_pclk_rate(channel);
1697
1698         /*
1699          * FIXME how to determine the 'A' factor
1700          * for the no downscaling case ?
1701          */
1702
1703         if (width > 3 * out_width)
1704                 hf = 4;
1705         else if (width > 2 * out_width)
1706                 hf = 3;
1707         else if (width > out_width)
1708                 hf = 2;
1709         else
1710                 hf = 1;
1711
1712         if (height > out_height)
1713                 vf = 2;
1714         else
1715                 vf = 1;
1716
1717         if (cpu_is_omap24xx()) {
1718                 if (vf > 1 && hf > 1)
1719                         return pclk * 4;
1720                 else
1721                         return pclk * 2;
1722         } else if (cpu_is_omap34xx()) {
1723                 return pclk * vf * hf;
1724         } else {
1725                 if (hf > 1)
1726                         return DIV_ROUND_UP(pclk, out_width) * width;
1727                 else
1728                         return pclk;
1729         }
1730 }
1731
1732 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1733                 enum omap_channel channel, u16 width, u16 height,
1734                 u16 out_width, u16 out_height,
1735                 enum omap_color_mode color_mode, bool *five_taps)
1736 {
1737         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1738         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1739         const int maxsinglelinewidth =
1740                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
1741         unsigned long fclk = 0;
1742
1743         if (width == out_width && height == out_height)
1744                 return 0;
1745
1746         if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1747                 return -EINVAL;
1748
1749         if (out_width < width / maxdownscale ||
1750                         out_width > width * 8)
1751                 return -EINVAL;
1752
1753         if (out_height < height / maxdownscale ||
1754                         out_height > height * 8)
1755                 return -EINVAL;
1756
1757         if (cpu_is_omap24xx()) {
1758                 if (width > maxsinglelinewidth)
1759                         DSSERR("Cannot scale max input width exceeded");
1760                 *five_taps = false;
1761                 fclk = calc_fclk(channel, width, height, out_width,
1762                                                                 out_height);
1763         } else if (cpu_is_omap34xx()) {
1764                 if (width > (maxsinglelinewidth * 2)) {
1765                         DSSERR("Cannot setup scaling");
1766                         DSSERR("width exceeds maximum width possible");
1767                         return -EINVAL;
1768                 }
1769                 fclk = calc_fclk_five_taps(channel, width, height, out_width,
1770                                                 out_height, color_mode);
1771                 if (width > maxsinglelinewidth) {
1772                         if (height > out_height && height < out_height * 2)
1773                                 *five_taps = false;
1774                         else {
1775                                 DSSERR("cannot setup scaling with five taps");
1776                                 return -EINVAL;
1777                         }
1778                 }
1779                 if (!*five_taps)
1780                         fclk = calc_fclk(channel, width, height, out_width,
1781                                         out_height);
1782         } else {
1783                 if (width > maxsinglelinewidth) {
1784                         DSSERR("Cannot scale width exceeds max line width");
1785                         return -EINVAL;
1786                 }
1787                 fclk = calc_fclk(channel, width, height, out_width,
1788                                 out_height);
1789         }
1790
1791         DSSDBG("required fclk rate = %lu Hz\n", fclk);
1792         DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1793
1794         if (!fclk || fclk > dispc_fclk_rate()) {
1795                 DSSERR("failed to set up scaling, "
1796                         "required fclk rate = %lu Hz, "
1797                         "current fclk rate = %lu Hz\n",
1798                         fclk, dispc_fclk_rate());
1799                 return -EINVAL;
1800         }
1801
1802         return 0;
1803 }
1804
1805 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1806                 bool ilace, bool replication)
1807 {
1808         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1809         bool five_taps = true;
1810         bool fieldmode = 0;
1811         int r, cconv = 0;
1812         unsigned offset0, offset1;
1813         s32 row_inc;
1814         s32 pix_inc;
1815         u16 frame_height = oi->height;
1816         unsigned int field_offset = 0;
1817         u16 outw, outh;
1818         enum omap_channel channel;
1819
1820         channel = dispc_ovl_get_channel_out(plane);
1821
1822         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1823                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1824                 plane, oi->paddr, oi->p_uv_addr,
1825                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1826                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1827                 oi->mirror, ilace, channel, replication);
1828
1829         if (oi->paddr == 0)
1830                 return -EINVAL;
1831
1832         outw = oi->out_width == 0 ? oi->width : oi->out_width;
1833         outh = oi->out_height == 0 ? oi->height : oi->out_height;
1834
1835         if (ilace && oi->height == outh)
1836                 fieldmode = 1;
1837
1838         if (ilace) {
1839                 if (fieldmode)
1840                         oi->height /= 2;
1841                 oi->pos_y /= 2;
1842                 outh /= 2;
1843
1844                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1845                                 "out_height %d\n",
1846                                 oi->height, oi->pos_y, outh);
1847         }
1848
1849         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1850                 return -EINVAL;
1851
1852         r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1853                         outw, outh, oi->color_mode,
1854                         &five_taps);
1855         if (r)
1856                 return r;
1857
1858         if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1859                         oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1860                         oi->color_mode == OMAP_DSS_COLOR_NV12)
1861                 cconv = 1;
1862
1863         if (ilace && !fieldmode) {
1864                 /*
1865                  * when downscaling the bottom field may have to start several
1866                  * source lines below the top field. Unfortunately ACCUI
1867                  * registers will only hold the fractional part of the offset
1868                  * so the integer part must be added to the base address of the
1869                  * bottom field.
1870                  */
1871                 if (!oi->height || oi->height == outh)
1872                         field_offset = 0;
1873                 else
1874                         field_offset = oi->height / outh / 2;
1875         }
1876
1877         /* Fields are independent but interleaved in memory. */
1878         if (fieldmode)
1879                 field_offset = 1;
1880
1881         if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1882                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1883                                 oi->screen_width, oi->width, frame_height,
1884                                 oi->color_mode, fieldmode, field_offset,
1885                                 &offset0, &offset1, &row_inc, &pix_inc);
1886         else
1887                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1888                                 oi->screen_width, oi->width, frame_height,
1889                                 oi->color_mode, fieldmode, field_offset,
1890                                 &offset0, &offset1, &row_inc, &pix_inc);
1891
1892         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1893                         offset0, offset1, row_inc, pix_inc);
1894
1895         dispc_ovl_set_color_mode(plane, oi->color_mode);
1896
1897         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1898         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1899
1900         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1901                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1902                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1903         }
1904
1905
1906         dispc_ovl_set_row_inc(plane, row_inc);
1907         dispc_ovl_set_pix_inc(plane, pix_inc);
1908
1909         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1910                         oi->height, outw, outh);
1911
1912         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1913
1914         dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1915
1916         if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1917                 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1918                                    outw, outh,
1919                                    ilace, five_taps, fieldmode,
1920                                    oi->color_mode, oi->rotation);
1921                 dispc_ovl_set_vid_size(plane, outw, outh);
1922                 dispc_ovl_set_vid_color_conv(plane, cconv);
1923         }
1924
1925         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1926                         oi->color_mode);
1927
1928         dispc_ovl_set_zorder(plane, oi->zorder);
1929         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1930         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1931
1932         dispc_ovl_enable_replication(plane, replication);
1933
1934         return 0;
1935 }
1936
1937 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1938 {
1939         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1940
1941         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1942
1943         return 0;
1944 }
1945
1946 static void dispc_disable_isr(void *data, u32 mask)
1947 {
1948         struct completion *compl = data;
1949         complete(compl);
1950 }
1951
1952 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1953 {
1954         if (channel == OMAP_DSS_CHANNEL_LCD2) {
1955                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1956                 /* flush posted write */
1957                 dispc_read_reg(DISPC_CONTROL2);
1958         } else {
1959                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1960                 dispc_read_reg(DISPC_CONTROL);
1961         }
1962 }
1963
1964 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1965 {
1966         struct completion frame_done_completion;
1967         bool is_on;
1968         int r;
1969         u32 irq;
1970
1971         /* When we disable LCD output, we need to wait until frame is done.
1972          * Otherwise the DSS is still working, and turning off the clocks
1973          * prevents DSS from going to OFF mode */
1974         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1975                         REG_GET(DISPC_CONTROL2, 0, 0) :
1976                         REG_GET(DISPC_CONTROL, 0, 0);
1977
1978         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1979                         DISPC_IRQ_FRAMEDONE;
1980
1981         if (!enable && is_on) {
1982                 init_completion(&frame_done_completion);
1983
1984                 r = omap_dispc_register_isr(dispc_disable_isr,
1985                                 &frame_done_completion, irq);
1986
1987                 if (r)
1988                         DSSERR("failed to register FRAMEDONE isr\n");
1989         }
1990
1991         _enable_lcd_out(channel, enable);
1992
1993         if (!enable && is_on) {
1994                 if (!wait_for_completion_timeout(&frame_done_completion,
1995                                         msecs_to_jiffies(100)))
1996                         DSSERR("timeout waiting for FRAME DONE\n");
1997
1998                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1999                                 &frame_done_completion, irq);
2000
2001                 if (r)
2002                         DSSERR("failed to unregister FRAMEDONE isr\n");
2003         }
2004 }
2005
2006 static void _enable_digit_out(bool enable)
2007 {
2008         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2009         /* flush posted write */
2010         dispc_read_reg(DISPC_CONTROL);
2011 }
2012
2013 static void dispc_mgr_enable_digit_out(bool enable)
2014 {
2015         struct completion frame_done_completion;
2016         enum dss_hdmi_venc_clk_source_select src;
2017         int r, i;
2018         u32 irq_mask;
2019         int num_irqs;
2020
2021         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2022                 return;
2023
2024         src = dss_get_hdmi_venc_clk_source();
2025
2026         if (enable) {
2027                 unsigned long flags;
2028                 /* When we enable digit output, we'll get an extra digit
2029                  * sync lost interrupt, that we need to ignore */
2030                 spin_lock_irqsave(&dispc.irq_lock, flags);
2031                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2032                 _omap_dispc_set_irqs();
2033                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2034         }
2035
2036         /* When we disable digit output, we need to wait until fields are done.
2037          * Otherwise the DSS is still working, and turning off the clocks
2038          * prevents DSS from going to OFF mode. And when enabling, we need to
2039          * wait for the extra sync losts */
2040         init_completion(&frame_done_completion);
2041
2042         if (src == DSS_HDMI_M_PCLK && enable == false) {
2043                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2044                 num_irqs = 1;
2045         } else {
2046                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2047                 /* XXX I understand from TRM that we should only wait for the
2048                  * current field to complete. But it seems we have to wait for
2049                  * both fields */
2050                 num_irqs = 2;
2051         }
2052
2053         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2054                         irq_mask);
2055         if (r)
2056                 DSSERR("failed to register %x isr\n", irq_mask);
2057
2058         _enable_digit_out(enable);
2059
2060         for (i = 0; i < num_irqs; ++i) {
2061                 if (!wait_for_completion_timeout(&frame_done_completion,
2062                                         msecs_to_jiffies(100)))
2063                         DSSERR("timeout waiting for digit out to %s\n",
2064                                         enable ? "start" : "stop");
2065         }
2066
2067         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2068                         irq_mask);
2069         if (r)
2070                 DSSERR("failed to unregister %x isr\n", irq_mask);
2071
2072         if (enable) {
2073                 unsigned long flags;
2074                 spin_lock_irqsave(&dispc.irq_lock, flags);
2075                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2076                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2077                 _omap_dispc_set_irqs();
2078                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2079         }
2080 }
2081
2082 bool dispc_mgr_is_enabled(enum omap_channel channel)
2083 {
2084         if (channel == OMAP_DSS_CHANNEL_LCD)
2085                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2086         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2087                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2088         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2089                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2090         else
2091                 BUG();
2092 }
2093
2094 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2095 {
2096         if (dispc_mgr_is_lcd(channel))
2097                 dispc_mgr_enable_lcd_out(channel, enable);
2098         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2099                 dispc_mgr_enable_digit_out(enable);
2100         else
2101                 BUG();
2102 }
2103
2104 void dispc_lcd_enable_signal_polarity(bool act_high)
2105 {
2106         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2107                 return;
2108
2109         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2110 }
2111
2112 void dispc_lcd_enable_signal(bool enable)
2113 {
2114         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2115                 return;
2116
2117         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2118 }
2119
2120 void dispc_pck_free_enable(bool enable)
2121 {
2122         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2123                 return;
2124
2125         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2126 }
2127
2128 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2129 {
2130         if (channel == OMAP_DSS_CHANNEL_LCD2)
2131                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2132         else
2133                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2134 }
2135
2136
2137 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2138                 enum omap_lcd_display_type type)
2139 {
2140         int mode;
2141
2142         switch (type) {
2143         case OMAP_DSS_LCD_DISPLAY_STN:
2144                 mode = 0;
2145                 break;
2146
2147         case OMAP_DSS_LCD_DISPLAY_TFT:
2148                 mode = 1;
2149                 break;
2150
2151         default:
2152                 BUG();
2153                 return;
2154         }
2155
2156         if (channel == OMAP_DSS_CHANNEL_LCD2)
2157                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2158         else
2159                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2160 }
2161
2162 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2163 {
2164         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2165 }
2166
2167
2168 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2169 {
2170         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2171 }
2172
2173 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2174                 enum omap_dss_trans_key_type type,
2175                 u32 trans_key)
2176 {
2177         if (ch == OMAP_DSS_CHANNEL_LCD)
2178                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2179         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2180                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2181         else /* OMAP_DSS_CHANNEL_LCD2 */
2182                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2183
2184         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2185 }
2186
2187 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2188 {
2189         if (ch == OMAP_DSS_CHANNEL_LCD)
2190                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2191         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2192                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2193         else /* OMAP_DSS_CHANNEL_LCD2 */
2194                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2195 }
2196
2197 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2198                 bool enable)
2199 {
2200         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2201                 return;
2202
2203         if (ch == OMAP_DSS_CHANNEL_LCD)
2204                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2205         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2206                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2207 }
2208
2209 void dispc_mgr_setup(enum omap_channel channel,
2210                 struct omap_overlay_manager_info *info)
2211 {
2212         dispc_mgr_set_default_color(channel, info->default_color);
2213         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2214         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2215         dispc_mgr_enable_alpha_fixed_zorder(channel,
2216                         info->partial_alpha_enabled);
2217         if (dss_has_feature(FEAT_CPR)) {
2218                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2219                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2220         }
2221 }
2222
2223 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2224 {
2225         int code;
2226
2227         switch (data_lines) {
2228         case 12:
2229                 code = 0;
2230                 break;
2231         case 16:
2232                 code = 1;
2233                 break;
2234         case 18:
2235                 code = 2;
2236                 break;
2237         case 24:
2238                 code = 3;
2239                 break;
2240         default:
2241                 BUG();
2242                 return;
2243         }
2244
2245         if (channel == OMAP_DSS_CHANNEL_LCD2)
2246                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2247         else
2248                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2249 }
2250
2251 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2252 {
2253         u32 l;
2254         int gpout0, gpout1;
2255
2256         switch (mode) {
2257         case DSS_IO_PAD_MODE_RESET:
2258                 gpout0 = 0;
2259                 gpout1 = 0;
2260                 break;
2261         case DSS_IO_PAD_MODE_RFBI:
2262                 gpout0 = 1;
2263                 gpout1 = 0;
2264                 break;
2265         case DSS_IO_PAD_MODE_BYPASS:
2266                 gpout0 = 1;
2267                 gpout1 = 1;
2268                 break;
2269         default:
2270                 BUG();
2271                 return;
2272         }
2273
2274         l = dispc_read_reg(DISPC_CONTROL);
2275         l = FLD_MOD(l, gpout0, 15, 15);
2276         l = FLD_MOD(l, gpout1, 16, 16);
2277         dispc_write_reg(DISPC_CONTROL, l);
2278 }
2279
2280 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2281 {
2282         if (channel == OMAP_DSS_CHANNEL_LCD2)
2283                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2284         else
2285                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2286 }
2287
2288 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2289                 int vsw, int vfp, int vbp)
2290 {
2291         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2292                 if (hsw < 1 || hsw > 64 ||
2293                                 hfp < 1 || hfp > 256 ||
2294                                 hbp < 1 || hbp > 256 ||
2295                                 vsw < 1 || vsw > 64 ||
2296                                 vfp < 0 || vfp > 255 ||
2297                                 vbp < 0 || vbp > 255)
2298                         return false;
2299         } else {
2300                 if (hsw < 1 || hsw > 256 ||
2301                                 hfp < 1 || hfp > 4096 ||
2302                                 hbp < 1 || hbp > 4096 ||
2303                                 vsw < 1 || vsw > 256 ||
2304                                 vfp < 0 || vfp > 4095 ||
2305                                 vbp < 0 || vbp > 4095)
2306                         return false;
2307         }
2308
2309         return true;
2310 }
2311
2312 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2313 {
2314         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2315                         timings->hbp, timings->vsw,
2316                         timings->vfp, timings->vbp);
2317 }
2318
2319 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2320                 int hfp, int hbp, int vsw, int vfp, int vbp)
2321 {
2322         u32 timing_h, timing_v;
2323
2324         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2325                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2326                         FLD_VAL(hbp-1, 27, 20);
2327
2328                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2329                         FLD_VAL(vbp, 27, 20);
2330         } else {
2331                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2332                         FLD_VAL(hbp-1, 31, 20);
2333
2334                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2335                         FLD_VAL(vbp, 31, 20);
2336         }
2337
2338         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2339         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2340 }
2341
2342 /* change name to mode? */
2343 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2344                 struct omap_video_timings *timings)
2345 {
2346         unsigned xtot, ytot;
2347         unsigned long ht, vt;
2348
2349         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2350                                 timings->hbp, timings->vsw,
2351                                 timings->vfp, timings->vbp))
2352                 BUG();
2353
2354         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2355                         timings->hbp, timings->vsw, timings->vfp,
2356                         timings->vbp);
2357
2358         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2359
2360         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2361         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2362
2363         ht = (timings->pixel_clock * 1000) / xtot;
2364         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2365
2366         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2367                         timings->y_res);
2368         DSSDBG("pck %u\n", timings->pixel_clock);
2369         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2370                         timings->hsw, timings->hfp, timings->hbp,
2371                         timings->vsw, timings->vfp, timings->vbp);
2372
2373         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2374 }
2375
2376 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2377                 u16 pck_div)
2378 {
2379         BUG_ON(lck_div < 1);
2380         BUG_ON(pck_div < 1);
2381
2382         dispc_write_reg(DISPC_DIVISORo(channel),
2383                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2384 }
2385
2386 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2387                 int *pck_div)
2388 {
2389         u32 l;
2390         l = dispc_read_reg(DISPC_DIVISORo(channel));
2391         *lck_div = FLD_GET(l, 23, 16);
2392         *pck_div = FLD_GET(l, 7, 0);
2393 }
2394
2395 unsigned long dispc_fclk_rate(void)
2396 {
2397         struct platform_device *dsidev;
2398         unsigned long r = 0;
2399
2400         switch (dss_get_dispc_clk_source()) {
2401         case OMAP_DSS_CLK_SRC_FCK:
2402                 r = clk_get_rate(dispc.dss_clk);
2403                 break;
2404         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2405                 dsidev = dsi_get_dsidev_from_id(0);
2406                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2407                 break;
2408         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2409                 dsidev = dsi_get_dsidev_from_id(1);
2410                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2411                 break;
2412         default:
2413                 BUG();
2414         }
2415
2416         return r;
2417 }
2418
2419 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2420 {
2421         struct platform_device *dsidev;
2422         int lcd;
2423         unsigned long r;
2424         u32 l;
2425
2426         l = dispc_read_reg(DISPC_DIVISORo(channel));
2427
2428         lcd = FLD_GET(l, 23, 16);
2429
2430         switch (dss_get_lcd_clk_source(channel)) {
2431         case OMAP_DSS_CLK_SRC_FCK:
2432                 r = clk_get_rate(dispc.dss_clk);
2433                 break;
2434         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2435                 dsidev = dsi_get_dsidev_from_id(0);
2436                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2437                 break;
2438         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2439                 dsidev = dsi_get_dsidev_from_id(1);
2440                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2441                 break;
2442         default:
2443                 BUG();
2444         }
2445
2446         return r / lcd;
2447 }
2448
2449 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2450 {
2451         unsigned long r;
2452
2453         if (dispc_mgr_is_lcd(channel)) {
2454                 int pcd;
2455                 u32 l;
2456
2457                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2458
2459                 pcd = FLD_GET(l, 7, 0);
2460
2461                 r = dispc_mgr_lclk_rate(channel);
2462
2463                 return r / pcd;
2464         } else {
2465                 struct omap_dss_device *dssdev =
2466                         dispc_mgr_get_device(channel);
2467
2468                 switch (dssdev->type) {
2469                 case OMAP_DISPLAY_TYPE_VENC:
2470                         return venc_get_pixel_clock();
2471                 case OMAP_DISPLAY_TYPE_HDMI:
2472                         return hdmi_get_pixel_clock();
2473                 default:
2474                         BUG();
2475                 }
2476         }
2477 }
2478
2479 void dispc_dump_clocks(struct seq_file *s)
2480 {
2481         int lcd, pcd;
2482         u32 l;
2483         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2484         enum omap_dss_clk_source lcd_clk_src;
2485
2486         if (dispc_runtime_get())
2487                 return;
2488
2489         seq_printf(s, "- DISPC -\n");
2490
2491         seq_printf(s, "dispc fclk source = %s (%s)\n",
2492                         dss_get_generic_clk_source_name(dispc_clk_src),
2493                         dss_feat_get_clk_source_name(dispc_clk_src));
2494
2495         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2496
2497         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2498                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2499                 l = dispc_read_reg(DISPC_DIVISOR);
2500                 lcd = FLD_GET(l, 23, 16);
2501
2502                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2503                                 (dispc_fclk_rate()/lcd), lcd);
2504         }
2505         seq_printf(s, "- LCD1 -\n");
2506
2507         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2508
2509         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2510                 dss_get_generic_clk_source_name(lcd_clk_src),
2511                 dss_feat_get_clk_source_name(lcd_clk_src));
2512
2513         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2514
2515         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2516                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2517         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2518                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2519         if (dss_has_feature(FEAT_MGR_LCD2)) {
2520                 seq_printf(s, "- LCD2 -\n");
2521
2522                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2523
2524                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2525                         dss_get_generic_clk_source_name(lcd_clk_src),
2526                         dss_feat_get_clk_source_name(lcd_clk_src));
2527
2528                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2529
2530                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2531                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2532                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2533                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2534         }
2535
2536         dispc_runtime_put();
2537 }
2538
2539 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2540 void dispc_dump_irqs(struct seq_file *s)
2541 {
2542         unsigned long flags;
2543         struct dispc_irq_stats stats;
2544
2545         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2546
2547         stats = dispc.irq_stats;
2548         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2549         dispc.irq_stats.last_reset = jiffies;
2550
2551         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2552
2553         seq_printf(s, "period %u ms\n",
2554                         jiffies_to_msecs(jiffies - stats.last_reset));
2555
2556         seq_printf(s, "irqs %d\n", stats.irq_count);
2557 #define PIS(x) \
2558         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2559
2560         PIS(FRAMEDONE);
2561         PIS(VSYNC);
2562         PIS(EVSYNC_EVEN);
2563         PIS(EVSYNC_ODD);
2564         PIS(ACBIAS_COUNT_STAT);
2565         PIS(PROG_LINE_NUM);
2566         PIS(GFX_FIFO_UNDERFLOW);
2567         PIS(GFX_END_WIN);
2568         PIS(PAL_GAMMA_MASK);
2569         PIS(OCP_ERR);
2570         PIS(VID1_FIFO_UNDERFLOW);
2571         PIS(VID1_END_WIN);
2572         PIS(VID2_FIFO_UNDERFLOW);
2573         PIS(VID2_END_WIN);
2574         if (dss_feat_get_num_ovls() > 3) {
2575                 PIS(VID3_FIFO_UNDERFLOW);
2576                 PIS(VID3_END_WIN);
2577         }
2578         PIS(SYNC_LOST);
2579         PIS(SYNC_LOST_DIGIT);
2580         PIS(WAKEUP);
2581         if (dss_has_feature(FEAT_MGR_LCD2)) {
2582                 PIS(FRAMEDONE2);
2583                 PIS(VSYNC2);
2584                 PIS(ACBIAS_COUNT_STAT2);
2585                 PIS(SYNC_LOST2);
2586         }
2587 #undef PIS
2588 }
2589 #endif
2590
2591 void dispc_dump_regs(struct seq_file *s)
2592 {
2593         int i, j;
2594         const char *mgr_names[] = {
2595                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2596                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2597                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2598         };
2599         const char *ovl_names[] = {
2600                 [OMAP_DSS_GFX]          = "GFX",
2601                 [OMAP_DSS_VIDEO1]       = "VID1",
2602                 [OMAP_DSS_VIDEO2]       = "VID2",
2603                 [OMAP_DSS_VIDEO3]       = "VID3",
2604         };
2605         const char **p_names;
2606
2607 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2608
2609         if (dispc_runtime_get())
2610                 return;
2611
2612         /* DISPC common registers */
2613         DUMPREG(DISPC_REVISION);
2614         DUMPREG(DISPC_SYSCONFIG);
2615         DUMPREG(DISPC_SYSSTATUS);
2616         DUMPREG(DISPC_IRQSTATUS);
2617         DUMPREG(DISPC_IRQENABLE);
2618         DUMPREG(DISPC_CONTROL);
2619         DUMPREG(DISPC_CONFIG);
2620         DUMPREG(DISPC_CAPABLE);
2621         DUMPREG(DISPC_LINE_STATUS);
2622         DUMPREG(DISPC_LINE_NUMBER);
2623         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2624                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2625                 DUMPREG(DISPC_GLOBAL_ALPHA);
2626         if (dss_has_feature(FEAT_MGR_LCD2)) {
2627                 DUMPREG(DISPC_CONTROL2);
2628                 DUMPREG(DISPC_CONFIG2);
2629         }
2630
2631 #undef DUMPREG
2632
2633 #define DISPC_REG(i, name) name(i)
2634 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2635         48 - strlen(#r) - strlen(p_names[i]), " ", \
2636         dispc_read_reg(DISPC_REG(i, r)))
2637
2638         p_names = mgr_names;
2639
2640         /* DISPC channel specific registers */
2641         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2642                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2643                 DUMPREG(i, DISPC_TRANS_COLOR);
2644                 DUMPREG(i, DISPC_SIZE_MGR);
2645
2646                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2647                         continue;
2648
2649                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2650                 DUMPREG(i, DISPC_TRANS_COLOR);
2651                 DUMPREG(i, DISPC_TIMING_H);
2652                 DUMPREG(i, DISPC_TIMING_V);
2653                 DUMPREG(i, DISPC_POL_FREQ);
2654                 DUMPREG(i, DISPC_DIVISORo);
2655                 DUMPREG(i, DISPC_SIZE_MGR);
2656
2657                 DUMPREG(i, DISPC_DATA_CYCLE1);
2658                 DUMPREG(i, DISPC_DATA_CYCLE2);
2659                 DUMPREG(i, DISPC_DATA_CYCLE3);
2660
2661                 if (dss_has_feature(FEAT_CPR)) {
2662                         DUMPREG(i, DISPC_CPR_COEF_R);
2663                         DUMPREG(i, DISPC_CPR_COEF_G);
2664                         DUMPREG(i, DISPC_CPR_COEF_B);
2665                 }
2666         }
2667
2668         p_names = ovl_names;
2669
2670         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2671                 DUMPREG(i, DISPC_OVL_BA0);
2672                 DUMPREG(i, DISPC_OVL_BA1);
2673                 DUMPREG(i, DISPC_OVL_POSITION);
2674                 DUMPREG(i, DISPC_OVL_SIZE);
2675                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2676                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2677                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2678                 DUMPREG(i, DISPC_OVL_ROW_INC);
2679                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2680                 if (dss_has_feature(FEAT_PRELOAD))
2681                         DUMPREG(i, DISPC_OVL_PRELOAD);
2682
2683                 if (i == OMAP_DSS_GFX) {
2684                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2685                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2686                         continue;
2687                 }
2688
2689                 DUMPREG(i, DISPC_OVL_FIR);
2690                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2691                 DUMPREG(i, DISPC_OVL_ACCU0);
2692                 DUMPREG(i, DISPC_OVL_ACCU1);
2693                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2694                         DUMPREG(i, DISPC_OVL_BA0_UV);
2695                         DUMPREG(i, DISPC_OVL_BA1_UV);
2696                         DUMPREG(i, DISPC_OVL_FIR2);
2697                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2698                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2699                 }
2700                 if (dss_has_feature(FEAT_ATTR2))
2701                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2702                 if (dss_has_feature(FEAT_PRELOAD))
2703                         DUMPREG(i, DISPC_OVL_PRELOAD);
2704         }
2705
2706 #undef DISPC_REG
2707 #undef DUMPREG
2708
2709 #define DISPC_REG(plane, name, i) name(plane, i)
2710 #define DUMPREG(plane, name, i) \
2711         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2712         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2713         dispc_read_reg(DISPC_REG(plane, name, i)))
2714
2715         /* Video pipeline coefficient registers */
2716
2717         /* start from OMAP_DSS_VIDEO1 */
2718         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2719                 for (j = 0; j < 8; j++)
2720                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2721
2722                 for (j = 0; j < 8; j++)
2723                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2724
2725                 for (j = 0; j < 5; j++)
2726                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2727
2728                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2729                         for (j = 0; j < 8; j++)
2730                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2731                 }
2732
2733                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2734                         for (j = 0; j < 8; j++)
2735                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2736
2737                         for (j = 0; j < 8; j++)
2738                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2739
2740                         for (j = 0; j < 8; j++)
2741                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2742                 }
2743         }
2744
2745         dispc_runtime_put();
2746
2747 #undef DISPC_REG
2748 #undef DUMPREG
2749 }
2750
2751 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2752                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2753                 u8 acb)
2754 {
2755         u32 l = 0;
2756
2757         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2758                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2759
2760         l |= FLD_VAL(onoff, 17, 17);
2761         l |= FLD_VAL(rf, 16, 16);
2762         l |= FLD_VAL(ieo, 15, 15);
2763         l |= FLD_VAL(ipc, 14, 14);
2764         l |= FLD_VAL(ihs, 13, 13);
2765         l |= FLD_VAL(ivs, 12, 12);
2766         l |= FLD_VAL(acbi, 11, 8);
2767         l |= FLD_VAL(acb, 7, 0);
2768
2769         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2770 }
2771
2772 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2773                 enum omap_panel_config config, u8 acbi, u8 acb)
2774 {
2775         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2776                         (config & OMAP_DSS_LCD_RF) != 0,
2777                         (config & OMAP_DSS_LCD_IEO) != 0,
2778                         (config & OMAP_DSS_LCD_IPC) != 0,
2779                         (config & OMAP_DSS_LCD_IHS) != 0,
2780                         (config & OMAP_DSS_LCD_IVS) != 0,
2781                         acbi, acb);
2782 }
2783
2784 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2785 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2786                 struct dispc_clock_info *cinfo)
2787 {
2788         u16 pcd_min, pcd_max;
2789         unsigned long best_pck;
2790         u16 best_ld, cur_ld;
2791         u16 best_pd, cur_pd;
2792
2793         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2794         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2795
2796         if (!is_tft)
2797                 pcd_min = 3;
2798
2799         best_pck = 0;
2800         best_ld = 0;
2801         best_pd = 0;
2802
2803         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2804                 unsigned long lck = fck / cur_ld;
2805
2806                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2807                         unsigned long pck = lck / cur_pd;
2808                         long old_delta = abs(best_pck - req_pck);
2809                         long new_delta = abs(pck - req_pck);
2810
2811                         if (best_pck == 0 || new_delta < old_delta) {
2812                                 best_pck = pck;
2813                                 best_ld = cur_ld;
2814                                 best_pd = cur_pd;
2815
2816                                 if (pck == req_pck)
2817                                         goto found;
2818                         }
2819
2820                         if (pck < req_pck)
2821                                 break;
2822                 }
2823
2824                 if (lck / pcd_min < req_pck)
2825                         break;
2826         }
2827
2828 found:
2829         cinfo->lck_div = best_ld;
2830         cinfo->pck_div = best_pd;
2831         cinfo->lck = fck / cinfo->lck_div;
2832         cinfo->pck = cinfo->lck / cinfo->pck_div;
2833 }
2834
2835 /* calculate clock rates using dividers in cinfo */
2836 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2837                 struct dispc_clock_info *cinfo)
2838 {
2839         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2840                 return -EINVAL;
2841         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2842                 return -EINVAL;
2843
2844         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2845         cinfo->pck = cinfo->lck / cinfo->pck_div;
2846
2847         return 0;
2848 }
2849
2850 int dispc_mgr_set_clock_div(enum omap_channel channel,
2851                 struct dispc_clock_info *cinfo)
2852 {
2853         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2854         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2855
2856         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2857
2858         return 0;
2859 }
2860
2861 int dispc_mgr_get_clock_div(enum omap_channel channel,
2862                 struct dispc_clock_info *cinfo)
2863 {
2864         unsigned long fck;
2865
2866         fck = dispc_fclk_rate();
2867
2868         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2869         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2870
2871         cinfo->lck = fck / cinfo->lck_div;
2872         cinfo->pck = cinfo->lck / cinfo->pck_div;
2873
2874         return 0;
2875 }
2876
2877 /* dispc.irq_lock has to be locked by the caller */
2878 static void _omap_dispc_set_irqs(void)
2879 {
2880         u32 mask;
2881         u32 old_mask;
2882         int i;
2883         struct omap_dispc_isr_data *isr_data;
2884
2885         mask = dispc.irq_error_mask;
2886
2887         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2888                 isr_data = &dispc.registered_isr[i];
2889
2890                 if (isr_data->isr == NULL)
2891                         continue;
2892
2893                 mask |= isr_data->mask;
2894         }
2895
2896         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2897         /* clear the irqstatus for newly enabled irqs */
2898         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2899
2900         dispc_write_reg(DISPC_IRQENABLE, mask);
2901 }
2902
2903 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2904 {
2905         int i;
2906         int ret;
2907         unsigned long flags;
2908         struct omap_dispc_isr_data *isr_data;
2909
2910         if (isr == NULL)
2911                 return -EINVAL;
2912
2913         spin_lock_irqsave(&dispc.irq_lock, flags);
2914
2915         /* check for duplicate entry */
2916         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2917                 isr_data = &dispc.registered_isr[i];
2918                 if (isr_data->isr == isr && isr_data->arg == arg &&
2919                                 isr_data->mask == mask) {
2920                         ret = -EINVAL;
2921                         goto err;
2922                 }
2923         }
2924
2925         isr_data = NULL;
2926         ret = -EBUSY;
2927
2928         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2929                 isr_data = &dispc.registered_isr[i];
2930
2931                 if (isr_data->isr != NULL)
2932                         continue;
2933
2934                 isr_data->isr = isr;
2935                 isr_data->arg = arg;
2936                 isr_data->mask = mask;
2937                 ret = 0;
2938
2939                 break;
2940         }
2941
2942         if (ret)
2943                 goto err;
2944
2945         _omap_dispc_set_irqs();
2946
2947         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2948
2949         return 0;
2950 err:
2951         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2952
2953         return ret;
2954 }
2955 EXPORT_SYMBOL(omap_dispc_register_isr);
2956
2957 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2958 {
2959         int i;
2960         unsigned long flags;
2961         int ret = -EINVAL;
2962         struct omap_dispc_isr_data *isr_data;
2963
2964         spin_lock_irqsave(&dispc.irq_lock, flags);
2965
2966         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2967                 isr_data = &dispc.registered_isr[i];
2968                 if (isr_data->isr != isr || isr_data->arg != arg ||
2969                                 isr_data->mask != mask)
2970                         continue;
2971
2972                 /* found the correct isr */
2973
2974                 isr_data->isr = NULL;
2975                 isr_data->arg = NULL;
2976                 isr_data->mask = 0;
2977
2978                 ret = 0;
2979                 break;
2980         }
2981
2982         if (ret == 0)
2983                 _omap_dispc_set_irqs();
2984
2985         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2986
2987         return ret;
2988 }
2989 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2990
2991 #ifdef DEBUG
2992 static void print_irq_status(u32 status)
2993 {
2994         if ((status & dispc.irq_error_mask) == 0)
2995                 return;
2996
2997         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2998
2999 #define PIS(x) \
3000         if (status & DISPC_IRQ_##x) \
3001                 printk(#x " ");
3002         PIS(GFX_FIFO_UNDERFLOW);
3003         PIS(OCP_ERR);
3004         PIS(VID1_FIFO_UNDERFLOW);
3005         PIS(VID2_FIFO_UNDERFLOW);
3006         if (dss_feat_get_num_ovls() > 3)
3007                 PIS(VID3_FIFO_UNDERFLOW);
3008         PIS(SYNC_LOST);
3009         PIS(SYNC_LOST_DIGIT);
3010         if (dss_has_feature(FEAT_MGR_LCD2))
3011                 PIS(SYNC_LOST2);
3012 #undef PIS
3013
3014         printk("\n");
3015 }
3016 #endif
3017
3018 /* Called from dss.c. Note that we don't touch clocks here,
3019  * but we presume they are on because we got an IRQ. However,
3020  * an irq handler may turn the clocks off, so we may not have
3021  * clock later in the function. */
3022 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3023 {
3024         int i;
3025         u32 irqstatus, irqenable;
3026         u32 handledirqs = 0;
3027         u32 unhandled_errors;
3028         struct omap_dispc_isr_data *isr_data;
3029         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3030
3031         spin_lock(&dispc.irq_lock);
3032
3033         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3034         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3035
3036         /* IRQ is not for us */
3037         if (!(irqstatus & irqenable)) {
3038                 spin_unlock(&dispc.irq_lock);
3039                 return IRQ_NONE;
3040         }
3041
3042 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3043         spin_lock(&dispc.irq_stats_lock);
3044         dispc.irq_stats.irq_count++;
3045         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3046         spin_unlock(&dispc.irq_stats_lock);
3047 #endif
3048
3049 #ifdef DEBUG
3050         if (dss_debug)
3051                 print_irq_status(irqstatus);
3052 #endif
3053         /* Ack the interrupt. Do it here before clocks are possibly turned
3054          * off */
3055         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3056         /* flush posted write */
3057         dispc_read_reg(DISPC_IRQSTATUS);
3058
3059         /* make a copy and unlock, so that isrs can unregister
3060          * themselves */
3061         memcpy(registered_isr, dispc.registered_isr,
3062                         sizeof(registered_isr));
3063
3064         spin_unlock(&dispc.irq_lock);
3065
3066         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3067                 isr_data = &registered_isr[i];
3068
3069                 if (!isr_data->isr)
3070                         continue;
3071
3072                 if (isr_data->mask & irqstatus) {
3073                         isr_data->isr(isr_data->arg, irqstatus);
3074                         handledirqs |= isr_data->mask;
3075                 }
3076         }
3077
3078         spin_lock(&dispc.irq_lock);
3079
3080         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3081
3082         if (unhandled_errors) {
3083                 dispc.error_irqs |= unhandled_errors;
3084
3085                 dispc.irq_error_mask &= ~unhandled_errors;
3086                 _omap_dispc_set_irqs();
3087
3088                 schedule_work(&dispc.error_work);
3089         }
3090
3091         spin_unlock(&dispc.irq_lock);
3092
3093         return IRQ_HANDLED;
3094 }
3095
3096 static void dispc_error_worker(struct work_struct *work)
3097 {
3098         int i;
3099         u32 errors;
3100         unsigned long flags;
3101         static const unsigned fifo_underflow_bits[] = {
3102                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3103                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3104                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3105                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3106         };
3107
3108         static const unsigned sync_lost_bits[] = {
3109                 DISPC_IRQ_SYNC_LOST,
3110                 DISPC_IRQ_SYNC_LOST_DIGIT,
3111                 DISPC_IRQ_SYNC_LOST2,
3112         };
3113
3114         spin_lock_irqsave(&dispc.irq_lock, flags);
3115         errors = dispc.error_irqs;
3116         dispc.error_irqs = 0;
3117         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3118
3119         dispc_runtime_get();
3120
3121         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3122                 struct omap_overlay *ovl;
3123                 unsigned bit;
3124
3125                 ovl = omap_dss_get_overlay(i);
3126                 bit = fifo_underflow_bits[i];
3127
3128                 if (bit & errors) {
3129                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3130                                         ovl->name);
3131                         dispc_ovl_enable(ovl->id, false);
3132                         dispc_mgr_go(ovl->manager->id);
3133                         mdelay(50);
3134                 }
3135         }
3136
3137         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3138                 struct omap_overlay_manager *mgr;
3139                 unsigned bit;
3140
3141                 mgr = omap_dss_get_overlay_manager(i);
3142                 bit = sync_lost_bits[i];
3143
3144                 if (bit & errors) {
3145                         struct omap_dss_device *dssdev = mgr->device;
3146                         bool enable;
3147
3148                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3149                                         "with video overlays disabled\n",
3150                                         mgr->name);
3151
3152                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3153                         dssdev->driver->disable(dssdev);
3154
3155                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3156                                 struct omap_overlay *ovl;
3157                                 ovl = omap_dss_get_overlay(i);
3158
3159                                 if (ovl->id != OMAP_DSS_GFX &&
3160                                                 ovl->manager == mgr)
3161                                         dispc_ovl_enable(ovl->id, false);
3162                         }
3163
3164                         dispc_mgr_go(mgr->id);
3165                         mdelay(50);
3166
3167                         if (enable)
3168                                 dssdev->driver->enable(dssdev);
3169                 }
3170         }
3171
3172         if (errors & DISPC_IRQ_OCP_ERR) {
3173                 DSSERR("OCP_ERR\n");
3174                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3175                         struct omap_overlay_manager *mgr;
3176                         mgr = omap_dss_get_overlay_manager(i);
3177                         if (mgr->device && mgr->device->driver)
3178                                 mgr->device->driver->disable(mgr->device);
3179                 }
3180         }
3181
3182         spin_lock_irqsave(&dispc.irq_lock, flags);
3183         dispc.irq_error_mask |= errors;
3184         _omap_dispc_set_irqs();
3185         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3186
3187         dispc_runtime_put();
3188 }
3189
3190 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3191 {
3192         void dispc_irq_wait_handler(void *data, u32 mask)
3193         {
3194                 complete((struct completion *)data);
3195         }
3196
3197         int r;
3198         DECLARE_COMPLETION_ONSTACK(completion);
3199
3200         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3201                         irqmask);
3202
3203         if (r)
3204                 return r;
3205
3206         timeout = wait_for_completion_timeout(&completion, timeout);
3207
3208         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3209
3210         if (timeout == 0)
3211                 return -ETIMEDOUT;
3212
3213         if (timeout == -ERESTARTSYS)
3214                 return -ERESTARTSYS;
3215
3216         return 0;
3217 }
3218
3219 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3220                 unsigned long timeout)
3221 {
3222         void dispc_irq_wait_handler(void *data, u32 mask)
3223         {
3224                 complete((struct completion *)data);
3225         }
3226
3227         int r;
3228         DECLARE_COMPLETION_ONSTACK(completion);
3229
3230         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3231                         irqmask);
3232
3233         if (r)
3234                 return r;
3235
3236         timeout = wait_for_completion_interruptible_timeout(&completion,
3237                         timeout);
3238
3239         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3240
3241         if (timeout == 0)
3242                 return -ETIMEDOUT;
3243
3244         if (timeout == -ERESTARTSYS)
3245                 return -ERESTARTSYS;
3246
3247         return 0;
3248 }
3249
3250 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3251 void dispc_fake_vsync_irq(void)
3252 {
3253         u32 irqstatus = DISPC_IRQ_VSYNC;
3254         int i;
3255
3256         WARN_ON(!in_interrupt());
3257
3258         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3259                 struct omap_dispc_isr_data *isr_data;
3260                 isr_data = &dispc.registered_isr[i];
3261
3262                 if (!isr_data->isr)
3263                         continue;
3264
3265                 if (isr_data->mask & irqstatus)
3266                         isr_data->isr(isr_data->arg, irqstatus);
3267         }
3268 }
3269 #endif
3270
3271 static void _omap_dispc_initialize_irq(void)
3272 {
3273         unsigned long flags;
3274
3275         spin_lock_irqsave(&dispc.irq_lock, flags);
3276
3277         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3278
3279         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3280         if (dss_has_feature(FEAT_MGR_LCD2))
3281                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3282         if (dss_feat_get_num_ovls() > 3)
3283                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3284
3285         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3286          * so clear it */
3287         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3288
3289         _omap_dispc_set_irqs();
3290
3291         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3292 }
3293
3294 void dispc_enable_sidle(void)
3295 {
3296         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3297 }
3298
3299 void dispc_disable_sidle(void)
3300 {
3301         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3302 }
3303
3304 static void _omap_dispc_initial_config(void)
3305 {
3306         u32 l;
3307
3308         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3309         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3310                 l = dispc_read_reg(DISPC_DIVISOR);
3311                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3312                 l = FLD_MOD(l, 1, 0, 0);
3313                 l = FLD_MOD(l, 1, 23, 16);
3314                 dispc_write_reg(DISPC_DIVISOR, l);
3315         }
3316
3317         /* FUNCGATED */
3318         if (dss_has_feature(FEAT_FUNCGATED))
3319                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3320
3321         /* L3 firewall setting: enable access to OCM RAM */
3322         /* XXX this should be somewhere in plat-omap */
3323         if (cpu_is_omap24xx())
3324                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3325
3326         _dispc_setup_color_conv_coef();
3327
3328         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3329
3330         dispc_read_plane_fifo_sizes();
3331
3332         dispc_configure_burst_sizes();
3333
3334         dispc_ovl_enable_zorder_planes();
3335 }
3336
3337 /* DISPC HW IP initialisation */
3338 static int omap_dispchw_probe(struct platform_device *pdev)
3339 {
3340         u32 rev;
3341         int r = 0;
3342         struct resource *dispc_mem;
3343         struct clk *clk;
3344
3345         dispc.pdev = pdev;
3346
3347         spin_lock_init(&dispc.irq_lock);
3348
3349 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3350         spin_lock_init(&dispc.irq_stats_lock);
3351         dispc.irq_stats.last_reset = jiffies;
3352 #endif
3353
3354         INIT_WORK(&dispc.error_work, dispc_error_worker);
3355
3356         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3357         if (!dispc_mem) {
3358                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3359                 return -EINVAL;
3360         }
3361
3362         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3363                                   resource_size(dispc_mem));
3364         if (!dispc.base) {
3365                 DSSERR("can't ioremap DISPC\n");
3366                 return -ENOMEM;
3367         }
3368
3369         dispc.irq = platform_get_irq(dispc.pdev, 0);
3370         if (dispc.irq < 0) {
3371                 DSSERR("platform_get_irq failed\n");
3372                 return -ENODEV;
3373         }
3374
3375         r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3376                              IRQF_SHARED, "OMAP DISPC", dispc.pdev);
3377         if (r < 0) {
3378                 DSSERR("request_irq failed\n");
3379                 return r;
3380         }
3381
3382         clk = clk_get(&pdev->dev, "fck");
3383         if (IS_ERR(clk)) {
3384                 DSSERR("can't get fck\n");
3385                 r = PTR_ERR(clk);
3386                 return r;
3387         }
3388
3389         dispc.dss_clk = clk;
3390
3391         pm_runtime_enable(&pdev->dev);
3392
3393         r = dispc_runtime_get();
3394         if (r)
3395                 goto err_runtime_get;
3396
3397         _omap_dispc_initial_config();
3398
3399         _omap_dispc_initialize_irq();
3400
3401         rev = dispc_read_reg(DISPC_REVISION);
3402         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3403                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3404
3405         dispc_runtime_put();
3406
3407         return 0;
3408
3409 err_runtime_get:
3410         pm_runtime_disable(&pdev->dev);
3411         clk_put(dispc.dss_clk);
3412         return r;
3413 }
3414
3415 static int omap_dispchw_remove(struct platform_device *pdev)
3416 {
3417         pm_runtime_disable(&pdev->dev);
3418
3419         clk_put(dispc.dss_clk);
3420
3421         return 0;
3422 }
3423
3424 static int dispc_runtime_suspend(struct device *dev)
3425 {
3426         dispc_save_context();
3427         dss_runtime_put();
3428
3429         return 0;
3430 }
3431
3432 static int dispc_runtime_resume(struct device *dev)
3433 {
3434         int r;
3435
3436         r = dss_runtime_get();
3437         if (r < 0)
3438                 return r;
3439
3440         dispc_restore_context();
3441
3442         return 0;
3443 }
3444
3445 static const struct dev_pm_ops dispc_pm_ops = {
3446         .runtime_suspend = dispc_runtime_suspend,
3447         .runtime_resume = dispc_runtime_resume,
3448 };
3449
3450 static struct platform_driver omap_dispchw_driver = {
3451         .probe          = omap_dispchw_probe,
3452         .remove         = omap_dispchw_remove,
3453         .driver         = {
3454                 .name   = "omapdss_dispc",
3455                 .owner  = THIS_MODULE,
3456                 .pm     = &dispc_pm_ops,
3457         },
3458 };
3459
3460 int dispc_init_platform_driver(void)
3461 {
3462         return platform_driver_register(&omap_dispchw_driver);
3463 }
3464
3465 void dispc_uninit_platform_driver(void)
3466 {
3467         return platform_driver_unregister(&omap_dispchw_driver);
3468 }