Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <plat/sram.h>
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 struct dispc_h_coef {
  67         s8 hc4;
  68         s8 hc3;
  69         u8 hc2;
  70         s8 hc1;
  71         s8 hc0;
  72 };
  73
  74 struct dispc_v_coef {
  75         s8 vc22;
  76         s8 vc2;
  77         u8 vc1;
  78         s8 vc0;
  79         s8 vc00;
  80 };
  81
  82 enum omap_burst_size {
  83         BURST_SIZE_X2 = 0,
  84         BURST_SIZE_X4 = 1,
  85         BURST_SIZE_X8 = 2,
  86 };
  87
  88 #define REG_GET(idx, start, end) \
  89         FLD_GET(dispc_read_reg(idx), start, end)
  90
  91 #define REG_FLD_MOD(idx, val, start, end)                               \
  92         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  93
  94 struct dispc_irq_stats {
  95         unsigned long last_reset;
  96         unsigned irq_count;
  97         unsigned irqs[32];
  98 };
  99
 100 static struct {
 101         struct platform_device *pdev;
 102         void __iomem    *base;
 103
 104         int             ctx_loss_cnt;
 105
 106         int irq;
 107         struct clk *dss_clk;
 108
 109         u32     fifo_size[MAX_DSS_OVERLAYS];
 110
 111         spinlock_t irq_lock;
 112         u32 irq_error_mask;
 113         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 114         u32 error_irqs;
 115         struct work_struct error_work;
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 121         spinlock_t irq_stats_lock;
 122         struct dispc_irq_stats irq_stats;
 123 #endif
 124 } dispc;
 125
 126 enum omap_color_component {
 127         /* used for all color formats for OMAP3 and earlier
 128          * and for RGB and Y color component on OMAP4
 129          */
 130         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 131         /* used for UV component for
 132          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 133          * color formats on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 136 };
 137
 138 static void _omap_dispc_set_irqs(void);
 139
 140 static inline void dispc_write_reg(const u16 idx, u32 val)
 141 {
 142         __raw_writel(val, dispc.base + idx);
 143 }
 144
 145 static inline u32 dispc_read_reg(const u16 idx)
 146 {
 147         return __raw_readl(dispc.base + idx);
 148 }
 149
 150 static int dispc_get_ctx_loss_count(void)
 151 {
 152         struct device *dev = &dispc.pdev->dev;
 153         struct omap_display_platform_data *pdata = dev->platform_data;
 154         struct omap_dss_board_info *board_data = pdata->board_data;
 155         int cnt;
 156
 157         if (!board_data->get_context_loss_count)
 158                 return -ENOENT;
 159
 160         cnt = board_data->get_context_loss_count(dev);
 161
 162         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 163
 164         return cnt;
 165 }
 166
 167 #define SR(reg) \
 168         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 169 #define RR(reg) \
 170         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 171
 172 static void dispc_save_context(void)
 173 {
 174         int i, j;
 175
 176         DSSDBG("dispc_save_context\n");
 177
 178         SR(IRQENABLE);
 179         SR(CONTROL);
 180         SR(CONFIG);
 181         SR(LINE_NUMBER);
 182         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 183                 SR(GLOBAL_ALPHA);
 184         if (dss_has_feature(FEAT_MGR_LCD2)) {
 185                 SR(CONTROL2);
 186                 SR(CONFIG2);
 187         }
 188
 189         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 190                 SR(DEFAULT_COLOR(i));
 191                 SR(TRANS_COLOR(i));
 192                 SR(SIZE_MGR(i));
 193                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 194                         continue;
 195                 SR(TIMING_H(i));
 196                 SR(TIMING_V(i));
 197                 SR(POL_FREQ(i));
 198                 SR(DIVISORo(i));
 199
 200                 SR(DATA_CYCLE1(i));
 201                 SR(DATA_CYCLE2(i));
 202                 SR(DATA_CYCLE3(i));
 203
 204                 if (dss_has_feature(FEAT_CPR)) {
 205                         SR(CPR_COEF_R(i));
 206                         SR(CPR_COEF_G(i));
 207                         SR(CPR_COEF_B(i));
 208                 }
 209         }
 210
 211         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 212                 SR(OVL_BA0(i));
 213                 SR(OVL_BA1(i));
 214                 SR(OVL_POSITION(i));
 215                 SR(OVL_SIZE(i));
 216                 SR(OVL_ATTRIBUTES(i));
 217                 SR(OVL_FIFO_THRESHOLD(i));
 218                 SR(OVL_ROW_INC(i));
 219                 SR(OVL_PIXEL_INC(i));
 220                 if (dss_has_feature(FEAT_PRELOAD))
 221                         SR(OVL_PRELOAD(i));
 222                 if (i == OMAP_DSS_GFX) {
 223                         SR(OVL_WINDOW_SKIP(i));
 224                         SR(OVL_TABLE_BA(i));
 225                         continue;
 226                 }
 227                 SR(OVL_FIR(i));
 228                 SR(OVL_PICTURE_SIZE(i));
 229                 SR(OVL_ACCU0(i));
 230                 SR(OVL_ACCU1(i));
 231
 232                 for (j = 0; j < 8; j++)
 233                         SR(OVL_FIR_COEF_H(i, j));
 234
 235                 for (j = 0; j < 8; j++)
 236                         SR(OVL_FIR_COEF_HV(i, j));
 237
 238                 for (j = 0; j < 5; j++)
 239                         SR(OVL_CONV_COEF(i, j));
 240
 241                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 242                         for (j = 0; j < 8; j++)
 243                                 SR(OVL_FIR_COEF_V(i, j));
 244                 }
 245
 246                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 247                         SR(OVL_BA0_UV(i));
 248                         SR(OVL_BA1_UV(i));
 249                         SR(OVL_FIR2(i));
 250                         SR(OVL_ACCU2_0(i));
 251                         SR(OVL_ACCU2_1(i));
 252
 253                         for (j = 0; j < 8; j++)
 254                                 SR(OVL_FIR_COEF_H2(i, j));
 255
 256                         for (j = 0; j < 8; j++)
 257                                 SR(OVL_FIR_COEF_HV2(i, j));
 258
 259                         for (j = 0; j < 8; j++)
 260                                 SR(OVL_FIR_COEF_V2(i, j));
 261                 }
 262                 if (dss_has_feature(FEAT_ATTR2))
 263                         SR(OVL_ATTRIBUTES2(i));
 264         }
 265
 266         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 267                 SR(DIVISOR);
 268
 269         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 270         dispc.ctx_valid = true;
 271
 272         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 273 }
 274
 275 static void dispc_restore_context(void)
 276 {
 277         int i, j, ctx;
 278
 279         DSSDBG("dispc_restore_context\n");
 280
 281         if (!dispc.ctx_valid)
 282                 return;
 283
 284         ctx = dispc_get_ctx_loss_count();
 285
 286         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 287                 return;
 288
 289         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 290                         dispc.ctx_loss_cnt, ctx);
 291
 292         /*RR(IRQENABLE);*/
 293         /*RR(CONTROL);*/
 294         RR(CONFIG);
 295         RR(LINE_NUMBER);
 296         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 297                 RR(GLOBAL_ALPHA);
 298         if (dss_has_feature(FEAT_MGR_LCD2))
 299                 RR(CONFIG2);
 300
 301         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 302                 RR(DEFAULT_COLOR(i));
 303                 RR(TRANS_COLOR(i));
 304                 RR(SIZE_MGR(i));
 305                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 306                         continue;
 307                 RR(TIMING_H(i));
 308                 RR(TIMING_V(i));
 309                 RR(POL_FREQ(i));
 310                 RR(DIVISORo(i));
 311
 312                 RR(DATA_CYCLE1(i));
 313                 RR(DATA_CYCLE2(i));
 314                 RR(DATA_CYCLE3(i));
 315
 316                 if (dss_has_feature(FEAT_CPR)) {
 317                         RR(CPR_COEF_R(i));
 318                         RR(CPR_COEF_G(i));
 319                         RR(CPR_COEF_B(i));
 320                 }
 321         }
 322
 323         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 324                 RR(OVL_BA0(i));
 325                 RR(OVL_BA1(i));
 326                 RR(OVL_POSITION(i));
 327                 RR(OVL_SIZE(i));
 328                 RR(OVL_ATTRIBUTES(i));
 329                 RR(OVL_FIFO_THRESHOLD(i));
 330                 RR(OVL_ROW_INC(i));
 331                 RR(OVL_PIXEL_INC(i));
 332                 if (dss_has_feature(FEAT_PRELOAD))
 333                         RR(OVL_PRELOAD(i));
 334                 if (i == OMAP_DSS_GFX) {
 335                         RR(OVL_WINDOW_SKIP(i));
 336                         RR(OVL_TABLE_BA(i));
 337                         continue;
 338                 }
 339                 RR(OVL_FIR(i));
 340                 RR(OVL_PICTURE_SIZE(i));
 341                 RR(OVL_ACCU0(i));
 342                 RR(OVL_ACCU1(i));
 343
 344                 for (j = 0; j < 8; j++)
 345                         RR(OVL_FIR_COEF_H(i, j));
 346
 347                 for (j = 0; j < 8; j++)
 348                         RR(OVL_FIR_COEF_HV(i, j));
 349
 350                 for (j = 0; j < 5; j++)
 351                         RR(OVL_CONV_COEF(i, j));
 352
 353                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_V(i, j));
 356                 }
 357
 358                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 359                         RR(OVL_BA0_UV(i));
 360                         RR(OVL_BA1_UV(i));
 361                         RR(OVL_FIR2(i));
 362                         RR(OVL_ACCU2_0(i));
 363                         RR(OVL_ACCU2_1(i));
 364
 365                         for (j = 0; j < 8; j++)
 366                                 RR(OVL_FIR_COEF_H2(i, j));
 367
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_HV2(i, j));
 370
 371                         for (j = 0; j < 8; j++)
 372                                 RR(OVL_FIR_COEF_V2(i, j));
 373                 }
 374                 if (dss_has_feature(FEAT_ATTR2))
 375                         RR(OVL_ATTRIBUTES2(i));
 376         }
 377
 378         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 379                 RR(DIVISOR);
 380
 381         /* enable last, because LCD & DIGIT enable are here */
 382         RR(CONTROL);
 383         if (dss_has_feature(FEAT_MGR_LCD2))
 384                 RR(CONTROL2);
 385         /* clear spurious SYNC_LOST_DIGIT interrupts */
 386         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 387
 388         /*
 389          * enable last so IRQs won't trigger before
 390          * the context is fully restored
 391          */
 392         RR(IRQENABLE);
 393
 394         DSSDBG("context restored\n");
 395 }
 396
 397 #undef SR
 398 #undef RR
 399
 400 int dispc_runtime_get(void)
 401 {
 402         int r;
 403
 404         DSSDBG("dispc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&dispc.pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 void dispc_runtime_put(void)
 412 {
 413         int r;
 414
 415         DSSDBG("dispc_runtime_put\n");
 416
 417         r = pm_runtime_put(&dispc.pdev->dev);
 418         WARN_ON(r < 0);
 419 }
 420
 421 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
 422 {
 423         if (channel == OMAP_DSS_CHANNEL_LCD ||
 424                         channel == OMAP_DSS_CHANNEL_LCD2)
 425                 return true;
 426         else
 427                 return false;
 428 }
 429
 430 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
 431 {
 432         struct omap_overlay_manager *mgr =
 433                 omap_dss_get_overlay_manager(channel);
 434
 435         return mgr ? mgr->device : NULL;
 436 }
 437
 438 bool dispc_mgr_go_busy(enum omap_channel channel)
 439 {
 440         int bit;
 441
 442         if (dispc_mgr_is_lcd(channel))
 443                 bit = 5; /* GOLCD */
 444         else
 445                 bit = 6; /* GODIGIT */
 446
 447         if (channel == OMAP_DSS_CHANNEL_LCD2)
 448                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 449         else
 450                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 451 }
 452
 453 void dispc_mgr_go(enum omap_channel channel)
 454 {
 455         int bit;
 456         bool enable_bit, go_bit;
 457
 458         if (dispc_mgr_is_lcd(channel))
 459                 bit = 0; /* LCDENABLE */
 460         else
 461                 bit = 1; /* DIGITALENABLE */
 462
 463         /* if the channel is not enabled, we don't need GO */
 464         if (channel == OMAP_DSS_CHANNEL_LCD2)
 465                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 466         else
 467                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 468
 469         if (!enable_bit)
 470                 return;
 471
 472         if (dispc_mgr_is_lcd(channel))
 473                 bit = 5; /* GOLCD */
 474         else
 475                 bit = 6; /* GODIGIT */
 476
 477         if (channel == OMAP_DSS_CHANNEL_LCD2)
 478                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 479         else
 480                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 481
 482         if (go_bit) {
 483                 DSSERR("GO bit not down for channel %d\n", channel);
 484                 return;
 485         }
 486
 487         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 488                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 489
 490         if (channel == OMAP_DSS_CHANNEL_LCD2)
 491                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 492         else
 493                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 494 }
 495
 496 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 497 {
 498         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 499 }
 500
 501 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 502 {
 503         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 504 }
 505
 506 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 507 {
 508         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 509 }
 510
 511 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 512 {
 513         BUG_ON(plane == OMAP_DSS_GFX);
 514
 515         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 516 }
 517
 518 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 519                 u32 value)
 520 {
 521         BUG_ON(plane == OMAP_DSS_GFX);
 522
 523         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 524 }
 525
 526 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 527 {
 528         BUG_ON(plane == OMAP_DSS_GFX);
 529
 530         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 531 }
 532
 533 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
 534                                   int vscaleup, int five_taps,
 535                                   enum omap_color_component color_comp)
 536 {
 537         /* Coefficients for horizontal up-sampling */
 538         static const struct dispc_h_coef coef_hup[8] = {
 539                 {  0,   0, 128,   0,  0 },
 540                 { -1,  13, 124,  -8,  0 },
 541                 { -2,  30, 112, -11, -1 },
 542                 { -5,  51,  95, -11, -2 },
 543                 {  0,  -9,  73,  73, -9 },
 544                 { -2, -11,  95,  51, -5 },
 545                 { -1, -11, 112,  30, -2 },
 546                 {  0,  -8, 124,  13, -1 },
 547         };
 548
 549         /* Coefficients for vertical up-sampling */
 550         static const struct dispc_v_coef coef_vup_3tap[8] = {
 551                 { 0,  0, 128,  0, 0 },
 552                 { 0,  3, 123,  2, 0 },
 553                 { 0, 12, 111,  5, 0 },
 554                 { 0, 32,  89,  7, 0 },
 555                 { 0,  0,  64, 64, 0 },
 556                 { 0,  7,  89, 32, 0 },
 557                 { 0,  5, 111, 12, 0 },
 558                 { 0,  2, 123,  3, 0 },
 559         };
 560
 561         static const struct dispc_v_coef coef_vup_5tap[8] = {
 562                 {  0,   0, 128,   0,  0 },
 563                 { -1,  13, 124,  -8,  0 },
 564                 { -2,  30, 112, -11, -1 },
 565                 { -5,  51,  95, -11, -2 },
 566                 {  0,  -9,  73,  73, -9 },
 567                 { -2, -11,  95,  51, -5 },
 568                 { -1, -11, 112,  30, -2 },
 569                 {  0,  -8, 124,  13, -1 },
 570         };
 571
 572         /* Coefficients for horizontal down-sampling */
 573         static const struct dispc_h_coef coef_hdown[8] = {
 574                 {   0, 36, 56, 36,  0 },
 575                 {   4, 40, 55, 31, -2 },
 576                 {   8, 44, 54, 27, -5 },
 577                 {  12, 48, 53, 22, -7 },
 578                 {  -9, 17, 52, 51, 17 },
 579                 {  -7, 22, 53, 48, 12 },
 580                 {  -5, 27, 54, 44,  8 },
 581                 {  -2, 31, 55, 40,  4 },
 582         };
 583
 584         /* Coefficients for vertical down-sampling */
 585         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 586                 { 0, 36, 56, 36, 0 },
 587                 { 0, 40, 57, 31, 0 },
 588                 { 0, 45, 56, 27, 0 },
 589                 { 0, 50, 55, 23, 0 },
 590                 { 0, 18, 55, 55, 0 },
 591                 { 0, 23, 55, 50, 0 },
 592                 { 0, 27, 56, 45, 0 },
 593                 { 0, 31, 57, 40, 0 },
 594         };
 595
 596         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 597                 {   0, 36, 56, 36,  0 },
 598                 {   4, 40, 55, 31, -2 },
 599                 {   8, 44, 54, 27, -5 },
 600                 {  12, 48, 53, 22, -7 },
 601                 {  -9, 17, 52, 51, 17 },
 602                 {  -7, 22, 53, 48, 12 },
 603                 {  -5, 27, 54, 44,  8 },
 604                 {  -2, 31, 55, 40,  4 },
 605         };
 606
 607         const struct dispc_h_coef *h_coef;
 608         const struct dispc_v_coef *v_coef;
 609         int i;
 610
 611         if (hscaleup)
 612                 h_coef = coef_hup;
 613         else
 614                 h_coef = coef_hdown;
 615
 616         if (vscaleup)
 617                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 618         else
 619                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 620
 621         for (i = 0; i < 8; i++) {
 622                 u32 h, hv;
 623
 624                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 625                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 626                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 627                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 628                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 629                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 630                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 631                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 632
 633                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 634                         dispc_ovl_write_firh_reg(plane, i, h);
 635                         dispc_ovl_write_firhv_reg(plane, i, hv);
 636                 } else {
 637                         dispc_ovl_write_firh2_reg(plane, i, h);
 638                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 639                 }
 640
 641         }
 642
 643         if (five_taps) {
 644                 for (i = 0; i < 8; i++) {
 645                         u32 v;
 646                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 647                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 648                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 649                                 dispc_ovl_write_firv_reg(plane, i, v);
 650                         else
 651                                 dispc_ovl_write_firv2_reg(plane, i, v);
 652                 }
 653         }
 654 }
 655
 656 static void _dispc_setup_color_conv_coef(void)
 657 {
 658         int i;
 659         const struct color_conv_coef {
 660                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 661                 int  full_range;
 662         }  ctbl_bt601_5 = {
 663                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 664         };
 665
 666         const struct color_conv_coef *ct;
 667
 668 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 669
 670         ct = &ctbl_bt601_5;
 671
 672         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 673                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 674                         CVAL(ct->rcr, ct->ry));
 675                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 676                         CVAL(ct->gy,  ct->rcb));
 677                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 678                         CVAL(ct->gcb, ct->gcr));
 679                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 680                         CVAL(ct->bcr, ct->by));
 681                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 682                         CVAL(0, ct->bcb));
 683
 684                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 685                         11, 11);
 686         }
 687
 688 #undef CVAL
 689 }
 690
 691
 692 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 693 {
 694         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 695 }
 696
 697 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 698 {
 699         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 700 }
 701
 702 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 703 {
 704         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 705 }
 706
 707 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 708 {
 709         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 710 }
 711
 712 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 713 {
 714         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 715
 716         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 717 }
 718
 719 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 720 {
 721         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 722
 723         if (plane == OMAP_DSS_GFX)
 724                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 725         else
 726                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 727 }
 728
 729 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 730 {
 731         u32 val;
 732
 733         BUG_ON(plane == OMAP_DSS_GFX);
 734
 735         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 736
 737         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 738 }
 739
 740 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 741 {
 742         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 743
 744         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 745                 return;
 746
 747         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 748 }
 749
 750 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 751 {
 752         static const unsigned shifts[] = { 0, 8, 16, };
 753         int shift;
 754         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 755
 756         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 757                 return;
 758
 759         shift = shifts[plane];
 760         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 761 }
 762
 763 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 764 {
 765         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 766 }
 767
 768 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 769 {
 770         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 771 }
 772
 773 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 774                 enum omap_color_mode color_mode)
 775 {
 776         u32 m = 0;
 777         if (plane != OMAP_DSS_GFX) {
 778                 switch (color_mode) {
 779                 case OMAP_DSS_COLOR_NV12:
 780                         m = 0x0; break;
 781                 case OMAP_DSS_COLOR_RGB12U:
 782                         m = 0x1; break;
 783                 case OMAP_DSS_COLOR_RGBA16:
 784                         m = 0x2; break;
 785                 case OMAP_DSS_COLOR_RGBX16:
 786                         m = 0x4; break;
 787                 case OMAP_DSS_COLOR_ARGB16:
 788                         m = 0x5; break;
 789                 case OMAP_DSS_COLOR_RGB16:
 790                         m = 0x6; break;
 791                 case OMAP_DSS_COLOR_ARGB16_1555:
 792                         m = 0x7; break;
 793                 case OMAP_DSS_COLOR_RGB24U:
 794                         m = 0x8; break;
 795                 case OMAP_DSS_COLOR_RGB24P:
 796                         m = 0x9; break;
 797                 case OMAP_DSS_COLOR_YUV2:
 798                         m = 0xa; break;
 799                 case OMAP_DSS_COLOR_UYVY:
 800                         m = 0xb; break;
 801                 case OMAP_DSS_COLOR_ARGB32:
 802                         m = 0xc; break;
 803                 case OMAP_DSS_COLOR_RGBA32:
 804                         m = 0xd; break;
 805                 case OMAP_DSS_COLOR_RGBX32:
 806                         m = 0xe; break;
 807                 case OMAP_DSS_COLOR_XRGB16_1555:
 808                         m = 0xf; break;
 809                 default:
 810                         BUG(); break;
 811                 }
 812         } else {
 813                 switch (color_mode) {
 814                 case OMAP_DSS_COLOR_CLUT1:
 815                         m = 0x0; break;
 816                 case OMAP_DSS_COLOR_CLUT2:
 817                         m = 0x1; break;
 818                 case OMAP_DSS_COLOR_CLUT4:
 819                         m = 0x2; break;
 820                 case OMAP_DSS_COLOR_CLUT8:
 821                         m = 0x3; break;
 822                 case OMAP_DSS_COLOR_RGB12U:
 823                         m = 0x4; break;
 824                 case OMAP_DSS_COLOR_ARGB16:
 825                         m = 0x5; break;
 826                 case OMAP_DSS_COLOR_RGB16:
 827                         m = 0x6; break;
 828                 case OMAP_DSS_COLOR_ARGB16_1555:
 829                         m = 0x7; break;
 830                 case OMAP_DSS_COLOR_RGB24U:
 831                         m = 0x8; break;
 832                 case OMAP_DSS_COLOR_RGB24P:
 833                         m = 0x9; break;
 834                 case OMAP_DSS_COLOR_YUV2:
 835                         m = 0xa; break;
 836                 case OMAP_DSS_COLOR_UYVY:
 837                         m = 0xb; break;
 838                 case OMAP_DSS_COLOR_ARGB32:
 839                         m = 0xc; break;
 840                 case OMAP_DSS_COLOR_RGBA32:
 841                         m = 0xd; break;
 842                 case OMAP_DSS_COLOR_RGBX32:
 843                         m = 0xe; break;
 844                 case OMAP_DSS_COLOR_XRGB16_1555:
 845                         m = 0xf; break;
 846                 default:
 847                         BUG(); break;
 848                 }
 849         }
 850
 851         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 852 }
 853
 854 static void dispc_ovl_set_channel_out(enum omap_plane plane,
 855                 enum omap_channel channel)
 856 {
 857         int shift;
 858         u32 val;
 859         int chan = 0, chan2 = 0;
 860
 861         switch (plane) {
 862         case OMAP_DSS_GFX:
 863                 shift = 8;
 864                 break;
 865         case OMAP_DSS_VIDEO1:
 866         case OMAP_DSS_VIDEO2:
 867                 shift = 16;
 868                 break;
 869         default:
 870                 BUG();
 871                 return;
 872         }
 873
 874         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 875         if (dss_has_feature(FEAT_MGR_LCD2)) {
 876                 switch (channel) {
 877                 case OMAP_DSS_CHANNEL_LCD:
 878                         chan = 0;
 879                         chan2 = 0;
 880                         break;
 881                 case OMAP_DSS_CHANNEL_DIGIT:
 882                         chan = 1;
 883                         chan2 = 0;
 884                         break;
 885                 case OMAP_DSS_CHANNEL_LCD2:
 886                         chan = 0;
 887                         chan2 = 1;
 888                         break;
 889                 default:
 890                         BUG();
 891                 }
 892
 893                 val = FLD_MOD(val, chan, shift, shift);
 894                 val = FLD_MOD(val, chan2, 31, 30);
 895         } else {
 896                 val = FLD_MOD(val, channel, shift, shift);
 897         }
 898         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 899 }
 900
 901 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 902                 enum omap_burst_size burst_size)
 903 {
 904         static const unsigned shifts[] = { 6, 14, 14, };
 905         int shift;
 906
 907         shift = shifts[plane];
 908         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 909 }
 910
 911 static void dispc_configure_burst_sizes(void)
 912 {
 913         int i;
 914         const int burst_size = BURST_SIZE_X8;
 915
 916         /* Configure burst size always to maximum size */
 917         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 918                 dispc_ovl_set_burst_size(i, burst_size);
 919 }
 920
 921 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
 922 {
 923         unsigned unit = dss_feat_get_burst_size_unit();
 924         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 925         return unit * 8;
 926 }
 927
 928 void dispc_enable_gamma_table(bool enable)
 929 {
 930         /*
 931          * This is partially implemented to support only disabling of
 932          * the gamma table.
 933          */
 934         if (enable) {
 935                 DSSWARN("Gamma table enabling for TV not yet supported");
 936                 return;
 937         }
 938
 939         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 940 }
 941
 942 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
 943 {
 944         u16 reg;
 945
 946         if (channel == OMAP_DSS_CHANNEL_LCD)
 947                 reg = DISPC_CONFIG;
 948         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 949                 reg = DISPC_CONFIG2;
 950         else
 951                 return;
 952
 953         REG_FLD_MOD(reg, enable, 15, 15);
 954 }
 955
 956 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 957                 struct omap_dss_cpr_coefs *coefs)
 958 {
 959         u32 coef_r, coef_g, coef_b;
 960
 961         if (!dispc_mgr_is_lcd(channel))
 962                 return;
 963
 964         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 965                 FLD_VAL(coefs->rb, 9, 0);
 966         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 967                 FLD_VAL(coefs->gb, 9, 0);
 968         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 969                 FLD_VAL(coefs->bb, 9, 0);
 970
 971         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 972         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 973         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 974 }
 975
 976 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
 977 {
 978         u32 val;
 979
 980         BUG_ON(plane == OMAP_DSS_GFX);
 981
 982         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 983         val = FLD_MOD(val, enable, 9, 9);
 984         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 985 }
 986
 987 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
 988 {
 989         static const unsigned shifts[] = { 5, 10, 10 };
 990         int shift;
 991
 992         shift = shifts[plane];
 993         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
 994 }
 995
 996 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 997 {
 998         u32 val;
 999         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1000         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1001         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1002 }
1003
1004 void dispc_set_digit_size(u16 width, u16 height)
1005 {
1006         u32 val;
1007         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1008         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1009         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1010 }
1011
1012 static void dispc_read_plane_fifo_sizes(void)
1013 {
1014         u32 size;
1015         int plane;
1016         u8 start, end;
1017         u32 unit;
1018
1019         unit = dss_feat_get_buffer_size_unit();
1020
1021         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1022
1023         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1024                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1025                 size *= unit;
1026                 dispc.fifo_size[plane] = size;
1027         }
1028 }
1029
1030 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1031 {
1032         return dispc.fifo_size[plane];
1033 }
1034
1035 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1036                 u32 high)
1037 {
1038         u8 hi_start, hi_end, lo_start, lo_end;
1039         u32 unit;
1040
1041         unit = dss_feat_get_buffer_size_unit();
1042
1043         WARN_ON(low % unit != 0);
1044         WARN_ON(high % unit != 0);
1045
1046         low /= unit;
1047         high /= unit;
1048
1049         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1050         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1051
1052         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1053                         plane,
1054                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1055                                 lo_start, lo_end),
1056                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1057                                 hi_start, hi_end),
1058                         low, high);
1059
1060         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1061                         FLD_VAL(high, hi_start, hi_end) |
1062                         FLD_VAL(low, lo_start, lo_end));
1063 }
1064
1065 void dispc_enable_fifomerge(bool enable)
1066 {
1067         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1068         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1069 }
1070
1071 static void dispc_ovl_set_fir(enum omap_plane plane,
1072                                 int hinc, int vinc,
1073                                 enum omap_color_component color_comp)
1074 {
1075         u32 val;
1076
1077         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1078                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1079
1080                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1081                                         &hinc_start, &hinc_end);
1082                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1083                                         &vinc_start, &vinc_end);
1084                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1085                                 FLD_VAL(hinc, hinc_start, hinc_end);
1086
1087                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1088         } else {
1089                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1090                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1091         }
1092 }
1093
1094 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1095 {
1096         u32 val;
1097         u8 hor_start, hor_end, vert_start, vert_end;
1098
1099         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1100         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1101
1102         val = FLD_VAL(vaccu, vert_start, vert_end) |
1103                         FLD_VAL(haccu, hor_start, hor_end);
1104
1105         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1106 }
1107
1108 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1109 {
1110         u32 val;
1111         u8 hor_start, hor_end, vert_start, vert_end;
1112
1113         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1114         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1115
1116         val = FLD_VAL(vaccu, vert_start, vert_end) |
1117                         FLD_VAL(haccu, hor_start, hor_end);
1118
1119         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1120 }
1121
1122 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1123                 int vaccu)
1124 {
1125         u32 val;
1126
1127         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1128         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1129 }
1130
1131 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1132                 int vaccu)
1133 {
1134         u32 val;
1135
1136         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1137         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1138 }
1139
1140 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1141                 u16 orig_width, u16 orig_height,
1142                 u16 out_width, u16 out_height,
1143                 bool five_taps, u8 rotation,
1144                 enum omap_color_component color_comp)
1145 {
1146         int fir_hinc, fir_vinc;
1147         int hscaleup, vscaleup;
1148
1149         hscaleup = orig_width <= out_width;
1150         vscaleup = orig_height <= out_height;
1151
1152         dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1153                         color_comp);
1154
1155         fir_hinc = 1024 * orig_width / out_width;
1156         fir_vinc = 1024 * orig_height / out_height;
1157
1158         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1159 }
1160
1161 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1162                 u16 orig_width, u16 orig_height,
1163                 u16 out_width, u16 out_height,
1164                 bool ilace, bool five_taps,
1165                 bool fieldmode, enum omap_color_mode color_mode,
1166                 u8 rotation)
1167 {
1168         int accu0 = 0;
1169         int accu1 = 0;
1170         u32 l;
1171
1172         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1173                                 out_width, out_height, five_taps,
1174                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1175         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1176
1177         /* RESIZEENABLE and VERTICALTAPS */
1178         l &= ~((0x3 << 5) | (0x1 << 21));
1179         l |= (orig_width != out_width) ? (1 << 5) : 0;
1180         l |= (orig_height != out_height) ? (1 << 6) : 0;
1181         l |= five_taps ? (1 << 21) : 0;
1182
1183         /* VRESIZECONF and HRESIZECONF */
1184         if (dss_has_feature(FEAT_RESIZECONF)) {
1185                 l &= ~(0x3 << 7);
1186                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1187                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1188         }
1189
1190         /* LINEBUFFERSPLIT */
1191         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1192                 l &= ~(0x1 << 22);
1193                 l |= five_taps ? (1 << 22) : 0;
1194         }
1195
1196         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1197
1198         /*
1199          * field 0 = even field = bottom field
1200          * field 1 = odd field = top field
1201          */
1202         if (ilace && !fieldmode) {
1203                 accu1 = 0;
1204                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1205                 if (accu0 >= 1024/2) {
1206                         accu1 = 1024/2;
1207                         accu0 -= accu1;
1208                 }
1209         }
1210
1211         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1212         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1213 }
1214
1215 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1216                 u16 orig_width, u16 orig_height,
1217                 u16 out_width, u16 out_height,
1218                 bool ilace, bool five_taps,
1219                 bool fieldmode, enum omap_color_mode color_mode,
1220                 u8 rotation)
1221 {
1222         int scale_x = out_width != orig_width;
1223         int scale_y = out_height != orig_height;
1224
1225         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1226                 return;
1227         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1228                         color_mode != OMAP_DSS_COLOR_UYVY &&
1229                         color_mode != OMAP_DSS_COLOR_NV12)) {
1230                 /* reset chroma resampling for RGB formats  */
1231                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1232                 return;
1233         }
1234         switch (color_mode) {
1235         case OMAP_DSS_COLOR_NV12:
1236                 /* UV is subsampled by 2 vertically*/
1237                 orig_height >>= 1;
1238                 /* UV is subsampled by 2 horz.*/
1239                 orig_width >>= 1;
1240                 break;
1241         case OMAP_DSS_COLOR_YUV2:
1242         case OMAP_DSS_COLOR_UYVY:
1243                 /*For YUV422 with 90/270 rotation,
1244                  *we don't upsample chroma
1245                  */
1246                 if (rotation == OMAP_DSS_ROT_0 ||
1247                         rotation == OMAP_DSS_ROT_180)
1248                         /* UV is subsampled by 2 hrz*/
1249                         orig_width >>= 1;
1250                 /* must use FIR for YUV422 if rotated */
1251                 if (rotation != OMAP_DSS_ROT_0)
1252                         scale_x = scale_y = true;
1253                 break;
1254         default:
1255                 BUG();
1256         }
1257
1258         if (out_width != orig_width)
1259                 scale_x = true;
1260         if (out_height != orig_height)
1261                 scale_y = true;
1262
1263         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1264                         out_width, out_height, five_taps,
1265                                 rotation, DISPC_COLOR_COMPONENT_UV);
1266
1267         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1268                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1269         /* set H scaling */
1270         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1271         /* set V scaling */
1272         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1273
1274         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1275         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1276 }
1277
1278 static void dispc_ovl_set_scaling(enum omap_plane plane,
1279                 u16 orig_width, u16 orig_height,
1280                 u16 out_width, u16 out_height,
1281                 bool ilace, bool five_taps,
1282                 bool fieldmode, enum omap_color_mode color_mode,
1283                 u8 rotation)
1284 {
1285         BUG_ON(plane == OMAP_DSS_GFX);
1286
1287         dispc_ovl_set_scaling_common(plane,
1288                         orig_width, orig_height,
1289                         out_width, out_height,
1290                         ilace, five_taps,
1291                         fieldmode, color_mode,
1292                         rotation);
1293
1294         dispc_ovl_set_scaling_uv(plane,
1295                 orig_width, orig_height,
1296                 out_width, out_height,
1297                 ilace, five_taps,
1298                 fieldmode, color_mode,
1299                 rotation);
1300 }
1301
1302 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1303                 bool mirroring, enum omap_color_mode color_mode)
1304 {
1305         bool row_repeat = false;
1306         int vidrot = 0;
1307
1308         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1309                         color_mode == OMAP_DSS_COLOR_UYVY) {
1310
1311                 if (mirroring) {
1312                         switch (rotation) {
1313                         case OMAP_DSS_ROT_0:
1314                                 vidrot = 2;
1315                                 break;
1316                         case OMAP_DSS_ROT_90:
1317                                 vidrot = 1;
1318                                 break;
1319                         case OMAP_DSS_ROT_180:
1320                                 vidrot = 0;
1321                                 break;
1322                         case OMAP_DSS_ROT_270:
1323                                 vidrot = 3;
1324                                 break;
1325                         }
1326                 } else {
1327                         switch (rotation) {
1328                         case OMAP_DSS_ROT_0:
1329                                 vidrot = 0;
1330                                 break;
1331                         case OMAP_DSS_ROT_90:
1332                                 vidrot = 1;
1333                                 break;
1334                         case OMAP_DSS_ROT_180:
1335                                 vidrot = 2;
1336                                 break;
1337                         case OMAP_DSS_ROT_270:
1338                                 vidrot = 3;
1339                                 break;
1340                         }
1341                 }
1342
1343                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1344                         row_repeat = true;
1345                 else
1346                         row_repeat = false;
1347         }
1348
1349         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1350         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1351                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1352                         row_repeat ? 1 : 0, 18, 18);
1353 }
1354
1355 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1356 {
1357         switch (color_mode) {
1358         case OMAP_DSS_COLOR_CLUT1:
1359                 return 1;
1360         case OMAP_DSS_COLOR_CLUT2:
1361                 return 2;
1362         case OMAP_DSS_COLOR_CLUT4:
1363                 return 4;
1364         case OMAP_DSS_COLOR_CLUT8:
1365         case OMAP_DSS_COLOR_NV12:
1366                 return 8;
1367         case OMAP_DSS_COLOR_RGB12U:
1368         case OMAP_DSS_COLOR_RGB16:
1369         case OMAP_DSS_COLOR_ARGB16:
1370         case OMAP_DSS_COLOR_YUV2:
1371         case OMAP_DSS_COLOR_UYVY:
1372         case OMAP_DSS_COLOR_RGBA16:
1373         case OMAP_DSS_COLOR_RGBX16:
1374         case OMAP_DSS_COLOR_ARGB16_1555:
1375         case OMAP_DSS_COLOR_XRGB16_1555:
1376                 return 16;
1377         case OMAP_DSS_COLOR_RGB24P:
1378                 return 24;
1379         case OMAP_DSS_COLOR_RGB24U:
1380         case OMAP_DSS_COLOR_ARGB32:
1381         case OMAP_DSS_COLOR_RGBA32:
1382         case OMAP_DSS_COLOR_RGBX32:
1383                 return 32;
1384         default:
1385                 BUG();
1386         }
1387 }
1388
1389 static s32 pixinc(int pixels, u8 ps)
1390 {
1391         if (pixels == 1)
1392                 return 1;
1393         else if (pixels > 1)
1394                 return 1 + (pixels - 1) * ps;
1395         else if (pixels < 0)
1396                 return 1 - (-pixels + 1) * ps;
1397         else
1398                 BUG();
1399 }
1400
1401 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1402                 u16 screen_width,
1403                 u16 width, u16 height,
1404                 enum omap_color_mode color_mode, bool fieldmode,
1405                 unsigned int field_offset,
1406                 unsigned *offset0, unsigned *offset1,
1407                 s32 *row_inc, s32 *pix_inc)
1408 {
1409         u8 ps;
1410
1411         /* FIXME CLUT formats */
1412         switch (color_mode) {
1413         case OMAP_DSS_COLOR_CLUT1:
1414         case OMAP_DSS_COLOR_CLUT2:
1415         case OMAP_DSS_COLOR_CLUT4:
1416         case OMAP_DSS_COLOR_CLUT8:
1417                 BUG();
1418                 return;
1419         case OMAP_DSS_COLOR_YUV2:
1420         case OMAP_DSS_COLOR_UYVY:
1421                 ps = 4;
1422                 break;
1423         default:
1424                 ps = color_mode_to_bpp(color_mode) / 8;
1425                 break;
1426         }
1427
1428         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1429                         width, height);
1430
1431         /*
1432          * field 0 = even field = bottom field
1433          * field 1 = odd field = top field
1434          */
1435         switch (rotation + mirror * 4) {
1436         case OMAP_DSS_ROT_0:
1437         case OMAP_DSS_ROT_180:
1438                 /*
1439                  * If the pixel format is YUV or UYVY divide the width
1440                  * of the image by 2 for 0 and 180 degree rotation.
1441                  */
1442                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1443                         color_mode == OMAP_DSS_COLOR_UYVY)
1444                         width = width >> 1;
1445         case OMAP_DSS_ROT_90:
1446         case OMAP_DSS_ROT_270:
1447                 *offset1 = 0;
1448                 if (field_offset)
1449                         *offset0 = field_offset * screen_width * ps;
1450                 else
1451                         *offset0 = 0;
1452
1453                 *row_inc = pixinc(1 + (screen_width - width) +
1454                                 (fieldmode ? screen_width : 0),
1455                                 ps);
1456                 *pix_inc = pixinc(1, ps);
1457                 break;
1458
1459         case OMAP_DSS_ROT_0 + 4:
1460         case OMAP_DSS_ROT_180 + 4:
1461                 /* If the pixel format is YUV or UYVY divide the width
1462                  * of the image by 2  for 0 degree and 180 degree
1463                  */
1464                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1465                         color_mode == OMAP_DSS_COLOR_UYVY)
1466                         width = width >> 1;
1467         case OMAP_DSS_ROT_90 + 4:
1468         case OMAP_DSS_ROT_270 + 4:
1469                 *offset1 = 0;
1470                 if (field_offset)
1471                         *offset0 = field_offset * screen_width * ps;
1472                 else
1473                         *offset0 = 0;
1474                 *row_inc = pixinc(1 - (screen_width + width) -
1475                                 (fieldmode ? screen_width : 0),
1476                                 ps);
1477                 *pix_inc = pixinc(1, ps);
1478                 break;
1479
1480         default:
1481                 BUG();
1482         }
1483 }
1484
1485 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1486                 u16 screen_width,
1487                 u16 width, u16 height,
1488                 enum omap_color_mode color_mode, bool fieldmode,
1489                 unsigned int field_offset,
1490                 unsigned *offset0, unsigned *offset1,
1491                 s32 *row_inc, s32 *pix_inc)
1492 {
1493         u8 ps;
1494         u16 fbw, fbh;
1495
1496         /* FIXME CLUT formats */
1497         switch (color_mode) {
1498         case OMAP_DSS_COLOR_CLUT1:
1499         case OMAP_DSS_COLOR_CLUT2:
1500         case OMAP_DSS_COLOR_CLUT4:
1501         case OMAP_DSS_COLOR_CLUT8:
1502                 BUG();
1503                 return;
1504         default:
1505                 ps = color_mode_to_bpp(color_mode) / 8;
1506                 break;
1507         }
1508
1509         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1510                         width, height);
1511
1512         /* width & height are overlay sizes, convert to fb sizes */
1513
1514         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1515                 fbw = width;
1516                 fbh = height;
1517         } else {
1518                 fbw = height;
1519                 fbh = width;
1520         }
1521
1522         /*
1523          * field 0 = even field = bottom field
1524          * field 1 = odd field = top field
1525          */
1526         switch (rotation + mirror * 4) {
1527         case OMAP_DSS_ROT_0:
1528                 *offset1 = 0;
1529                 if (field_offset)
1530                         *offset0 = *offset1 + field_offset * screen_width * ps;
1531                 else
1532                         *offset0 = *offset1;
1533                 *row_inc = pixinc(1 + (screen_width - fbw) +
1534                                 (fieldmode ? screen_width : 0),
1535                                 ps);
1536                 *pix_inc = pixinc(1, ps);
1537                 break;
1538         case OMAP_DSS_ROT_90:
1539                 *offset1 = screen_width * (fbh - 1) * ps;
1540                 if (field_offset)
1541                         *offset0 = *offset1 + field_offset * ps;
1542                 else
1543                         *offset0 = *offset1;
1544                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1545                                 (fieldmode ? 1 : 0), ps);
1546                 *pix_inc = pixinc(-screen_width, ps);
1547                 break;
1548         case OMAP_DSS_ROT_180:
1549                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1550                 if (field_offset)
1551                         *offset0 = *offset1 - field_offset * screen_width * ps;
1552                 else
1553                         *offset0 = *offset1;
1554                 *row_inc = pixinc(-1 -
1555                                 (screen_width - fbw) -
1556                                 (fieldmode ? screen_width : 0),
1557                                 ps);
1558                 *pix_inc = pixinc(-1, ps);
1559                 break;
1560         case OMAP_DSS_ROT_270:
1561                 *offset1 = (fbw - 1) * ps;
1562                 if (field_offset)
1563                         *offset0 = *offset1 - field_offset * ps;
1564                 else
1565                         *offset0 = *offset1;
1566                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1567                                 (fieldmode ? 1 : 0), ps);
1568                 *pix_inc = pixinc(screen_width, ps);
1569                 break;
1570
1571         /* mirroring */
1572         case OMAP_DSS_ROT_0 + 4:
1573                 *offset1 = (fbw - 1) * ps;
1574                 if (field_offset)
1575                         *offset0 = *offset1 + field_offset * screen_width * ps;
1576                 else
1577                         *offset0 = *offset1;
1578                 *row_inc = pixinc(screen_width * 2 - 1 +
1579                                 (fieldmode ? screen_width : 0),
1580                                 ps);
1581                 *pix_inc = pixinc(-1, ps);
1582                 break;
1583
1584         case OMAP_DSS_ROT_90 + 4:
1585                 *offset1 = 0;
1586                 if (field_offset)
1587                         *offset0 = *offset1 + field_offset * ps;
1588                 else
1589                         *offset0 = *offset1;
1590                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1591                                 (fieldmode ? 1 : 0),
1592                                 ps);
1593                 *pix_inc = pixinc(screen_width, ps);
1594                 break;
1595
1596         case OMAP_DSS_ROT_180 + 4:
1597                 *offset1 = screen_width * (fbh - 1) * ps;
1598                 if (field_offset)
1599                         *offset0 = *offset1 - field_offset * screen_width * ps;
1600                 else
1601                         *offset0 = *offset1;
1602                 *row_inc = pixinc(1 - screen_width * 2 -
1603                                 (fieldmode ? screen_width : 0),
1604                                 ps);
1605                 *pix_inc = pixinc(1, ps);
1606                 break;
1607
1608         case OMAP_DSS_ROT_270 + 4:
1609                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1610                 if (field_offset)
1611                         *offset0 = *offset1 - field_offset * ps;
1612                 else
1613                         *offset0 = *offset1;
1614                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1615                                 (fieldmode ? 1 : 0),
1616                                 ps);
1617                 *pix_inc = pixinc(-screen_width, ps);
1618                 break;
1619
1620         default:
1621                 BUG();
1622         }
1623 }
1624
1625 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1626                 u16 height, u16 out_width, u16 out_height,
1627                 enum omap_color_mode color_mode)
1628 {
1629         u32 fclk = 0;
1630         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1631
1632         if (height > out_height) {
1633                 /* FIXME get real display PPL */
1634                 unsigned int ppl = 800;
1635
1636                 tmp = pclk * height * out_width;
1637                 do_div(tmp, 2 * out_height * ppl);
1638                 fclk = tmp;
1639
1640                 if (height > 2 * out_height) {
1641                         if (ppl == out_width)
1642                                 return 0;
1643
1644                         tmp = pclk * (height - 2 * out_height) * out_width;
1645                         do_div(tmp, 2 * out_height * (ppl - out_width));
1646                         fclk = max(fclk, (u32) tmp);
1647                 }
1648         }
1649
1650         if (width > out_width) {
1651                 tmp = pclk * width;
1652                 do_div(tmp, out_width);
1653                 fclk = max(fclk, (u32) tmp);
1654
1655                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1656                         fclk <<= 1;
1657         }
1658
1659         return fclk;
1660 }
1661
1662 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1663                 u16 height, u16 out_width, u16 out_height)
1664 {
1665         unsigned int hf, vf;
1666
1667         /*
1668          * FIXME how to determine the 'A' factor
1669          * for the no downscaling case ?
1670          */
1671
1672         if (width > 3 * out_width)
1673                 hf = 4;
1674         else if (width > 2 * out_width)
1675                 hf = 3;
1676         else if (width > out_width)
1677                 hf = 2;
1678         else
1679                 hf = 1;
1680
1681         if (height > out_height)
1682                 vf = 2;
1683         else
1684                 vf = 1;
1685
1686         return dispc_mgr_pclk_rate(channel) * vf * hf;
1687 }
1688
1689 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1690                 bool ilace, enum omap_channel channel, bool replication,
1691                 u32 fifo_low, u32 fifo_high)
1692 {
1693         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1694         bool five_taps = 0;
1695         bool fieldmode = 0;
1696         int cconv = 0;
1697         unsigned offset0, offset1;
1698         s32 row_inc;
1699         s32 pix_inc;
1700         u16 frame_height = oi->height;
1701         unsigned int field_offset = 0;
1702
1703         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1704                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1705                 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1706                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1707                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1708                 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1709
1710         if (oi->paddr == 0)
1711                 return -EINVAL;
1712
1713         if (ilace && oi->height == oi->out_height)
1714                 fieldmode = 1;
1715
1716         if (ilace) {
1717                 if (fieldmode)
1718                         oi->height /= 2;
1719                 oi->pos_y /= 2;
1720                 oi->out_height /= 2;
1721
1722                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1723                                 "out_height %d\n",
1724                                 oi->height, oi->pos_y, oi->out_height);
1725         }
1726
1727         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1728                 return -EINVAL;
1729
1730         if (plane == OMAP_DSS_GFX) {
1731                 if (oi->width != oi->out_width || oi->height != oi->out_height)
1732                         return -EINVAL;
1733         } else {
1734                 /* video plane */
1735
1736                 unsigned long fclk = 0;
1737
1738                 if (oi->out_width < oi->width / maxdownscale ||
1739                    oi->out_width > oi->width * 8)
1740                         return -EINVAL;
1741
1742                 if (oi->out_height < oi->height / maxdownscale ||
1743                    oi->out_height > oi->height * 8)
1744                         return -EINVAL;
1745
1746                 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1747                                 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1748                                 oi->color_mode == OMAP_DSS_COLOR_NV12)
1749                         cconv = 1;
1750
1751                 /* Must use 5-tap filter? */
1752                 five_taps = oi->height > oi->out_height * 2;
1753
1754                 if (!five_taps) {
1755                         fclk = calc_fclk(channel, oi->width, oi->height,
1756                                         oi->out_width, oi->out_height);
1757
1758                         /* Try 5-tap filter if 3-tap fclk is too high */
1759                         if (cpu_is_omap34xx() && oi->height > oi->out_height &&
1760                                         fclk > dispc_fclk_rate())
1761                                 five_taps = true;
1762                 }
1763
1764                 if (oi->width > (2048 >> five_taps)) {
1765                         DSSERR("failed to set up scaling, fclk too low\n");
1766                         return -EINVAL;
1767                 }
1768
1769                 if (five_taps)
1770                         fclk = calc_fclk_five_taps(channel, oi->width,
1771                                         oi->height, oi->out_width,
1772                                         oi->out_height, oi->color_mode);
1773
1774                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1775                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1776
1777                 if (!fclk || fclk > dispc_fclk_rate()) {
1778                         DSSERR("failed to set up scaling, "
1779                                         "required fclk rate = %lu Hz, "
1780                                         "current fclk rate = %lu Hz\n",
1781                                         fclk, dispc_fclk_rate());
1782                         return -EINVAL;
1783                 }
1784         }
1785
1786         if (ilace && !fieldmode) {
1787                 /*
1788                  * when downscaling the bottom field may have to start several
1789                  * source lines below the top field. Unfortunately ACCUI
1790                  * registers will only hold the fractional part of the offset
1791                  * so the integer part must be added to the base address of the
1792                  * bottom field.
1793                  */
1794                 if (!oi->height || oi->height == oi->out_height)
1795                         field_offset = 0;
1796                 else
1797                         field_offset = oi->height / oi->out_height / 2;
1798         }
1799
1800         /* Fields are independent but interleaved in memory. */
1801         if (fieldmode)
1802                 field_offset = 1;
1803
1804         if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1805                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1806                                 oi->screen_width, oi->width, frame_height,
1807                                 oi->color_mode, fieldmode, field_offset,
1808                                 &offset0, &offset1, &row_inc, &pix_inc);
1809         else
1810                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1811                                 oi->screen_width, oi->width, frame_height,
1812                                 oi->color_mode, fieldmode, field_offset,
1813                                 &offset0, &offset1, &row_inc, &pix_inc);
1814
1815         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1816                         offset0, offset1, row_inc, pix_inc);
1817
1818         dispc_ovl_set_color_mode(plane, oi->color_mode);
1819
1820         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1821         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1822
1823         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1824                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1825                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1826         }
1827
1828
1829         dispc_ovl_set_row_inc(plane, row_inc);
1830         dispc_ovl_set_pix_inc(plane, pix_inc);
1831
1832         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1833                         oi->height, oi->out_width, oi->out_height);
1834
1835         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1836
1837         dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1838
1839         if (plane != OMAP_DSS_GFX) {
1840                 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1841                                    oi->out_width, oi->out_height,
1842                                    ilace, five_taps, fieldmode,
1843                                    oi->color_mode, oi->rotation);
1844                 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1845                 dispc_ovl_set_vid_color_conv(plane, cconv);
1846         }
1847
1848         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1849                         oi->color_mode);
1850
1851         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1852         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1853
1854         dispc_ovl_set_channel_out(plane, channel);
1855
1856         dispc_ovl_enable_replication(plane, replication);
1857         dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1858
1859         return 0;
1860 }
1861
1862 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1863 {
1864         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1865
1866         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1867
1868         return 0;
1869 }
1870
1871 static void dispc_disable_isr(void *data, u32 mask)
1872 {
1873         struct completion *compl = data;
1874         complete(compl);
1875 }
1876
1877 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1878 {
1879         if (channel == OMAP_DSS_CHANNEL_LCD2)
1880                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1881         else
1882                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1883 }
1884
1885 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1886 {
1887         struct completion frame_done_completion;
1888         bool is_on;
1889         int r;
1890         u32 irq;
1891
1892         /* When we disable LCD output, we need to wait until frame is done.
1893          * Otherwise the DSS is still working, and turning off the clocks
1894          * prevents DSS from going to OFF mode */
1895         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1896                         REG_GET(DISPC_CONTROL2, 0, 0) :
1897                         REG_GET(DISPC_CONTROL, 0, 0);
1898
1899         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1900                         DISPC_IRQ_FRAMEDONE;
1901
1902         if (!enable && is_on) {
1903                 init_completion(&frame_done_completion);
1904
1905                 r = omap_dispc_register_isr(dispc_disable_isr,
1906                                 &frame_done_completion, irq);
1907
1908                 if (r)
1909                         DSSERR("failed to register FRAMEDONE isr\n");
1910         }
1911
1912         _enable_lcd_out(channel, enable);
1913
1914         if (!enable && is_on) {
1915                 if (!wait_for_completion_timeout(&frame_done_completion,
1916                                         msecs_to_jiffies(100)))
1917                         DSSERR("timeout waiting for FRAME DONE\n");
1918
1919                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1920                                 &frame_done_completion, irq);
1921
1922                 if (r)
1923                         DSSERR("failed to unregister FRAMEDONE isr\n");
1924         }
1925 }
1926
1927 static void _enable_digit_out(bool enable)
1928 {
1929         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1930 }
1931
1932 static void dispc_mgr_enable_digit_out(bool enable)
1933 {
1934         struct completion frame_done_completion;
1935         enum dss_hdmi_venc_clk_source_select src;
1936         int r, i;
1937         u32 irq_mask;
1938         int num_irqs;
1939
1940         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1941                 return;
1942
1943         src = dss_get_hdmi_venc_clk_source();
1944
1945         if (enable) {
1946                 unsigned long flags;
1947                 /* When we enable digit output, we'll get an extra digit
1948                  * sync lost interrupt, that we need to ignore */
1949                 spin_lock_irqsave(&dispc.irq_lock, flags);
1950                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1951                 _omap_dispc_set_irqs();
1952                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1953         }
1954
1955         /* When we disable digit output, we need to wait until fields are done.
1956          * Otherwise the DSS is still working, and turning off the clocks
1957          * prevents DSS from going to OFF mode. And when enabling, we need to
1958          * wait for the extra sync losts */
1959         init_completion(&frame_done_completion);
1960
1961         if (src == DSS_HDMI_M_PCLK && enable == false) {
1962                 irq_mask = DISPC_IRQ_FRAMEDONETV;
1963                 num_irqs = 1;
1964         } else {
1965                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
1966                 /* XXX I understand from TRM that we should only wait for the
1967                  * current field to complete. But it seems we have to wait for
1968                  * both fields */
1969                 num_irqs = 2;
1970         }
1971
1972         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1973                         irq_mask);
1974         if (r)
1975                 DSSERR("failed to register %x isr\n", irq_mask);
1976
1977         _enable_digit_out(enable);
1978
1979         for (i = 0; i < num_irqs; ++i) {
1980                 if (!wait_for_completion_timeout(&frame_done_completion,
1981                                         msecs_to_jiffies(100)))
1982                         DSSERR("timeout waiting for digit out to %s\n",
1983                                         enable ? "start" : "stop");
1984         }
1985
1986         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
1987                         irq_mask);
1988         if (r)
1989                 DSSERR("failed to unregister %x isr\n", irq_mask);
1990
1991         if (enable) {
1992                 unsigned long flags;
1993                 spin_lock_irqsave(&dispc.irq_lock, flags);
1994                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
1995                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1996                 _omap_dispc_set_irqs();
1997                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1998         }
1999 }
2000
2001 bool dispc_mgr_is_enabled(enum omap_channel channel)
2002 {
2003         if (channel == OMAP_DSS_CHANNEL_LCD)
2004                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2005         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2006                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2007         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2008                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2009         else
2010                 BUG();
2011 }
2012
2013 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2014 {
2015         if (dispc_mgr_is_lcd(channel))
2016                 dispc_mgr_enable_lcd_out(channel, enable);
2017         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2018                 dispc_mgr_enable_digit_out(enable);
2019         else
2020                 BUG();
2021 }
2022
2023 void dispc_lcd_enable_signal_polarity(bool act_high)
2024 {
2025         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2026                 return;
2027
2028         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2029 }
2030
2031 void dispc_lcd_enable_signal(bool enable)
2032 {
2033         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2034                 return;
2035
2036         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2037 }
2038
2039 void dispc_pck_free_enable(bool enable)
2040 {
2041         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2042                 return;
2043
2044         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2045 }
2046
2047 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2048 {
2049         if (channel == OMAP_DSS_CHANNEL_LCD2)
2050                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2051         else
2052                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2053 }
2054
2055
2056 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2057                 enum omap_lcd_display_type type)
2058 {
2059         int mode;
2060
2061         switch (type) {
2062         case OMAP_DSS_LCD_DISPLAY_STN:
2063                 mode = 0;
2064                 break;
2065
2066         case OMAP_DSS_LCD_DISPLAY_TFT:
2067                 mode = 1;
2068                 break;
2069
2070         default:
2071                 BUG();
2072                 return;
2073         }
2074
2075         if (channel == OMAP_DSS_CHANNEL_LCD2)
2076                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2077         else
2078                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2079 }
2080
2081 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2082 {
2083         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2084 }
2085
2086
2087 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2088 {
2089         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2090 }
2091
2092 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2093 {
2094         u32 l;
2095
2096         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2097                 channel != OMAP_DSS_CHANNEL_LCD &&
2098                 channel != OMAP_DSS_CHANNEL_LCD2);
2099
2100         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2101
2102         return l;
2103 }
2104
2105 void dispc_mgr_set_trans_key(enum omap_channel ch,
2106                 enum omap_dss_trans_key_type type,
2107                 u32 trans_key)
2108 {
2109         if (ch == OMAP_DSS_CHANNEL_LCD)
2110                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2111         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2112                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2113         else /* OMAP_DSS_CHANNEL_LCD2 */
2114                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2115
2116         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2117 }
2118
2119 void dispc_mgr_get_trans_key(enum omap_channel ch,
2120                 enum omap_dss_trans_key_type *type,
2121                 u32 *trans_key)
2122 {
2123         if (type) {
2124                 if (ch == OMAP_DSS_CHANNEL_LCD)
2125                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2126                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2127                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2128                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2129                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2130                 else
2131                         BUG();
2132         }
2133
2134         if (trans_key)
2135                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2136 }
2137
2138 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2139 {
2140         if (ch == OMAP_DSS_CHANNEL_LCD)
2141                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2142         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2143                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2144         else /* OMAP_DSS_CHANNEL_LCD2 */
2145                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2146 }
2147 void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable)
2148 {
2149         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2150                 return;
2151
2152         if (ch == OMAP_DSS_CHANNEL_LCD)
2153                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2154         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2155                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2156         else /* OMAP_DSS_CHANNEL_LCD2 */
2157                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2158 }
2159 bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch)
2160 {
2161         bool enabled;
2162
2163         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2164                 return false;
2165
2166         if (ch == OMAP_DSS_CHANNEL_LCD)
2167                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2168         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2169                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2170         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2171                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2172         else
2173                 BUG();
2174
2175         return enabled;
2176 }
2177
2178
2179 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2180 {
2181         bool enabled;
2182
2183         if (ch == OMAP_DSS_CHANNEL_LCD)
2184                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2185         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2186                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2187         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2188                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2189         else
2190                 BUG();
2191
2192         return enabled;
2193 }
2194
2195
2196 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2197 {
2198         int code;
2199
2200         switch (data_lines) {
2201         case 12:
2202                 code = 0;
2203                 break;
2204         case 16:
2205                 code = 1;
2206                 break;
2207         case 18:
2208                 code = 2;
2209                 break;
2210         case 24:
2211                 code = 3;
2212                 break;
2213         default:
2214                 BUG();
2215                 return;
2216         }
2217
2218         if (channel == OMAP_DSS_CHANNEL_LCD2)
2219                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2220         else
2221                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2222 }
2223
2224 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2225 {
2226         u32 l;
2227         int gpout0, gpout1;
2228
2229         switch (mode) {
2230         case DSS_IO_PAD_MODE_RESET:
2231                 gpout0 = 0;
2232                 gpout1 = 0;
2233                 break;
2234         case DSS_IO_PAD_MODE_RFBI:
2235                 gpout0 = 1;
2236                 gpout1 = 0;
2237                 break;
2238         case DSS_IO_PAD_MODE_BYPASS:
2239                 gpout0 = 1;
2240                 gpout1 = 1;
2241                 break;
2242         default:
2243                 BUG();
2244                 return;
2245         }
2246
2247         l = dispc_read_reg(DISPC_CONTROL);
2248         l = FLD_MOD(l, gpout0, 15, 15);
2249         l = FLD_MOD(l, gpout1, 16, 16);
2250         dispc_write_reg(DISPC_CONTROL, l);
2251 }
2252
2253 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2254 {
2255         if (channel == OMAP_DSS_CHANNEL_LCD2)
2256                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2257         else
2258                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2259 }
2260
2261 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2262                 int vsw, int vfp, int vbp)
2263 {
2264         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2265                 if (hsw < 1 || hsw > 64 ||
2266                                 hfp < 1 || hfp > 256 ||
2267                                 hbp < 1 || hbp > 256 ||
2268                                 vsw < 1 || vsw > 64 ||
2269                                 vfp < 0 || vfp > 255 ||
2270                                 vbp < 0 || vbp > 255)
2271                         return false;
2272         } else {
2273                 if (hsw < 1 || hsw > 256 ||
2274                                 hfp < 1 || hfp > 4096 ||
2275                                 hbp < 1 || hbp > 4096 ||
2276                                 vsw < 1 || vsw > 256 ||
2277                                 vfp < 0 || vfp > 4095 ||
2278                                 vbp < 0 || vbp > 4095)
2279                         return false;
2280         }
2281
2282         return true;
2283 }
2284
2285 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2286 {
2287         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2288                         timings->hbp, timings->vsw,
2289                         timings->vfp, timings->vbp);
2290 }
2291
2292 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2293                 int hfp, int hbp, int vsw, int vfp, int vbp)
2294 {
2295         u32 timing_h, timing_v;
2296
2297         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2298                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2299                         FLD_VAL(hbp-1, 27, 20);
2300
2301                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2302                         FLD_VAL(vbp, 27, 20);
2303         } else {
2304                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2305                         FLD_VAL(hbp-1, 31, 20);
2306
2307                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2308                         FLD_VAL(vbp, 31, 20);
2309         }
2310
2311         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2312         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2313 }
2314
2315 /* change name to mode? */
2316 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2317                 struct omap_video_timings *timings)
2318 {
2319         unsigned xtot, ytot;
2320         unsigned long ht, vt;
2321
2322         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2323                                 timings->hbp, timings->vsw,
2324                                 timings->vfp, timings->vbp))
2325                 BUG();
2326
2327         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2328                         timings->hbp, timings->vsw, timings->vfp,
2329                         timings->vbp);
2330
2331         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2332
2333         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2334         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2335
2336         ht = (timings->pixel_clock * 1000) / xtot;
2337         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2338
2339         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2340                         timings->y_res);
2341         DSSDBG("pck %u\n", timings->pixel_clock);
2342         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2343                         timings->hsw, timings->hfp, timings->hbp,
2344                         timings->vsw, timings->vfp, timings->vbp);
2345
2346         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2347 }
2348
2349 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2350                 u16 pck_div)
2351 {
2352         BUG_ON(lck_div < 1);
2353         BUG_ON(pck_div < 1);
2354
2355         dispc_write_reg(DISPC_DIVISORo(channel),
2356                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2357 }
2358
2359 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2360                 int *pck_div)
2361 {
2362         u32 l;
2363         l = dispc_read_reg(DISPC_DIVISORo(channel));
2364         *lck_div = FLD_GET(l, 23, 16);
2365         *pck_div = FLD_GET(l, 7, 0);
2366 }
2367
2368 unsigned long dispc_fclk_rate(void)
2369 {
2370         struct platform_device *dsidev;
2371         unsigned long r = 0;
2372
2373         switch (dss_get_dispc_clk_source()) {
2374         case OMAP_DSS_CLK_SRC_FCK:
2375                 r = clk_get_rate(dispc.dss_clk);
2376                 break;
2377         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2378                 dsidev = dsi_get_dsidev_from_id(0);
2379                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2380                 break;
2381         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2382                 dsidev = dsi_get_dsidev_from_id(1);
2383                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2384                 break;
2385         default:
2386                 BUG();
2387         }
2388
2389         return r;
2390 }
2391
2392 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2393 {
2394         struct platform_device *dsidev;
2395         int lcd;
2396         unsigned long r;
2397         u32 l;
2398
2399         l = dispc_read_reg(DISPC_DIVISORo(channel));
2400
2401         lcd = FLD_GET(l, 23, 16);
2402
2403         switch (dss_get_lcd_clk_source(channel)) {
2404         case OMAP_DSS_CLK_SRC_FCK:
2405                 r = clk_get_rate(dispc.dss_clk);
2406                 break;
2407         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2408                 dsidev = dsi_get_dsidev_from_id(0);
2409                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2410                 break;
2411         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2412                 dsidev = dsi_get_dsidev_from_id(1);
2413                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2414                 break;
2415         default:
2416                 BUG();
2417         }
2418
2419         return r / lcd;
2420 }
2421
2422 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2423 {
2424         unsigned long r;
2425
2426         if (dispc_mgr_is_lcd(channel)) {
2427                 int pcd;
2428                 u32 l;
2429
2430                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2431
2432                 pcd = FLD_GET(l, 7, 0);
2433
2434                 r = dispc_mgr_lclk_rate(channel);
2435
2436                 return r / pcd;
2437         } else {
2438                 struct omap_dss_device *dssdev =
2439                         dispc_mgr_get_device(channel);
2440
2441                 switch (dssdev->type) {
2442                 case OMAP_DISPLAY_TYPE_VENC:
2443                         return venc_get_pixel_clock();
2444                 case OMAP_DISPLAY_TYPE_HDMI:
2445                         return hdmi_get_pixel_clock();
2446                 default:
2447                         BUG();
2448                 }
2449         }
2450 }
2451
2452 void dispc_dump_clocks(struct seq_file *s)
2453 {
2454         int lcd, pcd;
2455         u32 l;
2456         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2457         enum omap_dss_clk_source lcd_clk_src;
2458
2459         if (dispc_runtime_get())
2460                 return;
2461
2462         seq_printf(s, "- DISPC -\n");
2463
2464         seq_printf(s, "dispc fclk source = %s (%s)\n",
2465                         dss_get_generic_clk_source_name(dispc_clk_src),
2466                         dss_feat_get_clk_source_name(dispc_clk_src));
2467
2468         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2469
2470         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2471                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2472                 l = dispc_read_reg(DISPC_DIVISOR);
2473                 lcd = FLD_GET(l, 23, 16);
2474
2475                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2476                                 (dispc_fclk_rate()/lcd), lcd);
2477         }
2478         seq_printf(s, "- LCD1 -\n");
2479
2480         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2481
2482         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2483                 dss_get_generic_clk_source_name(lcd_clk_src),
2484                 dss_feat_get_clk_source_name(lcd_clk_src));
2485
2486         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2487
2488         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2489                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2490         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2491                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2492         if (dss_has_feature(FEAT_MGR_LCD2)) {
2493                 seq_printf(s, "- LCD2 -\n");
2494
2495                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2496
2497                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2498                         dss_get_generic_clk_source_name(lcd_clk_src),
2499                         dss_feat_get_clk_source_name(lcd_clk_src));
2500
2501                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2502
2503                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2504                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2505                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2506                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2507         }
2508
2509         dispc_runtime_put();
2510 }
2511
2512 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2513 void dispc_dump_irqs(struct seq_file *s)
2514 {
2515         unsigned long flags;
2516         struct dispc_irq_stats stats;
2517
2518         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2519
2520         stats = dispc.irq_stats;
2521         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2522         dispc.irq_stats.last_reset = jiffies;
2523
2524         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2525
2526         seq_printf(s, "period %u ms\n",
2527                         jiffies_to_msecs(jiffies - stats.last_reset));
2528
2529         seq_printf(s, "irqs %d\n", stats.irq_count);
2530 #define PIS(x) \
2531         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2532
2533         PIS(FRAMEDONE);
2534         PIS(VSYNC);
2535         PIS(EVSYNC_EVEN);
2536         PIS(EVSYNC_ODD);
2537         PIS(ACBIAS_COUNT_STAT);
2538         PIS(PROG_LINE_NUM);
2539         PIS(GFX_FIFO_UNDERFLOW);
2540         PIS(GFX_END_WIN);
2541         PIS(PAL_GAMMA_MASK);
2542         PIS(OCP_ERR);
2543         PIS(VID1_FIFO_UNDERFLOW);
2544         PIS(VID1_END_WIN);
2545         PIS(VID2_FIFO_UNDERFLOW);
2546         PIS(VID2_END_WIN);
2547         PIS(SYNC_LOST);
2548         PIS(SYNC_LOST_DIGIT);
2549         PIS(WAKEUP);
2550         if (dss_has_feature(FEAT_MGR_LCD2)) {
2551                 PIS(FRAMEDONE2);
2552                 PIS(VSYNC2);
2553                 PIS(ACBIAS_COUNT_STAT2);
2554                 PIS(SYNC_LOST2);
2555         }
2556 #undef PIS
2557 }
2558 #endif
2559
2560 void dispc_dump_regs(struct seq_file *s)
2561 {
2562         int i, j;
2563         const char *mgr_names[] = {
2564                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2565                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2566                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2567         };
2568         const char *ovl_names[] = {
2569                 [OMAP_DSS_GFX]          = "GFX",
2570                 [OMAP_DSS_VIDEO1]       = "VID1",
2571                 [OMAP_DSS_VIDEO2]       = "VID2",
2572         };
2573         const char **p_names;
2574
2575 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2576
2577         if (dispc_runtime_get())
2578                 return;
2579
2580         /* DISPC common registers */
2581         DUMPREG(DISPC_REVISION);
2582         DUMPREG(DISPC_SYSCONFIG);
2583         DUMPREG(DISPC_SYSSTATUS);
2584         DUMPREG(DISPC_IRQSTATUS);
2585         DUMPREG(DISPC_IRQENABLE);
2586         DUMPREG(DISPC_CONTROL);
2587         DUMPREG(DISPC_CONFIG);
2588         DUMPREG(DISPC_CAPABLE);
2589         DUMPREG(DISPC_LINE_STATUS);
2590         DUMPREG(DISPC_LINE_NUMBER);
2591         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2592                 DUMPREG(DISPC_GLOBAL_ALPHA);
2593         if (dss_has_feature(FEAT_MGR_LCD2)) {
2594                 DUMPREG(DISPC_CONTROL2);
2595                 DUMPREG(DISPC_CONFIG2);
2596         }
2597
2598 #undef DUMPREG
2599
2600 #define DISPC_REG(i, name) name(i)
2601 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2602         48 - strlen(#r) - strlen(p_names[i]), " ", \
2603         dispc_read_reg(DISPC_REG(i, r)))
2604
2605         p_names = mgr_names;
2606
2607         /* DISPC channel specific registers */
2608         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2609                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2610                 DUMPREG(i, DISPC_TRANS_COLOR);
2611                 DUMPREG(i, DISPC_SIZE_MGR);
2612
2613                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2614                         continue;
2615
2616                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2617                 DUMPREG(i, DISPC_TRANS_COLOR);
2618                 DUMPREG(i, DISPC_TIMING_H);
2619                 DUMPREG(i, DISPC_TIMING_V);
2620                 DUMPREG(i, DISPC_POL_FREQ);
2621                 DUMPREG(i, DISPC_DIVISORo);
2622                 DUMPREG(i, DISPC_SIZE_MGR);
2623
2624                 DUMPREG(i, DISPC_DATA_CYCLE1);
2625                 DUMPREG(i, DISPC_DATA_CYCLE2);
2626                 DUMPREG(i, DISPC_DATA_CYCLE3);
2627
2628                 if (dss_has_feature(FEAT_CPR)) {
2629                         DUMPREG(i, DISPC_CPR_COEF_R);
2630                         DUMPREG(i, DISPC_CPR_COEF_G);
2631                         DUMPREG(i, DISPC_CPR_COEF_B);
2632                 }
2633         }
2634
2635         p_names = ovl_names;
2636
2637         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2638                 DUMPREG(i, DISPC_OVL_BA0);
2639                 DUMPREG(i, DISPC_OVL_BA1);
2640                 DUMPREG(i, DISPC_OVL_POSITION);
2641                 DUMPREG(i, DISPC_OVL_SIZE);
2642                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2643                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2644                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2645                 DUMPREG(i, DISPC_OVL_ROW_INC);
2646                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2647                 if (dss_has_feature(FEAT_PRELOAD))
2648                         DUMPREG(i, DISPC_OVL_PRELOAD);
2649
2650                 if (i == OMAP_DSS_GFX) {
2651                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2652                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2653                         continue;
2654                 }
2655
2656                 DUMPREG(i, DISPC_OVL_FIR);
2657                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2658                 DUMPREG(i, DISPC_OVL_ACCU0);
2659                 DUMPREG(i, DISPC_OVL_ACCU1);
2660                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2661                         DUMPREG(i, DISPC_OVL_BA0_UV);
2662                         DUMPREG(i, DISPC_OVL_BA1_UV);
2663                         DUMPREG(i, DISPC_OVL_FIR2);
2664                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2665                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2666                 }
2667                 if (dss_has_feature(FEAT_ATTR2))
2668                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2669                 if (dss_has_feature(FEAT_PRELOAD))
2670                         DUMPREG(i, DISPC_OVL_PRELOAD);
2671         }
2672
2673 #undef DISPC_REG
2674 #undef DUMPREG
2675
2676 #define DISPC_REG(plane, name, i) name(plane, i)
2677 #define DUMPREG(plane, name, i) \
2678         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2679         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2680         dispc_read_reg(DISPC_REG(plane, name, i)))
2681
2682         /* Video pipeline coefficient registers */
2683
2684         /* start from OMAP_DSS_VIDEO1 */
2685         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2686                 for (j = 0; j < 8; j++)
2687                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2688
2689                 for (j = 0; j < 8; j++)
2690                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2691
2692                 for (j = 0; j < 5; j++)
2693                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2694
2695                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2696                         for (j = 0; j < 8; j++)
2697                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2698                 }
2699
2700                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2701                         for (j = 0; j < 8; j++)
2702                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2703
2704                         for (j = 0; j < 8; j++)
2705                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2706
2707                         for (j = 0; j < 8; j++)
2708                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2709                 }
2710         }
2711
2712         dispc_runtime_put();
2713
2714 #undef DISPC_REG
2715 #undef DUMPREG
2716 }
2717
2718 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2719                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2720                 u8 acb)
2721 {
2722         u32 l = 0;
2723
2724         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2725                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2726
2727         l |= FLD_VAL(onoff, 17, 17);
2728         l |= FLD_VAL(rf, 16, 16);
2729         l |= FLD_VAL(ieo, 15, 15);
2730         l |= FLD_VAL(ipc, 14, 14);
2731         l |= FLD_VAL(ihs, 13, 13);
2732         l |= FLD_VAL(ivs, 12, 12);
2733         l |= FLD_VAL(acbi, 11, 8);
2734         l |= FLD_VAL(acb, 7, 0);
2735
2736         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2737 }
2738
2739 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2740                 enum omap_panel_config config, u8 acbi, u8 acb)
2741 {
2742         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2743                         (config & OMAP_DSS_LCD_RF) != 0,
2744                         (config & OMAP_DSS_LCD_IEO) != 0,
2745                         (config & OMAP_DSS_LCD_IPC) != 0,
2746                         (config & OMAP_DSS_LCD_IHS) != 0,
2747                         (config & OMAP_DSS_LCD_IVS) != 0,
2748                         acbi, acb);
2749 }
2750
2751 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2752 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2753                 struct dispc_clock_info *cinfo)
2754 {
2755         u16 pcd_min, pcd_max;
2756         unsigned long best_pck;
2757         u16 best_ld, cur_ld;
2758         u16 best_pd, cur_pd;
2759
2760         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2761         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2762
2763         if (!is_tft)
2764                 pcd_min = 3;
2765
2766         best_pck = 0;
2767         best_ld = 0;
2768         best_pd = 0;
2769
2770         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2771                 unsigned long lck = fck / cur_ld;
2772
2773                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2774                         unsigned long pck = lck / cur_pd;
2775                         long old_delta = abs(best_pck - req_pck);
2776                         long new_delta = abs(pck - req_pck);
2777
2778                         if (best_pck == 0 || new_delta < old_delta) {
2779                                 best_pck = pck;
2780                                 best_ld = cur_ld;
2781                                 best_pd = cur_pd;
2782
2783                                 if (pck == req_pck)
2784                                         goto found;
2785                         }
2786
2787                         if (pck < req_pck)
2788                                 break;
2789                 }
2790
2791                 if (lck / pcd_min < req_pck)
2792                         break;
2793         }
2794
2795 found:
2796         cinfo->lck_div = best_ld;
2797         cinfo->pck_div = best_pd;
2798         cinfo->lck = fck / cinfo->lck_div;
2799         cinfo->pck = cinfo->lck / cinfo->pck_div;
2800 }
2801
2802 /* calculate clock rates using dividers in cinfo */
2803 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2804                 struct dispc_clock_info *cinfo)
2805 {
2806         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2807                 return -EINVAL;
2808         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2809                 return -EINVAL;
2810
2811         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2812         cinfo->pck = cinfo->lck / cinfo->pck_div;
2813
2814         return 0;
2815 }
2816
2817 int dispc_mgr_set_clock_div(enum omap_channel channel,
2818                 struct dispc_clock_info *cinfo)
2819 {
2820         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2821         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2822
2823         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2824
2825         return 0;
2826 }
2827
2828 int dispc_mgr_get_clock_div(enum omap_channel channel,
2829                 struct dispc_clock_info *cinfo)
2830 {
2831         unsigned long fck;
2832
2833         fck = dispc_fclk_rate();
2834
2835         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2836         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2837
2838         cinfo->lck = fck / cinfo->lck_div;
2839         cinfo->pck = cinfo->lck / cinfo->pck_div;
2840
2841         return 0;
2842 }
2843
2844 /* dispc.irq_lock has to be locked by the caller */
2845 static void _omap_dispc_set_irqs(void)
2846 {
2847         u32 mask;
2848         u32 old_mask;
2849         int i;
2850         struct omap_dispc_isr_data *isr_data;
2851
2852         mask = dispc.irq_error_mask;
2853
2854         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2855                 isr_data = &dispc.registered_isr[i];
2856
2857                 if (isr_data->isr == NULL)
2858                         continue;
2859
2860                 mask |= isr_data->mask;
2861         }
2862
2863         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2864         /* clear the irqstatus for newly enabled irqs */
2865         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2866
2867         dispc_write_reg(DISPC_IRQENABLE, mask);
2868 }
2869
2870 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2871 {
2872         int i;
2873         int ret;
2874         unsigned long flags;
2875         struct omap_dispc_isr_data *isr_data;
2876
2877         if (isr == NULL)
2878                 return -EINVAL;
2879
2880         spin_lock_irqsave(&dispc.irq_lock, flags);
2881
2882         /* check for duplicate entry */
2883         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2884                 isr_data = &dispc.registered_isr[i];
2885                 if (isr_data->isr == isr && isr_data->arg == arg &&
2886                                 isr_data->mask == mask) {
2887                         ret = -EINVAL;
2888                         goto err;
2889                 }
2890         }
2891
2892         isr_data = NULL;
2893         ret = -EBUSY;
2894
2895         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2896                 isr_data = &dispc.registered_isr[i];
2897
2898                 if (isr_data->isr != NULL)
2899                         continue;
2900
2901                 isr_data->isr = isr;
2902                 isr_data->arg = arg;
2903                 isr_data->mask = mask;
2904                 ret = 0;
2905
2906                 break;
2907         }
2908
2909         if (ret)
2910                 goto err;
2911
2912         _omap_dispc_set_irqs();
2913
2914         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2915
2916         return 0;
2917 err:
2918         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2919
2920         return ret;
2921 }
2922 EXPORT_SYMBOL(omap_dispc_register_isr);
2923
2924 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2925 {
2926         int i;
2927         unsigned long flags;
2928         int ret = -EINVAL;
2929         struct omap_dispc_isr_data *isr_data;
2930
2931         spin_lock_irqsave(&dispc.irq_lock, flags);
2932
2933         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2934                 isr_data = &dispc.registered_isr[i];
2935                 if (isr_data->isr != isr || isr_data->arg != arg ||
2936                                 isr_data->mask != mask)
2937                         continue;
2938
2939                 /* found the correct isr */
2940
2941                 isr_data->isr = NULL;
2942                 isr_data->arg = NULL;
2943                 isr_data->mask = 0;
2944
2945                 ret = 0;
2946                 break;
2947         }
2948
2949         if (ret == 0)
2950                 _omap_dispc_set_irqs();
2951
2952         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2953
2954         return ret;
2955 }
2956 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2957
2958 #ifdef DEBUG
2959 static void print_irq_status(u32 status)
2960 {
2961         if ((status & dispc.irq_error_mask) == 0)
2962                 return;
2963
2964         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2965
2966 #define PIS(x) \
2967         if (status & DISPC_IRQ_##x) \
2968                 printk(#x " ");
2969         PIS(GFX_FIFO_UNDERFLOW);
2970         PIS(OCP_ERR);
2971         PIS(VID1_FIFO_UNDERFLOW);
2972         PIS(VID2_FIFO_UNDERFLOW);
2973         PIS(SYNC_LOST);
2974         PIS(SYNC_LOST_DIGIT);
2975         if (dss_has_feature(FEAT_MGR_LCD2))
2976                 PIS(SYNC_LOST2);
2977 #undef PIS
2978
2979         printk("\n");
2980 }
2981 #endif
2982
2983 /* Called from dss.c. Note that we don't touch clocks here,
2984  * but we presume they are on because we got an IRQ. However,
2985  * an irq handler may turn the clocks off, so we may not have
2986  * clock later in the function. */
2987 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2988 {
2989         int i;
2990         u32 irqstatus, irqenable;
2991         u32 handledirqs = 0;
2992         u32 unhandled_errors;
2993         struct omap_dispc_isr_data *isr_data;
2994         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2995
2996         spin_lock(&dispc.irq_lock);
2997
2998         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2999         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3000
3001         /* IRQ is not for us */
3002         if (!(irqstatus & irqenable)) {
3003                 spin_unlock(&dispc.irq_lock);
3004                 return IRQ_NONE;
3005         }
3006
3007 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3008         spin_lock(&dispc.irq_stats_lock);
3009         dispc.irq_stats.irq_count++;
3010         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3011         spin_unlock(&dispc.irq_stats_lock);
3012 #endif
3013
3014 #ifdef DEBUG
3015         if (dss_debug)
3016                 print_irq_status(irqstatus);
3017 #endif
3018         /* Ack the interrupt. Do it here before clocks are possibly turned
3019          * off */
3020         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3021         /* flush posted write */
3022         dispc_read_reg(DISPC_IRQSTATUS);
3023
3024         /* make a copy and unlock, so that isrs can unregister
3025          * themselves */
3026         memcpy(registered_isr, dispc.registered_isr,
3027                         sizeof(registered_isr));
3028
3029         spin_unlock(&dispc.irq_lock);
3030
3031         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3032                 isr_data = &registered_isr[i];
3033
3034                 if (!isr_data->isr)
3035                         continue;
3036
3037                 if (isr_data->mask & irqstatus) {
3038                         isr_data->isr(isr_data->arg, irqstatus);
3039                         handledirqs |= isr_data->mask;
3040                 }
3041         }
3042
3043         spin_lock(&dispc.irq_lock);
3044
3045         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3046
3047         if (unhandled_errors) {
3048                 dispc.error_irqs |= unhandled_errors;
3049
3050                 dispc.irq_error_mask &= ~unhandled_errors;
3051                 _omap_dispc_set_irqs();
3052
3053                 schedule_work(&dispc.error_work);
3054         }
3055
3056         spin_unlock(&dispc.irq_lock);
3057
3058         return IRQ_HANDLED;
3059 }
3060
3061 static void dispc_error_worker(struct work_struct *work)
3062 {
3063         int i;
3064         u32 errors;
3065         unsigned long flags;
3066         static const unsigned fifo_underflow_bits[] = {
3067                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3068                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3069                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3070         };
3071
3072         static const unsigned sync_lost_bits[] = {
3073                 DISPC_IRQ_SYNC_LOST,
3074                 DISPC_IRQ_SYNC_LOST_DIGIT,
3075                 DISPC_IRQ_SYNC_LOST2,
3076         };
3077
3078         spin_lock_irqsave(&dispc.irq_lock, flags);
3079         errors = dispc.error_irqs;
3080         dispc.error_irqs = 0;
3081         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3082
3083         dispc_runtime_get();
3084
3085         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3086                 struct omap_overlay *ovl;
3087                 unsigned bit;
3088
3089                 ovl = omap_dss_get_overlay(i);
3090                 bit = fifo_underflow_bits[i];
3091
3092                 if (bit & errors) {
3093                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3094                                         ovl->name);
3095                         dispc_ovl_enable(ovl->id, false);
3096                         dispc_mgr_go(ovl->manager->id);
3097                         mdelay(50);
3098                 }
3099         }
3100
3101         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3102                 struct omap_overlay_manager *mgr;
3103                 unsigned bit;
3104
3105                 mgr = omap_dss_get_overlay_manager(i);
3106                 bit = sync_lost_bits[i];
3107
3108                 if (bit & errors) {
3109                         struct omap_dss_device *dssdev = mgr->device;
3110                         bool enable;
3111
3112                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3113                                         "with video overlays disabled\n",
3114                                         mgr->name);
3115
3116                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3117                         dssdev->driver->disable(dssdev);
3118
3119                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3120                                 struct omap_overlay *ovl;
3121                                 ovl = omap_dss_get_overlay(i);
3122
3123                                 if (ovl->id != OMAP_DSS_GFX &&
3124                                                 ovl->manager == mgr)
3125                                         dispc_ovl_enable(ovl->id, false);
3126                         }
3127
3128                         dispc_mgr_go(mgr->id);
3129                         mdelay(50);
3130
3131                         if (enable)
3132                                 dssdev->driver->enable(dssdev);
3133                 }
3134         }
3135
3136         if (errors & DISPC_IRQ_OCP_ERR) {
3137                 DSSERR("OCP_ERR\n");
3138                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3139                         struct omap_overlay_manager *mgr;
3140                         mgr = omap_dss_get_overlay_manager(i);
3141                         mgr->device->driver->disable(mgr->device);
3142                 }
3143         }
3144
3145         spin_lock_irqsave(&dispc.irq_lock, flags);
3146         dispc.irq_error_mask |= errors;
3147         _omap_dispc_set_irqs();
3148         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3149
3150         dispc_runtime_put();
3151 }
3152
3153 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3154 {
3155         void dispc_irq_wait_handler(void *data, u32 mask)
3156         {
3157                 complete((struct completion *)data);
3158         }
3159
3160         int r;
3161         DECLARE_COMPLETION_ONSTACK(completion);
3162
3163         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3164                         irqmask);
3165
3166         if (r)
3167                 return r;
3168
3169         timeout = wait_for_completion_timeout(&completion, timeout);
3170
3171         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3172
3173         if (timeout == 0)
3174                 return -ETIMEDOUT;
3175
3176         if (timeout == -ERESTARTSYS)
3177                 return -ERESTARTSYS;
3178
3179         return 0;
3180 }
3181
3182 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3183                 unsigned long timeout)
3184 {
3185         void dispc_irq_wait_handler(void *data, u32 mask)
3186         {
3187                 complete((struct completion *)data);
3188         }
3189
3190         int r;
3191         DECLARE_COMPLETION_ONSTACK(completion);
3192
3193         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3194                         irqmask);
3195
3196         if (r)
3197                 return r;
3198
3199         timeout = wait_for_completion_interruptible_timeout(&completion,
3200                         timeout);
3201
3202         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3203
3204         if (timeout == 0)
3205                 return -ETIMEDOUT;
3206
3207         if (timeout == -ERESTARTSYS)
3208                 return -ERESTARTSYS;
3209
3210         return 0;
3211 }
3212
3213 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3214 void dispc_fake_vsync_irq(void)
3215 {
3216         u32 irqstatus = DISPC_IRQ_VSYNC;
3217         int i;
3218
3219         WARN_ON(!in_interrupt());
3220
3221         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3222                 struct omap_dispc_isr_data *isr_data;
3223                 isr_data = &dispc.registered_isr[i];
3224
3225                 if (!isr_data->isr)
3226                         continue;
3227
3228                 if (isr_data->mask & irqstatus)
3229                         isr_data->isr(isr_data->arg, irqstatus);
3230         }
3231 }
3232 #endif
3233
3234 static void _omap_dispc_initialize_irq(void)
3235 {
3236         unsigned long flags;
3237
3238         spin_lock_irqsave(&dispc.irq_lock, flags);
3239
3240         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3241
3242         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3243         if (dss_has_feature(FEAT_MGR_LCD2))
3244                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3245
3246         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3247          * so clear it */
3248         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3249
3250         _omap_dispc_set_irqs();
3251
3252         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3253 }
3254
3255 void dispc_enable_sidle(void)
3256 {
3257         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3258 }
3259
3260 void dispc_disable_sidle(void)
3261 {
3262         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3263 }
3264
3265 static void _omap_dispc_initial_config(void)
3266 {
3267         u32 l;
3268
3269         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3270         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3271                 l = dispc_read_reg(DISPC_DIVISOR);
3272                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3273                 l = FLD_MOD(l, 1, 0, 0);
3274                 l = FLD_MOD(l, 1, 23, 16);
3275                 dispc_write_reg(DISPC_DIVISOR, l);
3276         }
3277
3278         /* FUNCGATED */
3279         if (dss_has_feature(FEAT_FUNCGATED))
3280                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3281
3282         /* L3 firewall setting: enable access to OCM RAM */
3283         /* XXX this should be somewhere in plat-omap */
3284         if (cpu_is_omap24xx())
3285                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3286
3287         _dispc_setup_color_conv_coef();
3288
3289         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3290
3291         dispc_read_plane_fifo_sizes();
3292
3293         dispc_configure_burst_sizes();
3294 }
3295
3296 /* DISPC HW IP initialisation */
3297 static int omap_dispchw_probe(struct platform_device *pdev)
3298 {
3299         u32 rev;
3300         int r = 0;
3301         struct resource *dispc_mem;
3302         struct clk *clk;
3303
3304         dispc.pdev = pdev;
3305
3306         clk = clk_get(&pdev->dev, "fck");
3307         if (IS_ERR(clk)) {
3308                 DSSERR("can't get fck\n");
3309                 r = PTR_ERR(clk);
3310                 goto err_get_clk;
3311         }
3312
3313         dispc.dss_clk = clk;
3314
3315         spin_lock_init(&dispc.irq_lock);
3316
3317 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3318         spin_lock_init(&dispc.irq_stats_lock);
3319         dispc.irq_stats.last_reset = jiffies;
3320 #endif
3321
3322         INIT_WORK(&dispc.error_work, dispc_error_worker);
3323
3324         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3325         if (!dispc_mem) {
3326                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3327                 r = -EINVAL;
3328                 goto err_ioremap;
3329         }
3330         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3331         if (!dispc.base) {
3332                 DSSERR("can't ioremap DISPC\n");
3333                 r = -ENOMEM;
3334                 goto err_ioremap;
3335         }
3336         dispc.irq = platform_get_irq(dispc.pdev, 0);
3337         if (dispc.irq < 0) {
3338                 DSSERR("platform_get_irq failed\n");
3339                 r = -ENODEV;
3340                 goto err_irq;
3341         }
3342
3343         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3344                 "OMAP DISPC", dispc.pdev);
3345         if (r < 0) {
3346                 DSSERR("request_irq failed\n");
3347                 goto err_irq;
3348         }
3349
3350         pm_runtime_enable(&pdev->dev);
3351
3352         r = dispc_runtime_get();
3353         if (r)
3354                 goto err_runtime_get;
3355
3356         _omap_dispc_initial_config();
3357
3358         _omap_dispc_initialize_irq();
3359
3360         rev = dispc_read_reg(DISPC_REVISION);
3361         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3362                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3363
3364         dispc_runtime_put();
3365
3366         return 0;
3367
3368 err_runtime_get:
3369         pm_runtime_disable(&pdev->dev);
3370         free_irq(dispc.irq, dispc.pdev);
3371 err_irq:
3372         iounmap(dispc.base);
3373 err_ioremap:
3374         clk_put(dispc.dss_clk);
3375 err_get_clk:
3376         return r;
3377 }
3378
3379 static int omap_dispchw_remove(struct platform_device *pdev)
3380 {
3381         pm_runtime_disable(&pdev->dev);
3382
3383         clk_put(dispc.dss_clk);
3384
3385         free_irq(dispc.irq, dispc.pdev);
3386         iounmap(dispc.base);
3387         return 0;
3388 }
3389
3390 static int dispc_runtime_suspend(struct device *dev)
3391 {
3392         dispc_save_context();
3393         dss_runtime_put();
3394
3395         return 0;
3396 }
3397
3398 static int dispc_runtime_resume(struct device *dev)
3399 {
3400         int r;
3401
3402         r = dss_runtime_get();
3403         if (r < 0)
3404                 return r;
3405
3406         dispc_restore_context();
3407
3408         return 0;
3409 }
3410
3411 static const struct dev_pm_ops dispc_pm_ops = {
3412         .runtime_suspend = dispc_runtime_suspend,
3413         .runtime_resume = dispc_runtime_resume,
3414 };
3415
3416 static struct platform_driver omap_dispchw_driver = {
3417         .probe          = omap_dispchw_probe,
3418         .remove         = omap_dispchw_remove,
3419         .driver         = {
3420                 .name   = "omapdss_dispc",
3421                 .owner  = THIS_MODULE,
3422                 .pm     = &dispc_pm_ops,
3423         },
3424 };
3425
3426 int dispc_init_platform_driver(void)
3427 {
3428         return platform_driver_register(&omap_dispchw_driver);
3429 }
3430
3431 void dispc_uninit_platform_driver(void)
3432 {
3433         return platform_driver_unregister(&omap_dispchw_driver);
3434 }