Pileus Git - ~andy/linux/blob - drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <plat/sram.h>
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 struct dispc_h_coef {
  67         s8 hc4;
  68         s8 hc3;
  69         u8 hc2;
  70         s8 hc1;
  71         s8 hc0;
  72 };
  73
  74 struct dispc_v_coef {
  75         s8 vc22;
  76         s8 vc2;
  77         u8 vc1;
  78         s8 vc0;
  79         s8 vc00;
  80 };
  81
  82 enum omap_burst_size {
  83         BURST_SIZE_X2 = 0,
  84         BURST_SIZE_X4 = 1,
  85         BURST_SIZE_X8 = 2,
  86 };
  87
  88 #define REG_GET(idx, start, end) \
  89         FLD_GET(dispc_read_reg(idx), start, end)
  90
  91 #define REG_FLD_MOD(idx, val, start, end)                               \
  92         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  93
  94 struct dispc_irq_stats {
  95         unsigned long last_reset;
  96         unsigned irq_count;
  97         unsigned irqs[32];
  98 };
  99
 100 static struct {
 101         struct platform_device *pdev;
 102         void __iomem    *base;
 103
 104         int             ctx_loss_cnt;
 105
 106         int irq;
 107         struct clk *dss_clk;
 108
 109         u32     fifo_size[MAX_DSS_OVERLAYS];
 110
 111         spinlock_t irq_lock;
 112         u32 irq_error_mask;
 113         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 114         u32 error_irqs;
 115         struct work_struct error_work;
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 121         spinlock_t irq_stats_lock;
 122         struct dispc_irq_stats irq_stats;
 123 #endif
 124 } dispc;
 125
 126 enum omap_color_component {
 127         /* used for all color formats for OMAP3 and earlier
 128          * and for RGB and Y color component on OMAP4
 129          */
 130         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 131         /* used for UV component for
 132          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 133          * color formats on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 136 };
 137
 138 static void _omap_dispc_set_irqs(void);
 139
 140 static inline void dispc_write_reg(const u16 idx, u32 val)
 141 {
 142         __raw_writel(val, dispc.base + idx);
 143 }
 144
 145 static inline u32 dispc_read_reg(const u16 idx)
 146 {
 147         return __raw_readl(dispc.base + idx);
 148 }
 149
 150 static int dispc_get_ctx_loss_count(void)
 151 {
 152         struct device *dev = &dispc.pdev->dev;
 153         struct omap_display_platform_data *pdata = dev->platform_data;
 154         struct omap_dss_board_info *board_data = pdata->board_data;
 155         int cnt;
 156
 157         if (!board_data->get_context_loss_count)
 158                 return -ENOENT;
 159
 160         cnt = board_data->get_context_loss_count(dev);
 161
 162         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 163
 164         return cnt;
 165 }
 166
 167 #define SR(reg) \
 168         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 169 #define RR(reg) \
 170         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 171
 172 static void dispc_save_context(void)
 173 {
 174         int i, j;
 175
 176         DSSDBG("dispc_save_context\n");
 177
 178         SR(IRQENABLE);
 179         SR(CONTROL);
 180         SR(CONFIG);
 181         SR(LINE_NUMBER);
 182         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 183                 SR(GLOBAL_ALPHA);
 184         if (dss_has_feature(FEAT_MGR_LCD2)) {
 185                 SR(CONTROL2);
 186                 SR(CONFIG2);
 187         }
 188
 189         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 190                 SR(DEFAULT_COLOR(i));
 191                 SR(TRANS_COLOR(i));
 192                 SR(SIZE_MGR(i));
 193                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 194                         continue;
 195                 SR(TIMING_H(i));
 196                 SR(TIMING_V(i));
 197                 SR(POL_FREQ(i));
 198                 SR(DIVISORo(i));
 199
 200                 SR(DATA_CYCLE1(i));
 201                 SR(DATA_CYCLE2(i));
 202                 SR(DATA_CYCLE3(i));
 203
 204                 if (dss_has_feature(FEAT_CPR)) {
 205                         SR(CPR_COEF_R(i));
 206                         SR(CPR_COEF_G(i));
 207                         SR(CPR_COEF_B(i));
 208                 }
 209         }
 210
 211         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 212                 SR(OVL_BA0(i));
 213                 SR(OVL_BA1(i));
 214                 SR(OVL_POSITION(i));
 215                 SR(OVL_SIZE(i));
 216                 SR(OVL_ATTRIBUTES(i));
 217                 SR(OVL_FIFO_THRESHOLD(i));
 218                 SR(OVL_ROW_INC(i));
 219                 SR(OVL_PIXEL_INC(i));
 220                 if (dss_has_feature(FEAT_PRELOAD))
 221                         SR(OVL_PRELOAD(i));
 222                 if (i == OMAP_DSS_GFX) {
 223                         SR(OVL_WINDOW_SKIP(i));
 224                         SR(OVL_TABLE_BA(i));
 225                         continue;
 226                 }
 227                 SR(OVL_FIR(i));
 228                 SR(OVL_PICTURE_SIZE(i));
 229                 SR(OVL_ACCU0(i));
 230                 SR(OVL_ACCU1(i));
 231
 232                 for (j = 0; j < 8; j++)
 233                         SR(OVL_FIR_COEF_H(i, j));
 234
 235                 for (j = 0; j < 8; j++)
 236                         SR(OVL_FIR_COEF_HV(i, j));
 237
 238                 for (j = 0; j < 5; j++)
 239                         SR(OVL_CONV_COEF(i, j));
 240
 241                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 242                         for (j = 0; j < 8; j++)
 243                                 SR(OVL_FIR_COEF_V(i, j));
 244                 }
 245
 246                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 247                         SR(OVL_BA0_UV(i));
 248                         SR(OVL_BA1_UV(i));
 249                         SR(OVL_FIR2(i));
 250                         SR(OVL_ACCU2_0(i));
 251                         SR(OVL_ACCU2_1(i));
 252
 253                         for (j = 0; j < 8; j++)
 254                                 SR(OVL_FIR_COEF_H2(i, j));
 255
 256                         for (j = 0; j < 8; j++)
 257                                 SR(OVL_FIR_COEF_HV2(i, j));
 258
 259                         for (j = 0; j < 8; j++)
 260                                 SR(OVL_FIR_COEF_V2(i, j));
 261                 }
 262                 if (dss_has_feature(FEAT_ATTR2))
 263                         SR(OVL_ATTRIBUTES2(i));
 264         }
 265
 266         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 267                 SR(DIVISOR);
 268
 269         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 270         dispc.ctx_valid = true;
 271
 272         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 273 }
 274
 275 static void dispc_restore_context(void)
 276 {
 277         int i, j, ctx;
 278
 279         DSSDBG("dispc_restore_context\n");
 280
 281         if (!dispc.ctx_valid)
 282                 return;
 283
 284         ctx = dispc_get_ctx_loss_count();
 285
 286         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 287                 return;
 288
 289         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 290                         dispc.ctx_loss_cnt, ctx);
 291
 292         /*RR(IRQENABLE);*/
 293         /*RR(CONTROL);*/
 294         RR(CONFIG);
 295         RR(LINE_NUMBER);
 296         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 297                 RR(GLOBAL_ALPHA);
 298         if (dss_has_feature(FEAT_MGR_LCD2))
 299                 RR(CONFIG2);
 300
 301         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 302                 RR(DEFAULT_COLOR(i));
 303                 RR(TRANS_COLOR(i));
 304                 RR(SIZE_MGR(i));
 305                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 306                         continue;
 307                 RR(TIMING_H(i));
 308                 RR(TIMING_V(i));
 309                 RR(POL_FREQ(i));
 310                 RR(DIVISORo(i));
 311
 312                 RR(DATA_CYCLE1(i));
 313                 RR(DATA_CYCLE2(i));
 314                 RR(DATA_CYCLE3(i));
 315
 316                 if (dss_has_feature(FEAT_CPR)) {
 317                         RR(CPR_COEF_R(i));
 318                         RR(CPR_COEF_G(i));
 319                         RR(CPR_COEF_B(i));
 320                 }
 321         }
 322
 323         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 324                 RR(OVL_BA0(i));
 325                 RR(OVL_BA1(i));
 326                 RR(OVL_POSITION(i));
 327                 RR(OVL_SIZE(i));
 328                 RR(OVL_ATTRIBUTES(i));
 329                 RR(OVL_FIFO_THRESHOLD(i));
 330                 RR(OVL_ROW_INC(i));
 331                 RR(OVL_PIXEL_INC(i));
 332                 if (dss_has_feature(FEAT_PRELOAD))
 333                         RR(OVL_PRELOAD(i));
 334                 if (i == OMAP_DSS_GFX) {
 335                         RR(OVL_WINDOW_SKIP(i));
 336                         RR(OVL_TABLE_BA(i));
 337                         continue;
 338                 }
 339                 RR(OVL_FIR(i));
 340                 RR(OVL_PICTURE_SIZE(i));
 341                 RR(OVL_ACCU0(i));
 342                 RR(OVL_ACCU1(i));
 343
 344                 for (j = 0; j < 8; j++)
 345                         RR(OVL_FIR_COEF_H(i, j));
 346
 347                 for (j = 0; j < 8; j++)
 348                         RR(OVL_FIR_COEF_HV(i, j));
 349
 350                 for (j = 0; j < 5; j++)
 351                         RR(OVL_CONV_COEF(i, j));
 352
 353                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_V(i, j));
 356                 }
 357
 358                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 359                         RR(OVL_BA0_UV(i));
 360                         RR(OVL_BA1_UV(i));
 361                         RR(OVL_FIR2(i));
 362                         RR(OVL_ACCU2_0(i));
 363                         RR(OVL_ACCU2_1(i));
 364
 365                         for (j = 0; j < 8; j++)
 366                                 RR(OVL_FIR_COEF_H2(i, j));
 367
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_HV2(i, j));
 370
 371                         for (j = 0; j < 8; j++)
 372                                 RR(OVL_FIR_COEF_V2(i, j));
 373                 }
 374                 if (dss_has_feature(FEAT_ATTR2))
 375                         RR(OVL_ATTRIBUTES2(i));
 376         }
 377
 378         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 379                 RR(DIVISOR);
 380
 381         /* enable last, because LCD & DIGIT enable are here */
 382         RR(CONTROL);
 383         if (dss_has_feature(FEAT_MGR_LCD2))
 384                 RR(CONTROL2);
 385         /* clear spurious SYNC_LOST_DIGIT interrupts */
 386         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 387
 388         /*
 389          * enable last so IRQs won't trigger before
 390          * the context is fully restored
 391          */
 392         RR(IRQENABLE);
 393
 394         DSSDBG("context restored\n");
 395 }
 396
 397 #undef SR
 398 #undef RR
 399
 400 int dispc_runtime_get(void)
 401 {
 402         int r;
 403
 404         DSSDBG("dispc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&dispc.pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 void dispc_runtime_put(void)
 412 {
 413         int r;
 414
 415         DSSDBG("dispc_runtime_put\n");
 416
 417         r = pm_runtime_put(&dispc.pdev->dev);
 418         WARN_ON(r < 0);
 419 }
 420
 421
 422 bool dispc_go_busy(enum omap_channel channel)
 423 {
 424         int bit;
 425
 426         if (channel == OMAP_DSS_CHANNEL_LCD ||
 427                         channel == OMAP_DSS_CHANNEL_LCD2)
 428                 bit = 5; /* GOLCD */
 429         else
 430                 bit = 6; /* GODIGIT */
 431
 432         if (channel == OMAP_DSS_CHANNEL_LCD2)
 433                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 434         else
 435                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 436 }
 437
 438 void dispc_go(enum omap_channel channel)
 439 {
 440         int bit;
 441         bool enable_bit, go_bit;
 442
 443         if (channel == OMAP_DSS_CHANNEL_LCD ||
 444                         channel == OMAP_DSS_CHANNEL_LCD2)
 445                 bit = 0; /* LCDENABLE */
 446         else
 447                 bit = 1; /* DIGITALENABLE */
 448
 449         /* if the channel is not enabled, we don't need GO */
 450         if (channel == OMAP_DSS_CHANNEL_LCD2)
 451                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 452         else
 453                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 454
 455         if (!enable_bit)
 456                 return;
 457
 458         if (channel == OMAP_DSS_CHANNEL_LCD ||
 459                         channel == OMAP_DSS_CHANNEL_LCD2)
 460                 bit = 5; /* GOLCD */
 461         else
 462                 bit = 6; /* GODIGIT */
 463
 464         if (channel == OMAP_DSS_CHANNEL_LCD2)
 465                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 466         else
 467                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 468
 469         if (go_bit) {
 470                 DSSERR("GO bit not down for channel %d\n", channel);
 471                 return;
 472         }
 473
 474         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 475                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 476
 477         if (channel == OMAP_DSS_CHANNEL_LCD2)
 478                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 479         else
 480                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 481 }
 482
 483 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 484 {
 485         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 486 }
 487
 488 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 489 {
 490         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 491 }
 492
 493 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 494 {
 495         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 496 }
 497
 498 static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 499 {
 500         BUG_ON(plane == OMAP_DSS_GFX);
 501
 502         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 503 }
 504
 505 static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
 506 {
 507         BUG_ON(plane == OMAP_DSS_GFX);
 508
 509         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 510 }
 511
 512 static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 513 {
 514         BUG_ON(plane == OMAP_DSS_GFX);
 515
 516         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 517 }
 518
 519 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 520                                   int vscaleup, int five_taps,
 521                                   enum omap_color_component color_comp)
 522 {
 523         /* Coefficients for horizontal up-sampling */
 524         static const struct dispc_h_coef coef_hup[8] = {
 525                 {  0,   0, 128,   0,  0 },
 526                 { -1,  13, 124,  -8,  0 },
 527                 { -2,  30, 112, -11, -1 },
 528                 { -5,  51,  95, -11, -2 },
 529                 {  0,  -9,  73,  73, -9 },
 530                 { -2, -11,  95,  51, -5 },
 531                 { -1, -11, 112,  30, -2 },
 532                 {  0,  -8, 124,  13, -1 },
 533         };
 534
 535         /* Coefficients for vertical up-sampling */
 536         static const struct dispc_v_coef coef_vup_3tap[8] = {
 537                 { 0,  0, 128,  0, 0 },
 538                 { 0,  3, 123,  2, 0 },
 539                 { 0, 12, 111,  5, 0 },
 540                 { 0, 32,  89,  7, 0 },
 541                 { 0,  0,  64, 64, 0 },
 542                 { 0,  7,  89, 32, 0 },
 543                 { 0,  5, 111, 12, 0 },
 544                 { 0,  2, 123,  3, 0 },
 545         };
 546
 547         static const struct dispc_v_coef coef_vup_5tap[8] = {
 548                 {  0,   0, 128,   0,  0 },
 549                 { -1,  13, 124,  -8,  0 },
 550                 { -2,  30, 112, -11, -1 },
 551                 { -5,  51,  95, -11, -2 },
 552                 {  0,  -9,  73,  73, -9 },
 553                 { -2, -11,  95,  51, -5 },
 554                 { -1, -11, 112,  30, -2 },
 555                 {  0,  -8, 124,  13, -1 },
 556         };
 557
 558         /* Coefficients for horizontal down-sampling */
 559         static const struct dispc_h_coef coef_hdown[8] = {
 560                 {   0, 36, 56, 36,  0 },
 561                 {   4, 40, 55, 31, -2 },
 562                 {   8, 44, 54, 27, -5 },
 563                 {  12, 48, 53, 22, -7 },
 564                 {  -9, 17, 52, 51, 17 },
 565                 {  -7, 22, 53, 48, 12 },
 566                 {  -5, 27, 54, 44,  8 },
 567                 {  -2, 31, 55, 40,  4 },
 568         };
 569
 570         /* Coefficients for vertical down-sampling */
 571         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 572                 { 0, 36, 56, 36, 0 },
 573                 { 0, 40, 57, 31, 0 },
 574                 { 0, 45, 56, 27, 0 },
 575                 { 0, 50, 55, 23, 0 },
 576                 { 0, 18, 55, 55, 0 },
 577                 { 0, 23, 55, 50, 0 },
 578                 { 0, 27, 56, 45, 0 },
 579                 { 0, 31, 57, 40, 0 },
 580         };
 581
 582         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 583                 {   0, 36, 56, 36,  0 },
 584                 {   4, 40, 55, 31, -2 },
 585                 {   8, 44, 54, 27, -5 },
 586                 {  12, 48, 53, 22, -7 },
 587                 {  -9, 17, 52, 51, 17 },
 588                 {  -7, 22, 53, 48, 12 },
 589                 {  -5, 27, 54, 44,  8 },
 590                 {  -2, 31, 55, 40,  4 },
 591         };
 592
 593         const struct dispc_h_coef *h_coef;
 594         const struct dispc_v_coef *v_coef;
 595         int i;
 596
 597         if (hscaleup)
 598                 h_coef = coef_hup;
 599         else
 600                 h_coef = coef_hdown;
 601
 602         if (vscaleup)
 603                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 604         else
 605                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 606
 607         for (i = 0; i < 8; i++) {
 608                 u32 h, hv;
 609
 610                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 611                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 612                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 613                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 614                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 615                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 616                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 617                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 618
 619                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 620                         _dispc_write_firh_reg(plane, i, h);
 621                         _dispc_write_firhv_reg(plane, i, hv);
 622                 } else {
 623                         _dispc_write_firh2_reg(plane, i, h);
 624                         _dispc_write_firhv2_reg(plane, i, hv);
 625                 }
 626
 627         }
 628
 629         if (five_taps) {
 630                 for (i = 0; i < 8; i++) {
 631                         u32 v;
 632                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 633                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 634                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 635                                 _dispc_write_firv_reg(plane, i, v);
 636                         else
 637                                 _dispc_write_firv2_reg(plane, i, v);
 638                 }
 639         }
 640 }
 641
 642 static void _dispc_setup_color_conv_coef(void)
 643 {
 644         int i;
 645         const struct color_conv_coef {
 646                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 647                 int  full_range;
 648         }  ctbl_bt601_5 = {
 649                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 650         };
 651
 652         const struct color_conv_coef *ct;
 653
 654 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 655
 656         ct = &ctbl_bt601_5;
 657
 658         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 659                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 660                         CVAL(ct->rcr, ct->ry));
 661                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 662                         CVAL(ct->gy,  ct->rcb));
 663                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 664                         CVAL(ct->gcb, ct->gcr));
 665                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 666                         CVAL(ct->bcr, ct->by));
 667                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 668                         CVAL(0, ct->bcb));
 669
 670                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 671                         11, 11);
 672         }
 673
 674 #undef CVAL
 675 }
 676
 677
 678 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 679 {
 680         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 681 }
 682
 683 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 684 {
 685         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 686 }
 687
 688 static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
 689 {
 690         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 691 }
 692
 693 static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
 694 {
 695         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 696 }
 697
 698 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 699 {
 700         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 701
 702         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 703 }
 704
 705 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 706 {
 707         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 708
 709         if (plane == OMAP_DSS_GFX)
 710                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 711         else
 712                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 713 }
 714
 715 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 716 {
 717         u32 val;
 718
 719         BUG_ON(plane == OMAP_DSS_GFX);
 720
 721         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 722
 723         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 724 }
 725
 726 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 727 {
 728         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 729                 return;
 730
 731         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 732                 plane == OMAP_DSS_VIDEO1)
 733                 return;
 734
 735         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 736 }
 737
 738 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 739 {
 740         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 741                 return;
 742
 743         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 744                 plane == OMAP_DSS_VIDEO1)
 745                 return;
 746
 747         if (plane == OMAP_DSS_GFX)
 748                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 749         else if (plane == OMAP_DSS_VIDEO2)
 750                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 751 }
 752
 753 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 754 {
 755         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 756 }
 757
 758 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 759 {
 760         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 761 }
 762
 763 static void _dispc_set_color_mode(enum omap_plane plane,
 764                 enum omap_color_mode color_mode)
 765 {
 766         u32 m = 0;
 767         if (plane != OMAP_DSS_GFX) {
 768                 switch (color_mode) {
 769                 case OMAP_DSS_COLOR_NV12:
 770                         m = 0x0; break;
 771                 case OMAP_DSS_COLOR_RGB12U:
 772                         m = 0x1; break;
 773                 case OMAP_DSS_COLOR_RGBA16:
 774                         m = 0x2; break;
 775                 case OMAP_DSS_COLOR_RGBX16:
 776                         m = 0x4; break;
 777                 case OMAP_DSS_COLOR_ARGB16:
 778                         m = 0x5; break;
 779                 case OMAP_DSS_COLOR_RGB16:
 780                         m = 0x6; break;
 781                 case OMAP_DSS_COLOR_ARGB16_1555:
 782                         m = 0x7; break;
 783                 case OMAP_DSS_COLOR_RGB24U:
 784                         m = 0x8; break;
 785                 case OMAP_DSS_COLOR_RGB24P:
 786                         m = 0x9; break;
 787                 case OMAP_DSS_COLOR_YUV2:
 788                         m = 0xa; break;
 789                 case OMAP_DSS_COLOR_UYVY:
 790                         m = 0xb; break;
 791                 case OMAP_DSS_COLOR_ARGB32:
 792                         m = 0xc; break;
 793                 case OMAP_DSS_COLOR_RGBA32:
 794                         m = 0xd; break;
 795                 case OMAP_DSS_COLOR_RGBX32:
 796                         m = 0xe; break;
 797                 case OMAP_DSS_COLOR_XRGB16_1555:
 798                         m = 0xf; break;
 799                 default:
 800                         BUG(); break;
 801                 }
 802         } else {
 803                 switch (color_mode) {
 804                 case OMAP_DSS_COLOR_CLUT1:
 805                         m = 0x0; break;
 806                 case OMAP_DSS_COLOR_CLUT2:
 807                         m = 0x1; break;
 808                 case OMAP_DSS_COLOR_CLUT4:
 809                         m = 0x2; break;
 810                 case OMAP_DSS_COLOR_CLUT8:
 811                         m = 0x3; break;
 812                 case OMAP_DSS_COLOR_RGB12U:
 813                         m = 0x4; break;
 814                 case OMAP_DSS_COLOR_ARGB16:
 815                         m = 0x5; break;
 816                 case OMAP_DSS_COLOR_RGB16:
 817                         m = 0x6; break;
 818                 case OMAP_DSS_COLOR_ARGB16_1555:
 819                         m = 0x7; break;
 820                 case OMAP_DSS_COLOR_RGB24U:
 821                         m = 0x8; break;
 822                 case OMAP_DSS_COLOR_RGB24P:
 823                         m = 0x9; break;
 824                 case OMAP_DSS_COLOR_YUV2:
 825                         m = 0xa; break;
 826                 case OMAP_DSS_COLOR_UYVY:
 827                         m = 0xb; break;
 828                 case OMAP_DSS_COLOR_ARGB32:
 829                         m = 0xc; break;
 830                 case OMAP_DSS_COLOR_RGBA32:
 831                         m = 0xd; break;
 832                 case OMAP_DSS_COLOR_RGBX32:
 833                         m = 0xe; break;
 834                 case OMAP_DSS_COLOR_XRGB16_1555:
 835                         m = 0xf; break;
 836                 default:
 837                         BUG(); break;
 838                 }
 839         }
 840
 841         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 842 }
 843
 844 static void dispc_set_channel_out(enum omap_plane plane,
 845                 enum omap_channel channel)
 846 {
 847         int shift;
 848         u32 val;
 849         int chan = 0, chan2 = 0;
 850
 851         switch (plane) {
 852         case OMAP_DSS_GFX:
 853                 shift = 8;
 854                 break;
 855         case OMAP_DSS_VIDEO1:
 856         case OMAP_DSS_VIDEO2:
 857                 shift = 16;
 858                 break;
 859         default:
 860                 BUG();
 861                 return;
 862         }
 863
 864         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 865         if (dss_has_feature(FEAT_MGR_LCD2)) {
 866                 switch (channel) {
 867                 case OMAP_DSS_CHANNEL_LCD:
 868                         chan = 0;
 869                         chan2 = 0;
 870                         break;
 871                 case OMAP_DSS_CHANNEL_DIGIT:
 872                         chan = 1;
 873                         chan2 = 0;
 874                         break;
 875                 case OMAP_DSS_CHANNEL_LCD2:
 876                         chan = 0;
 877                         chan2 = 1;
 878                         break;
 879                 default:
 880                         BUG();
 881                 }
 882
 883                 val = FLD_MOD(val, chan, shift, shift);
 884                 val = FLD_MOD(val, chan2, 31, 30);
 885         } else {
 886                 val = FLD_MOD(val, channel, shift, shift);
 887         }
 888         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 889 }
 890
 891 static void dispc_set_burst_size(enum omap_plane plane,
 892                 enum omap_burst_size burst_size)
 893 {
 894         int shift;
 895
 896         switch (plane) {
 897         case OMAP_DSS_GFX:
 898                 shift = 6;
 899                 break;
 900         case OMAP_DSS_VIDEO1:
 901         case OMAP_DSS_VIDEO2:
 902                 shift = 14;
 903                 break;
 904         default:
 905                 BUG();
 906                 return;
 907         }
 908
 909         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 910 }
 911
 912 static void dispc_configure_burst_sizes(void)
 913 {
 914         int i;
 915         const int burst_size = BURST_SIZE_X8;
 916
 917         /* Configure burst size always to maximum size */
 918         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 919                 dispc_set_burst_size(i, burst_size);
 920 }
 921
 922 u32 dispc_get_burst_size(enum omap_plane plane)
 923 {
 924         unsigned unit = dss_feat_get_burst_size_unit();
 925         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 926         return unit * 8;
 927 }
 928
 929 void dispc_enable_gamma_table(bool enable)
 930 {
 931         /*
 932          * This is partially implemented to support only disabling of
 933          * the gamma table.
 934          */
 935         if (enable) {
 936                 DSSWARN("Gamma table enabling for TV not yet supported");
 937                 return;
 938         }
 939
 940         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 941 }
 942
 943 void dispc_enable_cpr(enum omap_channel channel, bool enable)
 944 {
 945         u16 reg;
 946
 947         if (channel == OMAP_DSS_CHANNEL_LCD)
 948                 reg = DISPC_CONFIG;
 949         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 950                 reg = DISPC_CONFIG2;
 951         else
 952                 return;
 953
 954         REG_FLD_MOD(reg, enable, 15, 15);
 955 }
 956
 957 void dispc_set_cpr_coef(enum omap_channel channel,
 958                 struct omap_dss_cpr_coefs *coefs)
 959 {
 960         u32 coef_r, coef_g, coef_b;
 961
 962         if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
 963                 return;
 964
 965         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 966                 FLD_VAL(coefs->rb, 9, 0);
 967         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 968                 FLD_VAL(coefs->gb, 9, 0);
 969         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 970                 FLD_VAL(coefs->bb, 9, 0);
 971
 972         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 973         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 974         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 975 }
 976
 977 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 978 {
 979         u32 val;
 980
 981         BUG_ON(plane == OMAP_DSS_GFX);
 982
 983         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 984         val = FLD_MOD(val, enable, 9, 9);
 985         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 986 }
 987
 988 void dispc_enable_replication(enum omap_plane plane, bool enable)
 989 {
 990         int bit;
 991
 992         if (plane == OMAP_DSS_GFX)
 993                 bit = 5;
 994         else
 995                 bit = 10;
 996
 997         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
 998 }
 999
1000 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1001 {
1002         u32 val;
1003         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1004         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1005         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1006 }
1007
1008 void dispc_set_digit_size(u16 width, u16 height)
1009 {
1010         u32 val;
1011         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1012         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1013         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1014 }
1015
1016 static void dispc_read_plane_fifo_sizes(void)
1017 {
1018         u32 size;
1019         int plane;
1020         u8 start, end;
1021         u32 unit;
1022
1023         unit = dss_feat_get_buffer_size_unit();
1024
1025         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1026
1027         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1028                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1029                 size *= unit;
1030                 dispc.fifo_size[plane] = size;
1031         }
1032 }
1033
1034 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1035 {
1036         return dispc.fifo_size[plane];
1037 }
1038
1039 void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1040 {
1041         u8 hi_start, hi_end, lo_start, lo_end;
1042         u32 unit;
1043
1044         unit = dss_feat_get_buffer_size_unit();
1045
1046         WARN_ON(low % unit != 0);
1047         WARN_ON(high % unit != 0);
1048
1049         low /= unit;
1050         high /= unit;
1051
1052         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1053         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1054
1055         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1056                         plane,
1057                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1058                                 lo_start, lo_end),
1059                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1060                                 hi_start, hi_end),
1061                         low, high);
1062
1063         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1064                         FLD_VAL(high, hi_start, hi_end) |
1065                         FLD_VAL(low, lo_start, lo_end));
1066 }
1067
1068 void dispc_enable_fifomerge(bool enable)
1069 {
1070         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1071         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1072 }
1073
1074 static void _dispc_set_fir(enum omap_plane plane,
1075                                 int hinc, int vinc,
1076                                 enum omap_color_component color_comp)
1077 {
1078         u32 val;
1079
1080         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1081                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1082
1083                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1084                                         &hinc_start, &hinc_end);
1085                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1086                                         &vinc_start, &vinc_end);
1087                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1088                                 FLD_VAL(hinc, hinc_start, hinc_end);
1089
1090                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1091         } else {
1092                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1093                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1094         }
1095 }
1096
1097 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1098 {
1099         u32 val;
1100         u8 hor_start, hor_end, vert_start, vert_end;
1101
1102         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1103         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1104
1105         val = FLD_VAL(vaccu, vert_start, vert_end) |
1106                         FLD_VAL(haccu, hor_start, hor_end);
1107
1108         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1109 }
1110
1111 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1112 {
1113         u32 val;
1114         u8 hor_start, hor_end, vert_start, vert_end;
1115
1116         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1117         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1118
1119         val = FLD_VAL(vaccu, vert_start, vert_end) |
1120                         FLD_VAL(haccu, hor_start, hor_end);
1121
1122         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1123 }
1124
1125 static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1126 {
1127         u32 val;
1128
1129         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1130         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1131 }
1132
1133 static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1134 {
1135         u32 val;
1136
1137         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1138         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1139 }
1140
1141 static void _dispc_set_scale_param(enum omap_plane plane,
1142                 u16 orig_width, u16 orig_height,
1143                 u16 out_width, u16 out_height,
1144                 bool five_taps, u8 rotation,
1145                 enum omap_color_component color_comp)
1146 {
1147         int fir_hinc, fir_vinc;
1148         int hscaleup, vscaleup;
1149
1150         hscaleup = orig_width <= out_width;
1151         vscaleup = orig_height <= out_height;
1152
1153         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
1154
1155         fir_hinc = 1024 * orig_width / out_width;
1156         fir_vinc = 1024 * orig_height / out_height;
1157
1158         _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1159 }
1160
1161 static void _dispc_set_scaling_common(enum omap_plane plane,
1162                 u16 orig_width, u16 orig_height,
1163                 u16 out_width, u16 out_height,
1164                 bool ilace, bool five_taps,
1165                 bool fieldmode, enum omap_color_mode color_mode,
1166                 u8 rotation)
1167 {
1168         int accu0 = 0;
1169         int accu1 = 0;
1170         u32 l;
1171
1172         _dispc_set_scale_param(plane, orig_width, orig_height,
1173                                 out_width, out_height, five_taps,
1174                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1175         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1176
1177         /* RESIZEENABLE and VERTICALTAPS */
1178         l &= ~((0x3 << 5) | (0x1 << 21));
1179         l |= (orig_width != out_width) ? (1 << 5) : 0;
1180         l |= (orig_height != out_height) ? (1 << 6) : 0;
1181         l |= five_taps ? (1 << 21) : 0;
1182
1183         /* VRESIZECONF and HRESIZECONF */
1184         if (dss_has_feature(FEAT_RESIZECONF)) {
1185                 l &= ~(0x3 << 7);
1186                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1187                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1188         }
1189
1190         /* LINEBUFFERSPLIT */
1191         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1192                 l &= ~(0x1 << 22);
1193                 l |= five_taps ? (1 << 22) : 0;
1194         }
1195
1196         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1197
1198         /*
1199          * field 0 = even field = bottom field
1200          * field 1 = odd field = top field
1201          */
1202         if (ilace && !fieldmode) {
1203                 accu1 = 0;
1204                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1205                 if (accu0 >= 1024/2) {
1206                         accu1 = 1024/2;
1207                         accu0 -= accu1;
1208                 }
1209         }
1210
1211         _dispc_set_vid_accu0(plane, 0, accu0);
1212         _dispc_set_vid_accu1(plane, 0, accu1);
1213 }
1214
1215 static void _dispc_set_scaling_uv(enum omap_plane plane,
1216                 u16 orig_width, u16 orig_height,
1217                 u16 out_width, u16 out_height,
1218                 bool ilace, bool five_taps,
1219                 bool fieldmode, enum omap_color_mode color_mode,
1220                 u8 rotation)
1221 {
1222         int scale_x = out_width != orig_width;
1223         int scale_y = out_height != orig_height;
1224
1225         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1226                 return;
1227         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1228                         color_mode != OMAP_DSS_COLOR_UYVY &&
1229                         color_mode != OMAP_DSS_COLOR_NV12)) {
1230                 /* reset chroma resampling for RGB formats  */
1231                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1232                 return;
1233         }
1234         switch (color_mode) {
1235         case OMAP_DSS_COLOR_NV12:
1236                 /* UV is subsampled by 2 vertically*/
1237                 orig_height >>= 1;
1238                 /* UV is subsampled by 2 horz.*/
1239                 orig_width >>= 1;
1240                 break;
1241         case OMAP_DSS_COLOR_YUV2:
1242         case OMAP_DSS_COLOR_UYVY:
1243                 /*For YUV422 with 90/270 rotation,
1244                  *we don't upsample chroma
1245                  */
1246                 if (rotation == OMAP_DSS_ROT_0 ||
1247                         rotation == OMAP_DSS_ROT_180)
1248                         /* UV is subsampled by 2 hrz*/
1249                         orig_width >>= 1;
1250                 /* must use FIR for YUV422 if rotated */
1251                 if (rotation != OMAP_DSS_ROT_0)
1252                         scale_x = scale_y = true;
1253                 break;
1254         default:
1255                 BUG();
1256         }
1257
1258         if (out_width != orig_width)
1259                 scale_x = true;
1260         if (out_height != orig_height)
1261                 scale_y = true;
1262
1263         _dispc_set_scale_param(plane, orig_width, orig_height,
1264                         out_width, out_height, five_taps,
1265                                 rotation, DISPC_COLOR_COMPONENT_UV);
1266
1267         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1268                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1269         /* set H scaling */
1270         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1271         /* set V scaling */
1272         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1273
1274         _dispc_set_vid_accu2_0(plane, 0x80, 0);
1275         _dispc_set_vid_accu2_1(plane, 0x80, 0);
1276 }
1277
1278 static void _dispc_set_scaling(enum omap_plane plane,
1279                 u16 orig_width, u16 orig_height,
1280                 u16 out_width, u16 out_height,
1281                 bool ilace, bool five_taps,
1282                 bool fieldmode, enum omap_color_mode color_mode,
1283                 u8 rotation)
1284 {
1285         BUG_ON(plane == OMAP_DSS_GFX);
1286
1287         _dispc_set_scaling_common(plane,
1288                         orig_width, orig_height,
1289                         out_width, out_height,
1290                         ilace, five_taps,
1291                         fieldmode, color_mode,
1292                         rotation);
1293
1294         _dispc_set_scaling_uv(plane,
1295                 orig_width, orig_height,
1296                 out_width, out_height,
1297                 ilace, five_taps,
1298                 fieldmode, color_mode,
1299                 rotation);
1300 }
1301
1302 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1303                 bool mirroring, enum omap_color_mode color_mode)
1304 {
1305         bool row_repeat = false;
1306         int vidrot = 0;
1307
1308         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1309                         color_mode == OMAP_DSS_COLOR_UYVY) {
1310
1311                 if (mirroring) {
1312                         switch (rotation) {
1313                         case OMAP_DSS_ROT_0:
1314                                 vidrot = 2;
1315                                 break;
1316                         case OMAP_DSS_ROT_90:
1317                                 vidrot = 1;
1318                                 break;
1319                         case OMAP_DSS_ROT_180:
1320                                 vidrot = 0;
1321                                 break;
1322                         case OMAP_DSS_ROT_270:
1323                                 vidrot = 3;
1324                                 break;
1325                         }
1326                 } else {
1327                         switch (rotation) {
1328                         case OMAP_DSS_ROT_0:
1329                                 vidrot = 0;
1330                                 break;
1331                         case OMAP_DSS_ROT_90:
1332                                 vidrot = 1;
1333                                 break;
1334                         case OMAP_DSS_ROT_180:
1335                                 vidrot = 2;
1336                                 break;
1337                         case OMAP_DSS_ROT_270:
1338                                 vidrot = 3;
1339                                 break;
1340                         }
1341                 }
1342
1343                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1344                         row_repeat = true;
1345                 else
1346                         row_repeat = false;
1347         }
1348
1349         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1350         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1351                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1352                         row_repeat ? 1 : 0, 18, 18);
1353 }
1354
1355 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1356 {
1357         switch (color_mode) {
1358         case OMAP_DSS_COLOR_CLUT1:
1359                 return 1;
1360         case OMAP_DSS_COLOR_CLUT2:
1361                 return 2;
1362         case OMAP_DSS_COLOR_CLUT4:
1363                 return 4;
1364         case OMAP_DSS_COLOR_CLUT8:
1365         case OMAP_DSS_COLOR_NV12:
1366                 return 8;
1367         case OMAP_DSS_COLOR_RGB12U:
1368         case OMAP_DSS_COLOR_RGB16:
1369         case OMAP_DSS_COLOR_ARGB16:
1370         case OMAP_DSS_COLOR_YUV2:
1371         case OMAP_DSS_COLOR_UYVY:
1372         case OMAP_DSS_COLOR_RGBA16:
1373         case OMAP_DSS_COLOR_RGBX16:
1374         case OMAP_DSS_COLOR_ARGB16_1555:
1375         case OMAP_DSS_COLOR_XRGB16_1555:
1376                 return 16;
1377         case OMAP_DSS_COLOR_RGB24P:
1378                 return 24;
1379         case OMAP_DSS_COLOR_RGB24U:
1380         case OMAP_DSS_COLOR_ARGB32:
1381         case OMAP_DSS_COLOR_RGBA32:
1382         case OMAP_DSS_COLOR_RGBX32:
1383                 return 32;
1384         default:
1385                 BUG();
1386         }
1387 }
1388
1389 static s32 pixinc(int pixels, u8 ps)
1390 {
1391         if (pixels == 1)
1392                 return 1;
1393         else if (pixels > 1)
1394                 return 1 + (pixels - 1) * ps;
1395         else if (pixels < 0)
1396                 return 1 - (-pixels + 1) * ps;
1397         else
1398                 BUG();
1399 }
1400
1401 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1402                 u16 screen_width,
1403                 u16 width, u16 height,
1404                 enum omap_color_mode color_mode, bool fieldmode,
1405                 unsigned int field_offset,
1406                 unsigned *offset0, unsigned *offset1,
1407                 s32 *row_inc, s32 *pix_inc)
1408 {
1409         u8 ps;
1410
1411         /* FIXME CLUT formats */
1412         switch (color_mode) {
1413         case OMAP_DSS_COLOR_CLUT1:
1414         case OMAP_DSS_COLOR_CLUT2:
1415         case OMAP_DSS_COLOR_CLUT4:
1416         case OMAP_DSS_COLOR_CLUT8:
1417                 BUG();
1418                 return;
1419         case OMAP_DSS_COLOR_YUV2:
1420         case OMAP_DSS_COLOR_UYVY:
1421                 ps = 4;
1422                 break;
1423         default:
1424                 ps = color_mode_to_bpp(color_mode) / 8;
1425                 break;
1426         }
1427
1428         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1429                         width, height);
1430
1431         /*
1432          * field 0 = even field = bottom field
1433          * field 1 = odd field = top field
1434          */
1435         switch (rotation + mirror * 4) {
1436         case OMAP_DSS_ROT_0:
1437         case OMAP_DSS_ROT_180:
1438                 /*
1439                  * If the pixel format is YUV or UYVY divide the width
1440                  * of the image by 2 for 0 and 180 degree rotation.
1441                  */
1442                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1443                         color_mode == OMAP_DSS_COLOR_UYVY)
1444                         width = width >> 1;
1445         case OMAP_DSS_ROT_90:
1446         case OMAP_DSS_ROT_270:
1447                 *offset1 = 0;
1448                 if (field_offset)
1449                         *offset0 = field_offset * screen_width * ps;
1450                 else
1451                         *offset0 = 0;
1452
1453                 *row_inc = pixinc(1 + (screen_width - width) +
1454                                 (fieldmode ? screen_width : 0),
1455                                 ps);
1456                 *pix_inc = pixinc(1, ps);
1457                 break;
1458
1459         case OMAP_DSS_ROT_0 + 4:
1460         case OMAP_DSS_ROT_180 + 4:
1461                 /* If the pixel format is YUV or UYVY divide the width
1462                  * of the image by 2  for 0 degree and 180 degree
1463                  */
1464                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1465                         color_mode == OMAP_DSS_COLOR_UYVY)
1466                         width = width >> 1;
1467         case OMAP_DSS_ROT_90 + 4:
1468         case OMAP_DSS_ROT_270 + 4:
1469                 *offset1 = 0;
1470                 if (field_offset)
1471                         *offset0 = field_offset * screen_width * ps;
1472                 else
1473                         *offset0 = 0;
1474                 *row_inc = pixinc(1 - (screen_width + width) -
1475                                 (fieldmode ? screen_width : 0),
1476                                 ps);
1477                 *pix_inc = pixinc(1, ps);
1478                 break;
1479
1480         default:
1481                 BUG();
1482         }
1483 }
1484
1485 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1486                 u16 screen_width,
1487                 u16 width, u16 height,
1488                 enum omap_color_mode color_mode, bool fieldmode,
1489                 unsigned int field_offset,
1490                 unsigned *offset0, unsigned *offset1,
1491                 s32 *row_inc, s32 *pix_inc)
1492 {
1493         u8 ps;
1494         u16 fbw, fbh;
1495
1496         /* FIXME CLUT formats */
1497         switch (color_mode) {
1498         case OMAP_DSS_COLOR_CLUT1:
1499         case OMAP_DSS_COLOR_CLUT2:
1500         case OMAP_DSS_COLOR_CLUT4:
1501         case OMAP_DSS_COLOR_CLUT8:
1502                 BUG();
1503                 return;
1504         default:
1505                 ps = color_mode_to_bpp(color_mode) / 8;
1506                 break;
1507         }
1508
1509         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1510                         width, height);
1511
1512         /* width & height are overlay sizes, convert to fb sizes */
1513
1514         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1515                 fbw = width;
1516                 fbh = height;
1517         } else {
1518                 fbw = height;
1519                 fbh = width;
1520         }
1521
1522         /*
1523          * field 0 = even field = bottom field
1524          * field 1 = odd field = top field
1525          */
1526         switch (rotation + mirror * 4) {
1527         case OMAP_DSS_ROT_0:
1528                 *offset1 = 0;
1529                 if (field_offset)
1530                         *offset0 = *offset1 + field_offset * screen_width * ps;
1531                 else
1532                         *offset0 = *offset1;
1533                 *row_inc = pixinc(1 + (screen_width - fbw) +
1534                                 (fieldmode ? screen_width : 0),
1535                                 ps);
1536                 *pix_inc = pixinc(1, ps);
1537                 break;
1538         case OMAP_DSS_ROT_90:
1539                 *offset1 = screen_width * (fbh - 1) * ps;
1540                 if (field_offset)
1541                         *offset0 = *offset1 + field_offset * ps;
1542                 else
1543                         *offset0 = *offset1;
1544                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1545                                 (fieldmode ? 1 : 0), ps);
1546                 *pix_inc = pixinc(-screen_width, ps);
1547                 break;
1548         case OMAP_DSS_ROT_180:
1549                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1550                 if (field_offset)
1551                         *offset0 = *offset1 - field_offset * screen_width * ps;
1552                 else
1553                         *offset0 = *offset1;
1554                 *row_inc = pixinc(-1 -
1555                                 (screen_width - fbw) -
1556                                 (fieldmode ? screen_width : 0),
1557                                 ps);
1558                 *pix_inc = pixinc(-1, ps);
1559                 break;
1560         case OMAP_DSS_ROT_270:
1561                 *offset1 = (fbw - 1) * ps;
1562                 if (field_offset)
1563                         *offset0 = *offset1 - field_offset * ps;
1564                 else
1565                         *offset0 = *offset1;
1566                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1567                                 (fieldmode ? 1 : 0), ps);
1568                 *pix_inc = pixinc(screen_width, ps);
1569                 break;
1570
1571         /* mirroring */
1572         case OMAP_DSS_ROT_0 + 4:
1573                 *offset1 = (fbw - 1) * ps;
1574                 if (field_offset)
1575                         *offset0 = *offset1 + field_offset * screen_width * ps;
1576                 else
1577                         *offset0 = *offset1;
1578                 *row_inc = pixinc(screen_width * 2 - 1 +
1579                                 (fieldmode ? screen_width : 0),
1580                                 ps);
1581                 *pix_inc = pixinc(-1, ps);
1582                 break;
1583
1584         case OMAP_DSS_ROT_90 + 4:
1585                 *offset1 = 0;
1586                 if (field_offset)
1587                         *offset0 = *offset1 + field_offset * ps;
1588                 else
1589                         *offset0 = *offset1;
1590                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1591                                 (fieldmode ? 1 : 0),
1592                                 ps);
1593                 *pix_inc = pixinc(screen_width, ps);
1594                 break;
1595
1596         case OMAP_DSS_ROT_180 + 4:
1597                 *offset1 = screen_width * (fbh - 1) * ps;
1598                 if (field_offset)
1599                         *offset0 = *offset1 - field_offset * screen_width * ps;
1600                 else
1601                         *offset0 = *offset1;
1602                 *row_inc = pixinc(1 - screen_width * 2 -
1603                                 (fieldmode ? screen_width : 0),
1604                                 ps);
1605                 *pix_inc = pixinc(1, ps);
1606                 break;
1607
1608         case OMAP_DSS_ROT_270 + 4:
1609                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1610                 if (field_offset)
1611                         *offset0 = *offset1 - field_offset * ps;
1612                 else
1613                         *offset0 = *offset1;
1614                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1615                                 (fieldmode ? 1 : 0),
1616                                 ps);
1617                 *pix_inc = pixinc(-screen_width, ps);
1618                 break;
1619
1620         default:
1621                 BUG();
1622         }
1623 }
1624
1625 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1626                 u16 height, u16 out_width, u16 out_height,
1627                 enum omap_color_mode color_mode)
1628 {
1629         u32 fclk = 0;
1630         /* FIXME venc pclk? */
1631         u64 tmp, pclk = dispc_pclk_rate(channel);
1632
1633         if (height > out_height) {
1634                 /* FIXME get real display PPL */
1635                 unsigned int ppl = 800;
1636
1637                 tmp = pclk * height * out_width;
1638                 do_div(tmp, 2 * out_height * ppl);
1639                 fclk = tmp;
1640
1641                 if (height > 2 * out_height) {
1642                         if (ppl == out_width)
1643                                 return 0;
1644
1645                         tmp = pclk * (height - 2 * out_height) * out_width;
1646                         do_div(tmp, 2 * out_height * (ppl - out_width));
1647                         fclk = max(fclk, (u32) tmp);
1648                 }
1649         }
1650
1651         if (width > out_width) {
1652                 tmp = pclk * width;
1653                 do_div(tmp, out_width);
1654                 fclk = max(fclk, (u32) tmp);
1655
1656                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1657                         fclk <<= 1;
1658         }
1659
1660         return fclk;
1661 }
1662
1663 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1664                 u16 height, u16 out_width, u16 out_height)
1665 {
1666         unsigned int hf, vf;
1667
1668         /*
1669          * FIXME how to determine the 'A' factor
1670          * for the no downscaling case ?
1671          */
1672
1673         if (width > 3 * out_width)
1674                 hf = 4;
1675         else if (width > 2 * out_width)
1676                 hf = 3;
1677         else if (width > out_width)
1678                 hf = 2;
1679         else
1680                 hf = 1;
1681
1682         if (height > out_height)
1683                 vf = 2;
1684         else
1685                 vf = 1;
1686
1687         /* FIXME venc pclk? */
1688         return dispc_pclk_rate(channel) * vf * hf;
1689 }
1690
1691 int dispc_setup_plane(enum omap_plane plane,
1692                 u32 paddr, u16 screen_width,
1693                 u16 pos_x, u16 pos_y,
1694                 u16 width, u16 height,
1695                 u16 out_width, u16 out_height,
1696                 enum omap_color_mode color_mode,
1697                 bool ilace,
1698                 enum omap_dss_rotation_type rotation_type,
1699                 u8 rotation, bool mirror,
1700                 u8 global_alpha, u8 pre_mult_alpha,
1701                 enum omap_channel channel, u32 puv_addr)
1702 {
1703         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1704         bool five_taps = 0;
1705         bool fieldmode = 0;
1706         int cconv = 0;
1707         unsigned offset0, offset1;
1708         s32 row_inc;
1709         s32 pix_inc;
1710         u16 frame_height = height;
1711         unsigned int field_offset = 0;
1712
1713         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1714                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1715                plane, paddr, screen_width, pos_x, pos_y,
1716                width, height,
1717                out_width, out_height,
1718                ilace, color_mode,
1719                rotation, mirror, channel);
1720
1721         if (paddr == 0)
1722                 return -EINVAL;
1723
1724         if (ilace && height == out_height)
1725                 fieldmode = 1;
1726
1727         if (ilace) {
1728                 if (fieldmode)
1729                         height /= 2;
1730                 pos_y /= 2;
1731                 out_height /= 2;
1732
1733                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1734                                 "out_height %d\n",
1735                                 height, pos_y, out_height);
1736         }
1737
1738         if (!dss_feat_color_mode_supported(plane, color_mode))
1739                 return -EINVAL;
1740
1741         if (plane == OMAP_DSS_GFX) {
1742                 if (width != out_width || height != out_height)
1743                         return -EINVAL;
1744         } else {
1745                 /* video plane */
1746
1747                 unsigned long fclk = 0;
1748
1749                 if (out_width < width / maxdownscale ||
1750                    out_width > width * 8)
1751                         return -EINVAL;
1752
1753                 if (out_height < height / maxdownscale ||
1754                    out_height > height * 8)
1755                         return -EINVAL;
1756
1757                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1758                         color_mode == OMAP_DSS_COLOR_UYVY ||
1759                         color_mode == OMAP_DSS_COLOR_NV12)
1760                         cconv = 1;
1761
1762                 /* Must use 5-tap filter? */
1763                 five_taps = height > out_height * 2;
1764
1765                 if (!five_taps) {
1766                         fclk = calc_fclk(channel, width, height, out_width,
1767                                         out_height);
1768
1769                         /* Try 5-tap filter if 3-tap fclk is too high */
1770                         if (cpu_is_omap34xx() && height > out_height &&
1771                                         fclk > dispc_fclk_rate())
1772                                 five_taps = true;
1773                 }
1774
1775                 if (width > (2048 >> five_taps)) {
1776                         DSSERR("failed to set up scaling, fclk too low\n");
1777                         return -EINVAL;
1778                 }
1779
1780                 if (five_taps)
1781                         fclk = calc_fclk_five_taps(channel, width, height,
1782                                         out_width, out_height, color_mode);
1783
1784                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1785                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1786
1787                 if (!fclk || fclk > dispc_fclk_rate()) {
1788                         DSSERR("failed to set up scaling, "
1789                                         "required fclk rate = %lu Hz, "
1790                                         "current fclk rate = %lu Hz\n",
1791                                         fclk, dispc_fclk_rate());
1792                         return -EINVAL;
1793                 }
1794         }
1795
1796         if (ilace && !fieldmode) {
1797                 /*
1798                  * when downscaling the bottom field may have to start several
1799                  * source lines below the top field. Unfortunately ACCUI
1800                  * registers will only hold the fractional part of the offset
1801                  * so the integer part must be added to the base address of the
1802                  * bottom field.
1803                  */
1804                 if (!height || height == out_height)
1805                         field_offset = 0;
1806                 else
1807                         field_offset = height / out_height / 2;
1808         }
1809
1810         /* Fields are independent but interleaved in memory. */
1811         if (fieldmode)
1812                 field_offset = 1;
1813
1814         if (rotation_type == OMAP_DSS_ROT_DMA)
1815                 calc_dma_rotation_offset(rotation, mirror,
1816                                 screen_width, width, frame_height, color_mode,
1817                                 fieldmode, field_offset,
1818                                 &offset0, &offset1, &row_inc, &pix_inc);
1819         else
1820                 calc_vrfb_rotation_offset(rotation, mirror,
1821                                 screen_width, width, frame_height, color_mode,
1822                                 fieldmode, field_offset,
1823                                 &offset0, &offset1, &row_inc, &pix_inc);
1824
1825         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1826                         offset0, offset1, row_inc, pix_inc);
1827
1828         _dispc_set_color_mode(plane, color_mode);
1829
1830         _dispc_set_plane_ba0(plane, paddr + offset0);
1831         _dispc_set_plane_ba1(plane, paddr + offset1);
1832
1833         if (OMAP_DSS_COLOR_NV12 == color_mode) {
1834                 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1835                 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1836         }
1837
1838
1839         _dispc_set_row_inc(plane, row_inc);
1840         _dispc_set_pix_inc(plane, pix_inc);
1841
1842         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1843                         out_width, out_height);
1844
1845         _dispc_set_plane_pos(plane, pos_x, pos_y);
1846
1847         _dispc_set_pic_size(plane, width, height);
1848
1849         if (plane != OMAP_DSS_GFX) {
1850                 _dispc_set_scaling(plane, width, height,
1851                                    out_width, out_height,
1852                                    ilace, five_taps, fieldmode,
1853                                    color_mode, rotation);
1854                 _dispc_set_vid_size(plane, out_width, out_height);
1855                 _dispc_set_vid_color_conv(plane, cconv);
1856         }
1857
1858         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1859
1860         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1861         _dispc_setup_global_alpha(plane, global_alpha);
1862
1863         dispc_set_channel_out(plane, channel);
1864
1865         return 0;
1866 }
1867
1868 int dispc_enable_plane(enum omap_plane plane, bool enable)
1869 {
1870         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1871
1872         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1873
1874         return 0;
1875 }
1876
1877 static void dispc_disable_isr(void *data, u32 mask)
1878 {
1879         struct completion *compl = data;
1880         complete(compl);
1881 }
1882
1883 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1884 {
1885         if (channel == OMAP_DSS_CHANNEL_LCD2)
1886                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1887         else
1888                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1889 }
1890
1891 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1892 {
1893         struct completion frame_done_completion;
1894         bool is_on;
1895         int r;
1896         u32 irq;
1897
1898         /* When we disable LCD output, we need to wait until frame is done.
1899          * Otherwise the DSS is still working, and turning off the clocks
1900          * prevents DSS from going to OFF mode */
1901         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1902                         REG_GET(DISPC_CONTROL2, 0, 0) :
1903                         REG_GET(DISPC_CONTROL, 0, 0);
1904
1905         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1906                         DISPC_IRQ_FRAMEDONE;
1907
1908         if (!enable && is_on) {
1909                 init_completion(&frame_done_completion);
1910
1911                 r = omap_dispc_register_isr(dispc_disable_isr,
1912                                 &frame_done_completion, irq);
1913
1914                 if (r)
1915                         DSSERR("failed to register FRAMEDONE isr\n");
1916         }
1917
1918         _enable_lcd_out(channel, enable);
1919
1920         if (!enable && is_on) {
1921                 if (!wait_for_completion_timeout(&frame_done_completion,
1922                                         msecs_to_jiffies(100)))
1923                         DSSERR("timeout waiting for FRAME DONE\n");
1924
1925                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1926                                 &frame_done_completion, irq);
1927
1928                 if (r)
1929                         DSSERR("failed to unregister FRAMEDONE isr\n");
1930         }
1931 }
1932
1933 static void _enable_digit_out(bool enable)
1934 {
1935         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1936 }
1937
1938 static void dispc_enable_digit_out(bool enable)
1939 {
1940         struct completion frame_done_completion;
1941         int r;
1942
1943         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1944                 return;
1945
1946         if (enable) {
1947                 unsigned long flags;
1948                 /* When we enable digit output, we'll get an extra digit
1949                  * sync lost interrupt, that we need to ignore */
1950                 spin_lock_irqsave(&dispc.irq_lock, flags);
1951                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1952                 _omap_dispc_set_irqs();
1953                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1954         }
1955
1956         /* When we disable digit output, we need to wait until fields are done.
1957          * Otherwise the DSS is still working, and turning off the clocks
1958          * prevents DSS from going to OFF mode. And when enabling, we need to
1959          * wait for the extra sync losts */
1960         init_completion(&frame_done_completion);
1961
1962         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1963                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1964         if (r)
1965                 DSSERR("failed to register EVSYNC isr\n");
1966
1967         _enable_digit_out(enable);
1968
1969         /* XXX I understand from TRM that we should only wait for the
1970          * current field to complete. But it seems we have to wait
1971          * for both fields */
1972         if (!wait_for_completion_timeout(&frame_done_completion,
1973                                 msecs_to_jiffies(100)))
1974                 DSSERR("timeout waiting for EVSYNC\n");
1975
1976         if (!wait_for_completion_timeout(&frame_done_completion,
1977                                 msecs_to_jiffies(100)))
1978                 DSSERR("timeout waiting for EVSYNC\n");
1979
1980         r = omap_dispc_unregister_isr(dispc_disable_isr,
1981                         &frame_done_completion,
1982                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1983         if (r)
1984                 DSSERR("failed to unregister EVSYNC isr\n");
1985
1986         if (enable) {
1987                 unsigned long flags;
1988                 spin_lock_irqsave(&dispc.irq_lock, flags);
1989                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1990                 if (dss_has_feature(FEAT_MGR_LCD2))
1991                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
1992                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1993                 _omap_dispc_set_irqs();
1994                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1995         }
1996 }
1997
1998 bool dispc_is_channel_enabled(enum omap_channel channel)
1999 {
2000         if (channel == OMAP_DSS_CHANNEL_LCD)
2001                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2002         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2003                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2004         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2005                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2006         else
2007                 BUG();
2008 }
2009
2010 void dispc_enable_channel(enum omap_channel channel, bool enable)
2011 {
2012         if (channel == OMAP_DSS_CHANNEL_LCD ||
2013                         channel == OMAP_DSS_CHANNEL_LCD2)
2014                 dispc_enable_lcd_out(channel, enable);
2015         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2016                 dispc_enable_digit_out(enable);
2017         else
2018                 BUG();
2019 }
2020
2021 void dispc_lcd_enable_signal_polarity(bool act_high)
2022 {
2023         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2024                 return;
2025
2026         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2027 }
2028
2029 void dispc_lcd_enable_signal(bool enable)
2030 {
2031         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2032                 return;
2033
2034         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2035 }
2036
2037 void dispc_pck_free_enable(bool enable)
2038 {
2039         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2040                 return;
2041
2042         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2043 }
2044
2045 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
2046 {
2047         if (channel == OMAP_DSS_CHANNEL_LCD2)
2048                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2049         else
2050                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2051 }
2052
2053
2054 void dispc_set_lcd_display_type(enum omap_channel channel,
2055                 enum omap_lcd_display_type type)
2056 {
2057         int mode;
2058
2059         switch (type) {
2060         case OMAP_DSS_LCD_DISPLAY_STN:
2061                 mode = 0;
2062                 break;
2063
2064         case OMAP_DSS_LCD_DISPLAY_TFT:
2065                 mode = 1;
2066                 break;
2067
2068         default:
2069                 BUG();
2070                 return;
2071         }
2072
2073         if (channel == OMAP_DSS_CHANNEL_LCD2)
2074                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2075         else
2076                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2077 }
2078
2079 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2080 {
2081         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2082 }
2083
2084
2085 void dispc_set_default_color(enum omap_channel channel, u32 color)
2086 {
2087         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2088 }
2089
2090 u32 dispc_get_default_color(enum omap_channel channel)
2091 {
2092         u32 l;
2093
2094         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2095                 channel != OMAP_DSS_CHANNEL_LCD &&
2096                 channel != OMAP_DSS_CHANNEL_LCD2);
2097
2098         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2099
2100         return l;
2101 }
2102
2103 void dispc_set_trans_key(enum omap_channel ch,
2104                 enum omap_dss_trans_key_type type,
2105                 u32 trans_key)
2106 {
2107         if (ch == OMAP_DSS_CHANNEL_LCD)
2108                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2109         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2110                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2111         else /* OMAP_DSS_CHANNEL_LCD2 */
2112                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2113
2114         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2115 }
2116
2117 void dispc_get_trans_key(enum omap_channel ch,
2118                 enum omap_dss_trans_key_type *type,
2119                 u32 *trans_key)
2120 {
2121         if (type) {
2122                 if (ch == OMAP_DSS_CHANNEL_LCD)
2123                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2124                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2125                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2126                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2127                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2128                 else
2129                         BUG();
2130         }
2131
2132         if (trans_key)
2133                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2134 }
2135
2136 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2137 {
2138         if (ch == OMAP_DSS_CHANNEL_LCD)
2139                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2140         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2141                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2142         else /* OMAP_DSS_CHANNEL_LCD2 */
2143                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2144 }
2145 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2146 {
2147         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2148                 return;
2149
2150         if (ch == OMAP_DSS_CHANNEL_LCD)
2151                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2152         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2153                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2154         else /* OMAP_DSS_CHANNEL_LCD2 */
2155                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2156 }
2157 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2158 {
2159         bool enabled;
2160
2161         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2162                 return false;
2163
2164         if (ch == OMAP_DSS_CHANNEL_LCD)
2165                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2166         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2167                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2168         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2169                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2170         else
2171                 BUG();
2172
2173         return enabled;
2174 }
2175
2176
2177 bool dispc_trans_key_enabled(enum omap_channel ch)
2178 {
2179         bool enabled;
2180
2181         if (ch == OMAP_DSS_CHANNEL_LCD)
2182                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2183         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2184                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2185         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2186                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2187         else
2188                 BUG();
2189
2190         return enabled;
2191 }
2192
2193
2194 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2195 {
2196         int code;
2197
2198         switch (data_lines) {
2199         case 12:
2200                 code = 0;
2201                 break;
2202         case 16:
2203                 code = 1;
2204                 break;
2205         case 18:
2206                 code = 2;
2207                 break;
2208         case 24:
2209                 code = 3;
2210                 break;
2211         default:
2212                 BUG();
2213                 return;
2214         }
2215
2216         if (channel == OMAP_DSS_CHANNEL_LCD2)
2217                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2218         else
2219                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2220 }
2221
2222 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2223                 enum omap_parallel_interface_mode mode)
2224 {
2225         u32 l;
2226         int stallmode;
2227         int gpout0 = 1;
2228         int gpout1;
2229
2230         switch (mode) {
2231         case OMAP_DSS_PARALLELMODE_BYPASS:
2232                 stallmode = 0;
2233                 gpout1 = 1;
2234                 break;
2235
2236         case OMAP_DSS_PARALLELMODE_RFBI:
2237                 stallmode = 1;
2238                 gpout1 = 0;
2239                 break;
2240
2241         case OMAP_DSS_PARALLELMODE_DSI:
2242                 stallmode = 1;
2243                 gpout1 = 1;
2244                 break;
2245
2246         default:
2247                 BUG();
2248                 return;
2249         }
2250
2251         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2252                 l = dispc_read_reg(DISPC_CONTROL2);
2253                 l = FLD_MOD(l, stallmode, 11, 11);
2254                 dispc_write_reg(DISPC_CONTROL2, l);
2255         } else {
2256                 l = dispc_read_reg(DISPC_CONTROL);
2257                 l = FLD_MOD(l, stallmode, 11, 11);
2258                 l = FLD_MOD(l, gpout0, 15, 15);
2259                 l = FLD_MOD(l, gpout1, 16, 16);
2260                 dispc_write_reg(DISPC_CONTROL, l);
2261         }
2262 }
2263
2264 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2265                 int vsw, int vfp, int vbp)
2266 {
2267         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2268                 if (hsw < 1 || hsw > 64 ||
2269                                 hfp < 1 || hfp > 256 ||
2270                                 hbp < 1 || hbp > 256 ||
2271                                 vsw < 1 || vsw > 64 ||
2272                                 vfp < 0 || vfp > 255 ||
2273                                 vbp < 0 || vbp > 255)
2274                         return false;
2275         } else {
2276                 if (hsw < 1 || hsw > 256 ||
2277                                 hfp < 1 || hfp > 4096 ||
2278                                 hbp < 1 || hbp > 4096 ||
2279                                 vsw < 1 || vsw > 256 ||
2280                                 vfp < 0 || vfp > 4095 ||
2281                                 vbp < 0 || vbp > 4095)
2282                         return false;
2283         }
2284
2285         return true;
2286 }
2287
2288 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2289 {
2290         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2291                         timings->hbp, timings->vsw,
2292                         timings->vfp, timings->vbp);
2293 }
2294
2295 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2296                 int hfp, int hbp, int vsw, int vfp, int vbp)
2297 {
2298         u32 timing_h, timing_v;
2299
2300         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2301                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2302                         FLD_VAL(hbp-1, 27, 20);
2303
2304                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2305                         FLD_VAL(vbp, 27, 20);
2306         } else {
2307                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2308                         FLD_VAL(hbp-1, 31, 20);
2309
2310                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2311                         FLD_VAL(vbp, 31, 20);
2312         }
2313
2314         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2315         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2316 }
2317
2318 /* change name to mode? */
2319 void dispc_set_lcd_timings(enum omap_channel channel,
2320                 struct omap_video_timings *timings)
2321 {
2322         unsigned xtot, ytot;
2323         unsigned long ht, vt;
2324
2325         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2326                                 timings->hbp, timings->vsw,
2327                                 timings->vfp, timings->vbp))
2328                 BUG();
2329
2330         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2331                         timings->hbp, timings->vsw, timings->vfp,
2332                         timings->vbp);
2333
2334         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2335
2336         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2337         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2338
2339         ht = (timings->pixel_clock * 1000) / xtot;
2340         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2341
2342         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2343                         timings->y_res);
2344         DSSDBG("pck %u\n", timings->pixel_clock);
2345         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2346                         timings->hsw, timings->hfp, timings->hbp,
2347                         timings->vsw, timings->vfp, timings->vbp);
2348
2349         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2350 }
2351
2352 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2353                 u16 pck_div)
2354 {
2355         BUG_ON(lck_div < 1);
2356         BUG_ON(pck_div < 2);
2357
2358         dispc_write_reg(DISPC_DIVISORo(channel),
2359                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2360 }
2361
2362 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2363                 int *pck_div)
2364 {
2365         u32 l;
2366         l = dispc_read_reg(DISPC_DIVISORo(channel));
2367         *lck_div = FLD_GET(l, 23, 16);
2368         *pck_div = FLD_GET(l, 7, 0);
2369 }
2370
2371 unsigned long dispc_fclk_rate(void)
2372 {
2373         struct platform_device *dsidev;
2374         unsigned long r = 0;
2375
2376         switch (dss_get_dispc_clk_source()) {
2377         case OMAP_DSS_CLK_SRC_FCK:
2378                 r = clk_get_rate(dispc.dss_clk);
2379                 break;
2380         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2381                 dsidev = dsi_get_dsidev_from_id(0);
2382                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2383                 break;
2384         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2385                 dsidev = dsi_get_dsidev_from_id(1);
2386                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2387                 break;
2388         default:
2389                 BUG();
2390         }
2391
2392         return r;
2393 }
2394
2395 unsigned long dispc_lclk_rate(enum omap_channel channel)
2396 {
2397         struct platform_device *dsidev;
2398         int lcd;
2399         unsigned long r;
2400         u32 l;
2401
2402         l = dispc_read_reg(DISPC_DIVISORo(channel));
2403
2404         lcd = FLD_GET(l, 23, 16);
2405
2406         switch (dss_get_lcd_clk_source(channel)) {
2407         case OMAP_DSS_CLK_SRC_FCK:
2408                 r = clk_get_rate(dispc.dss_clk);
2409                 break;
2410         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2411                 dsidev = dsi_get_dsidev_from_id(0);
2412                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2413                 break;
2414         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2415                 dsidev = dsi_get_dsidev_from_id(1);
2416                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2417                 break;
2418         default:
2419                 BUG();
2420         }
2421
2422         return r / lcd;
2423 }
2424
2425 unsigned long dispc_pclk_rate(enum omap_channel channel)
2426 {
2427         int pcd;
2428         unsigned long r;
2429         u32 l;
2430
2431         l = dispc_read_reg(DISPC_DIVISORo(channel));
2432
2433         pcd = FLD_GET(l, 7, 0);
2434
2435         r = dispc_lclk_rate(channel);
2436
2437         return r / pcd;
2438 }
2439
2440 void dispc_dump_clocks(struct seq_file *s)
2441 {
2442         int lcd, pcd;
2443         u32 l;
2444         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2445         enum omap_dss_clk_source lcd_clk_src;
2446
2447         if (dispc_runtime_get())
2448                 return;
2449
2450         seq_printf(s, "- DISPC -\n");
2451
2452         seq_printf(s, "dispc fclk source = %s (%s)\n",
2453                         dss_get_generic_clk_source_name(dispc_clk_src),
2454                         dss_feat_get_clk_source_name(dispc_clk_src));
2455
2456         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2457
2458         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2459                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2460                 l = dispc_read_reg(DISPC_DIVISOR);
2461                 lcd = FLD_GET(l, 23, 16);
2462
2463                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2464                                 (dispc_fclk_rate()/lcd), lcd);
2465         }
2466         seq_printf(s, "- LCD1 -\n");
2467
2468         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2469
2470         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2471                 dss_get_generic_clk_source_name(lcd_clk_src),
2472                 dss_feat_get_clk_source_name(lcd_clk_src));
2473
2474         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2475
2476         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2477                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2478         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2479                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2480         if (dss_has_feature(FEAT_MGR_LCD2)) {
2481                 seq_printf(s, "- LCD2 -\n");
2482
2483                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2484
2485                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2486                         dss_get_generic_clk_source_name(lcd_clk_src),
2487                         dss_feat_get_clk_source_name(lcd_clk_src));
2488
2489                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2490
2491                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2492                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2493                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2494                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2495         }
2496
2497         dispc_runtime_put();
2498 }
2499
2500 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2501 void dispc_dump_irqs(struct seq_file *s)
2502 {
2503         unsigned long flags;
2504         struct dispc_irq_stats stats;
2505
2506         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2507
2508         stats = dispc.irq_stats;
2509         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2510         dispc.irq_stats.last_reset = jiffies;
2511
2512         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2513
2514         seq_printf(s, "period %u ms\n",
2515                         jiffies_to_msecs(jiffies - stats.last_reset));
2516
2517         seq_printf(s, "irqs %d\n", stats.irq_count);
2518 #define PIS(x) \
2519         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2520
2521         PIS(FRAMEDONE);
2522         PIS(VSYNC);
2523         PIS(EVSYNC_EVEN);
2524         PIS(EVSYNC_ODD);
2525         PIS(ACBIAS_COUNT_STAT);
2526         PIS(PROG_LINE_NUM);
2527         PIS(GFX_FIFO_UNDERFLOW);
2528         PIS(GFX_END_WIN);
2529         PIS(PAL_GAMMA_MASK);
2530         PIS(OCP_ERR);
2531         PIS(VID1_FIFO_UNDERFLOW);
2532         PIS(VID1_END_WIN);
2533         PIS(VID2_FIFO_UNDERFLOW);
2534         PIS(VID2_END_WIN);
2535         PIS(SYNC_LOST);
2536         PIS(SYNC_LOST_DIGIT);
2537         PIS(WAKEUP);
2538         if (dss_has_feature(FEAT_MGR_LCD2)) {
2539                 PIS(FRAMEDONE2);
2540                 PIS(VSYNC2);
2541                 PIS(ACBIAS_COUNT_STAT2);
2542                 PIS(SYNC_LOST2);
2543         }
2544 #undef PIS
2545 }
2546 #endif
2547
2548 void dispc_dump_regs(struct seq_file *s)
2549 {
2550         int i, j;
2551         const char *mgr_names[] = {
2552                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2553                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2554                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2555         };
2556         const char *ovl_names[] = {
2557                 [OMAP_DSS_GFX]          = "GFX",
2558                 [OMAP_DSS_VIDEO1]       = "VID1",
2559                 [OMAP_DSS_VIDEO2]       = "VID2",
2560         };
2561         const char **p_names;
2562
2563 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2564
2565         if (dispc_runtime_get())
2566                 return;
2567
2568         /* DISPC common registers */
2569         DUMPREG(DISPC_REVISION);
2570         DUMPREG(DISPC_SYSCONFIG);
2571         DUMPREG(DISPC_SYSSTATUS);
2572         DUMPREG(DISPC_IRQSTATUS);
2573         DUMPREG(DISPC_IRQENABLE);
2574         DUMPREG(DISPC_CONTROL);
2575         DUMPREG(DISPC_CONFIG);
2576         DUMPREG(DISPC_CAPABLE);
2577         DUMPREG(DISPC_LINE_STATUS);
2578         DUMPREG(DISPC_LINE_NUMBER);
2579         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2580                 DUMPREG(DISPC_GLOBAL_ALPHA);
2581         if (dss_has_feature(FEAT_MGR_LCD2)) {
2582                 DUMPREG(DISPC_CONTROL2);
2583                 DUMPREG(DISPC_CONFIG2);
2584         }
2585
2586 #undef DUMPREG
2587
2588 #define DISPC_REG(i, name) name(i)
2589 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2590         48 - strlen(#r) - strlen(p_names[i]), " ", \
2591         dispc_read_reg(DISPC_REG(i, r)))
2592
2593         p_names = mgr_names;
2594
2595         /* DISPC channel specific registers */
2596         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2597                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2598                 DUMPREG(i, DISPC_TRANS_COLOR);
2599                 DUMPREG(i, DISPC_SIZE_MGR);
2600
2601                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2602                         continue;
2603
2604                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2605                 DUMPREG(i, DISPC_TRANS_COLOR);
2606                 DUMPREG(i, DISPC_TIMING_H);
2607                 DUMPREG(i, DISPC_TIMING_V);
2608                 DUMPREG(i, DISPC_POL_FREQ);
2609                 DUMPREG(i, DISPC_DIVISORo);
2610                 DUMPREG(i, DISPC_SIZE_MGR);
2611
2612                 DUMPREG(i, DISPC_DATA_CYCLE1);
2613                 DUMPREG(i, DISPC_DATA_CYCLE2);
2614                 DUMPREG(i, DISPC_DATA_CYCLE3);
2615
2616                 if (dss_has_feature(FEAT_CPR)) {
2617                         DUMPREG(i, DISPC_CPR_COEF_R);
2618                         DUMPREG(i, DISPC_CPR_COEF_G);
2619                         DUMPREG(i, DISPC_CPR_COEF_B);
2620                 }
2621         }
2622
2623         p_names = ovl_names;
2624
2625         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2626                 DUMPREG(i, DISPC_OVL_BA0);
2627                 DUMPREG(i, DISPC_OVL_BA1);
2628                 DUMPREG(i, DISPC_OVL_POSITION);
2629                 DUMPREG(i, DISPC_OVL_SIZE);
2630                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2631                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2632                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2633                 DUMPREG(i, DISPC_OVL_ROW_INC);
2634                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2635                 if (dss_has_feature(FEAT_PRELOAD))
2636                         DUMPREG(i, DISPC_OVL_PRELOAD);
2637
2638                 if (i == OMAP_DSS_GFX) {
2639                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2640                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2641                         continue;
2642                 }
2643
2644                 DUMPREG(i, DISPC_OVL_FIR);
2645                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2646                 DUMPREG(i, DISPC_OVL_ACCU0);
2647                 DUMPREG(i, DISPC_OVL_ACCU1);
2648                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2649                         DUMPREG(i, DISPC_OVL_BA0_UV);
2650                         DUMPREG(i, DISPC_OVL_BA1_UV);
2651                         DUMPREG(i, DISPC_OVL_FIR2);
2652                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2653                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2654                 }
2655                 if (dss_has_feature(FEAT_ATTR2))
2656                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2657                 if (dss_has_feature(FEAT_PRELOAD))
2658                         DUMPREG(i, DISPC_OVL_PRELOAD);
2659         }
2660
2661 #undef DISPC_REG
2662 #undef DUMPREG
2663
2664 #define DISPC_REG(plane, name, i) name(plane, i)
2665 #define DUMPREG(plane, name, i) \
2666         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2667         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2668         dispc_read_reg(DISPC_REG(plane, name, i)))
2669
2670         /* Video pipeline coefficient registers */
2671
2672         /* start from OMAP_DSS_VIDEO1 */
2673         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2674                 for (j = 0; j < 8; j++)
2675                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2676
2677                 for (j = 0; j < 8; j++)
2678                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2679
2680                 for (j = 0; j < 5; j++)
2681                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2682
2683                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2684                         for (j = 0; j < 8; j++)
2685                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2686                 }
2687
2688                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2689                         for (j = 0; j < 8; j++)
2690                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2691
2692                         for (j = 0; j < 8; j++)
2693                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2694
2695                         for (j = 0; j < 8; j++)
2696                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2697                 }
2698         }
2699
2700         dispc_runtime_put();
2701
2702 #undef DISPC_REG
2703 #undef DUMPREG
2704 }
2705
2706 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2707                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2708 {
2709         u32 l = 0;
2710
2711         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2712                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2713
2714         l |= FLD_VAL(onoff, 17, 17);
2715         l |= FLD_VAL(rf, 16, 16);
2716         l |= FLD_VAL(ieo, 15, 15);
2717         l |= FLD_VAL(ipc, 14, 14);
2718         l |= FLD_VAL(ihs, 13, 13);
2719         l |= FLD_VAL(ivs, 12, 12);
2720         l |= FLD_VAL(acbi, 11, 8);
2721         l |= FLD_VAL(acb, 7, 0);
2722
2723         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2724 }
2725
2726 void dispc_set_pol_freq(enum omap_channel channel,
2727                 enum omap_panel_config config, u8 acbi, u8 acb)
2728 {
2729         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2730                         (config & OMAP_DSS_LCD_RF) != 0,
2731                         (config & OMAP_DSS_LCD_IEO) != 0,
2732                         (config & OMAP_DSS_LCD_IPC) != 0,
2733                         (config & OMAP_DSS_LCD_IHS) != 0,
2734                         (config & OMAP_DSS_LCD_IVS) != 0,
2735                         acbi, acb);
2736 }
2737
2738 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2739 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2740                 struct dispc_clock_info *cinfo)
2741 {
2742         u16 pcd_min = is_tft ? 2 : 3;
2743         unsigned long best_pck;
2744         u16 best_ld, cur_ld;
2745         u16 best_pd, cur_pd;
2746
2747         best_pck = 0;
2748         best_ld = 0;
2749         best_pd = 0;
2750
2751         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2752                 unsigned long lck = fck / cur_ld;
2753
2754                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2755                         unsigned long pck = lck / cur_pd;
2756                         long old_delta = abs(best_pck - req_pck);
2757                         long new_delta = abs(pck - req_pck);
2758
2759                         if (best_pck == 0 || new_delta < old_delta) {
2760                                 best_pck = pck;
2761                                 best_ld = cur_ld;
2762                                 best_pd = cur_pd;
2763
2764                                 if (pck == req_pck)
2765                                         goto found;
2766                         }
2767
2768                         if (pck < req_pck)
2769                                 break;
2770                 }
2771
2772                 if (lck / pcd_min < req_pck)
2773                         break;
2774         }
2775
2776 found:
2777         cinfo->lck_div = best_ld;
2778         cinfo->pck_div = best_pd;
2779         cinfo->lck = fck / cinfo->lck_div;
2780         cinfo->pck = cinfo->lck / cinfo->pck_div;
2781 }
2782
2783 /* calculate clock rates using dividers in cinfo */
2784 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2785                 struct dispc_clock_info *cinfo)
2786 {
2787         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2788                 return -EINVAL;
2789         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2790                 return -EINVAL;
2791
2792         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2793         cinfo->pck = cinfo->lck / cinfo->pck_div;
2794
2795         return 0;
2796 }
2797
2798 int dispc_set_clock_div(enum omap_channel channel,
2799                 struct dispc_clock_info *cinfo)
2800 {
2801         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2802         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2803
2804         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2805
2806         return 0;
2807 }
2808
2809 int dispc_get_clock_div(enum omap_channel channel,
2810                 struct dispc_clock_info *cinfo)
2811 {
2812         unsigned long fck;
2813
2814         fck = dispc_fclk_rate();
2815
2816         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2817         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2818
2819         cinfo->lck = fck / cinfo->lck_div;
2820         cinfo->pck = cinfo->lck / cinfo->pck_div;
2821
2822         return 0;
2823 }
2824
2825 /* dispc.irq_lock has to be locked by the caller */
2826 static void _omap_dispc_set_irqs(void)
2827 {
2828         u32 mask;
2829         u32 old_mask;
2830         int i;
2831         struct omap_dispc_isr_data *isr_data;
2832
2833         mask = dispc.irq_error_mask;
2834
2835         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2836                 isr_data = &dispc.registered_isr[i];
2837
2838                 if (isr_data->isr == NULL)
2839                         continue;
2840
2841                 mask |= isr_data->mask;
2842         }
2843
2844         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2845         /* clear the irqstatus for newly enabled irqs */
2846         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2847
2848         dispc_write_reg(DISPC_IRQENABLE, mask);
2849 }
2850
2851 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2852 {
2853         int i;
2854         int ret;
2855         unsigned long flags;
2856         struct omap_dispc_isr_data *isr_data;
2857
2858         if (isr == NULL)
2859                 return -EINVAL;
2860
2861         spin_lock_irqsave(&dispc.irq_lock, flags);
2862
2863         /* check for duplicate entry */
2864         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2865                 isr_data = &dispc.registered_isr[i];
2866                 if (isr_data->isr == isr && isr_data->arg == arg &&
2867                                 isr_data->mask == mask) {
2868                         ret = -EINVAL;
2869                         goto err;
2870                 }
2871         }
2872
2873         isr_data = NULL;
2874         ret = -EBUSY;
2875
2876         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2877                 isr_data = &dispc.registered_isr[i];
2878
2879                 if (isr_data->isr != NULL)
2880                         continue;
2881
2882                 isr_data->isr = isr;
2883                 isr_data->arg = arg;
2884                 isr_data->mask = mask;
2885                 ret = 0;
2886
2887                 break;
2888         }
2889
2890         if (ret)
2891                 goto err;
2892
2893         _omap_dispc_set_irqs();
2894
2895         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2896
2897         return 0;
2898 err:
2899         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2900
2901         return ret;
2902 }
2903 EXPORT_SYMBOL(omap_dispc_register_isr);
2904
2905 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2906 {
2907         int i;
2908         unsigned long flags;
2909         int ret = -EINVAL;
2910         struct omap_dispc_isr_data *isr_data;
2911
2912         spin_lock_irqsave(&dispc.irq_lock, flags);
2913
2914         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2915                 isr_data = &dispc.registered_isr[i];
2916                 if (isr_data->isr != isr || isr_data->arg != arg ||
2917                                 isr_data->mask != mask)
2918                         continue;
2919
2920                 /* found the correct isr */
2921
2922                 isr_data->isr = NULL;
2923                 isr_data->arg = NULL;
2924                 isr_data->mask = 0;
2925
2926                 ret = 0;
2927                 break;
2928         }
2929
2930         if (ret == 0)
2931                 _omap_dispc_set_irqs();
2932
2933         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2934
2935         return ret;
2936 }
2937 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2938
2939 #ifdef DEBUG
2940 static void print_irq_status(u32 status)
2941 {
2942         if ((status & dispc.irq_error_mask) == 0)
2943                 return;
2944
2945         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2946
2947 #define PIS(x) \
2948         if (status & DISPC_IRQ_##x) \
2949                 printk(#x " ");
2950         PIS(GFX_FIFO_UNDERFLOW);
2951         PIS(OCP_ERR);
2952         PIS(VID1_FIFO_UNDERFLOW);
2953         PIS(VID2_FIFO_UNDERFLOW);
2954         PIS(SYNC_LOST);
2955         PIS(SYNC_LOST_DIGIT);
2956         if (dss_has_feature(FEAT_MGR_LCD2))
2957                 PIS(SYNC_LOST2);
2958 #undef PIS
2959
2960         printk("\n");
2961 }
2962 #endif
2963
2964 /* Called from dss.c. Note that we don't touch clocks here,
2965  * but we presume they are on because we got an IRQ. However,
2966  * an irq handler may turn the clocks off, so we may not have
2967  * clock later in the function. */
2968 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2969 {
2970         int i;
2971         u32 irqstatus, irqenable;
2972         u32 handledirqs = 0;
2973         u32 unhandled_errors;
2974         struct omap_dispc_isr_data *isr_data;
2975         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2976
2977         spin_lock(&dispc.irq_lock);
2978
2979         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2980         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2981
2982         /* IRQ is not for us */
2983         if (!(irqstatus & irqenable)) {
2984                 spin_unlock(&dispc.irq_lock);
2985                 return IRQ_NONE;
2986         }
2987
2988 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2989         spin_lock(&dispc.irq_stats_lock);
2990         dispc.irq_stats.irq_count++;
2991         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2992         spin_unlock(&dispc.irq_stats_lock);
2993 #endif
2994
2995 #ifdef DEBUG
2996         if (dss_debug)
2997                 print_irq_status(irqstatus);
2998 #endif
2999         /* Ack the interrupt. Do it here before clocks are possibly turned
3000          * off */
3001         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3002         /* flush posted write */
3003         dispc_read_reg(DISPC_IRQSTATUS);
3004
3005         /* make a copy and unlock, so that isrs can unregister
3006          * themselves */
3007         memcpy(registered_isr, dispc.registered_isr,
3008                         sizeof(registered_isr));
3009
3010         spin_unlock(&dispc.irq_lock);
3011
3012         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3013                 isr_data = &registered_isr[i];
3014
3015                 if (!isr_data->isr)
3016                         continue;
3017
3018                 if (isr_data->mask & irqstatus) {
3019                         isr_data->isr(isr_data->arg, irqstatus);
3020                         handledirqs |= isr_data->mask;
3021                 }
3022         }
3023
3024         spin_lock(&dispc.irq_lock);
3025
3026         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3027
3028         if (unhandled_errors) {
3029                 dispc.error_irqs |= unhandled_errors;
3030
3031                 dispc.irq_error_mask &= ~unhandled_errors;
3032                 _omap_dispc_set_irqs();
3033
3034                 schedule_work(&dispc.error_work);
3035         }
3036
3037         spin_unlock(&dispc.irq_lock);
3038
3039         return IRQ_HANDLED;
3040 }
3041
3042 static void dispc_error_worker(struct work_struct *work)
3043 {
3044         int i;
3045         u32 errors;
3046         unsigned long flags;
3047
3048         spin_lock_irqsave(&dispc.irq_lock, flags);
3049         errors = dispc.error_irqs;
3050         dispc.error_irqs = 0;
3051         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3052
3053         dispc_runtime_get();
3054
3055         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3056                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3057                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3058                         struct omap_overlay *ovl;
3059                         ovl = omap_dss_get_overlay(i);
3060
3061                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3062                                 continue;
3063
3064                         if (ovl->id == 0) {
3065                                 dispc_enable_plane(ovl->id, 0);
3066                                 dispc_go(ovl->manager->id);
3067                                 mdelay(50);
3068                                 break;
3069                         }
3070                 }
3071         }
3072
3073         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3074                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3075                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3076                         struct omap_overlay *ovl;
3077                         ovl = omap_dss_get_overlay(i);
3078
3079                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3080                                 continue;
3081
3082                         if (ovl->id == 1) {
3083                                 dispc_enable_plane(ovl->id, 0);
3084                                 dispc_go(ovl->manager->id);
3085                                 mdelay(50);
3086                                 break;
3087                         }
3088                 }
3089         }
3090
3091         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3092                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3093                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3094                         struct omap_overlay *ovl;
3095                         ovl = omap_dss_get_overlay(i);
3096
3097                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3098                                 continue;
3099
3100                         if (ovl->id == 2) {
3101                                 dispc_enable_plane(ovl->id, 0);
3102                                 dispc_go(ovl->manager->id);
3103                                 mdelay(50);
3104                                 break;
3105                         }
3106                 }
3107         }
3108
3109         if (errors & DISPC_IRQ_SYNC_LOST) {
3110                 struct omap_overlay_manager *manager = NULL;
3111                 bool enable = false;
3112
3113                 DSSERR("SYNC_LOST, disabling LCD\n");
3114
3115                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3116                         struct omap_overlay_manager *mgr;
3117                         mgr = omap_dss_get_overlay_manager(i);
3118
3119                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3120                                 manager = mgr;
3121                                 enable = mgr->device->state ==
3122                                                 OMAP_DSS_DISPLAY_ACTIVE;
3123                                 mgr->device->driver->disable(mgr->device);
3124                                 break;
3125                         }
3126                 }
3127
3128                 if (manager) {
3129                         struct omap_dss_device *dssdev = manager->device;
3130                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3131                                 struct omap_overlay *ovl;
3132                                 ovl = omap_dss_get_overlay(i);
3133
3134                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3135                                         continue;
3136
3137                                 if (ovl->id != 0 && ovl->manager == manager)
3138                                         dispc_enable_plane(ovl->id, 0);
3139                         }
3140
3141                         dispc_go(manager->id);
3142                         mdelay(50);
3143                         if (enable)
3144                                 dssdev->driver->enable(dssdev);
3145                 }
3146         }
3147
3148         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3149                 struct omap_overlay_manager *manager = NULL;
3150                 bool enable = false;
3151
3152                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3153
3154                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3155                         struct omap_overlay_manager *mgr;
3156                         mgr = omap_dss_get_overlay_manager(i);
3157
3158                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3159                                 manager = mgr;
3160                                 enable = mgr->device->state ==
3161                                                 OMAP_DSS_DISPLAY_ACTIVE;
3162                                 mgr->device->driver->disable(mgr->device);
3163                                 break;
3164                         }
3165                 }
3166
3167                 if (manager) {
3168                         struct omap_dss_device *dssdev = manager->device;
3169                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3170                                 struct omap_overlay *ovl;
3171                                 ovl = omap_dss_get_overlay(i);
3172
3173                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3174                                         continue;
3175
3176                                 if (ovl->id != 0 && ovl->manager == manager)
3177                                         dispc_enable_plane(ovl->id, 0);
3178                         }
3179
3180                         dispc_go(manager->id);
3181                         mdelay(50);
3182                         if (enable)
3183                                 dssdev->driver->enable(dssdev);
3184                 }
3185         }
3186
3187         if (errors & DISPC_IRQ_SYNC_LOST2) {
3188                 struct omap_overlay_manager *manager = NULL;
3189                 bool enable = false;
3190
3191                 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3192
3193                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3194                         struct omap_overlay_manager *mgr;
3195                         mgr = omap_dss_get_overlay_manager(i);
3196
3197                         if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3198                                 manager = mgr;
3199                                 enable = mgr->device->state ==
3200                                                 OMAP_DSS_DISPLAY_ACTIVE;
3201                                 mgr->device->driver->disable(mgr->device);
3202                                 break;
3203                         }
3204                 }
3205
3206                 if (manager) {
3207                         struct omap_dss_device *dssdev = manager->device;
3208                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3209                                 struct omap_overlay *ovl;
3210                                 ovl = omap_dss_get_overlay(i);
3211
3212                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3213                                         continue;
3214
3215                                 if (ovl->id != 0 && ovl->manager == manager)
3216                                         dispc_enable_plane(ovl->id, 0);
3217                         }
3218
3219                         dispc_go(manager->id);
3220                         mdelay(50);
3221                         if (enable)
3222                                 dssdev->driver->enable(dssdev);
3223                 }
3224         }
3225
3226         if (errors & DISPC_IRQ_OCP_ERR) {
3227                 DSSERR("OCP_ERR\n");
3228                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3229                         struct omap_overlay_manager *mgr;
3230                         mgr = omap_dss_get_overlay_manager(i);
3231
3232                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3233                                 mgr->device->driver->disable(mgr->device);
3234                 }
3235         }
3236
3237         spin_lock_irqsave(&dispc.irq_lock, flags);
3238         dispc.irq_error_mask |= errors;
3239         _omap_dispc_set_irqs();
3240         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3241
3242         dispc_runtime_put();
3243 }
3244
3245 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3246 {
3247         void dispc_irq_wait_handler(void *data, u32 mask)
3248         {
3249                 complete((struct completion *)data);
3250         }
3251
3252         int r;
3253         DECLARE_COMPLETION_ONSTACK(completion);
3254
3255         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3256                         irqmask);
3257
3258         if (r)
3259                 return r;
3260
3261         timeout = wait_for_completion_timeout(&completion, timeout);
3262
3263         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3264
3265         if (timeout == 0)
3266                 return -ETIMEDOUT;
3267
3268         if (timeout == -ERESTARTSYS)
3269                 return -ERESTARTSYS;
3270
3271         return 0;
3272 }
3273
3274 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3275                 unsigned long timeout)
3276 {
3277         void dispc_irq_wait_handler(void *data, u32 mask)
3278         {
3279                 complete((struct completion *)data);
3280         }
3281
3282         int r;
3283         DECLARE_COMPLETION_ONSTACK(completion);
3284
3285         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3286                         irqmask);
3287
3288         if (r)
3289                 return r;
3290
3291         timeout = wait_for_completion_interruptible_timeout(&completion,
3292                         timeout);
3293
3294         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3295
3296         if (timeout == 0)
3297                 return -ETIMEDOUT;
3298
3299         if (timeout == -ERESTARTSYS)
3300                 return -ERESTARTSYS;
3301
3302         return 0;
3303 }
3304
3305 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3306 void dispc_fake_vsync_irq(void)
3307 {
3308         u32 irqstatus = DISPC_IRQ_VSYNC;
3309         int i;
3310
3311         WARN_ON(!in_interrupt());
3312
3313         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3314                 struct omap_dispc_isr_data *isr_data;
3315                 isr_data = &dispc.registered_isr[i];
3316
3317                 if (!isr_data->isr)
3318                         continue;
3319
3320                 if (isr_data->mask & irqstatus)
3321                         isr_data->isr(isr_data->arg, irqstatus);
3322         }
3323 }
3324 #endif
3325
3326 static void _omap_dispc_initialize_irq(void)
3327 {
3328         unsigned long flags;
3329
3330         spin_lock_irqsave(&dispc.irq_lock, flags);
3331
3332         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3333
3334         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3335         if (dss_has_feature(FEAT_MGR_LCD2))
3336                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3337
3338         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3339          * so clear it */
3340         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3341
3342         _omap_dispc_set_irqs();
3343
3344         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3345 }
3346
3347 void dispc_enable_sidle(void)
3348 {
3349         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3350 }
3351
3352 void dispc_disable_sidle(void)
3353 {
3354         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3355 }
3356
3357 static void _omap_dispc_initial_config(void)
3358 {
3359         u32 l;
3360
3361         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3362         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3363                 l = dispc_read_reg(DISPC_DIVISOR);
3364                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3365                 l = FLD_MOD(l, 1, 0, 0);
3366                 l = FLD_MOD(l, 1, 23, 16);
3367                 dispc_write_reg(DISPC_DIVISOR, l);
3368         }
3369
3370         /* FUNCGATED */
3371         if (dss_has_feature(FEAT_FUNCGATED))
3372                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3373
3374         /* L3 firewall setting: enable access to OCM RAM */
3375         /* XXX this should be somewhere in plat-omap */
3376         if (cpu_is_omap24xx())
3377                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3378
3379         _dispc_setup_color_conv_coef();
3380
3381         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3382
3383         dispc_read_plane_fifo_sizes();
3384
3385         dispc_configure_burst_sizes();
3386 }
3387
3388 /* DISPC HW IP initialisation */
3389 static int omap_dispchw_probe(struct platform_device *pdev)
3390 {
3391         u32 rev;
3392         int r = 0;
3393         struct resource *dispc_mem;
3394         struct clk *clk;
3395
3396         dispc.pdev = pdev;
3397
3398         clk = clk_get(&pdev->dev, "fck");
3399         if (IS_ERR(clk)) {
3400                 DSSERR("can't get fck\n");
3401                 r = PTR_ERR(clk);
3402                 goto err_get_clk;
3403         }
3404
3405         dispc.dss_clk = clk;
3406
3407         spin_lock_init(&dispc.irq_lock);
3408
3409 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3410         spin_lock_init(&dispc.irq_stats_lock);
3411         dispc.irq_stats.last_reset = jiffies;
3412 #endif
3413
3414         INIT_WORK(&dispc.error_work, dispc_error_worker);
3415
3416         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3417         if (!dispc_mem) {
3418                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3419                 r = -EINVAL;
3420                 goto err_ioremap;
3421         }
3422         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3423         if (!dispc.base) {
3424                 DSSERR("can't ioremap DISPC\n");
3425                 r = -ENOMEM;
3426                 goto err_ioremap;
3427         }
3428         dispc.irq = platform_get_irq(dispc.pdev, 0);
3429         if (dispc.irq < 0) {
3430                 DSSERR("platform_get_irq failed\n");
3431                 r = -ENODEV;
3432                 goto err_irq;
3433         }
3434
3435         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3436                 "OMAP DISPC", dispc.pdev);
3437         if (r < 0) {
3438                 DSSERR("request_irq failed\n");
3439                 goto err_irq;
3440         }
3441
3442         pm_runtime_enable(&pdev->dev);
3443
3444         r = dispc_runtime_get();
3445         if (r)
3446                 goto err_runtime_get;
3447
3448         _omap_dispc_initial_config();
3449
3450         _omap_dispc_initialize_irq();
3451
3452         rev = dispc_read_reg(DISPC_REVISION);
3453         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3454                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3455
3456         dispc_runtime_put();
3457
3458         return 0;
3459
3460 err_runtime_get:
3461         pm_runtime_disable(&pdev->dev);
3462         free_irq(dispc.irq, dispc.pdev);
3463 err_irq:
3464         iounmap(dispc.base);
3465 err_ioremap:
3466         clk_put(dispc.dss_clk);
3467 err_get_clk:
3468         return r;
3469 }
3470
3471 static int omap_dispchw_remove(struct platform_device *pdev)
3472 {
3473         pm_runtime_disable(&pdev->dev);
3474
3475         clk_put(dispc.dss_clk);
3476
3477         free_irq(dispc.irq, dispc.pdev);
3478         iounmap(dispc.base);
3479         return 0;
3480 }
3481
3482 static int dispc_runtime_suspend(struct device *dev)
3483 {
3484         dispc_save_context();
3485         dss_runtime_put();
3486
3487         return 0;
3488 }
3489
3490 static int dispc_runtime_resume(struct device *dev)
3491 {
3492         int r;
3493
3494         r = dss_runtime_get();
3495         if (r < 0)
3496                 return r;
3497
3498         dispc_restore_context();
3499
3500         return 0;
3501 }
3502
3503 static const struct dev_pm_ops dispc_pm_ops = {
3504         .runtime_suspend = dispc_runtime_suspend,
3505         .runtime_resume = dispc_runtime_resume,
3506 };
3507
3508 static struct platform_driver omap_dispchw_driver = {
3509         .probe          = omap_dispchw_probe,
3510         .remove         = omap_dispchw_remove,
3511         .driver         = {
3512                 .name   = "omapdss_dispc",
3513                 .owner  = THIS_MODULE,
3514                 .pm     = &dispc_pm_ops,
3515         },
3516 };
3517
3518 int dispc_init_platform_driver(void)
3519 {
3520         return platform_driver_register(&omap_dispchw_driver);
3521 }
3522
3523 void dispc_uninit_platform_driver(void)
3524 {
3525         return platform_driver_unregister(&omap_dispchw_driver);
3526 }