Pileus Git - ~andy/linux/blob - drivers/video/exynos/exynos_dp_core.h

   1 /*
   2  * Header file for Samsung DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #ifndef _EXYNOS_DP_CORE_H
  14 #define _EXYNOS_DP_CORE_H
  15
  16 #define DP_TIMEOUT_LOOP_COUNT 100
  17 #define MAX_CR_LOOP 5
  18 #define MAX_EQ_LOOP 5
  19
  20 enum link_rate_type {
  21         LINK_RATE_1_62GBPS = 0x06,
  22         LINK_RATE_2_70GBPS = 0x0a
  23 };
  24
  25 enum link_lane_count_type {
  26         LANE_COUNT1 = 1,
  27         LANE_COUNT2 = 2,
  28         LANE_COUNT4 = 4
  29 };
  30
  31 enum link_training_state {
  32         START,
  33         CLOCK_RECOVERY,
  34         EQUALIZER_TRAINING,
  35         FINISHED,
  36         FAILED
  37 };
  38
  39 enum voltage_swing_level {
  40         VOLTAGE_LEVEL_0,
  41         VOLTAGE_LEVEL_1,
  42         VOLTAGE_LEVEL_2,
  43         VOLTAGE_LEVEL_3,
  44 };
  45
  46 enum pre_emphasis_level {
  47         PRE_EMPHASIS_LEVEL_0,
  48         PRE_EMPHASIS_LEVEL_1,
  49         PRE_EMPHASIS_LEVEL_2,
  50         PRE_EMPHASIS_LEVEL_3,
  51 };
  52
  53 enum pattern_set {
  54         PRBS7,
  55         D10_2,
  56         TRAINING_PTN1,
  57         TRAINING_PTN2,
  58         DP_NONE
  59 };
  60
  61 enum color_space {
  62         COLOR_RGB,
  63         COLOR_YCBCR422,
  64         COLOR_YCBCR444
  65 };
  66
  67 enum color_depth {
  68         COLOR_6,
  69         COLOR_8,
  70         COLOR_10,
  71         COLOR_12
  72 };
  73
  74 enum color_coefficient {
  75         COLOR_YCBCR601,
  76         COLOR_YCBCR709
  77 };
  78
  79 enum dynamic_range {
  80         VESA,
  81         CEA
  82 };
  83
  84 enum pll_status {
  85         PLL_UNLOCKED,
  86         PLL_LOCKED
  87 };
  88
  89 enum clock_recovery_m_value_type {
  90         CALCULATED_M,
  91         REGISTER_M
  92 };
  93
  94 enum video_timing_recognition_type {
  95         VIDEO_TIMING_FROM_CAPTURE,
  96         VIDEO_TIMING_FROM_REGISTER
  97 };
  98
  99 enum analog_power_block {
 100         AUX_BLOCK,
 101         CH0_BLOCK,
 102         CH1_BLOCK,
 103         CH2_BLOCK,
 104         CH3_BLOCK,
 105         ANALOG_TOTAL,
 106         POWER_ALL
 107 };
 108
 109 enum dp_irq_type {
 110         DP_IRQ_TYPE_HP_CABLE_IN,
 111         DP_IRQ_TYPE_HP_CABLE_OUT,
 112         DP_IRQ_TYPE_HP_CHANGE,
 113         DP_IRQ_TYPE_UNKNOWN,
 114 };
 115
 116 struct video_info {
 117         char *name;
 118
 119         bool h_sync_polarity;
 120         bool v_sync_polarity;
 121         bool interlaced;
 122
 123         enum color_space color_space;
 124         enum dynamic_range dynamic_range;
 125         enum color_coefficient ycbcr_coeff;
 126         enum color_depth color_depth;
 127
 128         enum link_rate_type link_rate;
 129         enum link_lane_count_type lane_count;
 130 };
 131
 132 struct link_train {
 133         int eq_loop;
 134         int cr_loop[4];
 135
 136         u8 link_rate;
 137         u8 lane_count;
 138         u8 training_lane[4];
 139
 140         enum link_training_state lt_state;
 141 };
 142
 143 struct exynos_dp_device {
 144         struct device           *dev;
 145         struct clk              *clock;
 146         unsigned int            irq;
 147         void __iomem            *reg_base;
 148         void __iomem            *phy_addr;
 149         unsigned int            enable_mask;
 150
 151         struct video_info       *video_info;
 152         struct link_train       link_train;
 153         struct work_struct      hotplug_work;
 154         struct phy              *phy;
 155 };
 156
 157 /* exynos_dp_reg.c */
 158 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
 159 void exynos_dp_stop_video(struct exynos_dp_device *dp);
 160 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
 161 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
 162 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
 163 void exynos_dp_reset(struct exynos_dp_device *dp);
 164 void exynos_dp_swreset(struct exynos_dp_device *dp);
 165 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
 166 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
 167 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
 168 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 169                                 enum analog_power_block block,
 170                                 bool enable);
 171 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
 172 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
 173 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
 174 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
 175 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
 176 void exynos_dp_init_aux(struct exynos_dp_device *dp);
 177 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
 178 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
 179 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
 180 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 181                                 unsigned int reg_addr,
 182                                 unsigned char data);
 183 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 184                                 unsigned int reg_addr,
 185                                 unsigned char *data);
 186 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 187                                 unsigned int reg_addr,
 188                                 unsigned int count,
 189                                 unsigned char data[]);
 190 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 191                                 unsigned int reg_addr,
 192                                 unsigned int count,
 193                                 unsigned char data[]);
 194 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 195                                 unsigned int device_addr,
 196                                 unsigned int reg_addr);
 197 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 198                                 unsigned int device_addr,
 199                                 unsigned int reg_addr,
 200                                 unsigned int *data);
 201 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 202                                 unsigned int device_addr,
 203                                 unsigned int reg_addr,
 204                                 unsigned int count,
 205                                 unsigned char edid[]);
 206 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
 207 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
 208 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
 209 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
 210 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
 211 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 212                                  enum pattern_set pattern);
 213 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 214 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 215 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 216 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
 217 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 218                                 u32 training_lane);
 219 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 220                                 u32 training_lane);
 221 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 222                                 u32 training_lane);
 223 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 224                                 u32 training_lane);
 225 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
 226 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
 227 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
 228 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
 229 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
 230 void exynos_dp_init_video(struct exynos_dp_device *dp);
 231
 232 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
 233 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
 234 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
 235                         enum clock_recovery_m_value_type type,
 236                         u32 m_value,
 237                         u32 n_value);
 238 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
 239 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
 240 void exynos_dp_start_video(struct exynos_dp_device *dp);
 241 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
 242 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
 243 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
 244 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
 245
 246 /* I2C EDID Chip ID, Slave Address */
 247 #define I2C_EDID_DEVICE_ADDR                    0x50
 248 #define I2C_E_EDID_DEVICE_ADDR                  0x30
 249
 250 #define EDID_BLOCK_LENGTH                       0x80
 251 #define EDID_HEADER_PATTERN                     0x00
 252 #define EDID_EXTENSION_FLAG                     0x7e
 253 #define EDID_CHECKSUM                           0x7f
 254
 255 /* Definition for DPCD Register */
 256 #define DPCD_ADDR_DPCD_REV                      0x0000
 257 #define DPCD_ADDR_MAX_LINK_RATE                 0x0001
 258 #define DPCD_ADDR_MAX_LANE_COUNT                0x0002
 259 #define DPCD_ADDR_LINK_BW_SET                   0x0100
 260 #define DPCD_ADDR_LANE_COUNT_SET                0x0101
 261 #define DPCD_ADDR_TRAINING_PATTERN_SET          0x0102
 262 #define DPCD_ADDR_TRAINING_LANE0_SET            0x0103
 263 #define DPCD_ADDR_LANE0_1_STATUS                0x0202
 264 #define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED     0x0204
 265 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1        0x0206
 266 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3        0x0207
 267 #define DPCD_ADDR_TEST_REQUEST                  0x0218
 268 #define DPCD_ADDR_TEST_RESPONSE                 0x0260
 269 #define DPCD_ADDR_TEST_EDID_CHECKSUM            0x0261
 270 #define DPCD_ADDR_SINK_POWER_STATE              0x0600
 271
 272 /* DPCD_ADDR_MAX_LANE_COUNT */
 273 #define DPCD_ENHANCED_FRAME_CAP(x)              (((x) >> 7) & 0x1)
 274 #define DPCD_MAX_LANE_COUNT(x)                  ((x) & 0x1f)
 275
 276 /* DPCD_ADDR_LANE_COUNT_SET */
 277 #define DPCD_ENHANCED_FRAME_EN                  (0x1 << 7)
 278 #define DPCD_LANE_COUNT_SET(x)                  ((x) & 0x1f)
 279
 280 /* DPCD_ADDR_TRAINING_PATTERN_SET */
 281 #define DPCD_SCRAMBLING_DISABLED                (0x1 << 5)
 282 #define DPCD_SCRAMBLING_ENABLED                 (0x0 << 5)
 283 #define DPCD_TRAINING_PATTERN_2                 (0x2 << 0)
 284 #define DPCD_TRAINING_PATTERN_1                 (0x1 << 0)
 285 #define DPCD_TRAINING_PATTERN_DISABLED          (0x0 << 0)
 286
 287 /* DPCD_ADDR_TRAINING_LANE0_SET */
 288 #define DPCD_MAX_PRE_EMPHASIS_REACHED           (0x1 << 5)
 289 #define DPCD_PRE_EMPHASIS_SET(x)                (((x) & 0x3) << 3)
 290 #define DPCD_PRE_EMPHASIS_GET(x)                (((x) >> 3) & 0x3)
 291 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0       (0x0 << 3)
 292 #define DPCD_MAX_SWING_REACHED                  (0x1 << 2)
 293 #define DPCD_VOLTAGE_SWING_SET(x)               (((x) & 0x3) << 0)
 294 #define DPCD_VOLTAGE_SWING_GET(x)               (((x) >> 0) & 0x3)
 295 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0      (0x0 << 0)
 296
 297 /* DPCD_ADDR_LANE0_1_STATUS */
 298 #define DPCD_LANE_SYMBOL_LOCKED                 (0x1 << 2)
 299 #define DPCD_LANE_CHANNEL_EQ_DONE               (0x1 << 1)
 300 #define DPCD_LANE_CR_DONE                       (0x1 << 0)
 301 #define DPCD_CHANNEL_EQ_BITS                    (DPCD_LANE_CR_DONE|     \
 302                                                  DPCD_LANE_CHANNEL_EQ_DONE|\
 303                                                  DPCD_LANE_SYMBOL_LOCKED)
 304
 305 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
 306 #define DPCD_LINK_STATUS_UPDATED                (0x1 << 7)
 307 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED     (0x1 << 6)
 308 #define DPCD_INTERLANE_ALIGN_DONE               (0x1 << 0)
 309
 310 /* DPCD_ADDR_TEST_REQUEST */
 311 #define DPCD_TEST_EDID_READ                     (0x1 << 2)
 312
 313 /* DPCD_ADDR_TEST_RESPONSE */
 314 #define DPCD_TEST_EDID_CHECKSUM_WRITE           (0x1 << 2)
 315
 316 /* DPCD_ADDR_SINK_POWER_STATE */
 317 #define DPCD_SET_POWER_STATE_D0                 (0x1 << 0)
 318 #define DPCD_SET_POWER_STATE_D4                 (0x2 << 0)
 319
 320 #endif /* _EXYNOS_DP_CORE_H */