Pileus Git - ~andy/linux/blob - drivers/video/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/wait.h>
  32 #include <linux/clk.h>
  33 #include <linux/cpufreq.h>
  34 #include <linux/console.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/slab.h>
  37 #include <linux/delay.h>
  38 #include <linux/lcm.h>
  39 #include <video/da8xx-fb.h>
  40 #include <asm/div64.h>
  41
  42 #define DRIVER_NAME "da8xx_lcdc"
  43
  44 #define LCD_VERSION_1   1
  45 #define LCD_VERSION_2   2
  46
  47 /* LCD Status Register */
  48 #define LCD_END_OF_FRAME1               BIT(9)
  49 #define LCD_END_OF_FRAME0               BIT(8)
  50 #define LCD_PL_LOAD_DONE                BIT(6)
  51 #define LCD_FIFO_UNDERFLOW              BIT(5)
  52 #define LCD_SYNC_LOST                   BIT(2)
  53 #define LCD_FRAME_DONE                  BIT(0)
  54
  55 /* LCD DMA Control Register */
  56 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  57 #define LCD_DMA_BURST_1                 0x0
  58 #define LCD_DMA_BURST_2                 0x1
  59 #define LCD_DMA_BURST_4                 0x2
  60 #define LCD_DMA_BURST_8                 0x3
  61 #define LCD_DMA_BURST_16                0x4
  62 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  63 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  64 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  65 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  66
  67 /* LCD Control Register */
  68 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  69 #define LCD_RASTER_MODE                 0x01
  70
  71 /* LCD Raster Control Register */
  72 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  73 #define PALETTE_AND_DATA                0x00
  74 #define PALETTE_ONLY                    0x01
  75 #define DATA_ONLY                       0x02
  76
  77 #define LCD_MONO_8BIT_MODE              BIT(9)
  78 #define LCD_RASTER_ORDER                BIT(8)
  79 #define LCD_TFT_MODE                    BIT(7)
  80 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  81 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  82 #define LCD_V1_PL_INT_ENA               BIT(4)
  83 #define LCD_V2_PL_INT_ENA               BIT(6)
  84 #define LCD_MONOCHROME_MODE             BIT(1)
  85 #define LCD_RASTER_ENABLE               BIT(0)
  86 #define LCD_TFT_ALT_ENABLE              BIT(23)
  87 #define LCD_STN_565_ENABLE              BIT(24)
  88 #define LCD_V2_DMA_CLK_EN               BIT(2)
  89 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  90 #define LCD_V2_CORE_CLK_EN              BIT(0)
  91 #define LCD_V2_LPP_B10                  26
  92 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
  93 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
  94
  95 /* LCD Raster Timing 2 Register */
  96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  97 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  98 #define LCD_SYNC_CTRL                           BIT(25)
  99 #define LCD_SYNC_EDGE                           BIT(24)
 100 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
 101 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
 102 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
 103
 104 /* LCD Block */
 105 #define  LCD_PID_REG                            0x0
 106 #define  LCD_CTRL_REG                           0x4
 107 #define  LCD_STAT_REG                           0x8
 108 #define  LCD_RASTER_CTRL_REG                    0x28
 109 #define  LCD_RASTER_TIMING_0_REG                0x2C
 110 #define  LCD_RASTER_TIMING_1_REG                0x30
 111 #define  LCD_RASTER_TIMING_2_REG                0x34
 112 #define  LCD_DMA_CTRL_REG                       0x40
 113 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
 114 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
 115 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
 116 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
 117
 118 /* Interrupt Registers available only in Version 2 */
 119 #define  LCD_RAW_STAT_REG                       0x58
 120 #define  LCD_MASKED_STAT_REG                    0x5c
 121 #define  LCD_INT_ENABLE_SET_REG                 0x60
 122 #define  LCD_INT_ENABLE_CLR_REG                 0x64
 123 #define  LCD_END_OF_INT_IND_REG                 0x68
 124
 125 /* Clock registers available only on Version 2 */
 126 #define  LCD_CLK_ENABLE_REG                     0x6c
 127 #define  LCD_CLK_RESET_REG                      0x70
 128 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 129
 130 #define LCD_NUM_BUFFERS 2
 131
 132 #define WSI_TIMEOUT     50
 133 #define PALETTE_SIZE    256
 134
 135 #define CLK_MIN_DIV     2
 136 #define CLK_MAX_DIV     255
 137
 138 static void __iomem *da8xx_fb_reg_base;
 139 static unsigned int lcd_revision;
 140 static irq_handler_t lcdc_irq_handler;
 141 static wait_queue_head_t frame_done_wq;
 142 static int frame_done_flag;
 143
 144 static unsigned int lcdc_read(unsigned int addr)
 145 {
 146         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 147 }
 148
 149 static void lcdc_write(unsigned int val, unsigned int addr)
 150 {
 151         __raw_writel(val, da8xx_fb_reg_base + (addr));
 152 }
 153
 154 struct da8xx_fb_par {
 155         struct device           *dev;
 156         resource_size_t p_palette_base;
 157         unsigned char *v_palette_base;
 158         dma_addr_t              vram_phys;
 159         unsigned long           vram_size;
 160         void                    *vram_virt;
 161         unsigned int            dma_start;
 162         unsigned int            dma_end;
 163         struct clk *lcdc_clk;
 164         int irq;
 165         unsigned int palette_sz;
 166         int blank;
 167         wait_queue_head_t       vsync_wait;
 168         int                     vsync_flag;
 169         int                     vsync_timeout;
 170         spinlock_t              lock_for_chan_update;
 171
 172         /*
 173          * LCDC has 2 ping pong DMA channels, channel 0
 174          * and channel 1.
 175          */
 176         unsigned int            which_dma_channel_done;
 177 #ifdef CONFIG_CPU_FREQ
 178         struct notifier_block   freq_transition;
 179 #endif
 180         unsigned int            lcdc_clk_rate;
 181         void (*panel_power_ctrl)(int);
 182         u32 pseudo_palette[16];
 183         struct fb_videomode     mode;
 184         struct lcd_ctrl_config  cfg;
 185 };
 186
 187 static struct fb_var_screeninfo da8xx_fb_var;
 188
 189 static struct fb_fix_screeninfo da8xx_fb_fix = {
 190         .id = "DA8xx FB Drv",
 191         .type = FB_TYPE_PACKED_PIXELS,
 192         .type_aux = 0,
 193         .visual = FB_VISUAL_PSEUDOCOLOR,
 194         .xpanstep = 0,
 195         .ypanstep = 1,
 196         .ywrapstep = 0,
 197         .accel = FB_ACCEL_NONE
 198 };
 199
 200 static struct fb_videomode known_lcd_panels[] = {
 201         /* Sharp LCD035Q3DG01 */
 202         [0] = {
 203                 .name           = "Sharp_LCD035Q3DG01",
 204                 .xres           = 320,
 205                 .yres           = 240,
 206                 .pixclock       = KHZ2PICOS(4607),
 207                 .left_margin    = 6,
 208                 .right_margin   = 8,
 209                 .upper_margin   = 2,
 210                 .lower_margin   = 2,
 211                 .hsync_len      = 0,
 212                 .vsync_len      = 0,
 213                 .sync           = FB_SYNC_CLK_INVERT |
 214                         FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 215         },
 216         /* Sharp LK043T1DG01 */
 217         [1] = {
 218                 .name           = "Sharp_LK043T1DG01",
 219                 .xres           = 480,
 220                 .yres           = 272,
 221                 .pixclock       = KHZ2PICOS(7833),
 222                 .left_margin    = 2,
 223                 .right_margin   = 2,
 224                 .upper_margin   = 2,
 225                 .lower_margin   = 2,
 226                 .hsync_len      = 41,
 227                 .vsync_len      = 10,
 228                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 229                 .flag           = 0,
 230         },
 231         [2] = {
 232                 /* Hitachi SP10Q010 */
 233                 .name           = "SP10Q010",
 234                 .xres           = 320,
 235                 .yres           = 240,
 236                 .pixclock       = KHZ2PICOS(7833),
 237                 .left_margin    = 10,
 238                 .right_margin   = 10,
 239                 .upper_margin   = 10,
 240                 .lower_margin   = 10,
 241                 .hsync_len      = 10,
 242                 .vsync_len      = 10,
 243                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 244                 .flag           = 0,
 245         },
 246 };
 247
 248 static bool da8xx_fb_is_raster_enabled(void)
 249 {
 250         return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
 251 }
 252
 253 /* Enable the Raster Engine of the LCD Controller */
 254 static void lcd_enable_raster(void)
 255 {
 256         u32 reg;
 257
 258         /* Put LCDC in reset for several cycles */
 259         if (lcd_revision == LCD_VERSION_2)
 260                 /* Write 1 to reset LCDC */
 261                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 262         mdelay(1);
 263
 264         /* Bring LCDC out of reset */
 265         if (lcd_revision == LCD_VERSION_2)
 266                 lcdc_write(0, LCD_CLK_RESET_REG);
 267         mdelay(1);
 268
 269         /* Above reset sequence doesnot reset register context */
 270         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 271         if (!(reg & LCD_RASTER_ENABLE))
 272                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 273 }
 274
 275 /* Disable the Raster Engine of the LCD Controller */
 276 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
 277 {
 278         u32 reg;
 279         int ret;
 280
 281         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 282         if (reg & LCD_RASTER_ENABLE)
 283                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 284         else
 285                 /* return if already disabled */
 286                 return;
 287
 288         if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
 289                         (lcd_revision == LCD_VERSION_2)) {
 290                 frame_done_flag = 0;
 291                 ret = wait_event_interruptible_timeout(frame_done_wq,
 292                                 frame_done_flag != 0,
 293                                 msecs_to_jiffies(50));
 294                 if (ret == 0)
 295                         pr_err("LCD Controller timed out\n");
 296         }
 297 }
 298
 299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 300 {
 301         u32 start;
 302         u32 end;
 303         u32 reg_ras;
 304         u32 reg_dma;
 305         u32 reg_int;
 306
 307         /* init reg to clear PLM (loading mode) fields */
 308         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 309         reg_ras &= ~(3 << 20);
 310
 311         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 312
 313         if (load_mode == LOAD_DATA) {
 314                 start    = par->dma_start;
 315                 end      = par->dma_end;
 316
 317                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 318                 if (lcd_revision == LCD_VERSION_1) {
 319                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 320                 } else {
 321                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 322                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 323                                 LCD_V2_END_OF_FRAME1_INT_ENA |
 324                                 LCD_FRAME_DONE | LCD_SYNC_LOST;
 325                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 326                 }
 327                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 328
 329                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 330                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 331                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 332                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 333         } else if (load_mode == LOAD_PALETTE) {
 334                 start    = par->p_palette_base;
 335                 end      = start + par->palette_sz - 1;
 336
 337                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 338
 339                 if (lcd_revision == LCD_VERSION_1) {
 340                         reg_ras |= LCD_V1_PL_INT_ENA;
 341                 } else {
 342                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 343                                 LCD_V2_PL_INT_ENA;
 344                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 345                 }
 346
 347                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 348                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 349         }
 350
 351         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 352         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 353
 354         /*
 355          * The Raster enable bit must be set after all other control fields are
 356          * set.
 357          */
 358         lcd_enable_raster();
 359 }
 360
 361 /* Configure the Burst Size and fifo threhold of DMA */
 362 static int lcd_cfg_dma(int burst_size, int fifo_th)
 363 {
 364         u32 reg;
 365
 366         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 367         switch (burst_size) {
 368         case 1:
 369                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 370                 break;
 371         case 2:
 372                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 373                 break;
 374         case 4:
 375                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 376                 break;
 377         case 8:
 378                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 379                 break;
 380         case 16:
 381         default:
 382                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 383                 break;
 384         }
 385
 386         reg |= (fifo_th << 8);
 387
 388         lcdc_write(reg, LCD_DMA_CTRL_REG);
 389
 390         return 0;
 391 }
 392
 393 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 394 {
 395         u32 reg;
 396
 397         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 398         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 399         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 400                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 401         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 402 }
 403
 404 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 405                 int front_porch)
 406 {
 407         u32 reg;
 408
 409         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 410         reg |= (((back_porch-1) & 0xff) << 24)
 411             | (((front_porch-1) & 0xff) << 16)
 412             | (((pulse_width-1) & 0x3f) << 10);
 413         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 414 }
 415
 416 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 417                 int front_porch)
 418 {
 419         u32 reg;
 420
 421         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 422         reg |= ((back_porch & 0xff) << 24)
 423             | ((front_porch & 0xff) << 16)
 424             | (((pulse_width-1) & 0x3f) << 10);
 425         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 426 }
 427
 428 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
 429                 struct fb_videomode *panel)
 430 {
 431         u32 reg;
 432         u32 reg_int;
 433
 434         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 435                                                 LCD_MONO_8BIT_MODE |
 436                                                 LCD_MONOCHROME_MODE);
 437
 438         switch (cfg->panel_shade) {
 439         case MONOCHROME:
 440                 reg |= LCD_MONOCHROME_MODE;
 441                 if (cfg->mono_8bit_mode)
 442                         reg |= LCD_MONO_8BIT_MODE;
 443                 break;
 444         case COLOR_ACTIVE:
 445                 reg |= LCD_TFT_MODE;
 446                 if (cfg->tft_alt_mode)
 447                         reg |= LCD_TFT_ALT_ENABLE;
 448                 break;
 449
 450         case COLOR_PASSIVE:
 451                 /* AC bias applicable only for Pasive panels */
 452                 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 453                 if (cfg->bpp == 12 && cfg->stn_565_mode)
 454                         reg |= LCD_STN_565_ENABLE;
 455                 break;
 456
 457         default:
 458                 return -EINVAL;
 459         }
 460
 461         /* enable additional interrupts here */
 462         if (lcd_revision == LCD_VERSION_1) {
 463                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 464         } else {
 465                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 466                         LCD_V2_UNDERFLOW_INT_ENA;
 467                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 468         }
 469
 470         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 471
 472         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 473
 474         reg |= LCD_SYNC_CTRL;
 475
 476         if (cfg->sync_edge)
 477                 reg |= LCD_SYNC_EDGE;
 478         else
 479                 reg &= ~LCD_SYNC_EDGE;
 480
 481         if (panel->sync & FB_SYNC_HOR_HIGH_ACT)
 482                 reg |= LCD_INVERT_LINE_CLOCK;
 483         else
 484                 reg &= ~LCD_INVERT_LINE_CLOCK;
 485
 486         if (panel->sync & FB_SYNC_VERT_HIGH_ACT)
 487                 reg |= LCD_INVERT_FRAME_CLOCK;
 488         else
 489                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 490
 491         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 492
 493         return 0;
 494 }
 495
 496 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 497                 u32 bpp, u32 raster_order)
 498 {
 499         u32 reg;
 500
 501         if (bpp > 16 && lcd_revision == LCD_VERSION_1)
 502                 return -EINVAL;
 503
 504         /* Set the Panel Width */
 505         /* Pixels per line = (PPL + 1)*16 */
 506         if (lcd_revision == LCD_VERSION_1) {
 507                 /*
 508                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 509                  * pixels.
 510                  */
 511                 width &= 0x3f0;
 512         } else {
 513                 /*
 514                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 515                  * pixels.
 516                  */
 517                 width &= 0x7f0;
 518         }
 519
 520         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 521         reg &= 0xfffffc00;
 522         if (lcd_revision == LCD_VERSION_1) {
 523                 reg |= ((width >> 4) - 1) << 4;
 524         } else {
 525                 width = (width >> 4) - 1;
 526                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 527         }
 528         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 529
 530         /* Set the Panel Height */
 531         /* Set bits 9:0 of Lines Per Pixel */
 532         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 533         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 534         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 535
 536         /* Set bit 10 of Lines Per Pixel */
 537         if (lcd_revision == LCD_VERSION_2) {
 538                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 539                 reg |= ((height - 1) & 0x400) << 16;
 540                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 541         }
 542
 543         /* Set the Raster Order of the Frame Buffer */
 544         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 545         if (raster_order)
 546                 reg |= LCD_RASTER_ORDER;
 547
 548         par->palette_sz = 16 * 2;
 549
 550         switch (bpp) {
 551         case 1:
 552         case 2:
 553         case 4:
 554         case 16:
 555                 break;
 556         case 24:
 557                 reg |= LCD_V2_TFT_24BPP_MODE;
 558                 break;
 559         case 32:
 560                 reg |= LCD_V2_TFT_24BPP_MODE;
 561                 reg |= LCD_V2_TFT_24BPP_UNPACK;
 562                 break;
 563         case 8:
 564                 par->palette_sz = 256 * 2;
 565                 break;
 566
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 572
 573         return 0;
 574 }
 575
 576 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 577 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 578                               unsigned blue, unsigned transp,
 579                               struct fb_info *info)
 580 {
 581         struct da8xx_fb_par *par = info->par;
 582         unsigned short *palette = (unsigned short *) par->v_palette_base;
 583         u_short pal;
 584         int update_hw = 0;
 585
 586         if (regno > 255)
 587                 return 1;
 588
 589         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 590                 return 1;
 591
 592         if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 593                 return -EINVAL;
 594
 595         switch (info->fix.visual) {
 596         case FB_VISUAL_TRUECOLOR:
 597                 red = CNVT_TOHW(red, info->var.red.length);
 598                 green = CNVT_TOHW(green, info->var.green.length);
 599                 blue = CNVT_TOHW(blue, info->var.blue.length);
 600                 break;
 601         case FB_VISUAL_PSEUDOCOLOR:
 602                 switch (info->var.bits_per_pixel) {
 603                 case 4:
 604                         if (regno > 15)
 605                                 return -EINVAL;
 606
 607                         if (info->var.grayscale) {
 608                                 pal = regno;
 609                         } else {
 610                                 red >>= 4;
 611                                 green >>= 8;
 612                                 blue >>= 12;
 613
 614                                 pal = red & 0x0f00;
 615                                 pal |= green & 0x00f0;
 616                                 pal |= blue & 0x000f;
 617                         }
 618                         if (regno == 0)
 619                                 pal |= 0x2000;
 620                         palette[regno] = pal;
 621                         break;
 622
 623                 case 8:
 624                         red >>= 4;
 625                         green >>= 8;
 626                         blue >>= 12;
 627
 628                         pal = (red & 0x0f00);
 629                         pal |= (green & 0x00f0);
 630                         pal |= (blue & 0x000f);
 631
 632                         if (palette[regno] != pal) {
 633                                 update_hw = 1;
 634                                 palette[regno] = pal;
 635                         }
 636                         break;
 637                 }
 638                 break;
 639         }
 640
 641         /* Truecolor has hardware independent palette */
 642         if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
 643                 u32 v;
 644
 645                 if (regno > 15)
 646                         return -EINVAL;
 647
 648                 v = (red << info->var.red.offset) |
 649                         (green << info->var.green.offset) |
 650                         (blue << info->var.blue.offset);
 651
 652                 switch (info->var.bits_per_pixel) {
 653                 case 16:
 654                         ((u16 *) (info->pseudo_palette))[regno] = v;
 655                         break;
 656                 case 24:
 657                 case 32:
 658                         ((u32 *) (info->pseudo_palette))[regno] = v;
 659                         break;
 660                 }
 661                 if (palette[0] != 0x4000) {
 662                         update_hw = 1;
 663                         palette[0] = 0x4000;
 664                 }
 665         }
 666
 667         /* Update the palette in the h/w as needed. */
 668         if (update_hw)
 669                 lcd_blit(LOAD_PALETTE, par);
 670
 671         return 0;
 672 }
 673 #undef CNVT_TOHW
 674
 675 static void da8xx_fb_lcd_reset(void)
 676 {
 677         /* DMA has to be disabled */
 678         lcdc_write(0, LCD_DMA_CTRL_REG);
 679         lcdc_write(0, LCD_RASTER_CTRL_REG);
 680
 681         if (lcd_revision == LCD_VERSION_2) {
 682                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 683                 /* Write 1 to reset */
 684                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 685                 lcdc_write(0, LCD_CLK_RESET_REG);
 686         }
 687 }
 688
 689 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
 690                                               unsigned lcdc_clk_div,
 691                                               unsigned lcdc_clk_rate)
 692 {
 693         int ret;
 694
 695         if (par->lcdc_clk_rate != lcdc_clk_rate) {
 696                 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
 697                 if (IS_ERR_VALUE(ret)) {
 698                         dev_err(par->dev,
 699                                 "unable to set clock rate at %u\n",
 700                                 lcdc_clk_rate);
 701                         return ret;
 702                 }
 703                 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
 704         }
 705
 706         /* Configure the LCD clock divisor. */
 707         lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
 708                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 709
 710         if (lcd_revision == LCD_VERSION_2)
 711                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 712                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 713
 714         return 0;
 715 }
 716
 717 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
 718                                               unsigned pixclock,
 719                                               unsigned *lcdc_clk_rate)
 720 {
 721         unsigned lcdc_clk_div;
 722
 723         pixclock = PICOS2KHZ(pixclock) * 1000;
 724
 725         *lcdc_clk_rate = par->lcdc_clk_rate;
 726
 727         if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
 728                 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
 729                                                 pixclock * CLK_MAX_DIV);
 730                 lcdc_clk_div = CLK_MAX_DIV;
 731         } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
 732                 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
 733                                                 pixclock * CLK_MIN_DIV);
 734                 lcdc_clk_div = CLK_MIN_DIV;
 735         } else {
 736                 lcdc_clk_div = *lcdc_clk_rate / pixclock;
 737         }
 738
 739         return lcdc_clk_div;
 740 }
 741
 742 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
 743                                             struct fb_videomode *mode)
 744 {
 745         unsigned lcdc_clk_rate;
 746         unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
 747                                                           &lcdc_clk_rate);
 748
 749         return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
 750 }
 751
 752 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
 753                                           unsigned pixclock)
 754 {
 755         unsigned lcdc_clk_div, lcdc_clk_rate;
 756
 757         lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
 758         return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
 759 }
 760
 761 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 762                 struct fb_videomode *panel)
 763 {
 764         u32 bpp;
 765         int ret = 0;
 766
 767         ret = da8xx_fb_calc_config_clk_divider(par, panel);
 768         if (IS_ERR_VALUE(ret)) {
 769                 dev_err(par->dev, "unable to configure clock\n");
 770                 return ret;
 771         }
 772
 773         if (panel->sync & FB_SYNC_CLK_INVERT)
 774                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 775                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 776         else
 777                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 778                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 779
 780         /* Configure the DMA burst size and fifo threshold. */
 781         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
 782         if (ret < 0)
 783                 return ret;
 784
 785         /* Configure the vertical and horizontal sync properties. */
 786         lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
 787                         panel->lower_margin);
 788         lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
 789                         panel->right_margin);
 790
 791         /* Configure for disply */
 792         ret = lcd_cfg_display(cfg, panel);
 793         if (ret < 0)
 794                 return ret;
 795
 796         bpp = cfg->bpp;
 797
 798         if (bpp == 12)
 799                 bpp = 16;
 800         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
 801                                 (unsigned int)panel->yres, bpp,
 802                                 cfg->raster_order);
 803         if (ret < 0)
 804                 return ret;
 805
 806         /* Configure FDD */
 807         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 808                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 809
 810         return 0;
 811 }
 812
 813 /* IRQ handler for version 2 of LCDC */
 814 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 815 {
 816         struct da8xx_fb_par *par = arg;
 817         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 818
 819         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 820                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 821                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 822                 lcd_enable_raster();
 823         } else if (stat & LCD_PL_LOAD_DONE) {
 824                 /*
 825                  * Must disable raster before changing state of any control bit.
 826                  * And also must be disabled before clearing the PL loading
 827                  * interrupt via the following write to the status register. If
 828                  * this is done after then one gets multiple PL done interrupts.
 829                  */
 830                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 831
 832                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 833
 834                 /* Disable PL completion interrupt */
 835                 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
 836
 837                 /* Setup and start data loading mode */
 838                 lcd_blit(LOAD_DATA, par);
 839         } else {
 840                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 841
 842                 if (stat & LCD_END_OF_FRAME0) {
 843                         par->which_dma_channel_done = 0;
 844                         lcdc_write(par->dma_start,
 845                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 846                         lcdc_write(par->dma_end,
 847                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 848                         par->vsync_flag = 1;
 849                         wake_up_interruptible(&par->vsync_wait);
 850                 }
 851
 852                 if (stat & LCD_END_OF_FRAME1) {
 853                         par->which_dma_channel_done = 1;
 854                         lcdc_write(par->dma_start,
 855                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 856                         lcdc_write(par->dma_end,
 857                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 858                         par->vsync_flag = 1;
 859                         wake_up_interruptible(&par->vsync_wait);
 860                 }
 861
 862                 /* Set only when controller is disabled and at the end of
 863                  * active frame
 864                  */
 865                 if (stat & BIT(0)) {
 866                         frame_done_flag = 1;
 867                         wake_up_interruptible(&frame_done_wq);
 868                 }
 869         }
 870
 871         lcdc_write(0, LCD_END_OF_INT_IND_REG);
 872         return IRQ_HANDLED;
 873 }
 874
 875 /* IRQ handler for version 1 LCDC */
 876 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 877 {
 878         struct da8xx_fb_par *par = arg;
 879         u32 stat = lcdc_read(LCD_STAT_REG);
 880         u32 reg_ras;
 881
 882         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 883                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 884                 lcdc_write(stat, LCD_STAT_REG);
 885                 lcd_enable_raster();
 886         } else if (stat & LCD_PL_LOAD_DONE) {
 887                 /*
 888                  * Must disable raster before changing state of any control bit.
 889                  * And also must be disabled before clearing the PL loading
 890                  * interrupt via the following write to the status register. If
 891                  * this is done after then one gets multiple PL done interrupts.
 892                  */
 893                 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
 894
 895                 lcdc_write(stat, LCD_STAT_REG);
 896
 897                 /* Disable PL completion inerrupt */
 898                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 899                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 900                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 901
 902                 /* Setup and start data loading mode */
 903                 lcd_blit(LOAD_DATA, par);
 904         } else {
 905                 lcdc_write(stat, LCD_STAT_REG);
 906
 907                 if (stat & LCD_END_OF_FRAME0) {
 908                         par->which_dma_channel_done = 0;
 909                         lcdc_write(par->dma_start,
 910                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 911                         lcdc_write(par->dma_end,
 912                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 913                         par->vsync_flag = 1;
 914                         wake_up_interruptible(&par->vsync_wait);
 915                 }
 916
 917                 if (stat & LCD_END_OF_FRAME1) {
 918                         par->which_dma_channel_done = 1;
 919                         lcdc_write(par->dma_start,
 920                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 921                         lcdc_write(par->dma_end,
 922                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 923                         par->vsync_flag = 1;
 924                         wake_up_interruptible(&par->vsync_wait);
 925                 }
 926         }
 927
 928         return IRQ_HANDLED;
 929 }
 930
 931 static int fb_check_var(struct fb_var_screeninfo *var,
 932                         struct fb_info *info)
 933 {
 934         int err = 0;
 935         struct da8xx_fb_par *par = info->par;
 936         int bpp = var->bits_per_pixel >> 3;
 937         unsigned long line_size = var->xres_virtual * bpp;
 938
 939         if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
 940                 return -EINVAL;
 941
 942         switch (var->bits_per_pixel) {
 943         case 1:
 944         case 8:
 945                 var->red.offset = 0;
 946                 var->red.length = 8;
 947                 var->green.offset = 0;
 948                 var->green.length = 8;
 949                 var->blue.offset = 0;
 950                 var->blue.length = 8;
 951                 var->transp.offset = 0;
 952                 var->transp.length = 0;
 953                 var->nonstd = 0;
 954                 break;
 955         case 4:
 956                 var->red.offset = 0;
 957                 var->red.length = 4;
 958                 var->green.offset = 0;
 959                 var->green.length = 4;
 960                 var->blue.offset = 0;
 961                 var->blue.length = 4;
 962                 var->transp.offset = 0;
 963                 var->transp.length = 0;
 964                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
 965                 break;
 966         case 16:                /* RGB 565 */
 967                 var->red.offset = 11;
 968                 var->red.length = 5;
 969                 var->green.offset = 5;
 970                 var->green.length = 6;
 971                 var->blue.offset = 0;
 972                 var->blue.length = 5;
 973                 var->transp.offset = 0;
 974                 var->transp.length = 0;
 975                 var->nonstd = 0;
 976                 break;
 977         case 24:
 978                 var->red.offset = 16;
 979                 var->red.length = 8;
 980                 var->green.offset = 8;
 981                 var->green.length = 8;
 982                 var->blue.offset = 0;
 983                 var->blue.length = 8;
 984                 var->nonstd = 0;
 985                 break;
 986         case 32:
 987                 var->transp.offset = 24;
 988                 var->transp.length = 8;
 989                 var->red.offset = 16;
 990                 var->red.length = 8;
 991                 var->green.offset = 8;
 992                 var->green.length = 8;
 993                 var->blue.offset = 0;
 994                 var->blue.length = 8;
 995                 var->nonstd = 0;
 996                 break;
 997         default:
 998                 err = -EINVAL;
 999         }
1000
1001         var->red.msb_right = 0;
1002         var->green.msb_right = 0;
1003         var->blue.msb_right = 0;
1004         var->transp.msb_right = 0;
1005
1006         if (line_size * var->yres_virtual > par->vram_size)
1007                 var->yres_virtual = par->vram_size / line_size;
1008
1009         if (var->yres > var->yres_virtual)
1010                 var->yres = var->yres_virtual;
1011
1012         if (var->xres > var->xres_virtual)
1013                 var->xres = var->xres_virtual;
1014
1015         if (var->xres + var->xoffset > var->xres_virtual)
1016                 var->xoffset = var->xres_virtual - var->xres;
1017         if (var->yres + var->yoffset > var->yres_virtual)
1018                 var->yoffset = var->yres_virtual - var->yres;
1019
1020         var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1021
1022         return err;
1023 }
1024
1025 #ifdef CONFIG_CPU_FREQ
1026 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1027                                      unsigned long val, void *data)
1028 {
1029         struct da8xx_fb_par *par;
1030
1031         par = container_of(nb, struct da8xx_fb_par, freq_transition);
1032         if (val == CPUFREQ_POSTCHANGE) {
1033                 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1034                         par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1035                         lcd_disable_raster(DA8XX_FRAME_WAIT);
1036                         da8xx_fb_calc_config_clk_divider(par, &par->mode);
1037                         if (par->blank == FB_BLANK_UNBLANK)
1038                                 lcd_enable_raster();
1039                 }
1040         }
1041
1042         return 0;
1043 }
1044
1045 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1046 {
1047         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1048
1049         return cpufreq_register_notifier(&par->freq_transition,
1050                                          CPUFREQ_TRANSITION_NOTIFIER);
1051 }
1052
1053 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1054 {
1055         cpufreq_unregister_notifier(&par->freq_transition,
1056                                     CPUFREQ_TRANSITION_NOTIFIER);
1057 }
1058 #endif
1059
1060 static int fb_remove(struct platform_device *dev)
1061 {
1062         struct fb_info *info = dev_get_drvdata(&dev->dev);
1063
1064         if (info) {
1065                 struct da8xx_fb_par *par = info->par;
1066
1067 #ifdef CONFIG_CPU_FREQ
1068                 lcd_da8xx_cpufreq_deregister(par);
1069 #endif
1070                 if (par->panel_power_ctrl)
1071                         par->panel_power_ctrl(0);
1072
1073                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1074                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1075
1076                 /* disable DMA  */
1077                 lcdc_write(0, LCD_DMA_CTRL_REG);
1078
1079                 unregister_framebuffer(info);
1080                 fb_dealloc_cmap(&info->cmap);
1081                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1082                                   par->p_palette_base);
1083                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1084                                   par->vram_phys);
1085                 pm_runtime_put_sync(&dev->dev);
1086                 pm_runtime_disable(&dev->dev);
1087                 framebuffer_release(info);
1088
1089         }
1090         return 0;
1091 }
1092
1093 /*
1094  * Function to wait for vertical sync which for this LCD peripheral
1095  * translates into waiting for the current raster frame to complete.
1096  */
1097 static int fb_wait_for_vsync(struct fb_info *info)
1098 {
1099         struct da8xx_fb_par *par = info->par;
1100         int ret;
1101
1102         /*
1103          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1104          * race condition here where the ISR could have occurred just before or
1105          * just after this set. But since we are just coarsely waiting for
1106          * a frame to complete then that's OK. i.e. if the frame completed
1107          * just before this code executed then we have to wait another full
1108          * frame time but there is no way to avoid such a situation. On the
1109          * other hand if the frame completed just after then we don't need
1110          * to wait long at all. Either way we are guaranteed to return to the
1111          * user immediately after a frame completion which is all that is
1112          * required.
1113          */
1114         par->vsync_flag = 0;
1115         ret = wait_event_interruptible_timeout(par->vsync_wait,
1116                                                par->vsync_flag != 0,
1117                                                par->vsync_timeout);
1118         if (ret < 0)
1119                 return ret;
1120         if (ret == 0)
1121                 return -ETIMEDOUT;
1122
1123         return 0;
1124 }
1125
1126 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1127                           unsigned long arg)
1128 {
1129         struct lcd_sync_arg sync_arg;
1130
1131         switch (cmd) {
1132         case FBIOGET_CONTRAST:
1133         case FBIOPUT_CONTRAST:
1134         case FBIGET_BRIGHTNESS:
1135         case FBIPUT_BRIGHTNESS:
1136         case FBIGET_COLOR:
1137         case FBIPUT_COLOR:
1138                 return -ENOTTY;
1139         case FBIPUT_HSYNC:
1140                 if (copy_from_user(&sync_arg, (char *)arg,
1141                                 sizeof(struct lcd_sync_arg)))
1142                         return -EFAULT;
1143                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1144                                         sync_arg.pulse_width,
1145                                         sync_arg.front_porch);
1146                 break;
1147         case FBIPUT_VSYNC:
1148                 if (copy_from_user(&sync_arg, (char *)arg,
1149                                 sizeof(struct lcd_sync_arg)))
1150                         return -EFAULT;
1151                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1152                                         sync_arg.pulse_width,
1153                                         sync_arg.front_porch);
1154                 break;
1155         case FBIO_WAITFORVSYNC:
1156                 return fb_wait_for_vsync(info);
1157         default:
1158                 return -EINVAL;
1159         }
1160         return 0;
1161 }
1162
1163 static int cfb_blank(int blank, struct fb_info *info)
1164 {
1165         struct da8xx_fb_par *par = info->par;
1166         int ret = 0;
1167
1168         if (par->blank == blank)
1169                 return 0;
1170
1171         par->blank = blank;
1172         switch (blank) {
1173         case FB_BLANK_UNBLANK:
1174                 lcd_enable_raster();
1175
1176                 if (par->panel_power_ctrl)
1177                         par->panel_power_ctrl(1);
1178                 break;
1179         case FB_BLANK_NORMAL:
1180         case FB_BLANK_VSYNC_SUSPEND:
1181         case FB_BLANK_HSYNC_SUSPEND:
1182         case FB_BLANK_POWERDOWN:
1183                 if (par->panel_power_ctrl)
1184                         par->panel_power_ctrl(0);
1185
1186                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1187                 break;
1188         default:
1189                 ret = -EINVAL;
1190         }
1191
1192         return ret;
1193 }
1194
1195 /*
1196  * Set new x,y offsets in the virtual display for the visible area and switch
1197  * to the new mode.
1198  */
1199 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1200                              struct fb_info *fbi)
1201 {
1202         int ret = 0;
1203         struct fb_var_screeninfo new_var;
1204         struct da8xx_fb_par         *par = fbi->par;
1205         struct fb_fix_screeninfo    *fix = &fbi->fix;
1206         unsigned int end;
1207         unsigned int start;
1208         unsigned long irq_flags;
1209
1210         if (var->xoffset != fbi->var.xoffset ||
1211                         var->yoffset != fbi->var.yoffset) {
1212                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1213                 new_var.xoffset = var->xoffset;
1214                 new_var.yoffset = var->yoffset;
1215                 if (fb_check_var(&new_var, fbi))
1216                         ret = -EINVAL;
1217                 else {
1218                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1219
1220                         start   = fix->smem_start +
1221                                 new_var.yoffset * fix->line_length +
1222                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1223                         end     = start + fbi->var.yres * fix->line_length - 1;
1224                         par->dma_start  = start;
1225                         par->dma_end    = end;
1226                         spin_lock_irqsave(&par->lock_for_chan_update,
1227                                         irq_flags);
1228                         if (par->which_dma_channel_done == 0) {
1229                                 lcdc_write(par->dma_start,
1230                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1231                                 lcdc_write(par->dma_end,
1232                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1233                         } else if (par->which_dma_channel_done == 1) {
1234                                 lcdc_write(par->dma_start,
1235                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1236                                 lcdc_write(par->dma_end,
1237                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1238                         }
1239                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1240                                         irq_flags);
1241                 }
1242         }
1243
1244         return ret;
1245 }
1246
1247 static int da8xxfb_set_par(struct fb_info *info)
1248 {
1249         struct da8xx_fb_par *par = info->par;
1250         int ret;
1251         bool raster = da8xx_fb_is_raster_enabled();
1252
1253         if (raster)
1254                 lcd_disable_raster(DA8XX_FRAME_WAIT);
1255
1256         fb_var_to_videomode(&par->mode, &info->var);
1257
1258         par->cfg.bpp = info->var.bits_per_pixel;
1259
1260         info->fix.visual = (par->cfg.bpp <= 8) ?
1261                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1262         info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1263
1264         ret = lcd_init(par, &par->cfg, &par->mode);
1265         if (ret < 0) {
1266                 dev_err(par->dev, "lcd init failed\n");
1267                 return ret;
1268         }
1269
1270         par->dma_start = info->fix.smem_start +
1271                          info->var.yoffset * info->fix.line_length +
1272                          info->var.xoffset * info->var.bits_per_pixel / 8;
1273         par->dma_end   = par->dma_start +
1274                          info->var.yres * info->fix.line_length - 1;
1275
1276         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1277         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1278         lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1279         lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1280
1281         if (raster)
1282                 lcd_enable_raster();
1283
1284         return 0;
1285 }
1286
1287 static struct fb_ops da8xx_fb_ops = {
1288         .owner = THIS_MODULE,
1289         .fb_check_var = fb_check_var,
1290         .fb_set_par = da8xxfb_set_par,
1291         .fb_setcolreg = fb_setcolreg,
1292         .fb_pan_display = da8xx_pan_display,
1293         .fb_ioctl = fb_ioctl,
1294         .fb_fillrect = cfb_fillrect,
1295         .fb_copyarea = cfb_copyarea,
1296         .fb_imageblit = cfb_imageblit,
1297         .fb_blank = cfb_blank,
1298 };
1299
1300 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1301 {
1302         struct da8xx_lcdc_platform_data *fb_pdata = dev->dev.platform_data;
1303         struct fb_videomode *lcdc_info;
1304         int i;
1305
1306         for (i = 0, lcdc_info = known_lcd_panels;
1307                 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1308                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1309                         break;
1310         }
1311
1312         if (i == ARRAY_SIZE(known_lcd_panels)) {
1313                 dev_err(&dev->dev, "no panel found\n");
1314                 return NULL;
1315         }
1316         dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1317
1318         return lcdc_info;
1319 }
1320
1321 static int fb_probe(struct platform_device *device)
1322 {
1323         struct da8xx_lcdc_platform_data *fb_pdata =
1324                                                 device->dev.platform_data;
1325         static struct resource *lcdc_regs;
1326         struct lcd_ctrl_config *lcd_cfg;
1327         struct fb_videomode *lcdc_info;
1328         struct fb_info *da8xx_fb_info;
1329         struct da8xx_fb_par *par;
1330         struct clk *tmp_lcdc_clk;
1331         int ret;
1332         unsigned long ulcm;
1333
1334         if (fb_pdata == NULL) {
1335                 dev_err(&device->dev, "Can not get platform data\n");
1336                 return -ENOENT;
1337         }
1338
1339         lcdc_info = da8xx_fb_get_videomode(device);
1340         if (lcdc_info == NULL)
1341                 return -ENODEV;
1342
1343         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1344         da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs);
1345         if (IS_ERR(da8xx_fb_reg_base))
1346                 return PTR_ERR(da8xx_fb_reg_base);
1347
1348         tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1349         if (IS_ERR(tmp_lcdc_clk)) {
1350                 dev_err(&device->dev, "Can not get device clock\n");
1351                 return PTR_ERR(tmp_lcdc_clk);
1352         }
1353
1354         pm_runtime_enable(&device->dev);
1355         pm_runtime_get_sync(&device->dev);
1356
1357         /* Determine LCD IP Version */
1358         switch (lcdc_read(LCD_PID_REG)) {
1359         case 0x4C100102:
1360                 lcd_revision = LCD_VERSION_1;
1361                 break;
1362         case 0x4F200800:
1363         case 0x4F201000:
1364                 lcd_revision = LCD_VERSION_2;
1365                 break;
1366         default:
1367                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1368                                 "defaulting to LCD revision 1\n",
1369                                 lcdc_read(LCD_PID_REG));
1370                 lcd_revision = LCD_VERSION_1;
1371                 break;
1372         }
1373
1374         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1375
1376         if (!lcd_cfg) {
1377                 ret = -EINVAL;
1378                 goto err_pm_runtime_disable;
1379         }
1380
1381         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1382                                         &device->dev);
1383         if (!da8xx_fb_info) {
1384                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1385                 ret = -ENOMEM;
1386                 goto err_pm_runtime_disable;
1387         }
1388
1389         par = da8xx_fb_info->par;
1390         par->dev = &device->dev;
1391         par->lcdc_clk = tmp_lcdc_clk;
1392         par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1393         if (fb_pdata->panel_power_ctrl) {
1394                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1395                 par->panel_power_ctrl(1);
1396         }
1397
1398         fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1399         par->cfg = *lcd_cfg;
1400
1401         da8xx_fb_lcd_reset();
1402
1403         /* allocate frame buffer */
1404         par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1405         ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1406         par->vram_size = roundup(par->vram_size/8, ulcm);
1407         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1408
1409         par->vram_virt = dma_alloc_coherent(NULL,
1410                                             par->vram_size,
1411                                             (resource_size_t *) &par->vram_phys,
1412                                             GFP_KERNEL | GFP_DMA);
1413         if (!par->vram_virt) {
1414                 dev_err(&device->dev,
1415                         "GLCD: kmalloc for frame buffer failed\n");
1416                 ret = -EINVAL;
1417                 goto err_release_fb;
1418         }
1419
1420         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1421         da8xx_fb_fix.smem_start    = par->vram_phys;
1422         da8xx_fb_fix.smem_len      = par->vram_size;
1423         da8xx_fb_fix.line_length   = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1424
1425         par->dma_start = par->vram_phys;
1426         par->dma_end   = par->dma_start + lcdc_info->yres *
1427                 da8xx_fb_fix.line_length - 1;
1428
1429         /* allocate palette buffer */
1430         par->v_palette_base = dma_alloc_coherent(NULL,
1431                                                PALETTE_SIZE,
1432                                                (resource_size_t *)
1433                                                &par->p_palette_base,
1434                                                GFP_KERNEL | GFP_DMA);
1435         if (!par->v_palette_base) {
1436                 dev_err(&device->dev,
1437                         "GLCD: kmalloc for palette buffer failed\n");
1438                 ret = -EINVAL;
1439                 goto err_release_fb_mem;
1440         }
1441         memset(par->v_palette_base, 0, PALETTE_SIZE);
1442
1443         par->irq = platform_get_irq(device, 0);
1444         if (par->irq < 0) {
1445                 ret = -ENOENT;
1446                 goto err_release_pl_mem;
1447         }
1448
1449         da8xx_fb_var.grayscale =
1450             lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1451         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1452
1453         /* Initialize fbinfo */
1454         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1455         da8xx_fb_info->fix = da8xx_fb_fix;
1456         da8xx_fb_info->var = da8xx_fb_var;
1457         da8xx_fb_info->fbops = &da8xx_fb_ops;
1458         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1459         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1460                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1461
1462         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1463         if (ret)
1464                 goto err_release_pl_mem;
1465         da8xx_fb_info->cmap.len = par->palette_sz;
1466
1467         /* initialize var_screeninfo */
1468         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1469         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1470
1471         dev_set_drvdata(&device->dev, da8xx_fb_info);
1472
1473         /* initialize the vsync wait queue */
1474         init_waitqueue_head(&par->vsync_wait);
1475         par->vsync_timeout = HZ / 5;
1476         par->which_dma_channel_done = -1;
1477         spin_lock_init(&par->lock_for_chan_update);
1478
1479         /* Register the Frame Buffer  */
1480         if (register_framebuffer(da8xx_fb_info) < 0) {
1481                 dev_err(&device->dev,
1482                         "GLCD: Frame Buffer Registration Failed!\n");
1483                 ret = -EINVAL;
1484                 goto err_dealloc_cmap;
1485         }
1486
1487 #ifdef CONFIG_CPU_FREQ
1488         ret = lcd_da8xx_cpufreq_register(par);
1489         if (ret) {
1490                 dev_err(&device->dev, "failed to register cpufreq\n");
1491                 goto err_cpu_freq;
1492         }
1493 #endif
1494
1495         if (lcd_revision == LCD_VERSION_1)
1496                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1497         else {
1498                 init_waitqueue_head(&frame_done_wq);
1499                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1500         }
1501
1502         ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1503                                DRIVER_NAME, par);
1504         if (ret)
1505                 goto irq_freq;
1506         return 0;
1507
1508 irq_freq:
1509 #ifdef CONFIG_CPU_FREQ
1510         lcd_da8xx_cpufreq_deregister(par);
1511 err_cpu_freq:
1512 #endif
1513         unregister_framebuffer(da8xx_fb_info);
1514
1515 err_dealloc_cmap:
1516         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1517
1518 err_release_pl_mem:
1519         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1520                           par->p_palette_base);
1521
1522 err_release_fb_mem:
1523         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1524
1525 err_release_fb:
1526         framebuffer_release(da8xx_fb_info);
1527
1528 err_pm_runtime_disable:
1529         pm_runtime_put_sync(&device->dev);
1530         pm_runtime_disable(&device->dev);
1531
1532         return ret;
1533 }
1534
1535 #ifdef CONFIG_PM
1536 struct lcdc_context {
1537         u32 clk_enable;
1538         u32 ctrl;
1539         u32 dma_ctrl;
1540         u32 raster_timing_0;
1541         u32 raster_timing_1;
1542         u32 raster_timing_2;
1543         u32 int_enable_set;
1544         u32 dma_frm_buf_base_addr_0;
1545         u32 dma_frm_buf_ceiling_addr_0;
1546         u32 dma_frm_buf_base_addr_1;
1547         u32 dma_frm_buf_ceiling_addr_1;
1548         u32 raster_ctrl;
1549 } reg_context;
1550
1551 static void lcd_context_save(void)
1552 {
1553         if (lcd_revision == LCD_VERSION_2) {
1554                 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1555                 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1556         }
1557
1558         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1559         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1560         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1561         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1562         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1563         reg_context.dma_frm_buf_base_addr_0 =
1564                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1565         reg_context.dma_frm_buf_ceiling_addr_0 =
1566                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1567         reg_context.dma_frm_buf_base_addr_1 =
1568                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1569         reg_context.dma_frm_buf_ceiling_addr_1 =
1570                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1571         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1572         return;
1573 }
1574
1575 static void lcd_context_restore(void)
1576 {
1577         if (lcd_revision == LCD_VERSION_2) {
1578                 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1579                 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1580         }
1581
1582         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1583         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1584         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1585         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1586         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1587         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1588                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1589         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1590                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1591         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1592                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1593         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1594                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1595         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1596         return;
1597 }
1598
1599 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1600 {
1601         struct fb_info *info = platform_get_drvdata(dev);
1602         struct da8xx_fb_par *par = info->par;
1603
1604         console_lock();
1605         if (par->panel_power_ctrl)
1606                 par->panel_power_ctrl(0);
1607
1608         fb_set_suspend(info, 1);
1609         lcd_disable_raster(DA8XX_FRAME_WAIT);
1610         lcd_context_save();
1611         pm_runtime_put_sync(&dev->dev);
1612         console_unlock();
1613
1614         return 0;
1615 }
1616 static int fb_resume(struct platform_device *dev)
1617 {
1618         struct fb_info *info = platform_get_drvdata(dev);
1619         struct da8xx_fb_par *par = info->par;
1620
1621         console_lock();
1622         pm_runtime_get_sync(&dev->dev);
1623         lcd_context_restore();
1624         if (par->blank == FB_BLANK_UNBLANK) {
1625                 lcd_enable_raster();
1626
1627                 if (par->panel_power_ctrl)
1628                         par->panel_power_ctrl(1);
1629         }
1630
1631         fb_set_suspend(info, 0);
1632         console_unlock();
1633
1634         return 0;
1635 }
1636 #else
1637 #define fb_suspend NULL
1638 #define fb_resume NULL
1639 #endif
1640
1641 static struct platform_driver da8xx_fb_driver = {
1642         .probe = fb_probe,
1643         .remove = fb_remove,
1644         .suspend = fb_suspend,
1645         .resume = fb_resume,
1646         .driver = {
1647                    .name = DRIVER_NAME,
1648                    .owner = THIS_MODULE,
1649                    },
1650 };
1651
1652 static int __init da8xx_fb_init(void)
1653 {
1654         return platform_driver_register(&da8xx_fb_driver);
1655 }
1656
1657 static void __exit da8xx_fb_cleanup(void)
1658 {
1659         platform_driver_unregister(&da8xx_fb_driver);
1660 }
1661
1662 module_init(da8xx_fb_init);
1663 module_exit(da8xx_fb_cleanup);
1664
1665 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1666 MODULE_AUTHOR("Texas Instruments");
1667 MODULE_LICENSE("GPL");