2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
35 #include <asm/div64.h>
37 #define DRIVER_NAME "da8xx_lcdc"
39 #define LCD_VERSION_1 1
40 #define LCD_VERSION_2 2
42 /* LCD Status Register */
43 #define LCD_END_OF_FRAME1 BIT(9)
44 #define LCD_END_OF_FRAME0 BIT(8)
45 #define LCD_PL_LOAD_DONE BIT(6)
46 #define LCD_FIFO_UNDERFLOW BIT(5)
47 #define LCD_SYNC_LOST BIT(2)
49 /* LCD DMA Control Register */
50 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
51 #define LCD_DMA_BURST_1 0x0
52 #define LCD_DMA_BURST_2 0x1
53 #define LCD_DMA_BURST_4 0x2
54 #define LCD_DMA_BURST_8 0x3
55 #define LCD_DMA_BURST_16 0x4
56 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
57 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
58 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
59 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
61 /* LCD Control Register */
62 #define LCD_CLK_DIVISOR(x) ((x) << 8)
63 #define LCD_RASTER_MODE 0x01
65 /* LCD Raster Control Register */
66 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
67 #define PALETTE_AND_DATA 0x00
68 #define PALETTE_ONLY 0x01
69 #define DATA_ONLY 0x02
71 #define LCD_MONO_8BIT_MODE BIT(9)
72 #define LCD_RASTER_ORDER BIT(8)
73 #define LCD_TFT_MODE BIT(7)
74 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
75 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
76 #define LCD_V1_PL_INT_ENA BIT(4)
77 #define LCD_V2_PL_INT_ENA BIT(6)
78 #define LCD_MONOCHROME_MODE BIT(1)
79 #define LCD_RASTER_ENABLE BIT(0)
80 #define LCD_TFT_ALT_ENABLE BIT(23)
81 #define LCD_STN_565_ENABLE BIT(24)
82 #define LCD_V2_DMA_CLK_EN BIT(2)
83 #define LCD_V2_LIDD_CLK_EN BIT(1)
84 #define LCD_V2_CORE_CLK_EN BIT(0)
85 #define LCD_V2_LPP_B10 26
87 /* LCD Raster Timing 2 Register */
88 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
89 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
90 #define LCD_SYNC_CTRL BIT(25)
91 #define LCD_SYNC_EDGE BIT(24)
92 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
93 #define LCD_INVERT_LINE_CLOCK BIT(21)
94 #define LCD_INVERT_FRAME_CLOCK BIT(20)
97 #define LCD_PID_REG 0x0
98 #define LCD_CTRL_REG 0x4
99 #define LCD_STAT_REG 0x8
100 #define LCD_RASTER_CTRL_REG 0x28
101 #define LCD_RASTER_TIMING_0_REG 0x2C
102 #define LCD_RASTER_TIMING_1_REG 0x30
103 #define LCD_RASTER_TIMING_2_REG 0x34
104 #define LCD_DMA_CTRL_REG 0x40
105 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
106 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
107 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
108 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
110 /* Interrupt Registers available only in Version 2 */
111 #define LCD_RAW_STAT_REG 0x58
112 #define LCD_MASKED_STAT_REG 0x5c
113 #define LCD_INT_ENABLE_SET_REG 0x60
114 #define LCD_INT_ENABLE_CLR_REG 0x64
115 #define LCD_END_OF_INT_IND_REG 0x68
117 /* Clock registers available only on Version 2 */
118 #define LCD_CLK_ENABLE_REG 0x6c
119 #define LCD_CLK_RESET_REG 0x70
120 #define LCD_CLK_MAIN_RESET BIT(3)
122 #define LCD_NUM_BUFFERS 2
124 #define WSI_TIMEOUT 50
125 #define PALETTE_SIZE 256
126 #define LEFT_MARGIN 64
127 #define RIGHT_MARGIN 64
128 #define UPPER_MARGIN 32
129 #define LOWER_MARGIN 32
131 static resource_size_t da8xx_fb_reg_base;
132 static struct resource *lcdc_regs;
133 static unsigned int lcd_revision;
134 static irq_handler_t lcdc_irq_handler;
136 static inline unsigned int lcdc_read(unsigned int addr)
138 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
141 static inline void lcdc_write(unsigned int val, unsigned int addr)
143 __raw_writel(val, da8xx_fb_reg_base + (addr));
146 struct da8xx_fb_par {
147 resource_size_t p_palette_base;
148 unsigned char *v_palette_base;
149 dma_addr_t vram_phys;
150 unsigned long vram_size;
152 unsigned int dma_start;
153 unsigned int dma_end;
154 struct clk *lcdc_clk;
156 unsigned short pseudo_palette[16];
157 unsigned int palette_sz;
158 unsigned int pxl_clk;
160 wait_queue_head_t vsync_wait;
163 #ifdef CONFIG_CPU_FREQ
164 struct notifier_block freq_transition;
165 unsigned int lcd_fck_rate;
167 void (*panel_power_ctrl)(int);
170 /* Variable Screen Information */
171 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
180 .left_margin = LEFT_MARGIN,
181 .right_margin = RIGHT_MARGIN,
182 .upper_margin = UPPER_MARGIN,
183 .lower_margin = LOWER_MARGIN,
185 .vmode = FB_VMODE_NONINTERLACED
188 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
189 .id = "DA8xx FB Drv",
190 .type = FB_TYPE_PACKED_PIXELS,
192 .visual = FB_VISUAL_PSEUDOCOLOR,
196 .accel = FB_ACCEL_NONE
200 const char name[25]; /* Full name <vendor>_<model> */
201 unsigned short width;
202 unsigned short height;
203 int hfp; /* Horizontal front porch */
204 int hbp; /* Horizontal back porch */
205 int hsw; /* Horizontal Sync Pulse Width */
206 int vfp; /* Vertical front porch */
207 int vbp; /* Vertical back porch */
208 int vsw; /* Vertical Sync Pulse Width */
209 unsigned int pxl_clk; /* Pixel clock */
210 unsigned char invert_pxl_clk; /* Invert Pixel clock */
213 static struct da8xx_panel known_lcd_panels[] = {
214 /* Sharp LCD035Q3DG01 */
216 .name = "Sharp_LCD035Q3DG01",
228 /* Sharp LK043T1DG01 */
230 .name = "Sharp_LK043T1DG01",
244 /* Enable the Raster Engine of the LCD Controller */
245 static inline void lcd_enable_raster(void)
249 /* Bring LCDC out of reset */
250 if (lcd_revision == LCD_VERSION_2)
251 lcdc_write(0, LCD_CLK_RESET_REG);
253 reg = lcdc_read(LCD_RASTER_CTRL_REG);
254 if (!(reg & LCD_RASTER_ENABLE))
255 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
258 /* Disable the Raster Engine of the LCD Controller */
259 static inline void lcd_disable_raster(void)
263 reg = lcdc_read(LCD_RASTER_CTRL_REG);
264 if (reg & LCD_RASTER_ENABLE)
265 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
267 if (lcd_revision == LCD_VERSION_2)
268 /* Write 1 to reset LCDC */
269 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
272 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
280 /* init reg to clear PLM (loading mode) fields */
281 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
282 reg_ras &= ~(3 << 20);
284 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
286 if (load_mode == LOAD_DATA) {
287 start = par->dma_start;
290 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
291 if (lcd_revision == LCD_VERSION_1) {
292 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
294 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
295 LCD_V2_END_OF_FRAME0_INT_ENA |
296 LCD_V2_END_OF_FRAME1_INT_ENA;
297 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
299 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
301 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
302 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
303 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
304 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
305 } else if (load_mode == LOAD_PALETTE) {
306 start = par->p_palette_base;
307 end = start + par->palette_sz - 1;
309 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
311 if (lcd_revision == LCD_VERSION_1) {
312 reg_ras |= LCD_V1_PL_INT_ENA;
314 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
316 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
319 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
320 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
323 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
324 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
327 * The Raster enable bit must be set after all other control fields are
333 /* Configure the Burst Size of DMA */
334 static int lcd_cfg_dma(int burst_size)
338 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
339 switch (burst_size) {
341 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
344 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
347 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
350 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
353 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
358 lcdc_write(reg, LCD_DMA_CTRL_REG);
363 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
367 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
368 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
369 reg |= LCD_AC_BIAS_FREQUENCY(period) |
370 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
371 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
374 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
379 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
380 reg |= ((back_porch & 0xff) << 24)
381 | ((front_porch & 0xff) << 16)
382 | ((pulse_width & 0x3f) << 10);
383 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
386 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
391 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
392 reg |= ((back_porch & 0xff) << 24)
393 | ((front_porch & 0xff) << 16)
394 | ((pulse_width & 0x3f) << 10);
395 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
398 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
403 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
405 LCD_MONOCHROME_MODE);
407 switch (cfg->p_disp_panel->panel_shade) {
409 reg |= LCD_MONOCHROME_MODE;
410 if (cfg->mono_8bit_mode)
411 reg |= LCD_MONO_8BIT_MODE;
415 if (cfg->tft_alt_mode)
416 reg |= LCD_TFT_ALT_ENABLE;
420 if (cfg->stn_565_mode)
421 reg |= LCD_STN_565_ENABLE;
428 /* enable additional interrupts here */
429 if (lcd_revision == LCD_VERSION_1) {
430 reg |= LCD_V1_UNDERFLOW_INT_ENA;
432 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
433 LCD_V2_UNDERFLOW_INT_ENA;
434 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
437 lcdc_write(reg, LCD_RASTER_CTRL_REG);
439 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
442 reg |= LCD_SYNC_CTRL;
444 reg &= ~LCD_SYNC_CTRL;
447 reg |= LCD_SYNC_EDGE;
449 reg &= ~LCD_SYNC_EDGE;
451 if (cfg->invert_line_clock)
452 reg |= LCD_INVERT_LINE_CLOCK;
454 reg &= ~LCD_INVERT_LINE_CLOCK;
456 if (cfg->invert_frm_clock)
457 reg |= LCD_INVERT_FRAME_CLOCK;
459 reg &= ~LCD_INVERT_FRAME_CLOCK;
461 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
466 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
467 u32 bpp, u32 raster_order)
471 /* Set the Panel Width */
472 /* Pixels per line = (PPL + 1)*16 */
473 if (lcd_revision == LCD_VERSION_1) {
475 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
481 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
487 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
489 if (lcd_revision == LCD_VERSION_1) {
490 reg |= ((width >> 4) - 1) << 4;
492 width = (width >> 4) - 1;
493 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
495 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
497 /* Set the Panel Height */
498 /* Set bits 9:0 of Lines Per Pixel */
499 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
500 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
501 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
503 /* Set bit 10 of Lines Per Pixel */
504 if (lcd_revision == LCD_VERSION_2) {
505 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
506 reg |= ((height - 1) & 0x400) << 16;
507 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
510 /* Set the Raster Order of the Frame Buffer */
511 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
513 reg |= LCD_RASTER_ORDER;
514 lcdc_write(reg, LCD_RASTER_CTRL_REG);
521 par->palette_sz = 16 * 2;
525 par->palette_sz = 256 * 2;
535 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
536 unsigned blue, unsigned transp,
537 struct fb_info *info)
539 struct da8xx_fb_par *par = info->par;
540 unsigned short *palette = (unsigned short *) par->v_palette_base;
547 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
550 if (info->var.bits_per_pixel == 8) {
555 pal = (red & 0x0f00);
556 pal |= (green & 0x00f0);
557 pal |= (blue & 0x000f);
559 if (palette[regno] != pal) {
561 palette[regno] = pal;
563 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
564 red >>= (16 - info->var.red.length);
565 red <<= info->var.red.offset;
567 green >>= (16 - info->var.green.length);
568 green <<= info->var.green.offset;
570 blue >>= (16 - info->var.blue.length);
571 blue <<= info->var.blue.offset;
573 par->pseudo_palette[regno] = red | green | blue;
575 if (palette[0] != 0x4000) {
581 /* Update the palette in the h/w as needed. */
583 lcd_blit(LOAD_PALETTE, par);
588 static void lcd_reset(struct da8xx_fb_par *par)
590 /* Disable the Raster if previously Enabled */
591 lcd_disable_raster();
593 /* DMA has to be disabled */
594 lcdc_write(0, LCD_DMA_CTRL_REG);
595 lcdc_write(0, LCD_RASTER_CTRL_REG);
597 if (lcd_revision == LCD_VERSION_2) {
598 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
599 /* Write 1 to reset */
600 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
601 lcdc_write(0, LCD_CLK_RESET_REG);
605 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
607 unsigned int lcd_clk, div;
609 lcd_clk = clk_get_rate(par->lcdc_clk);
610 div = lcd_clk / par->pxl_clk;
612 /* Configure the LCD clock divisor. */
613 lcdc_write(LCD_CLK_DIVISOR(div) |
614 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
616 if (lcd_revision == LCD_VERSION_2)
617 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
618 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
622 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
623 struct da8xx_panel *panel)
630 /* Calculate the divider */
631 lcd_calc_clk_divider(par);
633 if (panel->invert_pxl_clk)
634 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
635 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
637 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
638 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
640 /* Configure the DMA burst size. */
641 ret = lcd_cfg_dma(cfg->dma_burst_sz);
645 /* Configure the AC bias properties. */
646 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
648 /* Configure the vertical and horizontal sync properties. */
649 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
650 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
652 /* Configure for disply */
653 ret = lcd_cfg_display(cfg);
657 if (QVGA != cfg->p_disp_panel->panel_type)
660 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
661 cfg->bpp >= cfg->p_disp_panel->min_bpp)
664 bpp = cfg->p_disp_panel->max_bpp;
667 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
668 (unsigned int)panel->height, bpp,
674 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
675 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
680 /* IRQ handler for version 2 of LCDC */
681 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
683 struct da8xx_fb_par *par = arg;
684 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
687 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
688 lcd_disable_raster();
689 lcdc_write(stat, LCD_MASKED_STAT_REG);
691 } else if (stat & LCD_PL_LOAD_DONE) {
693 * Must disable raster before changing state of any control bit.
694 * And also must be disabled before clearing the PL loading
695 * interrupt via the following write to the status register. If
696 * this is done after then one gets multiple PL done interrupts.
698 lcd_disable_raster();
700 lcdc_write(stat, LCD_MASKED_STAT_REG);
702 /* Disable PL completion inerrupt */
703 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
705 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
707 /* Setup and start data loading mode */
708 lcd_blit(LOAD_DATA, par);
710 lcdc_write(stat, LCD_MASKED_STAT_REG);
712 if (stat & LCD_END_OF_FRAME0) {
713 lcdc_write(par->dma_start,
714 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
715 lcdc_write(par->dma_end,
716 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
718 wake_up_interruptible(&par->vsync_wait);
721 if (stat & LCD_END_OF_FRAME1) {
722 lcdc_write(par->dma_start,
723 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
724 lcdc_write(par->dma_end,
725 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
727 wake_up_interruptible(&par->vsync_wait);
731 lcdc_write(0, LCD_END_OF_INT_IND_REG);
735 /* IRQ handler for version 1 LCDC */
736 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
738 struct da8xx_fb_par *par = arg;
739 u32 stat = lcdc_read(LCD_STAT_REG);
742 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
743 lcd_disable_raster();
744 lcdc_write(stat, LCD_STAT_REG);
746 } else if (stat & LCD_PL_LOAD_DONE) {
748 * Must disable raster before changing state of any control bit.
749 * And also must be disabled before clearing the PL loading
750 * interrupt via the following write to the status register. If
751 * this is done after then one gets multiple PL done interrupts.
753 lcd_disable_raster();
755 lcdc_write(stat, LCD_STAT_REG);
757 /* Disable PL completion inerrupt */
758 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
759 reg_ras &= ~LCD_V1_PL_INT_ENA;
760 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
762 /* Setup and start data loading mode */
763 lcd_blit(LOAD_DATA, par);
765 lcdc_write(stat, LCD_STAT_REG);
767 if (stat & LCD_END_OF_FRAME0) {
768 lcdc_write(par->dma_start,
769 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
770 lcdc_write(par->dma_end,
771 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
773 wake_up_interruptible(&par->vsync_wait);
776 if (stat & LCD_END_OF_FRAME1) {
777 lcdc_write(par->dma_start,
778 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
779 lcdc_write(par->dma_end,
780 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
782 wake_up_interruptible(&par->vsync_wait);
789 static int fb_check_var(struct fb_var_screeninfo *var,
790 struct fb_info *info)
794 switch (var->bits_per_pixel) {
799 var->green.offset = 0;
800 var->green.length = 8;
801 var->blue.offset = 0;
802 var->blue.length = 8;
803 var->transp.offset = 0;
804 var->transp.length = 0;
809 var->green.offset = 0;
810 var->green.length = 4;
811 var->blue.offset = 0;
812 var->blue.length = 4;
813 var->transp.offset = 0;
814 var->transp.length = 0;
816 case 16: /* RGB 565 */
817 var->red.offset = 11;
819 var->green.offset = 5;
820 var->green.length = 6;
821 var->blue.offset = 0;
822 var->blue.length = 5;
823 var->transp.offset = 0;
824 var->transp.length = 0;
830 var->red.msb_right = 0;
831 var->green.msb_right = 0;
832 var->blue.msb_right = 0;
833 var->transp.msb_right = 0;
837 #ifdef CONFIG_CPU_FREQ
838 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
839 unsigned long val, void *data)
841 struct da8xx_fb_par *par;
843 par = container_of(nb, struct da8xx_fb_par, freq_transition);
844 if (val == CPUFREQ_POSTCHANGE) {
845 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
846 par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
847 lcd_disable_raster();
848 lcd_calc_clk_divider(par);
856 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
858 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
860 return cpufreq_register_notifier(&par->freq_transition,
861 CPUFREQ_TRANSITION_NOTIFIER);
864 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
866 cpufreq_unregister_notifier(&par->freq_transition,
867 CPUFREQ_TRANSITION_NOTIFIER);
871 static int __devexit fb_remove(struct platform_device *dev)
873 struct fb_info *info = dev_get_drvdata(&dev->dev);
876 struct da8xx_fb_par *par = info->par;
878 #ifdef CONFIG_CPU_FREQ
879 lcd_da8xx_cpufreq_deregister(par);
881 if (par->panel_power_ctrl)
882 par->panel_power_ctrl(0);
884 lcd_disable_raster();
885 lcdc_write(0, LCD_RASTER_CTRL_REG);
888 lcdc_write(0, LCD_DMA_CTRL_REG);
890 unregister_framebuffer(info);
891 fb_dealloc_cmap(&info->cmap);
892 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
893 par->p_palette_base);
894 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
896 free_irq(par->irq, par);
897 clk_disable(par->lcdc_clk);
898 clk_put(par->lcdc_clk);
899 framebuffer_release(info);
900 iounmap((void __iomem *)da8xx_fb_reg_base);
901 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
908 * Function to wait for vertical sync which for this LCD peripheral
909 * translates into waiting for the current raster frame to complete.
911 static int fb_wait_for_vsync(struct fb_info *info)
913 struct da8xx_fb_par *par = info->par;
917 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
918 * race condition here where the ISR could have occurred just before or
919 * just after this set. But since we are just coarsely waiting for
920 * a frame to complete then that's OK. i.e. if the frame completed
921 * just before this code executed then we have to wait another full
922 * frame time but there is no way to avoid such a situation. On the
923 * other hand if the frame completed just after then we don't need
924 * to wait long at all. Either way we are guaranteed to return to the
925 * user immediately after a frame completion which is all that is
929 ret = wait_event_interruptible_timeout(par->vsync_wait,
930 par->vsync_flag != 0,
940 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
943 struct lcd_sync_arg sync_arg;
946 case FBIOGET_CONTRAST:
947 case FBIOPUT_CONTRAST:
948 case FBIGET_BRIGHTNESS:
949 case FBIPUT_BRIGHTNESS:
954 if (copy_from_user(&sync_arg, (char *)arg,
955 sizeof(struct lcd_sync_arg)))
957 lcd_cfg_horizontal_sync(sync_arg.back_porch,
958 sync_arg.pulse_width,
959 sync_arg.front_porch);
962 if (copy_from_user(&sync_arg, (char *)arg,
963 sizeof(struct lcd_sync_arg)))
965 lcd_cfg_vertical_sync(sync_arg.back_porch,
966 sync_arg.pulse_width,
967 sync_arg.front_porch);
969 case FBIO_WAITFORVSYNC:
970 return fb_wait_for_vsync(info);
977 static int cfb_blank(int blank, struct fb_info *info)
979 struct da8xx_fb_par *par = info->par;
982 if (par->blank == blank)
987 case FB_BLANK_UNBLANK:
988 if (par->panel_power_ctrl)
989 par->panel_power_ctrl(1);
993 case FB_BLANK_POWERDOWN:
994 if (par->panel_power_ctrl)
995 par->panel_power_ctrl(0);
997 lcd_disable_raster();
1007 * Set new x,y offsets in the virtual display for the visible area and switch
1010 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1011 struct fb_info *fbi)
1014 struct fb_var_screeninfo new_var;
1015 struct da8xx_fb_par *par = fbi->par;
1016 struct fb_fix_screeninfo *fix = &fbi->fix;
1020 if (var->xoffset != fbi->var.xoffset ||
1021 var->yoffset != fbi->var.yoffset) {
1022 memcpy(&new_var, &fbi->var, sizeof(new_var));
1023 new_var.xoffset = var->xoffset;
1024 new_var.yoffset = var->yoffset;
1025 if (fb_check_var(&new_var, fbi))
1028 memcpy(&fbi->var, &new_var, sizeof(new_var));
1030 start = fix->smem_start +
1031 new_var.yoffset * fix->line_length +
1032 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1033 end = start + fbi->var.yres * fix->line_length - 1;
1034 par->dma_start = start;
1042 static struct fb_ops da8xx_fb_ops = {
1043 .owner = THIS_MODULE,
1044 .fb_check_var = fb_check_var,
1045 .fb_setcolreg = fb_setcolreg,
1046 .fb_pan_display = da8xx_pan_display,
1047 .fb_ioctl = fb_ioctl,
1048 .fb_fillrect = cfb_fillrect,
1049 .fb_copyarea = cfb_copyarea,
1050 .fb_imageblit = cfb_imageblit,
1051 .fb_blank = cfb_blank,
1054 /* Calculate and return pixel clock period in pico seconds */
1055 static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
1057 unsigned int lcd_clk, div;
1058 unsigned int configured_pix_clk;
1059 unsigned long long pix_clk_period_picosec = 1000000000000ULL;
1061 lcd_clk = clk_get_rate(par->lcdc_clk);
1062 div = lcd_clk / par->pxl_clk;
1063 configured_pix_clk = (lcd_clk / div);
1065 do_div(pix_clk_period_picosec, configured_pix_clk);
1067 return pix_clk_period_picosec;
1070 static int __devinit fb_probe(struct platform_device *device)
1072 struct da8xx_lcdc_platform_data *fb_pdata =
1073 device->dev.platform_data;
1074 struct lcd_ctrl_config *lcd_cfg;
1075 struct da8xx_panel *lcdc_info;
1076 struct fb_info *da8xx_fb_info;
1077 struct clk *fb_clk = NULL;
1078 struct da8xx_fb_par *par;
1079 resource_size_t len;
1082 if (fb_pdata == NULL) {
1083 dev_err(&device->dev, "Can not get platform data\n");
1087 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1089 dev_err(&device->dev,
1090 "Can not get memory resource for LCD controller\n");
1094 len = resource_size(lcdc_regs);
1096 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1100 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1101 if (!da8xx_fb_reg_base) {
1103 goto err_request_mem;
1106 fb_clk = clk_get(&device->dev, NULL);
1107 if (IS_ERR(fb_clk)) {
1108 dev_err(&device->dev, "Can not get device clock\n");
1112 ret = clk_enable(fb_clk);
1116 /* Determine LCD IP Version */
1117 switch (lcdc_read(LCD_PID_REG)) {
1119 lcd_revision = LCD_VERSION_1;
1122 lcd_revision = LCD_VERSION_2;
1125 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1126 "defaulting to LCD revision 1\n",
1127 lcdc_read(LCD_PID_REG));
1128 lcd_revision = LCD_VERSION_1;
1132 for (i = 0, lcdc_info = known_lcd_panels;
1133 i < ARRAY_SIZE(known_lcd_panels);
1135 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1139 if (i == ARRAY_SIZE(known_lcd_panels)) {
1140 dev_err(&device->dev, "GLCD: No valid panel found\n");
1142 goto err_clk_disable;
1144 dev_info(&device->dev, "GLCD: Found %s panel\n",
1147 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1149 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1151 if (!da8xx_fb_info) {
1152 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1154 goto err_clk_disable;
1157 par = da8xx_fb_info->par;
1158 par->lcdc_clk = fb_clk;
1159 #ifdef CONFIG_CPU_FREQ
1160 par->lcd_fck_rate = clk_get_rate(fb_clk);
1162 par->pxl_clk = lcdc_info->pxl_clk;
1163 if (fb_pdata->panel_power_ctrl) {
1164 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1165 par->panel_power_ctrl(1);
1168 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1169 dev_err(&device->dev, "lcd_init failed\n");
1171 goto err_release_fb;
1174 /* allocate frame buffer */
1175 par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1176 par->vram_size = PAGE_ALIGN(par->vram_size/8);
1177 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1179 par->vram_virt = dma_alloc_coherent(NULL,
1181 (resource_size_t *) &par->vram_phys,
1182 GFP_KERNEL | GFP_DMA);
1183 if (!par->vram_virt) {
1184 dev_err(&device->dev,
1185 "GLCD: kmalloc for frame buffer failed\n");
1187 goto err_release_fb;
1190 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1191 da8xx_fb_fix.smem_start = par->vram_phys;
1192 da8xx_fb_fix.smem_len = par->vram_size;
1193 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
1195 par->dma_start = par->vram_phys;
1196 par->dma_end = par->dma_start + lcdc_info->height *
1197 da8xx_fb_fix.line_length - 1;
1199 /* allocate palette buffer */
1200 par->v_palette_base = dma_alloc_coherent(NULL,
1203 &par->p_palette_base,
1204 GFP_KERNEL | GFP_DMA);
1205 if (!par->v_palette_base) {
1206 dev_err(&device->dev,
1207 "GLCD: kmalloc for palette buffer failed\n");
1209 goto err_release_fb_mem;
1211 memset(par->v_palette_base, 0, PALETTE_SIZE);
1213 par->irq = platform_get_irq(device, 0);
1216 goto err_release_pl_mem;
1219 /* Initialize par */
1220 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1222 da8xx_fb_var.xres = lcdc_info->width;
1223 da8xx_fb_var.xres_virtual = lcdc_info->width;
1225 da8xx_fb_var.yres = lcdc_info->height;
1226 da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1228 da8xx_fb_var.grayscale =
1229 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1230 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1232 da8xx_fb_var.hsync_len = lcdc_info->hsw;
1233 da8xx_fb_var.vsync_len = lcdc_info->vsw;
1234 da8xx_fb_var.right_margin = lcdc_info->hfp;
1235 da8xx_fb_var.left_margin = lcdc_info->hbp;
1236 da8xx_fb_var.lower_margin = lcdc_info->vfp;
1237 da8xx_fb_var.upper_margin = lcdc_info->vbp;
1238 da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
1240 /* Initialize fbinfo */
1241 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1242 da8xx_fb_info->fix = da8xx_fb_fix;
1243 da8xx_fb_info->var = da8xx_fb_var;
1244 da8xx_fb_info->fbops = &da8xx_fb_ops;
1245 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1246 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1247 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1249 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1251 goto err_release_pl_mem;
1252 da8xx_fb_info->cmap.len = par->palette_sz;
1254 /* initialize var_screeninfo */
1255 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1256 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1258 dev_set_drvdata(&device->dev, da8xx_fb_info);
1260 /* initialize the vsync wait queue */
1261 init_waitqueue_head(&par->vsync_wait);
1262 par->vsync_timeout = HZ / 5;
1264 /* Register the Frame Buffer */
1265 if (register_framebuffer(da8xx_fb_info) < 0) {
1266 dev_err(&device->dev,
1267 "GLCD: Frame Buffer Registration Failed!\n");
1269 goto err_dealloc_cmap;
1272 #ifdef CONFIG_CPU_FREQ
1273 ret = lcd_da8xx_cpufreq_register(par);
1275 dev_err(&device->dev, "failed to register cpufreq\n");
1280 if (lcd_revision == LCD_VERSION_1)
1281 lcdc_irq_handler = lcdc_irq_handler_rev01;
1283 lcdc_irq_handler = lcdc_irq_handler_rev02;
1285 ret = request_irq(par->irq, lcdc_irq_handler, 0,
1292 #ifdef CONFIG_CPU_FREQ
1293 lcd_da8xx_cpufreq_deregister(par);
1296 unregister_framebuffer(da8xx_fb_info);
1299 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1302 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1303 par->p_palette_base);
1306 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1309 framebuffer_release(da8xx_fb_info);
1312 clk_disable(fb_clk);
1318 iounmap((void __iomem *)da8xx_fb_reg_base);
1321 release_mem_region(lcdc_regs->start, len);
1327 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1329 struct fb_info *info = platform_get_drvdata(dev);
1330 struct da8xx_fb_par *par = info->par;
1333 if (par->panel_power_ctrl)
1334 par->panel_power_ctrl(0);
1336 fb_set_suspend(info, 1);
1337 lcd_disable_raster();
1338 clk_disable(par->lcdc_clk);
1343 static int fb_resume(struct platform_device *dev)
1345 struct fb_info *info = platform_get_drvdata(dev);
1346 struct da8xx_fb_par *par = info->par;
1349 if (par->panel_power_ctrl)
1350 par->panel_power_ctrl(1);
1352 clk_enable(par->lcdc_clk);
1353 lcd_enable_raster();
1354 fb_set_suspend(info, 0);
1360 #define fb_suspend NULL
1361 #define fb_resume NULL
1364 static struct platform_driver da8xx_fb_driver = {
1366 .remove = __devexit_p(fb_remove),
1367 .suspend = fb_suspend,
1368 .resume = fb_resume,
1370 .name = DRIVER_NAME,
1371 .owner = THIS_MODULE,
1375 static int __init da8xx_fb_init(void)
1377 return platform_driver_register(&da8xx_fb_driver);
1380 static void __exit da8xx_fb_cleanup(void)
1382 platform_driver_unregister(&da8xx_fb_driver);
1385 module_init(da8xx_fb_init);
1386 module_exit(da8xx_fb_cleanup);
1388 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1389 MODULE_AUTHOR("Texas Instruments");
1390 MODULE_LICENSE("GPL");