Pileus Git - ~andy/linux/blob - drivers/video/da8xx-fb.c

   1 /*
   2  * Copyright (C) 2008-2009 MontaVista Software Inc.
   3  * Copyright (C) 2008-2009 Texas Instruments Inc
   4  *
   5  * Based on the LCD driver for TI Avalanche processors written by
   6  * Ajay Singh and Shalom Hai.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option)any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/fb.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/clk.h>
  31 #include <linux/cpufreq.h>
  32 #include <linux/console.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/slab.h>
  35 #include <linux/delay.h>
  36 #include <linux/lcm.h>
  37 #include <video/da8xx-fb.h>
  38 #include <asm/div64.h>
  39
  40 #define DRIVER_NAME "da8xx_lcdc"
  41
  42 #define LCD_VERSION_1   1
  43 #define LCD_VERSION_2   2
  44
  45 /* LCD Status Register */
  46 #define LCD_END_OF_FRAME1               BIT(9)
  47 #define LCD_END_OF_FRAME0               BIT(8)
  48 #define LCD_PL_LOAD_DONE                BIT(6)
  49 #define LCD_FIFO_UNDERFLOW              BIT(5)
  50 #define LCD_SYNC_LOST                   BIT(2)
  51
  52 /* LCD DMA Control Register */
  53 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
  54 #define LCD_DMA_BURST_1                 0x0
  55 #define LCD_DMA_BURST_2                 0x1
  56 #define LCD_DMA_BURST_4                 0x2
  57 #define LCD_DMA_BURST_8                 0x3
  58 #define LCD_DMA_BURST_16                0x4
  59 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
  60 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
  61 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
  62 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
  63
  64 /* LCD Control Register */
  65 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
  66 #define LCD_RASTER_MODE                 0x01
  67
  68 /* LCD Raster Control Register */
  69 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
  70 #define PALETTE_AND_DATA                0x00
  71 #define PALETTE_ONLY                    0x01
  72 #define DATA_ONLY                       0x02
  73
  74 #define LCD_MONO_8BIT_MODE              BIT(9)
  75 #define LCD_RASTER_ORDER                BIT(8)
  76 #define LCD_TFT_MODE                    BIT(7)
  77 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
  78 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
  79 #define LCD_V1_PL_INT_ENA               BIT(4)
  80 #define LCD_V2_PL_INT_ENA               BIT(6)
  81 #define LCD_MONOCHROME_MODE             BIT(1)
  82 #define LCD_RASTER_ENABLE               BIT(0)
  83 #define LCD_TFT_ALT_ENABLE              BIT(23)
  84 #define LCD_STN_565_ENABLE              BIT(24)
  85 #define LCD_V2_DMA_CLK_EN               BIT(2)
  86 #define LCD_V2_LIDD_CLK_EN              BIT(1)
  87 #define LCD_V2_CORE_CLK_EN              BIT(0)
  88 #define LCD_V2_LPP_B10                  26
  89
  90 /* LCD Raster Timing 2 Register */
  91 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
  92 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
  93 #define LCD_SYNC_CTRL                           BIT(25)
  94 #define LCD_SYNC_EDGE                           BIT(24)
  95 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
  96 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
  97 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
  98
  99 /* LCD Block */
 100 #define  LCD_PID_REG                            0x0
 101 #define  LCD_CTRL_REG                           0x4
 102 #define  LCD_STAT_REG                           0x8
 103 #define  LCD_RASTER_CTRL_REG                    0x28
 104 #define  LCD_RASTER_TIMING_0_REG                0x2C
 105 #define  LCD_RASTER_TIMING_1_REG                0x30
 106 #define  LCD_RASTER_TIMING_2_REG                0x34
 107 #define  LCD_DMA_CTRL_REG                       0x40
 108 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
 109 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
 110 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
 111 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
 112
 113 /* Interrupt Registers available only in Version 2 */
 114 #define  LCD_RAW_STAT_REG                       0x58
 115 #define  LCD_MASKED_STAT_REG                    0x5c
 116 #define  LCD_INT_ENABLE_SET_REG                 0x60
 117 #define  LCD_INT_ENABLE_CLR_REG                 0x64
 118 #define  LCD_END_OF_INT_IND_REG                 0x68
 119
 120 /* Clock registers available only on Version 2 */
 121 #define  LCD_CLK_ENABLE_REG                     0x6c
 122 #define  LCD_CLK_RESET_REG                      0x70
 123 #define  LCD_CLK_MAIN_RESET                     BIT(3)
 124
 125 #define LCD_NUM_BUFFERS 2
 126
 127 #define WSI_TIMEOUT     50
 128 #define PALETTE_SIZE    256
 129 #define LEFT_MARGIN     64
 130 #define RIGHT_MARGIN    64
 131 #define UPPER_MARGIN    32
 132 #define LOWER_MARGIN    32
 133
 134 static resource_size_t da8xx_fb_reg_base;
 135 static struct resource *lcdc_regs;
 136 static unsigned int lcd_revision;
 137 static irq_handler_t lcdc_irq_handler;
 138
 139 static inline unsigned int lcdc_read(unsigned int addr)
 140 {
 141         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
 142 }
 143
 144 static inline void lcdc_write(unsigned int val, unsigned int addr)
 145 {
 146         __raw_writel(val, da8xx_fb_reg_base + (addr));
 147 }
 148
 149 struct da8xx_fb_par {
 150         resource_size_t p_palette_base;
 151         unsigned char *v_palette_base;
 152         dma_addr_t              vram_phys;
 153         unsigned long           vram_size;
 154         void                    *vram_virt;
 155         unsigned int            dma_start;
 156         unsigned int            dma_end;
 157         struct clk *lcdc_clk;
 158         int irq;
 159         unsigned short pseudo_palette[16];
 160         unsigned int palette_sz;
 161         unsigned int pxl_clk;
 162         int blank;
 163         wait_queue_head_t       vsync_wait;
 164         int                     vsync_flag;
 165         int                     vsync_timeout;
 166         spinlock_t              lock_for_chan_update;
 167
 168         /*
 169          * LCDC has 2 ping pong DMA channels, channel 0
 170          * and channel 1.
 171          */
 172         unsigned int            which_dma_channel_done;
 173 #ifdef CONFIG_CPU_FREQ
 174         struct notifier_block   freq_transition;
 175         unsigned int            lcd_fck_rate;
 176 #endif
 177         void (*panel_power_ctrl)(int);
 178 };
 179
 180 /* Variable Screen Information */
 181 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
 182         .xoffset = 0,
 183         .yoffset = 0,
 184         .transp = {0, 0, 0},
 185         .nonstd = 0,
 186         .activate = 0,
 187         .height = -1,
 188         .width = -1,
 189         .accel_flags = 0,
 190         .left_margin = LEFT_MARGIN,
 191         .right_margin = RIGHT_MARGIN,
 192         .upper_margin = UPPER_MARGIN,
 193         .lower_margin = LOWER_MARGIN,
 194         .sync = 0,
 195         .vmode = FB_VMODE_NONINTERLACED
 196 };
 197
 198 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
 199         .id = "DA8xx FB Drv",
 200         .type = FB_TYPE_PACKED_PIXELS,
 201         .type_aux = 0,
 202         .visual = FB_VISUAL_PSEUDOCOLOR,
 203         .xpanstep = 0,
 204         .ypanstep = 1,
 205         .ywrapstep = 0,
 206         .accel = FB_ACCEL_NONE
 207 };
 208
 209 struct da8xx_panel {
 210         const char      name[25];       /* Full name <vendor>_<model> */
 211         unsigned short  width;
 212         unsigned short  height;
 213         int             hfp;            /* Horizontal front porch */
 214         int             hbp;            /* Horizontal back porch */
 215         int             hsw;            /* Horizontal Sync Pulse Width */
 216         int             vfp;            /* Vertical front porch */
 217         int             vbp;            /* Vertical back porch */
 218         int             vsw;            /* Vertical Sync Pulse Width */
 219         unsigned int    pxl_clk;        /* Pixel clock */
 220         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
 221 };
 222
 223 static struct da8xx_panel known_lcd_panels[] = {
 224         /* Sharp LCD035Q3DG01 */
 225         [0] = {
 226                 .name = "Sharp_LCD035Q3DG01",
 227                 .width = 320,
 228                 .height = 240,
 229                 .hfp = 8,
 230                 .hbp = 6,
 231                 .hsw = 0,
 232                 .vfp = 2,
 233                 .vbp = 2,
 234                 .vsw = 0,
 235                 .pxl_clk = 4608000,
 236                 .invert_pxl_clk = 1,
 237         },
 238         /* Sharp LK043T1DG01 */
 239         [1] = {
 240                 .name = "Sharp_LK043T1DG01",
 241                 .width = 480,
 242                 .height = 272,
 243                 .hfp = 2,
 244                 .hbp = 2,
 245                 .hsw = 41,
 246                 .vfp = 2,
 247                 .vbp = 2,
 248                 .vsw = 10,
 249                 .pxl_clk = 7833600,
 250                 .invert_pxl_clk = 0,
 251         },
 252         [2] = {
 253                 /* Hitachi SP10Q010 */
 254                 .name = "SP10Q010",
 255                 .width = 320,
 256                 .height = 240,
 257                 .hfp = 10,
 258                 .hbp = 10,
 259                 .hsw = 10,
 260                 .vfp = 10,
 261                 .vbp = 10,
 262                 .vsw = 10,
 263                 .pxl_clk = 7833600,
 264                 .invert_pxl_clk = 0,
 265         },
 266 };
 267
 268 /* Enable the Raster Engine of the LCD Controller */
 269 static inline void lcd_enable_raster(void)
 270 {
 271         u32 reg;
 272
 273         /* Put LCDC in reset for several cycles */
 274         if (lcd_revision == LCD_VERSION_2)
 275                 /* Write 1 to reset LCDC */
 276                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 277         mdelay(1);
 278
 279         /* Bring LCDC out of reset */
 280         if (lcd_revision == LCD_VERSION_2)
 281                 lcdc_write(0, LCD_CLK_RESET_REG);
 282         mdelay(1);
 283
 284         /* Above reset sequence doesnot reset register context */
 285         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 286         if (!(reg & LCD_RASTER_ENABLE))
 287                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 288 }
 289
 290 /* Disable the Raster Engine of the LCD Controller */
 291 static inline void lcd_disable_raster(void)
 292 {
 293         u32 reg;
 294
 295         reg = lcdc_read(LCD_RASTER_CTRL_REG);
 296         if (reg & LCD_RASTER_ENABLE)
 297                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
 298 }
 299
 300 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
 301 {
 302         u32 start;
 303         u32 end;
 304         u32 reg_ras;
 305         u32 reg_dma;
 306         u32 reg_int;
 307
 308         /* init reg to clear PLM (loading mode) fields */
 309         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
 310         reg_ras &= ~(3 << 20);
 311
 312         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
 313
 314         if (load_mode == LOAD_DATA) {
 315                 start    = par->dma_start;
 316                 end      = par->dma_end;
 317
 318                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
 319                 if (lcd_revision == LCD_VERSION_1) {
 320                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
 321                 } else {
 322                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 323                                 LCD_V2_END_OF_FRAME0_INT_ENA |
 324                                 LCD_V2_END_OF_FRAME1_INT_ENA;
 325                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 326                 }
 327                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
 328
 329                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 330                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 331                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 332                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 333         } else if (load_mode == LOAD_PALETTE) {
 334                 start    = par->p_palette_base;
 335                 end      = start + par->palette_sz - 1;
 336
 337                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
 338
 339                 if (lcd_revision == LCD_VERSION_1) {
 340                         reg_ras |= LCD_V1_PL_INT_ENA;
 341                 } else {
 342                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 343                                 LCD_V2_PL_INT_ENA;
 344                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 345                 }
 346
 347                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 348                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 349         }
 350
 351         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
 352         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 353
 354         /*
 355          * The Raster enable bit must be set after all other control fields are
 356          * set.
 357          */
 358         lcd_enable_raster();
 359 }
 360
 361 /* Configure the Burst Size and fifo threhold of DMA */
 362 static int lcd_cfg_dma(int burst_size, int fifo_th)
 363 {
 364         u32 reg;
 365
 366         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
 367         switch (burst_size) {
 368         case 1:
 369                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
 370                 break;
 371         case 2:
 372                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
 373                 break;
 374         case 4:
 375                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
 376                 break;
 377         case 8:
 378                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
 379                 break;
 380         case 16:
 381                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
 382                 break;
 383         default:
 384                 return -EINVAL;
 385         }
 386
 387         reg |= (fifo_th << 8);
 388
 389         lcdc_write(reg, LCD_DMA_CTRL_REG);
 390
 391         return 0;
 392 }
 393
 394 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
 395 {
 396         u32 reg;
 397
 398         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
 399         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
 400         reg |= LCD_AC_BIAS_FREQUENCY(period) |
 401                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
 402         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 403 }
 404
 405 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
 406                 int front_porch)
 407 {
 408         u32 reg;
 409
 410         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
 411         reg |= ((back_porch & 0xff) << 24)
 412             | ((front_porch & 0xff) << 16)
 413             | ((pulse_width & 0x3f) << 10);
 414         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 415 }
 416
 417 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
 418                 int front_porch)
 419 {
 420         u32 reg;
 421
 422         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
 423         reg |= ((back_porch & 0xff) << 24)
 424             | ((front_porch & 0xff) << 16)
 425             | ((pulse_width & 0x3f) << 10);
 426         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 427 }
 428
 429 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
 430 {
 431         u32 reg;
 432         u32 reg_int;
 433
 434         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
 435                                                 LCD_MONO_8BIT_MODE |
 436                                                 LCD_MONOCHROME_MODE);
 437
 438         switch (cfg->p_disp_panel->panel_shade) {
 439         case MONOCHROME:
 440                 reg |= LCD_MONOCHROME_MODE;
 441                 if (cfg->mono_8bit_mode)
 442                         reg |= LCD_MONO_8BIT_MODE;
 443                 break;
 444         case COLOR_ACTIVE:
 445                 reg |= LCD_TFT_MODE;
 446                 if (cfg->tft_alt_mode)
 447                         reg |= LCD_TFT_ALT_ENABLE;
 448                 break;
 449
 450         case COLOR_PASSIVE:
 451                 if (cfg->stn_565_mode)
 452                         reg |= LCD_STN_565_ENABLE;
 453                 break;
 454
 455         default:
 456                 return -EINVAL;
 457         }
 458
 459         /* enable additional interrupts here */
 460         if (lcd_revision == LCD_VERSION_1) {
 461                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
 462         } else {
 463                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
 464                         LCD_V2_UNDERFLOW_INT_ENA;
 465                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
 466         }
 467
 468         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 469
 470         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 471
 472         if (cfg->sync_ctrl)
 473                 reg |= LCD_SYNC_CTRL;
 474         else
 475                 reg &= ~LCD_SYNC_CTRL;
 476
 477         if (cfg->sync_edge)
 478                 reg |= LCD_SYNC_EDGE;
 479         else
 480                 reg &= ~LCD_SYNC_EDGE;
 481
 482         if (cfg->invert_line_clock)
 483                 reg |= LCD_INVERT_LINE_CLOCK;
 484         else
 485                 reg &= ~LCD_INVERT_LINE_CLOCK;
 486
 487         if (cfg->invert_frm_clock)
 488                 reg |= LCD_INVERT_FRAME_CLOCK;
 489         else
 490                 reg &= ~LCD_INVERT_FRAME_CLOCK;
 491
 492         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 493
 494         return 0;
 495 }
 496
 497 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
 498                 u32 bpp, u32 raster_order)
 499 {
 500         u32 reg;
 501
 502         /* Set the Panel Width */
 503         /* Pixels per line = (PPL + 1)*16 */
 504         if (lcd_revision == LCD_VERSION_1) {
 505                 /*
 506                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
 507                  * pixels.
 508                  */
 509                 width &= 0x3f0;
 510         } else {
 511                 /*
 512                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
 513                  * pixels.
 514                  */
 515                 width &= 0x7f0;
 516         }
 517
 518         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
 519         reg &= 0xfffffc00;
 520         if (lcd_revision == LCD_VERSION_1) {
 521                 reg |= ((width >> 4) - 1) << 4;
 522         } else {
 523                 width = (width >> 4) - 1;
 524                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
 525         }
 526         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
 527
 528         /* Set the Panel Height */
 529         /* Set bits 9:0 of Lines Per Pixel */
 530         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
 531         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
 532         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
 533
 534         /* Set bit 10 of Lines Per Pixel */
 535         if (lcd_revision == LCD_VERSION_2) {
 536                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
 537                 reg |= ((height - 1) & 0x400) << 16;
 538                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
 539         }
 540
 541         /* Set the Raster Order of the Frame Buffer */
 542         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
 543         if (raster_order)
 544                 reg |= LCD_RASTER_ORDER;
 545         lcdc_write(reg, LCD_RASTER_CTRL_REG);
 546
 547         switch (bpp) {
 548         case 1:
 549         case 2:
 550         case 4:
 551         case 16:
 552                 par->palette_sz = 16 * 2;
 553                 break;
 554
 555         case 8:
 556                 par->palette_sz = 256 * 2;
 557                 break;
 558
 559         default:
 560                 return -EINVAL;
 561         }
 562
 563         return 0;
 564 }
 565
 566 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 567                               unsigned blue, unsigned transp,
 568                               struct fb_info *info)
 569 {
 570         struct da8xx_fb_par *par = info->par;
 571         unsigned short *palette = (unsigned short *) par->v_palette_base;
 572         u_short pal;
 573         int update_hw = 0;
 574
 575         if (regno > 255)
 576                 return 1;
 577
 578         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
 579                 return 1;
 580
 581         if (info->var.bits_per_pixel == 4) {
 582                 if (regno > 15)
 583                         return 1;
 584
 585                 if (info->var.grayscale) {
 586                         pal = regno;
 587                 } else {
 588                         red >>= 4;
 589                         green >>= 8;
 590                         blue >>= 12;
 591
 592                         pal = (red & 0x0f00);
 593                         pal |= (green & 0x00f0);
 594                         pal |= (blue & 0x000f);
 595                 }
 596                 if (regno == 0)
 597                         pal |= 0x2000;
 598                 palette[regno] = pal;
 599
 600         } else if (info->var.bits_per_pixel == 8) {
 601                 red >>= 4;
 602                 green >>= 8;
 603                 blue >>= 12;
 604
 605                 pal = (red & 0x0f00);
 606                 pal |= (green & 0x00f0);
 607                 pal |= (blue & 0x000f);
 608
 609                 if (palette[regno] != pal) {
 610                         update_hw = 1;
 611                         palette[regno] = pal;
 612                 }
 613         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
 614                 red >>= (16 - info->var.red.length);
 615                 red <<= info->var.red.offset;
 616
 617                 green >>= (16 - info->var.green.length);
 618                 green <<= info->var.green.offset;
 619
 620                 blue >>= (16 - info->var.blue.length);
 621                 blue <<= info->var.blue.offset;
 622
 623                 par->pseudo_palette[regno] = red | green | blue;
 624
 625                 if (palette[0] != 0x4000) {
 626                         update_hw = 1;
 627                         palette[0] = 0x4000;
 628                 }
 629         }
 630
 631         /* Update the palette in the h/w as needed. */
 632         if (update_hw)
 633                 lcd_blit(LOAD_PALETTE, par);
 634
 635         return 0;
 636 }
 637
 638 static void lcd_reset(struct da8xx_fb_par *par)
 639 {
 640         /* Disable the Raster if previously Enabled */
 641         lcd_disable_raster();
 642
 643         /* DMA has to be disabled */
 644         lcdc_write(0, LCD_DMA_CTRL_REG);
 645         lcdc_write(0, LCD_RASTER_CTRL_REG);
 646
 647         if (lcd_revision == LCD_VERSION_2) {
 648                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
 649                 /* Write 1 to reset */
 650                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
 651                 lcdc_write(0, LCD_CLK_RESET_REG);
 652         }
 653 }
 654
 655 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
 656 {
 657         unsigned int lcd_clk, div;
 658
 659         lcd_clk = clk_get_rate(par->lcdc_clk);
 660         div = lcd_clk / par->pxl_clk;
 661
 662         /* Configure the LCD clock divisor. */
 663         lcdc_write(LCD_CLK_DIVISOR(div) |
 664                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
 665
 666         if (lcd_revision == LCD_VERSION_2)
 667                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
 668                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
 669
 670 }
 671
 672 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
 673                 struct da8xx_panel *panel)
 674 {
 675         u32 bpp;
 676         int ret = 0;
 677
 678         lcd_reset(par);
 679
 680         /* Calculate the divider */
 681         lcd_calc_clk_divider(par);
 682
 683         if (panel->invert_pxl_clk)
 684                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
 685                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 686         else
 687                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
 688                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
 689
 690         /* Configure the DMA burst size and fifo threshold. */
 691         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
 692         if (ret < 0)
 693                 return ret;
 694
 695         /* Configure the AC bias properties. */
 696         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
 697
 698         /* Configure the vertical and horizontal sync properties. */
 699         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
 700         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
 701
 702         /* Configure for disply */
 703         ret = lcd_cfg_display(cfg);
 704         if (ret < 0)
 705                 return ret;
 706
 707         if (QVGA != cfg->p_disp_panel->panel_type)
 708                 return -EINVAL;
 709
 710         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
 711             cfg->bpp >= cfg->p_disp_panel->min_bpp)
 712                 bpp = cfg->bpp;
 713         else
 714                 bpp = cfg->p_disp_panel->max_bpp;
 715         if (bpp == 12)
 716                 bpp = 16;
 717         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
 718                                 (unsigned int)panel->height, bpp,
 719                                 cfg->raster_order);
 720         if (ret < 0)
 721                 return ret;
 722
 723         /* Configure FDD */
 724         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
 725                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
 726
 727         return 0;
 728 }
 729
 730 /* IRQ handler for version 2 of LCDC */
 731 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
 732 {
 733         struct da8xx_fb_par *par = arg;
 734         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
 735
 736         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 737                 lcd_disable_raster();
 738                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 739                 lcd_enable_raster();
 740         } else if (stat & LCD_PL_LOAD_DONE) {
 741                 /*
 742                  * Must disable raster before changing state of any control bit.
 743                  * And also must be disabled before clearing the PL loading
 744                  * interrupt via the following write to the status register. If
 745                  * this is done after then one gets multiple PL done interrupts.
 746                  */
 747                 lcd_disable_raster();
 748
 749                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 750
 751                 /* Disable PL completion interrupt */
 752                 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
 753
 754                 /* Setup and start data loading mode */
 755                 lcd_blit(LOAD_DATA, par);
 756         } else {
 757                 lcdc_write(stat, LCD_MASKED_STAT_REG);
 758
 759                 if (stat & LCD_END_OF_FRAME0) {
 760                         par->which_dma_channel_done = 0;
 761                         lcdc_write(par->dma_start,
 762                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 763                         lcdc_write(par->dma_end,
 764                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 765                         par->vsync_flag = 1;
 766                         wake_up_interruptible(&par->vsync_wait);
 767                 }
 768
 769                 if (stat & LCD_END_OF_FRAME1) {
 770                         par->which_dma_channel_done = 1;
 771                         lcdc_write(par->dma_start,
 772                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 773                         lcdc_write(par->dma_end,
 774                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 775                         par->vsync_flag = 1;
 776                         wake_up_interruptible(&par->vsync_wait);
 777                 }
 778         }
 779
 780         lcdc_write(0, LCD_END_OF_INT_IND_REG);
 781         return IRQ_HANDLED;
 782 }
 783
 784 /* IRQ handler for version 1 LCDC */
 785 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
 786 {
 787         struct da8xx_fb_par *par = arg;
 788         u32 stat = lcdc_read(LCD_STAT_REG);
 789         u32 reg_ras;
 790
 791         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
 792                 lcd_disable_raster();
 793                 lcdc_write(stat, LCD_STAT_REG);
 794                 lcd_enable_raster();
 795         } else if (stat & LCD_PL_LOAD_DONE) {
 796                 /*
 797                  * Must disable raster before changing state of any control bit.
 798                  * And also must be disabled before clearing the PL loading
 799                  * interrupt via the following write to the status register. If
 800                  * this is done after then one gets multiple PL done interrupts.
 801                  */
 802                 lcd_disable_raster();
 803
 804                 lcdc_write(stat, LCD_STAT_REG);
 805
 806                 /* Disable PL completion inerrupt */
 807                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
 808                 reg_ras &= ~LCD_V1_PL_INT_ENA;
 809                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
 810
 811                 /* Setup and start data loading mode */
 812                 lcd_blit(LOAD_DATA, par);
 813         } else {
 814                 lcdc_write(stat, LCD_STAT_REG);
 815
 816                 if (stat & LCD_END_OF_FRAME0) {
 817                         par->which_dma_channel_done = 0;
 818                         lcdc_write(par->dma_start,
 819                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
 820                         lcdc_write(par->dma_end,
 821                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
 822                         par->vsync_flag = 1;
 823                         wake_up_interruptible(&par->vsync_wait);
 824                 }
 825
 826                 if (stat & LCD_END_OF_FRAME1) {
 827                         par->which_dma_channel_done = 1;
 828                         lcdc_write(par->dma_start,
 829                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
 830                         lcdc_write(par->dma_end,
 831                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
 832                         par->vsync_flag = 1;
 833                         wake_up_interruptible(&par->vsync_wait);
 834                 }
 835         }
 836
 837         return IRQ_HANDLED;
 838 }
 839
 840 static int fb_check_var(struct fb_var_screeninfo *var,
 841                         struct fb_info *info)
 842 {
 843         int err = 0;
 844
 845         switch (var->bits_per_pixel) {
 846         case 1:
 847         case 8:
 848                 var->red.offset = 0;
 849                 var->red.length = 8;
 850                 var->green.offset = 0;
 851                 var->green.length = 8;
 852                 var->blue.offset = 0;
 853                 var->blue.length = 8;
 854                 var->transp.offset = 0;
 855                 var->transp.length = 0;
 856                 var->nonstd = 0;
 857                 break;
 858         case 4:
 859                 var->red.offset = 0;
 860                 var->red.length = 4;
 861                 var->green.offset = 0;
 862                 var->green.length = 4;
 863                 var->blue.offset = 0;
 864                 var->blue.length = 4;
 865                 var->transp.offset = 0;
 866                 var->transp.length = 0;
 867                 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
 868                 break;
 869         case 16:                /* RGB 565 */
 870                 var->red.offset = 11;
 871                 var->red.length = 5;
 872                 var->green.offset = 5;
 873                 var->green.length = 6;
 874                 var->blue.offset = 0;
 875                 var->blue.length = 5;
 876                 var->transp.offset = 0;
 877                 var->transp.length = 0;
 878                 var->nonstd = 0;
 879                 break;
 880         default:
 881                 err = -EINVAL;
 882         }
 883
 884         var->red.msb_right = 0;
 885         var->green.msb_right = 0;
 886         var->blue.msb_right = 0;
 887         var->transp.msb_right = 0;
 888         return err;
 889 }
 890
 891 #ifdef CONFIG_CPU_FREQ
 892 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
 893                                      unsigned long val, void *data)
 894 {
 895         struct da8xx_fb_par *par;
 896
 897         par = container_of(nb, struct da8xx_fb_par, freq_transition);
 898         if (val == CPUFREQ_POSTCHANGE) {
 899                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
 900                         par->lcd_fck_rate = clk_get_rate(par->lcdc_clk);
 901                         lcd_disable_raster();
 902                         lcd_calc_clk_divider(par);
 903                         lcd_enable_raster();
 904                 }
 905         }
 906
 907         return 0;
 908 }
 909
 910 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
 911 {
 912         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
 913
 914         return cpufreq_register_notifier(&par->freq_transition,
 915                                          CPUFREQ_TRANSITION_NOTIFIER);
 916 }
 917
 918 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
 919 {
 920         cpufreq_unregister_notifier(&par->freq_transition,
 921                                     CPUFREQ_TRANSITION_NOTIFIER);
 922 }
 923 #endif
 924
 925 static int __devexit fb_remove(struct platform_device *dev)
 926 {
 927         struct fb_info *info = dev_get_drvdata(&dev->dev);
 928
 929         if (info) {
 930                 struct da8xx_fb_par *par = info->par;
 931
 932 #ifdef CONFIG_CPU_FREQ
 933                 lcd_da8xx_cpufreq_deregister(par);
 934 #endif
 935                 if (par->panel_power_ctrl)
 936                         par->panel_power_ctrl(0);
 937
 938                 lcd_disable_raster();
 939                 lcdc_write(0, LCD_RASTER_CTRL_REG);
 940
 941                 /* disable DMA  */
 942                 lcdc_write(0, LCD_DMA_CTRL_REG);
 943
 944                 unregister_framebuffer(info);
 945                 fb_dealloc_cmap(&info->cmap);
 946                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
 947                                   par->p_palette_base);
 948                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
 949                                   par->vram_phys);
 950                 free_irq(par->irq, par);
 951                 clk_disable(par->lcdc_clk);
 952                 clk_put(par->lcdc_clk);
 953                 framebuffer_release(info);
 954                 iounmap((void __iomem *)da8xx_fb_reg_base);
 955                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
 956
 957         }
 958         return 0;
 959 }
 960
 961 /*
 962  * Function to wait for vertical sync which for this LCD peripheral
 963  * translates into waiting for the current raster frame to complete.
 964  */
 965 static int fb_wait_for_vsync(struct fb_info *info)
 966 {
 967         struct da8xx_fb_par *par = info->par;
 968         int ret;
 969
 970         /*
 971          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
 972          * race condition here where the ISR could have occurred just before or
 973          * just after this set. But since we are just coarsely waiting for
 974          * a frame to complete then that's OK. i.e. if the frame completed
 975          * just before this code executed then we have to wait another full
 976          * frame time but there is no way to avoid such a situation. On the
 977          * other hand if the frame completed just after then we don't need
 978          * to wait long at all. Either way we are guaranteed to return to the
 979          * user immediately after a frame completion which is all that is
 980          * required.
 981          */
 982         par->vsync_flag = 0;
 983         ret = wait_event_interruptible_timeout(par->vsync_wait,
 984                                                par->vsync_flag != 0,
 985                                                par->vsync_timeout);
 986         if (ret < 0)
 987                 return ret;
 988         if (ret == 0)
 989                 return -ETIMEDOUT;
 990
 991         return 0;
 992 }
 993
 994 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
 995                           unsigned long arg)
 996 {
 997         struct lcd_sync_arg sync_arg;
 998
 999         switch (cmd) {
1000         case FBIOGET_CONTRAST:
1001         case FBIOPUT_CONTRAST:
1002         case FBIGET_BRIGHTNESS:
1003         case FBIPUT_BRIGHTNESS:
1004         case FBIGET_COLOR:
1005         case FBIPUT_COLOR:
1006                 return -ENOTTY;
1007         case FBIPUT_HSYNC:
1008                 if (copy_from_user(&sync_arg, (char *)arg,
1009                                 sizeof(struct lcd_sync_arg)))
1010                         return -EFAULT;
1011                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1012                                         sync_arg.pulse_width,
1013                                         sync_arg.front_porch);
1014                 break;
1015         case FBIPUT_VSYNC:
1016                 if (copy_from_user(&sync_arg, (char *)arg,
1017                                 sizeof(struct lcd_sync_arg)))
1018                         return -EFAULT;
1019                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1020                                         sync_arg.pulse_width,
1021                                         sync_arg.front_porch);
1022                 break;
1023         case FBIO_WAITFORVSYNC:
1024                 return fb_wait_for_vsync(info);
1025         default:
1026                 return -EINVAL;
1027         }
1028         return 0;
1029 }
1030
1031 static int cfb_blank(int blank, struct fb_info *info)
1032 {
1033         struct da8xx_fb_par *par = info->par;
1034         int ret = 0;
1035
1036         if (par->blank == blank)
1037                 return 0;
1038
1039         par->blank = blank;
1040         switch (blank) {
1041         case FB_BLANK_UNBLANK:
1042                 lcd_enable_raster();
1043
1044                 if (par->panel_power_ctrl)
1045                         par->panel_power_ctrl(1);
1046                 break;
1047         case FB_BLANK_NORMAL:
1048         case FB_BLANK_VSYNC_SUSPEND:
1049         case FB_BLANK_HSYNC_SUSPEND:
1050         case FB_BLANK_POWERDOWN:
1051                 if (par->panel_power_ctrl)
1052                         par->panel_power_ctrl(0);
1053
1054                 lcd_disable_raster();
1055                 break;
1056         default:
1057                 ret = -EINVAL;
1058         }
1059
1060         return ret;
1061 }
1062
1063 /*
1064  * Set new x,y offsets in the virtual display for the visible area and switch
1065  * to the new mode.
1066  */
1067 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1068                              struct fb_info *fbi)
1069 {
1070         int ret = 0;
1071         struct fb_var_screeninfo new_var;
1072         struct da8xx_fb_par         *par = fbi->par;
1073         struct fb_fix_screeninfo    *fix = &fbi->fix;
1074         unsigned int end;
1075         unsigned int start;
1076         unsigned long irq_flags;
1077
1078         if (var->xoffset != fbi->var.xoffset ||
1079                         var->yoffset != fbi->var.yoffset) {
1080                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1081                 new_var.xoffset = var->xoffset;
1082                 new_var.yoffset = var->yoffset;
1083                 if (fb_check_var(&new_var, fbi))
1084                         ret = -EINVAL;
1085                 else {
1086                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1087
1088                         start   = fix->smem_start +
1089                                 new_var.yoffset * fix->line_length +
1090                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1091                         end     = start + fbi->var.yres * fix->line_length - 1;
1092                         par->dma_start  = start;
1093                         par->dma_end    = end;
1094                         spin_lock_irqsave(&par->lock_for_chan_update,
1095                                         irq_flags);
1096                         if (par->which_dma_channel_done == 0) {
1097                                 lcdc_write(par->dma_start,
1098                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1099                                 lcdc_write(par->dma_end,
1100                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1101                         } else if (par->which_dma_channel_done == 1) {
1102                                 lcdc_write(par->dma_start,
1103                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1104                                 lcdc_write(par->dma_end,
1105                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1106                         }
1107                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1108                                         irq_flags);
1109                 }
1110         }
1111
1112         return ret;
1113 }
1114
1115 static struct fb_ops da8xx_fb_ops = {
1116         .owner = THIS_MODULE,
1117         .fb_check_var = fb_check_var,
1118         .fb_setcolreg = fb_setcolreg,
1119         .fb_pan_display = da8xx_pan_display,
1120         .fb_ioctl = fb_ioctl,
1121         .fb_fillrect = cfb_fillrect,
1122         .fb_copyarea = cfb_copyarea,
1123         .fb_imageblit = cfb_imageblit,
1124         .fb_blank = cfb_blank,
1125 };
1126
1127 /* Calculate and return pixel clock period in pico seconds */
1128 static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par)
1129 {
1130         unsigned int lcd_clk, div;
1131         unsigned int configured_pix_clk;
1132         unsigned long long pix_clk_period_picosec = 1000000000000ULL;
1133
1134         lcd_clk = clk_get_rate(par->lcdc_clk);
1135         div = lcd_clk / par->pxl_clk;
1136         configured_pix_clk = (lcd_clk / div);
1137
1138         do_div(pix_clk_period_picosec, configured_pix_clk);
1139
1140         return pix_clk_period_picosec;
1141 }
1142
1143 static int __devinit fb_probe(struct platform_device *device)
1144 {
1145         struct da8xx_lcdc_platform_data *fb_pdata =
1146                                                 device->dev.platform_data;
1147         struct lcd_ctrl_config *lcd_cfg;
1148         struct da8xx_panel *lcdc_info;
1149         struct fb_info *da8xx_fb_info;
1150         struct clk *fb_clk = NULL;
1151         struct da8xx_fb_par *par;
1152         resource_size_t len;
1153         int ret, i;
1154         unsigned long ulcm;
1155
1156         if (fb_pdata == NULL) {
1157                 dev_err(&device->dev, "Can not get platform data\n");
1158                 return -ENOENT;
1159         }
1160
1161         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1162         if (!lcdc_regs) {
1163                 dev_err(&device->dev,
1164                         "Can not get memory resource for LCD controller\n");
1165                 return -ENOENT;
1166         }
1167
1168         len = resource_size(lcdc_regs);
1169
1170         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1171         if (!lcdc_regs)
1172                 return -EBUSY;
1173
1174         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1175         if (!da8xx_fb_reg_base) {
1176                 ret = -EBUSY;
1177                 goto err_request_mem;
1178         }
1179
1180         fb_clk = clk_get(&device->dev, NULL);
1181         if (IS_ERR(fb_clk)) {
1182                 dev_err(&device->dev, "Can not get device clock\n");
1183                 ret = -ENODEV;
1184                 goto err_ioremap;
1185         }
1186         ret = clk_enable(fb_clk);
1187         if (ret)
1188                 goto err_clk_put;
1189
1190         /* Determine LCD IP Version */
1191         switch (lcdc_read(LCD_PID_REG)) {
1192         case 0x4C100102:
1193                 lcd_revision = LCD_VERSION_1;
1194                 break;
1195         case 0x4F200800:
1196                 lcd_revision = LCD_VERSION_2;
1197                 break;
1198         default:
1199                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1200                                 "defaulting to LCD revision 1\n",
1201                                 lcdc_read(LCD_PID_REG));
1202                 lcd_revision = LCD_VERSION_1;
1203                 break;
1204         }
1205
1206         for (i = 0, lcdc_info = known_lcd_panels;
1207                 i < ARRAY_SIZE(known_lcd_panels);
1208                 i++, lcdc_info++) {
1209                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1210                         break;
1211         }
1212
1213         if (i == ARRAY_SIZE(known_lcd_panels)) {
1214                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1215                 ret = -ENODEV;
1216                 goto err_clk_disable;
1217         } else
1218                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1219                                         fb_pdata->type);
1220
1221         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1222
1223         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1224                                         &device->dev);
1225         if (!da8xx_fb_info) {
1226                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1227                 ret = -ENOMEM;
1228                 goto err_clk_disable;
1229         }
1230
1231         par = da8xx_fb_info->par;
1232         par->lcdc_clk = fb_clk;
1233 #ifdef CONFIG_CPU_FREQ
1234         par->lcd_fck_rate = clk_get_rate(fb_clk);
1235 #endif
1236         par->pxl_clk = lcdc_info->pxl_clk;
1237         if (fb_pdata->panel_power_ctrl) {
1238                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1239                 par->panel_power_ctrl(1);
1240         }
1241
1242         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1243                 dev_err(&device->dev, "lcd_init failed\n");
1244                 ret = -EFAULT;
1245                 goto err_release_fb;
1246         }
1247
1248         /* allocate frame buffer */
1249         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1250         ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE);
1251         par->vram_size = roundup(par->vram_size/8, ulcm);
1252         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1253
1254         par->vram_virt = dma_alloc_coherent(NULL,
1255                                             par->vram_size,
1256                                             (resource_size_t *) &par->vram_phys,
1257                                             GFP_KERNEL | GFP_DMA);
1258         if (!par->vram_virt) {
1259                 dev_err(&device->dev,
1260                         "GLCD: kmalloc for frame buffer failed\n");
1261                 ret = -EINVAL;
1262                 goto err_release_fb;
1263         }
1264
1265         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1266         da8xx_fb_fix.smem_start    = par->vram_phys;
1267         da8xx_fb_fix.smem_len      = par->vram_size;
1268         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1269
1270         par->dma_start = par->vram_phys;
1271         par->dma_end   = par->dma_start + lcdc_info->height *
1272                 da8xx_fb_fix.line_length - 1;
1273
1274         /* allocate palette buffer */
1275         par->v_palette_base = dma_alloc_coherent(NULL,
1276                                                PALETTE_SIZE,
1277                                                (resource_size_t *)
1278                                                &par->p_palette_base,
1279                                                GFP_KERNEL | GFP_DMA);
1280         if (!par->v_palette_base) {
1281                 dev_err(&device->dev,
1282                         "GLCD: kmalloc for palette buffer failed\n");
1283                 ret = -EINVAL;
1284                 goto err_release_fb_mem;
1285         }
1286         memset(par->v_palette_base, 0, PALETTE_SIZE);
1287
1288         par->irq = platform_get_irq(device, 0);
1289         if (par->irq < 0) {
1290                 ret = -ENOENT;
1291                 goto err_release_pl_mem;
1292         }
1293
1294         /* Initialize par */
1295         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1296
1297         da8xx_fb_var.xres = lcdc_info->width;
1298         da8xx_fb_var.xres_virtual = lcdc_info->width;
1299
1300         da8xx_fb_var.yres         = lcdc_info->height;
1301         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1302
1303         da8xx_fb_var.grayscale =
1304             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1305         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1306
1307         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1308         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1309         da8xx_fb_var.right_margin = lcdc_info->hfp;
1310         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1311         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1312         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1313         da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par);
1314
1315         /* Initialize fbinfo */
1316         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1317         da8xx_fb_info->fix = da8xx_fb_fix;
1318         da8xx_fb_info->var = da8xx_fb_var;
1319         da8xx_fb_info->fbops = &da8xx_fb_ops;
1320         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1321         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1322                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1323
1324         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1325         if (ret)
1326                 goto err_release_pl_mem;
1327         da8xx_fb_info->cmap.len = par->palette_sz;
1328
1329         /* initialize var_screeninfo */
1330         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1331         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1332
1333         dev_set_drvdata(&device->dev, da8xx_fb_info);
1334
1335         /* initialize the vsync wait queue */
1336         init_waitqueue_head(&par->vsync_wait);
1337         par->vsync_timeout = HZ / 5;
1338         par->which_dma_channel_done = -1;
1339         spin_lock_init(&par->lock_for_chan_update);
1340
1341         /* Register the Frame Buffer  */
1342         if (register_framebuffer(da8xx_fb_info) < 0) {
1343                 dev_err(&device->dev,
1344                         "GLCD: Frame Buffer Registration Failed!\n");
1345                 ret = -EINVAL;
1346                 goto err_dealloc_cmap;
1347         }
1348
1349 #ifdef CONFIG_CPU_FREQ
1350         ret = lcd_da8xx_cpufreq_register(par);
1351         if (ret) {
1352                 dev_err(&device->dev, "failed to register cpufreq\n");
1353                 goto err_cpu_freq;
1354         }
1355 #endif
1356
1357         if (lcd_revision == LCD_VERSION_1)
1358                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1359         else
1360                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1361
1362         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1363                         DRIVER_NAME, par);
1364         if (ret)
1365                 goto irq_freq;
1366         return 0;
1367
1368 irq_freq:
1369 #ifdef CONFIG_CPU_FREQ
1370         lcd_da8xx_cpufreq_deregister(par);
1371 err_cpu_freq:
1372 #endif
1373         unregister_framebuffer(da8xx_fb_info);
1374
1375 err_dealloc_cmap:
1376         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1377
1378 err_release_pl_mem:
1379         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1380                           par->p_palette_base);
1381
1382 err_release_fb_mem:
1383         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1384
1385 err_release_fb:
1386         framebuffer_release(da8xx_fb_info);
1387
1388 err_clk_disable:
1389         clk_disable(fb_clk);
1390
1391 err_clk_put:
1392         clk_put(fb_clk);
1393
1394 err_ioremap:
1395         iounmap((void __iomem *)da8xx_fb_reg_base);
1396
1397 err_request_mem:
1398         release_mem_region(lcdc_regs->start, len);
1399
1400         return ret;
1401 }
1402
1403 #ifdef CONFIG_PM
1404 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1405 {
1406         struct fb_info *info = platform_get_drvdata(dev);
1407         struct da8xx_fb_par *par = info->par;
1408
1409         console_lock();
1410         if (par->panel_power_ctrl)
1411                 par->panel_power_ctrl(0);
1412
1413         fb_set_suspend(info, 1);
1414         lcd_disable_raster();
1415         clk_disable(par->lcdc_clk);
1416         console_unlock();
1417
1418         return 0;
1419 }
1420 static int fb_resume(struct platform_device *dev)
1421 {
1422         struct fb_info *info = platform_get_drvdata(dev);
1423         struct da8xx_fb_par *par = info->par;
1424
1425         console_lock();
1426         clk_enable(par->lcdc_clk);
1427         lcd_enable_raster();
1428
1429         if (par->panel_power_ctrl)
1430                 par->panel_power_ctrl(1);
1431
1432         fb_set_suspend(info, 0);
1433         console_unlock();
1434
1435         return 0;
1436 }
1437 #else
1438 #define fb_suspend NULL
1439 #define fb_resume NULL
1440 #endif
1441
1442 static struct platform_driver da8xx_fb_driver = {
1443         .probe = fb_probe,
1444         .remove = __devexit_p(fb_remove),
1445         .suspend = fb_suspend,
1446         .resume = fb_resume,
1447         .driver = {
1448                    .name = DRIVER_NAME,
1449                    .owner = THIS_MODULE,
1450                    },
1451 };
1452
1453 static int __init da8xx_fb_init(void)
1454 {
1455         return platform_driver_register(&da8xx_fb_driver);
1456 }
1457
1458 static void __exit da8xx_fb_cleanup(void)
1459 {
1460         platform_driver_unregister(&da8xx_fb_driver);
1461 }
1462
1463 module_init(da8xx_fb_init);
1464 module_exit(da8xx_fb_cleanup);
1465
1466 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1467 MODULE_AUTHOR("Texas Instruments");
1468 MODULE_LICENSE("GPL");