Pileus Git - ~andy/linux/blob - drivers/usb/phy/tegra_usb_phy.c

   1 /*
   2  * Copyright (C) 2010 Google, Inc.
   3  *
   4  * Author:
   5  *      Erik Gilling <konkers@google.com>
   6  *      Benoit Goby <benoit@android.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/resource.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/err.h>
  23 #include <linux/export.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/io.h>
  26 #include <linux/gpio.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/usb/otg.h>
  29 #include <linux/usb/ulpi.h>
  30 #include <asm/mach-types.h>
  31 #include <linux/usb/tegra_usb_phy.h>
  32
  33 #define TEGRA_USB_BASE          0xC5000000
  34 #define TEGRA_USB_SIZE          SZ_16K
  35
  36 #define ULPI_VIEWPORT           0x170
  37
  38 #define USB_PORTSC1             0x184
  39 #define   USB_PORTSC1_PTS(x)    (((x) & 0x3) << 30)
  40 #define   USB_PORTSC1_PSPD(x)   (((x) & 0x3) << 26)
  41 #define   USB_PORTSC1_PHCD      (1 << 23)
  42 #define   USB_PORTSC1_WKOC      (1 << 22)
  43 #define   USB_PORTSC1_WKDS      (1 << 21)
  44 #define   USB_PORTSC1_WKCN      (1 << 20)
  45 #define   USB_PORTSC1_PTC(x)    (((x) & 0xf) << 16)
  46 #define   USB_PORTSC1_PP        (1 << 12)
  47 #define   USB_PORTSC1_SUSP      (1 << 7)
  48 #define   USB_PORTSC1_PE        (1 << 2)
  49 #define   USB_PORTSC1_CCS       (1 << 0)
  50
  51 #define USB_SUSP_CTRL           0x400
  52 #define   USB_WAKE_ON_CNNT_EN_DEV       (1 << 3)
  53 #define   USB_WAKE_ON_DISCON_EN_DEV     (1 << 4)
  54 #define   USB_SUSP_CLR          (1 << 5)
  55 #define   USB_PHY_CLK_VALID     (1 << 7)
  56 #define   UTMIP_RESET                   (1 << 11)
  57 #define   UHSIC_RESET                   (1 << 11)
  58 #define   UTMIP_PHY_ENABLE              (1 << 12)
  59 #define   ULPI_PHY_ENABLE       (1 << 13)
  60 #define   USB_SUSP_SET          (1 << 14)
  61 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)  (((x) & 0x7) << 16)
  62
  63 #define USB1_LEGACY_CTRL        0x410
  64 #define   USB1_NO_LEGACY_MODE                   (1 << 0)
  65 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  66 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  67 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  68                                                 (1 << 1)
  69 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  70 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  71
  72 #define ULPI_TIMING_CTRL_0      0x424
  73 #define   ULPI_OUTPUT_PINMUX_BYP        (1 << 10)
  74 #define   ULPI_CLKOUT_PINMUX_BYP        (1 << 11)
  75
  76 #define ULPI_TIMING_CTRL_1      0x428
  77 #define   ULPI_DATA_TRIMMER_LOAD        (1 << 0)
  78 #define   ULPI_DATA_TRIMMER_SEL(x)      (((x) & 0x7) << 1)
  79 #define   ULPI_STPDIRNXT_TRIMMER_LOAD   (1 << 16)
  80 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  81 #define   ULPI_DIR_TRIMMER_LOAD         (1 << 24)
  82 #define   ULPI_DIR_TRIMMER_SEL(x)       (((x) & 0x7) << 25)
  83
  84 #define UTMIP_PLL_CFG1          0x804
  85 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  86 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  87
  88 #define UTMIP_XCVR_CFG0         0x808
  89 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  90 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  91 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  92 #define   UTMIP_FORCE_PD_POWERDOWN              (1 << 14)
  93 #define   UTMIP_FORCE_PD2_POWERDOWN             (1 << 16)
  94 #define   UTMIP_FORCE_PDZI_POWERDOWN            (1 << 18)
  95 #define   UTMIP_XCVR_HSSLEW_MSB(x)              (((x) & 0x7f) << 25)
  96
  97 #define UTMIP_BIAS_CFG0         0x80c
  98 #define   UTMIP_OTGPD                   (1 << 11)
  99 #define   UTMIP_BIASPD                  (1 << 10)
 100
 101 #define UTMIP_HSRX_CFG0         0x810
 102 #define   UTMIP_ELASTIC_LIMIT(x)        (((x) & 0x1f) << 10)
 103 #define   UTMIP_IDLE_WAIT(x)            (((x) & 0x1f) << 15)
 104
 105 #define UTMIP_HSRX_CFG1         0x814
 106 #define   UTMIP_HS_SYNC_START_DLY(x)    (((x) & 0x1f) << 1)
 107
 108 #define UTMIP_TX_CFG0           0x820
 109 #define   UTMIP_FS_PREABMLE_J           (1 << 19)
 110 #define   UTMIP_HS_DISCON_DISABLE       (1 << 8)
 111
 112 #define UTMIP_MISC_CFG0         0x824
 113 #define   UTMIP_DPDM_OBSERVE            (1 << 26)
 114 #define   UTMIP_DPDM_OBSERVE_SEL(x)     (((x) & 0xf) << 27)
 115 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J   UTMIP_DPDM_OBSERVE_SEL(0xf)
 116 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K   UTMIP_DPDM_OBSERVE_SEL(0xe)
 117 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
 118 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
 119 #define   UTMIP_SUSPEND_EXIT_ON_EDGE    (1 << 22)
 120
 121 #define UTMIP_MISC_CFG1         0x828
 122 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
 123 #define   UTMIP_PLLU_STABLE_COUNT(x)    (((x) & 0xfff) << 6)
 124
 125 #define UTMIP_DEBOUNCE_CFG0     0x82c
 126 #define   UTMIP_BIAS_DEBOUNCE_A(x)      (((x) & 0xffff) << 0)
 127
 128 #define UTMIP_BAT_CHRG_CFG0     0x830
 129 #define   UTMIP_PD_CHRG                 (1 << 0)
 130
 131 #define UTMIP_SPARE_CFG0        0x834
 132 #define   FUSE_SETUP_SEL                (1 << 3)
 133
 134 #define UTMIP_XCVR_CFG1         0x838
 135 #define   UTMIP_FORCE_PDDISC_POWERDOWN  (1 << 0)
 136 #define   UTMIP_FORCE_PDCHRP_POWERDOWN  (1 << 2)
 137 #define   UTMIP_FORCE_PDDR_POWERDOWN    (1 << 4)
 138 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)  (((x) & 0xf) << 18)
 139
 140 #define UTMIP_BIAS_CFG1         0x83c
 141 #define   UTMIP_BIAS_PDTRK_COUNT(x)     (((x) & 0x1f) << 3)
 142
 143 static DEFINE_SPINLOCK(utmip_pad_lock);
 144 static int utmip_pad_count;
 145
 146 struct tegra_xtal_freq {
 147         int freq;
 148         u8 enable_delay;
 149         u8 stable_count;
 150         u8 active_delay;
 151         u8 xtal_freq_count;
 152         u16 debounce;
 153 };
 154
 155 static const struct tegra_xtal_freq tegra_freq_table[] = {
 156         {
 157                 .freq = 12000000,
 158                 .enable_delay = 0x02,
 159                 .stable_count = 0x2F,
 160                 .active_delay = 0x04,
 161                 .xtal_freq_count = 0x76,
 162                 .debounce = 0x7530,
 163         },
 164         {
 165                 .freq = 13000000,
 166                 .enable_delay = 0x02,
 167                 .stable_count = 0x33,
 168                 .active_delay = 0x05,
 169                 .xtal_freq_count = 0x7F,
 170                 .debounce = 0x7EF4,
 171         },
 172         {
 173                 .freq = 19200000,
 174                 .enable_delay = 0x03,
 175                 .stable_count = 0x4B,
 176                 .active_delay = 0x06,
 177                 .xtal_freq_count = 0xBB,
 178                 .debounce = 0xBB80,
 179         },
 180         {
 181                 .freq = 26000000,
 182                 .enable_delay = 0x04,
 183                 .stable_count = 0x66,
 184                 .active_delay = 0x09,
 185                 .xtal_freq_count = 0xFE,
 186                 .debounce = 0xFDE8,
 187         },
 188 };
 189
 190 static struct tegra_utmip_config utmip_default[] = {
 191         [0] = {
 192                 .hssync_start_delay = 9,
 193                 .idle_wait_delay = 17,
 194                 .elastic_limit = 16,
 195                 .term_range_adj = 6,
 196                 .xcvr_setup = 9,
 197                 .xcvr_lsfslew = 1,
 198                 .xcvr_lsrslew = 1,
 199         },
 200         [2] = {
 201                 .hssync_start_delay = 9,
 202                 .idle_wait_delay = 17,
 203                 .elastic_limit = 16,
 204                 .term_range_adj = 6,
 205                 .xcvr_setup = 9,
 206                 .xcvr_lsfslew = 2,
 207                 .xcvr_lsrslew = 2,
 208         },
 209 };
 210
 211 static inline bool phy_is_ulpi(struct tegra_usb_phy *phy)
 212 {
 213         return (phy->instance == 1);
 214 }
 215
 216 static int utmip_pad_open(struct tegra_usb_phy *phy)
 217 {
 218         phy->pad_clk = clk_get_sys("utmip-pad", NULL);
 219         if (IS_ERR(phy->pad_clk)) {
 220                 pr_err("%s: can't get utmip pad clock\n", __func__);
 221                 return PTR_ERR(phy->pad_clk);
 222         }
 223
 224         if (phy->instance == 0) {
 225                 phy->pad_regs = phy->regs;
 226         } else {
 227                 phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE);
 228                 if (!phy->pad_regs) {
 229                         pr_err("%s: can't remap usb registers\n", __func__);
 230                         clk_put(phy->pad_clk);
 231                         return -ENOMEM;
 232                 }
 233         }
 234         return 0;
 235 }
 236
 237 static void utmip_pad_close(struct tegra_usb_phy *phy)
 238 {
 239         if (phy->instance != 0)
 240                 iounmap(phy->pad_regs);
 241         clk_put(phy->pad_clk);
 242 }
 243
 244 static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 245 {
 246         unsigned long val, flags;
 247         void __iomem *base = phy->pad_regs;
 248
 249         clk_prepare_enable(phy->pad_clk);
 250
 251         spin_lock_irqsave(&utmip_pad_lock, flags);
 252
 253         if (utmip_pad_count++ == 0) {
 254                 val = readl(base + UTMIP_BIAS_CFG0);
 255                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 256                 writel(val, base + UTMIP_BIAS_CFG0);
 257         }
 258
 259         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 260
 261         clk_disable_unprepare(phy->pad_clk);
 262 }
 263
 264 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 265 {
 266         unsigned long val, flags;
 267         void __iomem *base = phy->pad_regs;
 268
 269         if (!utmip_pad_count) {
 270                 pr_err("%s: utmip pad already powered off\n", __func__);
 271                 return -EINVAL;
 272         }
 273
 274         clk_prepare_enable(phy->pad_clk);
 275
 276         spin_lock_irqsave(&utmip_pad_lock, flags);
 277
 278         if (--utmip_pad_count == 0) {
 279                 val = readl(base + UTMIP_BIAS_CFG0);
 280                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 281                 writel(val, base + UTMIP_BIAS_CFG0);
 282         }
 283
 284         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 285
 286         clk_disable_unprepare(phy->pad_clk);
 287
 288         return 0;
 289 }
 290
 291 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 292 {
 293         unsigned long timeout = 2000;
 294         do {
 295                 if ((readl(reg) & mask) == result)
 296                         return 0;
 297                 udelay(1);
 298                 timeout--;
 299         } while (timeout);
 300         return -1;
 301 }
 302
 303 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 304 {
 305         unsigned long val;
 306         void __iomem *base = phy->regs;
 307
 308         if (phy->instance == 0) {
 309                 val = readl(base + USB_SUSP_CTRL);
 310                 val |= USB_SUSP_SET;
 311                 writel(val, base + USB_SUSP_CTRL);
 312
 313                 udelay(10);
 314
 315                 val = readl(base + USB_SUSP_CTRL);
 316                 val &= ~USB_SUSP_SET;
 317                 writel(val, base + USB_SUSP_CTRL);
 318         }
 319
 320         if (phy->instance == 2) {
 321                 val = readl(base + USB_PORTSC1);
 322                 val |= USB_PORTSC1_PHCD;
 323                 writel(val, base + USB_PORTSC1);
 324         }
 325
 326         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0)
 327                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 328 }
 329
 330 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 331 {
 332         unsigned long val;
 333         void __iomem *base = phy->regs;
 334
 335         if (phy->instance == 0) {
 336                 val = readl(base + USB_SUSP_CTRL);
 337                 val |= USB_SUSP_CLR;
 338                 writel(val, base + USB_SUSP_CTRL);
 339
 340                 udelay(10);
 341
 342                 val = readl(base + USB_SUSP_CTRL);
 343                 val &= ~USB_SUSP_CLR;
 344                 writel(val, base + USB_SUSP_CTRL);
 345         }
 346
 347         if (phy->instance == 2) {
 348                 val = readl(base + USB_PORTSC1);
 349                 val &= ~USB_PORTSC1_PHCD;
 350                 writel(val, base + USB_PORTSC1);
 351         }
 352
 353         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 354                                                      USB_PHY_CLK_VALID))
 355                 pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
 356 }
 357
 358 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 359 {
 360         unsigned long val;
 361         void __iomem *base = phy->regs;
 362         struct tegra_utmip_config *config = phy->config;
 363
 364         val = readl(base + USB_SUSP_CTRL);
 365         val |= UTMIP_RESET;
 366         writel(val, base + USB_SUSP_CTRL);
 367
 368         if (phy->instance == 0) {
 369                 val = readl(base + USB1_LEGACY_CTRL);
 370                 val |= USB1_NO_LEGACY_MODE;
 371                 writel(val, base + USB1_LEGACY_CTRL);
 372         }
 373
 374         val = readl(base + UTMIP_TX_CFG0);
 375         val &= ~UTMIP_FS_PREABMLE_J;
 376         writel(val, base + UTMIP_TX_CFG0);
 377
 378         val = readl(base + UTMIP_HSRX_CFG0);
 379         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 380         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 381         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 382         writel(val, base + UTMIP_HSRX_CFG0);
 383
 384         val = readl(base + UTMIP_HSRX_CFG1);
 385         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 386         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 387         writel(val, base + UTMIP_HSRX_CFG1);
 388
 389         val = readl(base + UTMIP_DEBOUNCE_CFG0);
 390         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 391         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 392         writel(val, base + UTMIP_DEBOUNCE_CFG0);
 393
 394         val = readl(base + UTMIP_MISC_CFG0);
 395         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 396         writel(val, base + UTMIP_MISC_CFG0);
 397
 398         val = readl(base + UTMIP_MISC_CFG1);
 399         val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0));
 400         val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 401                 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 402         writel(val, base + UTMIP_MISC_CFG1);
 403
 404         val = readl(base + UTMIP_PLL_CFG1);
 405         val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 406         val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 407                 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 408         writel(val, base + UTMIP_PLL_CFG1);
 409
 410         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 411                 val = readl(base + USB_SUSP_CTRL);
 412                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 413                 writel(val, base + USB_SUSP_CTRL);
 414         }
 415
 416         utmip_pad_power_on(phy);
 417
 418         val = readl(base + UTMIP_XCVR_CFG0);
 419         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 420                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) |
 421                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) |
 422                  UTMIP_XCVR_HSSLEW_MSB(~0));
 423         val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 424         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 425         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 426         writel(val, base + UTMIP_XCVR_CFG0);
 427
 428         val = readl(base + UTMIP_XCVR_CFG1);
 429         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 430                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 431         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 432         writel(val, base + UTMIP_XCVR_CFG1);
 433
 434         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 435         val &= ~UTMIP_PD_CHRG;
 436         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 437
 438         val = readl(base + UTMIP_BIAS_CFG1);
 439         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 440         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 441         writel(val, base + UTMIP_BIAS_CFG1);
 442
 443         if (phy->instance == 0) {
 444                 val = readl(base + UTMIP_SPARE_CFG0);
 445                 if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE)
 446                         val &= ~FUSE_SETUP_SEL;
 447                 else
 448                         val |= FUSE_SETUP_SEL;
 449                 writel(val, base + UTMIP_SPARE_CFG0);
 450         }
 451
 452         if (phy->instance == 2) {
 453                 val = readl(base + USB_SUSP_CTRL);
 454                 val |= UTMIP_PHY_ENABLE;
 455                 writel(val, base + USB_SUSP_CTRL);
 456         }
 457
 458         val = readl(base + USB_SUSP_CTRL);
 459         val &= ~UTMIP_RESET;
 460         writel(val, base + USB_SUSP_CTRL);
 461
 462         if (phy->instance == 0) {
 463                 val = readl(base + USB1_LEGACY_CTRL);
 464                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 465                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 466                 writel(val, base + USB1_LEGACY_CTRL);
 467
 468                 val = readl(base + USB_SUSP_CTRL);
 469                 val &= ~USB_SUSP_SET;
 470                 writel(val, base + USB_SUSP_CTRL);
 471         }
 472
 473         utmi_phy_clk_enable(phy);
 474
 475         if (phy->instance == 2) {
 476                 val = readl(base + USB_PORTSC1);
 477                 val &= ~USB_PORTSC1_PTS(~0);
 478                 writel(val, base + USB_PORTSC1);
 479         }
 480
 481         return 0;
 482 }
 483
 484 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 485 {
 486         unsigned long val;
 487         void __iomem *base = phy->regs;
 488
 489         utmi_phy_clk_disable(phy);
 490
 491         if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 492                 val = readl(base + USB_SUSP_CTRL);
 493                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 494                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 495                 writel(val, base + USB_SUSP_CTRL);
 496         }
 497
 498         val = readl(base + USB_SUSP_CTRL);
 499         val |= UTMIP_RESET;
 500         writel(val, base + USB_SUSP_CTRL);
 501
 502         val = readl(base + UTMIP_BAT_CHRG_CFG0);
 503         val |= UTMIP_PD_CHRG;
 504         writel(val, base + UTMIP_BAT_CHRG_CFG0);
 505
 506         val = readl(base + UTMIP_XCVR_CFG0);
 507         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 508                UTMIP_FORCE_PDZI_POWERDOWN;
 509         writel(val, base + UTMIP_XCVR_CFG0);
 510
 511         val = readl(base + UTMIP_XCVR_CFG1);
 512         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 513                UTMIP_FORCE_PDDR_POWERDOWN;
 514         writel(val, base + UTMIP_XCVR_CFG1);
 515
 516         return utmip_pad_power_off(phy);
 517 }
 518
 519 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 520 {
 521         unsigned long val;
 522         void __iomem *base = phy->regs;
 523
 524         val = readl(base + UTMIP_TX_CFG0);
 525         val |= UTMIP_HS_DISCON_DISABLE;
 526         writel(val, base + UTMIP_TX_CFG0);
 527 }
 528
 529 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 530 {
 531         unsigned long val;
 532         void __iomem *base = phy->regs;
 533
 534         val = readl(base + UTMIP_TX_CFG0);
 535         val &= ~UTMIP_HS_DISCON_DISABLE;
 536         writel(val, base + UTMIP_TX_CFG0);
 537 }
 538
 539 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 540                                    enum tegra_usb_phy_port_speed port_speed)
 541 {
 542         unsigned long val;
 543         void __iomem *base = phy->regs;
 544
 545         val = readl(base + UTMIP_MISC_CFG0);
 546         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 547         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 548                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 549         else
 550                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 551         writel(val, base + UTMIP_MISC_CFG0);
 552         udelay(1);
 553
 554         val = readl(base + UTMIP_MISC_CFG0);
 555         val |= UTMIP_DPDM_OBSERVE;
 556         writel(val, base + UTMIP_MISC_CFG0);
 557         udelay(10);
 558 }
 559
 560 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 561 {
 562         unsigned long val;
 563         void __iomem *base = phy->regs;
 564
 565         val = readl(base + UTMIP_MISC_CFG0);
 566         val &= ~UTMIP_DPDM_OBSERVE;
 567         writel(val, base + UTMIP_MISC_CFG0);
 568         udelay(10);
 569 }
 570
 571 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 572 {
 573         int ret;
 574         unsigned long val;
 575         void __iomem *base = phy->regs;
 576         struct tegra_ulpi_config *config = phy->config;
 577
 578         gpio_direction_output(config->reset_gpio, 0);
 579         msleep(5);
 580         gpio_direction_output(config->reset_gpio, 1);
 581
 582         clk_prepare_enable(phy->clk);
 583         msleep(1);
 584
 585         val = readl(base + USB_SUSP_CTRL);
 586         val |= UHSIC_RESET;
 587         writel(val, base + USB_SUSP_CTRL);
 588
 589         val = readl(base + ULPI_TIMING_CTRL_0);
 590         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 591         writel(val, base + ULPI_TIMING_CTRL_0);
 592
 593         val = readl(base + USB_SUSP_CTRL);
 594         val |= ULPI_PHY_ENABLE;
 595         writel(val, base + USB_SUSP_CTRL);
 596
 597         val = 0;
 598         writel(val, base + ULPI_TIMING_CTRL_1);
 599
 600         val |= ULPI_DATA_TRIMMER_SEL(4);
 601         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 602         val |= ULPI_DIR_TRIMMER_SEL(4);
 603         writel(val, base + ULPI_TIMING_CTRL_1);
 604         udelay(10);
 605
 606         val |= ULPI_DATA_TRIMMER_LOAD;
 607         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 608         val |= ULPI_DIR_TRIMMER_LOAD;
 609         writel(val, base + ULPI_TIMING_CTRL_1);
 610
 611         /* Fix VbusInvalid due to floating VBUS */
 612         ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 613         if (ret) {
 614                 pr_err("%s: ulpi write failed\n", __func__);
 615                 return ret;
 616         }
 617
 618         ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 619         if (ret) {
 620                 pr_err("%s: ulpi write failed\n", __func__);
 621                 return ret;
 622         }
 623
 624         val = readl(base + USB_PORTSC1);
 625         val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN;
 626         writel(val, base + USB_PORTSC1);
 627
 628         val = readl(base + USB_SUSP_CTRL);
 629         val |= USB_SUSP_CLR;
 630         writel(val, base + USB_SUSP_CTRL);
 631         udelay(100);
 632
 633         val = readl(base + USB_SUSP_CTRL);
 634         val &= ~USB_SUSP_CLR;
 635         writel(val, base + USB_SUSP_CTRL);
 636
 637         return 0;
 638 }
 639
 640 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 641 {
 642         unsigned long val;
 643         void __iomem *base = phy->regs;
 644         struct tegra_ulpi_config *config = phy->config;
 645
 646         /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB
 647          * Controller to immediately bring the ULPI PHY out of low power
 648          */
 649         val = readl(base + USB_PORTSC1);
 650         val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN);
 651         writel(val, base + USB_PORTSC1);
 652
 653         clk_disable(phy->clk);
 654         return gpio_direction_output(config->reset_gpio, 0);
 655 }
 656
 657 static int      tegra_phy_init(struct usb_phy *x)
 658 {
 659         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 660         struct tegra_ulpi_config *ulpi_config;
 661         int err;
 662
 663         if (phy_is_ulpi(phy)) {
 664                 ulpi_config = phy->config;
 665                 phy->clk = clk_get_sys(NULL, ulpi_config->clk);
 666                 if (IS_ERR(phy->clk)) {
 667                         pr_err("%s: can't get ulpi clock\n", __func__);
 668                         err = -ENXIO;
 669                         goto err1;
 670                 }
 671                 if (!gpio_is_valid(ulpi_config->reset_gpio))
 672                         ulpi_config->reset_gpio =
 673                                 of_get_named_gpio(phy->dev->of_node,
 674                                                   "nvidia,phy-reset-gpio", 0);
 675                 if (!gpio_is_valid(ulpi_config->reset_gpio)) {
 676                         pr_err("%s: invalid reset gpio: %d\n", __func__,
 677                                ulpi_config->reset_gpio);
 678                         err = -EINVAL;
 679                         goto err1;
 680                 }
 681                 gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
 682                 gpio_direction_output(ulpi_config->reset_gpio, 0);
 683                 phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
 684                 phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT;
 685         } else {
 686                 err = utmip_pad_open(phy);
 687                 if (err < 0)
 688                         goto err1;
 689         }
 690         return 0;
 691 err1:
 692         clk_disable_unprepare(phy->pll_u);
 693         clk_put(phy->pll_u);
 694         return err;
 695 }
 696
 697 static void tegra_usb_phy_close(struct usb_phy *x)
 698 {
 699         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 700
 701         if (phy_is_ulpi(phy))
 702                 clk_put(phy->clk);
 703         else
 704                 utmip_pad_close(phy);
 705         clk_disable_unprepare(phy->pll_u);
 706         clk_put(phy->pll_u);
 707         kfree(phy);
 708 }
 709
 710 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 711 {
 712         if (phy_is_ulpi(phy))
 713                 return ulpi_phy_power_on(phy);
 714         else
 715                 return utmi_phy_power_on(phy);
 716 }
 717
 718 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 719 {
 720         if (phy_is_ulpi(phy))
 721                 return ulpi_phy_power_off(phy);
 722         else
 723                 return utmi_phy_power_off(phy);
 724 }
 725
 726 static int      tegra_usb_phy_suspend(struct usb_phy *x, int suspend)
 727 {
 728         struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy);
 729         if (suspend)
 730                 return tegra_usb_phy_power_off(phy);
 731         else
 732                 return tegra_usb_phy_power_on(phy);
 733 }
 734
 735 struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
 736         void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode)
 737 {
 738         struct tegra_usb_phy *phy;
 739         unsigned long parent_rate;
 740         int i;
 741         int err;
 742
 743         phy = kmalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL);
 744         if (!phy)
 745                 return ERR_PTR(-ENOMEM);
 746
 747         phy->instance = instance;
 748         phy->regs = regs;
 749         phy->config = config;
 750         phy->mode = phy_mode;
 751         phy->dev = dev;
 752
 753         if (!phy->config) {
 754                 if (phy_is_ulpi(phy)) {
 755                         pr_err("%s: ulpi phy configuration missing", __func__);
 756                         err = -EINVAL;
 757                         goto err0;
 758                 } else {
 759                         phy->config = &utmip_default[instance];
 760                 }
 761         }
 762
 763         phy->pll_u = clk_get_sys(NULL, "pll_u");
 764         if (IS_ERR(phy->pll_u)) {
 765                 pr_err("Can't get pll_u clock\n");
 766                 err = PTR_ERR(phy->pll_u);
 767                 goto err0;
 768         }
 769         clk_prepare_enable(phy->pll_u);
 770
 771         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 772         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 773                 if (tegra_freq_table[i].freq == parent_rate) {
 774                         phy->freq = &tegra_freq_table[i];
 775                         break;
 776                 }
 777         }
 778         if (!phy->freq) {
 779                 pr_err("invalid pll_u parent rate %ld\n", parent_rate);
 780                 err = -EINVAL;
 781                 goto err1;
 782         }
 783
 784         phy->u_phy.init = tegra_phy_init;
 785         phy->u_phy.shutdown = tegra_usb_phy_close;
 786         phy->u_phy.set_suspend = tegra_usb_phy_suspend;
 787
 788         return phy;
 789
 790 err1:
 791         clk_disable_unprepare(phy->pll_u);
 792         clk_put(phy->pll_u);
 793 err0:
 794         kfree(phy);
 795         return ERR_PTR(err);
 796 }
 797 EXPORT_SYMBOL_GPL(tegra_usb_phy_open);
 798
 799 void tegra_usb_phy_preresume(struct tegra_usb_phy *phy)
 800 {
 801         if (!phy_is_ulpi(phy))
 802                 utmi_phy_preresume(phy);
 803 }
 804 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 805
 806 void tegra_usb_phy_postresume(struct tegra_usb_phy *phy)
 807 {
 808         if (!phy_is_ulpi(phy))
 809                 utmi_phy_postresume(phy);
 810 }
 811 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 812
 813 void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy,
 814                                  enum tegra_usb_phy_port_speed port_speed)
 815 {
 816         if (!phy_is_ulpi(phy))
 817                 utmi_phy_restore_start(phy, port_speed);
 818 }
 819 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 820
 821 void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy)
 822 {
 823         if (!phy_is_ulpi(phy))
 824                 utmi_phy_restore_end(phy);
 825 }
 826 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 827
 828 void tegra_usb_phy_clk_disable(struct tegra_usb_phy *phy)
 829 {
 830         if (!phy_is_ulpi(phy))
 831                 utmi_phy_clk_disable(phy);
 832 }
 833 EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_disable);
 834
 835 void tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 836 {
 837         if (!phy_is_ulpi(phy))
 838                 utmi_phy_clk_enable(phy);
 839 }
 840 EXPORT_SYMBOL_GPL(tegra_usb_phy_clk_enable);