Pileus Git - ~andy/linux/blob - drivers/usb/musb/tusb6010.c

   1 /*
   2  * TUSB6010 USB 2.0 OTG Dual Role controller
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Notes:
  12  * - Driver assumes that interface to external host (main CPU) is
  13  *   configured for NOR FLASH interface instead of VLYNQ serial
  14  *   interface.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/init.h>
  21 #include <linux/prefetch.h>
  22 #include <linux/usb.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include "musb_core.h"
  28
  29 struct tusb6010_glue {
  30         struct device           *dev;
  31         struct platform_device  *musb;
  32 };
  33
  34 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
  35
  36 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
  37 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
  38
  39 /*
  40  * Checks the revision. We need to use the DMA register as 3.0 does not
  41  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  42  */
  43 u8 tusb_get_revision(struct musb *musb)
  44 {
  45         void __iomem    *tbase = musb->ctrl_base;
  46         u32             die_id;
  47         u8              rev;
  48
  49         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  50         if (TUSB_REV_MAJOR(rev) == 3) {
  51                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  52                                 TUSB_DIDR1_HI));
  53                 if (die_id >= TUSB_DIDR1_HI_REV_31)
  54                         rev |= 1;
  55         }
  56
  57         return rev;
  58 }
  59 EXPORT_SYMBOL_GPL(tusb_get_revision);
  60
  61 static int tusb_print_revision(struct musb *musb)
  62 {
  63         void __iomem    *tbase = musb->ctrl_base;
  64         u8              rev;
  65
  66         rev = tusb_get_revision(musb);
  67
  68         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  69                 "prcm",
  70                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  71                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  72                 "int",
  73                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  74                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  75                 "gpio",
  76                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  77                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  78                 "dma",
  79                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  80                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  81                 "dieid",
  82                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  83                 "rev",
  84                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  85
  86         return tusb_get_revision(musb);
  87 }
  88
  89 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  90                                 | TUSB_PHY_OTG_CTRL_TESTM0)
  91
  92 /*
  93  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  94  * Disables power detection in PHY for the duration of idle.
  95  */
  96 static void tusb_wbus_quirk(struct musb *musb, int enabled)
  97 {
  98         void __iomem    *tbase = musb->ctrl_base;
  99         static u32      phy_otg_ctrl, phy_otg_ena;
 100         u32             tmp;
 101
 102         if (enabled) {
 103                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 104                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 105                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
 106                                 | phy_otg_ena | WBUS_QUIRK_MASK;
 107                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 108                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
 109                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
 110                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 111                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
 112                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 113                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 114         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
 115                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
 116                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
 117                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
 118                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
 119                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
 120                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
 121                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
 122                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
 123                 phy_otg_ctrl = 0;
 124                 phy_otg_ena = 0;
 125         }
 126 }
 127
 128 /*
 129  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
 130  * so both loading and unloading FIFOs need explicit byte counts.
 131  */
 132
 133 static inline void
 134 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
 135 {
 136         u32             val;
 137         int             i;
 138
 139         if (len > 4) {
 140                 for (i = 0; i < (len >> 2); i++) {
 141                         memcpy(&val, buf, 4);
 142                         musb_writel(fifo, 0, val);
 143                         buf += 4;
 144                 }
 145                 len %= 4;
 146         }
 147         if (len > 0) {
 148                 /* Write the rest 1 - 3 bytes to FIFO */
 149                 memcpy(&val, buf, len);
 150                 musb_writel(fifo, 0, val);
 151         }
 152 }
 153
 154 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
 155                                                 void __iomem *buf, u16 len)
 156 {
 157         u32             val;
 158         int             i;
 159
 160         if (len > 4) {
 161                 for (i = 0; i < (len >> 2); i++) {
 162                         val = musb_readl(fifo, 0);
 163                         memcpy(buf, &val, 4);
 164                         buf += 4;
 165                 }
 166                 len %= 4;
 167         }
 168         if (len > 0) {
 169                 /* Read the rest 1 - 3 bytes from FIFO */
 170                 val = musb_readl(fifo, 0);
 171                 memcpy(buf, &val, len);
 172         }
 173 }
 174
 175 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
 176 {
 177         struct musb *musb = hw_ep->musb;
 178         void __iomem    *ep_conf = hw_ep->conf;
 179         void __iomem    *fifo = hw_ep->fifo;
 180         u8              epnum = hw_ep->epnum;
 181
 182         prefetch(buf);
 183
 184         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 185                         'T', epnum, fifo, len, buf);
 186
 187         if (epnum)
 188                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 189                         TUSB_EP_CONFIG_XFR_SIZE(len));
 190         else
 191                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
 192                         TUSB_EP0_CONFIG_XFR_SIZE(len));
 193
 194         if (likely((0x01 & (unsigned long) buf) == 0)) {
 195
 196                 /* Best case is 32bit-aligned destination address */
 197                 if ((0x02 & (unsigned long) buf) == 0) {
 198                         if (len >= 4) {
 199                                 writesl(fifo, buf, len >> 2);
 200                                 buf += (len & ~0x03);
 201                                 len &= 0x03;
 202                         }
 203                 } else {
 204                         if (len >= 2) {
 205                                 u32 val;
 206                                 int i;
 207
 208                                 /* Cannot use writesw, fifo is 32-bit */
 209                                 for (i = 0; i < (len >> 2); i++) {
 210                                         val = (u32)(*(u16 *)buf);
 211                                         buf += 2;
 212                                         val |= (*(u16 *)buf) << 16;
 213                                         buf += 2;
 214                                         musb_writel(fifo, 0, val);
 215                                 }
 216                                 len &= 0x03;
 217                         }
 218                 }
 219         }
 220
 221         if (len > 0)
 222                 tusb_fifo_write_unaligned(fifo, buf, len);
 223 }
 224
 225 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
 226 {
 227         struct musb *musb = hw_ep->musb;
 228         void __iomem    *ep_conf = hw_ep->conf;
 229         void __iomem    *fifo = hw_ep->fifo;
 230         u8              epnum = hw_ep->epnum;
 231
 232         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
 233                         'R', epnum, fifo, len, buf);
 234
 235         if (epnum)
 236                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 237                         TUSB_EP_CONFIG_XFR_SIZE(len));
 238         else
 239                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
 240
 241         if (likely((0x01 & (unsigned long) buf) == 0)) {
 242
 243                 /* Best case is 32bit-aligned destination address */
 244                 if ((0x02 & (unsigned long) buf) == 0) {
 245                         if (len >= 4) {
 246                                 readsl(fifo, buf, len >> 2);
 247                                 buf += (len & ~0x03);
 248                                 len &= 0x03;
 249                         }
 250                 } else {
 251                         if (len >= 2) {
 252                                 u32 val;
 253                                 int i;
 254
 255                                 /* Cannot use readsw, fifo is 32-bit */
 256                                 for (i = 0; i < (len >> 2); i++) {
 257                                         val = musb_readl(fifo, 0);
 258                                         *(u16 *)buf = (u16)(val & 0xffff);
 259                                         buf += 2;
 260                                         *(u16 *)buf = (u16)(val >> 16);
 261                                         buf += 2;
 262                                 }
 263                                 len &= 0x03;
 264                         }
 265                 }
 266         }
 267
 268         if (len > 0)
 269                 tusb_fifo_read_unaligned(fifo, buf, len);
 270 }
 271
 272 static struct musb *the_musb;
 273
 274 /* This is used by gadget drivers, and OTG transceiver logic, allowing
 275  * at most mA current to be drawn from VBUS during a Default-B session
 276  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
 277  * mode), or low power Default-B sessions, something else supplies power.
 278  * Caller must take care of locking.
 279  */
 280 static int tusb_draw_power(struct usb_phy *x, unsigned mA)
 281 {
 282         struct musb     *musb = the_musb;
 283         void __iomem    *tbase = musb->ctrl_base;
 284         u32             reg;
 285
 286         /* tps65030 seems to consume max 100mA, with maybe 60mA available
 287          * (measured on one board) for things other than tps and tusb.
 288          *
 289          * Boards sharing the CPU clock with CLKIN will need to prevent
 290          * certain idle sleep states while the USB link is active.
 291          *
 292          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
 293          * The actual current usage would be very board-specific.  For now,
 294          * it's simpler to just use an aggregate (also board-specific).
 295          */
 296         if (x->otg->default_a || mA < (musb->min_power << 1))
 297                 mA = 0;
 298
 299         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 300         if (mA) {
 301                 musb->is_bus_powered = 1;
 302                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
 303         } else {
 304                 musb->is_bus_powered = 0;
 305                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 306         }
 307         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 308
 309         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
 310         return 0;
 311 }
 312
 313 /* workaround for issue 13:  change clock during chip idle
 314  * (to be fixed in rev3 silicon) ... symptoms include disconnect
 315  * or looping suspend/resume cycles
 316  */
 317 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
 318 {
 319         void __iomem    *tbase = musb->ctrl_base;
 320         u32             reg;
 321
 322         reg = musb_readl(tbase, TUSB_PRCM_CONF);
 323         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
 324
 325         /* 0 = refclk (clkin, XI)
 326          * 1 = PHY 60 MHz (internal PLL)
 327          * 2 = not supported
 328          * 3 = what?
 329          */
 330         if (mode > 0)
 331                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
 332
 333         musb_writel(tbase, TUSB_PRCM_CONF, reg);
 334
 335         /* FIXME tusb6010_platform_retime(mode == 0); */
 336 }
 337
 338 /*
 339  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
 340  * Other code ensures that we idle unless we're connected _and_ the
 341  * USB link is not suspended ... and tells us the relevant wakeup
 342  * events.  SW_EN for voltage is handled separately.
 343  */
 344 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
 345 {
 346         void __iomem    *tbase = musb->ctrl_base;
 347         u32             reg;
 348
 349         if ((wakeup_enables & TUSB_PRCM_WBUS)
 350                         && (tusb_get_revision(musb) == TUSB_REV_30))
 351                 tusb_wbus_quirk(musb, 1);
 352
 353         tusb_set_clock_source(musb, 0);
 354
 355         wakeup_enables |= TUSB_PRCM_WNORCS;
 356         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
 357
 358         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
 359          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
 360          * Presumably that's mostly to save power, hence WID is immaterial ...
 361          */
 362
 363         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
 364         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
 365         if (is_host_active(musb)) {
 366                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 367                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 368         } else {
 369                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
 370                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 371         }
 372         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
 373         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
 374
 375         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
 376 }
 377
 378 /*
 379  * Updates cable VBUS status. Caller must take care of locking.
 380  */
 381 static int tusb_musb_vbus_status(struct musb *musb)
 382 {
 383         void __iomem    *tbase = musb->ctrl_base;
 384         u32             otg_stat, prcm_mngmt;
 385         int             ret = 0;
 386
 387         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 388         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
 389
 390         /* Temporarily enable VBUS detection if it was disabled for
 391          * suspend mode. Unless it's enabled otg_stat and devctl will
 392          * not show correct VBUS state.
 393          */
 394         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
 395                 u32 tmp = prcm_mngmt;
 396                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
 397                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
 398                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 399                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
 400         }
 401
 402         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
 403                 ret = 1;
 404
 405         return ret;
 406 }
 407
 408 static struct timer_list musb_idle_timer;
 409
 410 static void musb_do_idle(unsigned long _musb)
 411 {
 412         struct musb     *musb = (void *)_musb;
 413         unsigned long   flags;
 414
 415         spin_lock_irqsave(&musb->lock, flags);
 416
 417         switch (musb->xceiv->state) {
 418         case OTG_STATE_A_WAIT_BCON:
 419                 if ((musb->a_wait_bcon != 0)
 420                         && (musb->idle_timeout == 0
 421                                 || time_after(jiffies, musb->idle_timeout))) {
 422                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
 423                                         otg_state_string(musb->xceiv->state));
 424                 }
 425                 /* FALLTHROUGH */
 426         case OTG_STATE_A_IDLE:
 427                 tusb_musb_set_vbus(musb, 0);
 428         default:
 429                 break;
 430         }
 431
 432         if (!musb->is_active) {
 433                 u32     wakeups;
 434
 435                 /* wait until khubd handles port change status */
 436                 if (is_host_active(musb) && (musb->port1_status >> 16))
 437                         goto done;
 438
 439                 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
 440                         wakeups = 0;
 441                 } else {
 442                         wakeups = TUSB_PRCM_WHOSTDISCON
 443                                 | TUSB_PRCM_WBUS
 444                                         | TUSB_PRCM_WVBUS;
 445                         if (is_otg_enabled(musb))
 446                                 wakeups |= TUSB_PRCM_WID;
 447                 }
 448                 tusb_allow_idle(musb, wakeups);
 449         }
 450 done:
 451         spin_unlock_irqrestore(&musb->lock, flags);
 452 }
 453
 454 /*
 455  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
 456  * like "disconnected" or "suspended".  We'll be woken out of it by
 457  * connect, resume, or disconnect.
 458  *
 459  * Needs to be called as the last function everywhere where there is
 460  * register access to TUSB6010 because of NOR flash wake-up.
 461  * Caller should own controller spinlock.
 462  *
 463  * Delay because peripheral enables D+ pullup 3msec after SE0, and
 464  * we don't want to treat that full speed J as a wakeup event.
 465  * ... peripherals must draw only suspend current after 10 msec.
 466  */
 467 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
 468 {
 469         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 470         static unsigned long    last_timer;
 471
 472         if (timeout == 0)
 473                 timeout = default_timeout;
 474
 475         /* Never idle if active, or when VBUS timeout is not set as host */
 476         if (musb->is_active || ((musb->a_wait_bcon == 0)
 477                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
 478                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 479                         otg_state_string(musb->xceiv->state));
 480                 del_timer(&musb_idle_timer);
 481                 last_timer = jiffies;
 482                 return;
 483         }
 484
 485         if (time_after(last_timer, timeout)) {
 486                 if (!timer_pending(&musb_idle_timer))
 487                         last_timer = timeout;
 488                 else {
 489                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
 490                         return;
 491                 }
 492         }
 493         last_timer = timeout;
 494
 495         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
 496                 otg_state_string(musb->xceiv->state),
 497                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 498         mod_timer(&musb_idle_timer, timeout);
 499 }
 500
 501 /* ticks of 60 MHz clock */
 502 #define DEVCLOCK                60000000
 503 #define OTG_TIMER_MS(msecs)     ((msecs) \
 504                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
 505                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
 506                 : 0)
 507
 508 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
 509 {
 510         void __iomem    *tbase = musb->ctrl_base;
 511         u32             conf, prcm, timer;
 512         u8              devctl;
 513         struct usb_otg  *otg = musb->xceiv->otg;
 514
 515         /* HDRC controls CPEN, but beware current surges during device
 516          * connect.  They can trigger transient overcurrent conditions
 517          * that must be ignored.
 518          */
 519
 520         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
 521         conf = musb_readl(tbase, TUSB_DEV_CONF);
 522         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 523
 524         if (is_on) {
 525                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
 526                 otg->default_a = 1;
 527                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 528                 devctl |= MUSB_DEVCTL_SESSION;
 529
 530                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
 531                 MUSB_HST_MODE(musb);
 532         } else {
 533                 u32     otg_stat;
 534
 535                 timer = 0;
 536
 537                 /* If ID pin is grounded, we want to be a_idle */
 538                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 539                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
 540                         switch (musb->xceiv->state) {
 541                         case OTG_STATE_A_WAIT_VRISE:
 542                         case OTG_STATE_A_WAIT_BCON:
 543                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 544                                 break;
 545                         case OTG_STATE_A_WAIT_VFALL:
 546                                 musb->xceiv->state = OTG_STATE_A_IDLE;
 547                                 break;
 548                         default:
 549                                 musb->xceiv->state = OTG_STATE_A_IDLE;
 550                         }
 551                         musb->is_active = 0;
 552                         otg->default_a = 1;
 553                         MUSB_HST_MODE(musb);
 554                 } else {
 555                         musb->is_active = 0;
 556                         otg->default_a = 0;
 557                         musb->xceiv->state = OTG_STATE_B_IDLE;
 558                         MUSB_DEV_MODE(musb);
 559                 }
 560
 561                 devctl &= ~MUSB_DEVCTL_SESSION;
 562                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
 563         }
 564         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
 565
 566         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
 567         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
 568         musb_writel(tbase, TUSB_DEV_CONF, conf);
 569         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 570
 571         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
 572                 otg_state_string(musb->xceiv->state),
 573                 musb_readb(musb->mregs, MUSB_DEVCTL),
 574                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
 575                 conf, prcm);
 576 }
 577
 578 /*
 579  * Sets the mode to OTG, peripheral or host by changing the ID detection.
 580  * Caller must take care of locking.
 581  *
 582  * Note that if a mini-A cable is plugged in the ID line will stay down as
 583  * the weak ID pull-up is not able to pull the ID up.
 584  *
 585  * REVISIT: It would be possible to add support for changing between host
 586  * and peripheral modes in non-OTG configurations by reconfiguring hardware
 587  * and then setting musb->board_mode. For now, only support OTG mode.
 588  */
 589 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
 590 {
 591         void __iomem    *tbase = musb->ctrl_base;
 592         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
 593
 594         if (musb->board_mode != MUSB_OTG) {
 595                 ERR("Changing mode currently only supported in OTG mode\n");
 596                 return -EINVAL;
 597         }
 598
 599         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 600         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
 601         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
 602         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
 603
 604         switch (musb_mode) {
 605
 606         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
 607                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 608                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 609                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
 610                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
 611                 break;
 612         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
 613                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 614                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 615                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 616                 break;
 617         case MUSB_OTG:          /* Use PHY ID detection */
 618                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 619                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
 620                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
 621                 break;
 622
 623         default:
 624                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
 625                 return -EINVAL;
 626         }
 627
 628         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
 629                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
 630         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
 631                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
 632         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
 633
 634         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 635         if ((musb_mode == MUSB_PERIPHERAL) &&
 636                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
 637                         INFO("Cannot be peripheral with mini-A cable "
 638                         "otg_stat: %08x\n", otg_stat);
 639
 640         return 0;
 641 }
 642
 643 static inline unsigned long
 644 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 645 {
 646         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
 647         unsigned long   idle_timeout = 0;
 648         struct usb_otg  *otg = musb->xceiv->otg;
 649
 650         /* ID pin */
 651         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
 652                 int     default_a;
 653
 654                 if (is_otg_enabled(musb))
 655                         default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
 656                 else
 657                         default_a = is_host_enabled(musb);
 658                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
 659                 otg->default_a = default_a;
 660                 tusb_musb_set_vbus(musb, default_a);
 661
 662                 /* Don't allow idling immediately */
 663                 if (default_a)
 664                         idle_timeout = jiffies + (HZ * 3);
 665         }
 666
 667         /* VBUS state change */
 668         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
 669
 670                 /* B-dev state machine:  no vbus ~= disconnect */
 671                 if ((is_otg_enabled(musb) && !otg->default_a)
 672                                 || !is_host_enabled(musb)) {
 673                         /* ? musb_root_disconnect(musb); */
 674                         musb->port1_status &=
 675                                 ~(USB_PORT_STAT_CONNECTION
 676                                 | USB_PORT_STAT_ENABLE
 677                                 | USB_PORT_STAT_LOW_SPEED
 678                                 | USB_PORT_STAT_HIGH_SPEED
 679                                 | USB_PORT_STAT_TEST
 680                                 );
 681
 682                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
 683                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
 684                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
 685                                         /* INTR_DISCONNECT can hide... */
 686                                         musb->xceiv->state = OTG_STATE_B_IDLE;
 687                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
 688                                 }
 689                                 musb->is_active = 0;
 690                         }
 691                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 692                                 otg_state_string(musb->xceiv->state), otg_stat);
 693                         idle_timeout = jiffies + (1 * HZ);
 694                         schedule_work(&musb->irq_work);
 695
 696                 } else /* A-dev state machine */ {
 697                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
 698                                 otg_state_string(musb->xceiv->state), otg_stat);
 699
 700                         switch (musb->xceiv->state) {
 701                         case OTG_STATE_A_IDLE:
 702                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
 703                                 musb_platform_set_vbus(musb, 1);
 704
 705                                 /* CONNECT can wake if a_wait_bcon is set */
 706                                 if (musb->a_wait_bcon != 0)
 707                                         musb->is_active = 0;
 708                                 else
 709                                         musb->is_active = 1;
 710
 711                                 /*
 712                                  * OPT FS A TD.4.6 needs few seconds for
 713                                  * A_WAIT_VRISE
 714                                  */
 715                                 idle_timeout = jiffies + (2 * HZ);
 716
 717                                 break;
 718                         case OTG_STATE_A_WAIT_VRISE:
 719                                 /* ignore; A-session-valid < VBUS_VALID/2,
 720                                  * we monitor this with the timer
 721                                  */
 722                                 break;
 723                         case OTG_STATE_A_WAIT_VFALL:
 724                                 /* REVISIT this irq triggers during short
 725                                  * spikes caused by enumeration ...
 726                                  */
 727                                 if (musb->vbuserr_retry) {
 728                                         musb->vbuserr_retry--;
 729                                         tusb_musb_set_vbus(musb, 1);
 730                                 } else {
 731                                         musb->vbuserr_retry
 732                                                 = VBUSERR_RETRY_COUNT;
 733                                         tusb_musb_set_vbus(musb, 0);
 734                                 }
 735                                 break;
 736                         default:
 737                                 break;
 738                         }
 739                 }
 740         }
 741
 742         /* OTG timer expiration */
 743         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
 744                 u8      devctl;
 745
 746                 dev_dbg(musb->controller, "%s timer, %03x\n",
 747                         otg_state_string(musb->xceiv->state), otg_stat);
 748
 749                 switch (musb->xceiv->state) {
 750                 case OTG_STATE_A_WAIT_VRISE:
 751                         /* VBUS has probably been valid for a while now,
 752                          * but may well have bounced out of range a bit
 753                          */
 754                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 755                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
 756                                 if ((devctl & MUSB_DEVCTL_VBUS)
 757                                                 != MUSB_DEVCTL_VBUS) {
 758                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
 759                                         break;
 760                                 }
 761                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 762                                 musb->is_active = 0;
 763                                 idle_timeout = jiffies
 764                                         + msecs_to_jiffies(musb->a_wait_bcon);
 765                         } else {
 766                                 /* REVISIT report overcurrent to hub? */
 767                                 ERR("vbus too slow, devctl %02x\n", devctl);
 768                                 tusb_musb_set_vbus(musb, 0);
 769                         }
 770                         break;
 771                 case OTG_STATE_A_WAIT_BCON:
 772                         if (musb->a_wait_bcon != 0)
 773                                 idle_timeout = jiffies
 774                                         + msecs_to_jiffies(musb->a_wait_bcon);
 775                         break;
 776                 case OTG_STATE_A_SUSPEND:
 777                         break;
 778                 case OTG_STATE_B_WAIT_ACON:
 779                         break;
 780                 default:
 781                         break;
 782                 }
 783         }
 784         schedule_work(&musb->irq_work);
 785
 786         return idle_timeout;
 787 }
 788
 789 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
 790 {
 791         struct musb     *musb = __hci;
 792         void __iomem    *tbase = musb->ctrl_base;
 793         unsigned long   flags, idle_timeout = 0;
 794         u32             int_mask, int_src;
 795
 796         spin_lock_irqsave(&musb->lock, flags);
 797
 798         /* Mask all interrupts to allow using both edge and level GPIO irq */
 799         int_mask = musb_readl(tbase, TUSB_INT_MASK);
 800         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 801
 802         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
 803         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
 804
 805         musb->int_usb = (u8) int_src;
 806
 807         /* Acknowledge wake-up source interrupts */
 808         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
 809                 u32     reg;
 810                 u32     i;
 811
 812                 if (tusb_get_revision(musb) == TUSB_REV_30)
 813                         tusb_wbus_quirk(musb, 0);
 814
 815                 /* there are issues re-locking the PLL on wakeup ... */
 816
 817                 /* work around issue 8 */
 818                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
 819                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
 820                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
 821                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
 822                         if (reg == i)
 823                                 break;
 824                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
 825                 }
 826
 827                 /* work around issue 13 (2nd half) */
 828                 tusb_set_clock_source(musb, 1);
 829
 830                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
 831                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
 832                 if (reg & ~TUSB_PRCM_WNORCS) {
 833                         musb->is_active = 1;
 834                         schedule_work(&musb->irq_work);
 835                 }
 836                 dev_dbg(musb->controller, "wake %sactive %02x\n",
 837                                 musb->is_active ? "" : "in", reg);
 838
 839                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
 840         }
 841
 842         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
 843                 del_timer(&musb_idle_timer);
 844
 845         /* OTG state change reports (annoyingly) not issued by Mentor core */
 846         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
 847                                 | TUSB_INT_SRC_OTG_TIMEOUT
 848                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
 849                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
 850
 851         /* TX dma callback must be handled here, RX dma callback is
 852          * handled in tusb_omap_dma_cb.
 853          */
 854         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
 855                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
 856                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
 857
 858                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
 859                 real_dma_src = ~real_dma_src & dma_src;
 860                 if (tusb_dma_omap() && real_dma_src) {
 861                         int     tx_source = (real_dma_src & 0xffff);
 862                         int     i;
 863
 864                         for (i = 1; i <= 15; i++) {
 865                                 if (tx_source & (1 << i)) {
 866                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
 867                                         musb_dma_completion(musb, i, 1);
 868                                 }
 869                         }
 870                 }
 871                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
 872         }
 873
 874         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
 875         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
 876                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
 877
 878                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
 879                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
 880                 musb->int_tx = (musb_src & 0xffff);
 881         } else {
 882                 musb->int_rx = 0;
 883                 musb->int_tx = 0;
 884         }
 885
 886         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
 887                 musb_interrupt(musb);
 888
 889         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
 890         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
 891                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
 892
 893         tusb_musb_try_idle(musb, idle_timeout);
 894
 895         musb_writel(tbase, TUSB_INT_MASK, int_mask);
 896         spin_unlock_irqrestore(&musb->lock, flags);
 897
 898         return IRQ_HANDLED;
 899 }
 900
 901 static int dma_off;
 902
 903 /*
 904  * Enables TUSB6010. Caller must take care of locking.
 905  * REVISIT:
 906  * - Check what is unnecessary in MGC_HdrcStart()
 907  */
 908 static void tusb_musb_enable(struct musb *musb)
 909 {
 910         void __iomem    *tbase = musb->ctrl_base;
 911
 912         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
 913          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
 914         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
 915
 916         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
 917         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
 918         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 919         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 920
 921         /* Clear all subsystem interrups */
 922         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
 923         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
 924         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
 925
 926         /* Acknowledge pending interrupt(s) */
 927         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
 928
 929         /* Only 0 clock cycles for minimum interrupt de-assertion time and
 930          * interrupt polarity active low seems to work reliably here */
 931         musb_writel(tbase, TUSB_INT_CTRL_CONF,
 932                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
 933
 934         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
 935
 936         /* maybe force into the Default-A OTG state machine */
 937         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
 938                         & TUSB_DEV_OTG_STAT_ID_STATUS))
 939                 musb_writel(tbase, TUSB_INT_SRC_SET,
 940                                 TUSB_INT_SRC_ID_STATUS_CHNG);
 941
 942         if (is_dma_capable() && dma_off)
 943                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
 944                                 __FILE__, __func__);
 945         else
 946                 dma_off = 1;
 947 }
 948
 949 /*
 950  * Disables TUSB6010. Caller must take care of locking.
 951  */
 952 static void tusb_musb_disable(struct musb *musb)
 953 {
 954         void __iomem    *tbase = musb->ctrl_base;
 955
 956         /* FIXME stop DMA, IRQs, timers, ... */
 957
 958         /* disable all IRQs */
 959         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
 960         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
 961         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
 962         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
 963
 964         del_timer(&musb_idle_timer);
 965
 966         if (is_dma_capable() && !dma_off) {
 967                 printk(KERN_WARNING "%s %s: dma still active\n",
 968                                 __FILE__, __func__);
 969                 dma_off = 1;
 970         }
 971 }
 972
 973 /*
 974  * Sets up TUSB6010 CPU interface specific signals and registers
 975  * Note: Settings optimized for OMAP24xx
 976  */
 977 static void tusb_setup_cpu_interface(struct musb *musb)
 978 {
 979         void __iomem    *tbase = musb->ctrl_base;
 980
 981         /*
 982          * Disable GPIO[5:0] pullups (used as output DMA requests)
 983          * Don't disable GPIO[7:6] as they are needed for wake-up.
 984          */
 985         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
 986
 987         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
 988         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
 989
 990         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
 991         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
 992
 993         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
 994          * de-assertion time 2 system clocks p 62 */
 995         musb_writel(tbase, TUSB_DMA_REQ_CONF,
 996                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
 997                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
 998                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
 999
1000         /* Set 0 wait count for synchronous burst access */
1001         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1002 }
1003
1004 static int tusb_musb_start(struct musb *musb)
1005 {
1006         void __iomem    *tbase = musb->ctrl_base;
1007         int             ret = 0;
1008         unsigned long   flags;
1009         u32             reg;
1010
1011         if (musb->board_set_power)
1012                 ret = musb->board_set_power(1);
1013         if (ret != 0) {
1014                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1015                 return ret;
1016         }
1017
1018         spin_lock_irqsave(&musb->lock, flags);
1019
1020         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1021                 TUSB_PROD_TEST_RESET_VAL) {
1022                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1023                 goto err;
1024         }
1025
1026         ret = tusb_print_revision(musb);
1027         if (ret < 2) {
1028                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1029                                 ret);
1030                 goto err;
1031         }
1032
1033         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1034          * NOR FLASH interface is used */
1035         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1036
1037         /* Select PHY free running 60MHz as a system clock */
1038         tusb_set_clock_source(musb, 1);
1039
1040         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1041          * power saving, enable VBus detect and session end comparators,
1042          * enable IDpullup, enable VBus charging */
1043         musb_writel(tbase, TUSB_PRCM_MNGMT,
1044                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1045                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1046                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1047                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1048                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1049         tusb_setup_cpu_interface(musb);
1050
1051         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1052         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1053         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1054         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1055
1056         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1057         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1058         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1059
1060         spin_unlock_irqrestore(&musb->lock, flags);
1061
1062         return 0;
1063
1064 err:
1065         spin_unlock_irqrestore(&musb->lock, flags);
1066
1067         if (musb->board_set_power)
1068                 musb->board_set_power(0);
1069
1070         return -ENODEV;
1071 }
1072
1073 static int tusb_musb_init(struct musb *musb)
1074 {
1075         struct platform_device  *pdev;
1076         struct resource         *mem;
1077         void __iomem            *sync = NULL;
1078         int                     ret;
1079
1080         usb_nop_xceiv_register();
1081         musb->xceiv = usb_get_transceiver();
1082         if (!musb->xceiv)
1083                 return -ENODEV;
1084
1085         pdev = to_platform_device(musb->controller);
1086
1087         /* dma address for async dma */
1088         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089         musb->async = mem->start;
1090
1091         /* dma address for sync dma */
1092         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1093         if (!mem) {
1094                 pr_debug("no sync dma resource?\n");
1095                 ret = -ENODEV;
1096                 goto done;
1097         }
1098         musb->sync = mem->start;
1099
1100         sync = ioremap(mem->start, resource_size(mem));
1101         if (!sync) {
1102                 pr_debug("ioremap for sync failed\n");
1103                 ret = -ENOMEM;
1104                 goto done;
1105         }
1106         musb->sync_va = sync;
1107
1108         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1109          * FIFOs at 0x600, TUSB at 0x800
1110          */
1111         musb->mregs += TUSB_BASE_OFFSET;
1112
1113         ret = tusb_musb_start(musb);
1114         if (ret) {
1115                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1116                                 ret);
1117                 goto done;
1118         }
1119         musb->isr = tusb_musb_interrupt;
1120
1121         if (is_peripheral_enabled(musb)) {
1122                 musb->xceiv->set_power = tusb_draw_power;
1123                 the_musb = musb;
1124         }
1125
1126         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1127
1128 done:
1129         if (ret < 0) {
1130                 if (sync)
1131                         iounmap(sync);
1132
1133                 usb_put_transceiver(musb->xceiv);
1134                 usb_nop_xceiv_unregister();
1135         }
1136         return ret;
1137 }
1138
1139 static int tusb_musb_exit(struct musb *musb)
1140 {
1141         del_timer_sync(&musb_idle_timer);
1142         the_musb = NULL;
1143
1144         if (musb->board_set_power)
1145                 musb->board_set_power(0);
1146
1147         iounmap(musb->sync_va);
1148
1149         usb_put_transceiver(musb->xceiv);
1150         usb_nop_xceiv_unregister();
1151         return 0;
1152 }
1153
1154 static const struct musb_platform_ops tusb_ops = {
1155         .init           = tusb_musb_init,
1156         .exit           = tusb_musb_exit,
1157
1158         .enable         = tusb_musb_enable,
1159         .disable        = tusb_musb_disable,
1160
1161         .set_mode       = tusb_musb_set_mode,
1162         .try_idle       = tusb_musb_try_idle,
1163
1164         .vbus_status    = tusb_musb_vbus_status,
1165         .set_vbus       = tusb_musb_set_vbus,
1166 };
1167
1168 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1169
1170 static int __devinit tusb_probe(struct platform_device *pdev)
1171 {
1172         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
1173         struct platform_device          *musb;
1174         struct tusb6010_glue            *glue;
1175
1176         int                             ret = -ENOMEM;
1177
1178         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1179         if (!glue) {
1180                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1181                 goto err0;
1182         }
1183
1184         musb = platform_device_alloc("musb-hdrc", -1);
1185         if (!musb) {
1186                 dev_err(&pdev->dev, "failed to allocate musb device\n");
1187                 goto err1;
1188         }
1189
1190         musb->dev.parent                = &pdev->dev;
1191         musb->dev.dma_mask              = &tusb_dmamask;
1192         musb->dev.coherent_dma_mask     = tusb_dmamask;
1193
1194         glue->dev                       = &pdev->dev;
1195         glue->musb                      = musb;
1196
1197         pdata->platform_ops             = &tusb_ops;
1198
1199         platform_set_drvdata(pdev, glue);
1200
1201         ret = platform_device_add_resources(musb, pdev->resource,
1202                         pdev->num_resources);
1203         if (ret) {
1204                 dev_err(&pdev->dev, "failed to add resources\n");
1205                 goto err2;
1206         }
1207
1208         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1209         if (ret) {
1210                 dev_err(&pdev->dev, "failed to add platform_data\n");
1211                 goto err2;
1212         }
1213
1214         ret = platform_device_add(musb);
1215         if (ret) {
1216                 dev_err(&pdev->dev, "failed to register musb device\n");
1217                 goto err1;
1218         }
1219
1220         return 0;
1221
1222 err2:
1223         platform_device_put(musb);
1224
1225 err1:
1226         kfree(glue);
1227
1228 err0:
1229         return ret;
1230 }
1231
1232 static int __devexit tusb_remove(struct platform_device *pdev)
1233 {
1234         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1235
1236         platform_device_del(glue->musb);
1237         platform_device_put(glue->musb);
1238         kfree(glue);
1239
1240         return 0;
1241 }
1242
1243 static struct platform_driver tusb_driver = {
1244         .probe          = tusb_probe,
1245         .remove         = __devexit_p(tusb_remove),
1246         .driver         = {
1247                 .name   = "musb-tusb",
1248         },
1249 };
1250
1251 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1252 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1253 MODULE_LICENSE("GPL v2");
1254
1255 static int __init tusb_init(void)
1256 {
1257         return platform_driver_register(&tusb_driver);
1258 }
1259 module_init(tusb_init);
1260
1261 static void __exit tusb_exit(void)
1262 {
1263         platform_driver_unregister(&tusb_driver);
1264 }
1265 module_exit(tusb_exit);