2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
34 /* xHCI PCI Configuration Registers */
35 #define XHCI_SBRN_OFFSET (0x60)
37 /* Max number of USB devices for any host controller - limit in section 6.1 */
38 #define MAX_HC_SLOTS 256
39 /* Section 5.3.3 - MaxPorts */
40 #define MAX_HC_PORTS 127
43 * xHCI register interface.
44 * This corresponds to the eXtensible Host Controller Interface (xHCI)
45 * Revision 0.95 specification
49 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
50 * @hc_capbase: length of the capabilities register and HC version number
51 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
52 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
53 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
54 * @hcc_params: HCCPARAMS - Capability Parameters
55 * @db_off: DBOFF - Doorbell array offset
56 * @run_regs_off: RTSOFF - Runtime register space offset
58 struct xhci_cap_regs {
66 /* Reserved up to (CAPLENGTH - 0x1C) */
69 /* hc_capbase bitmasks */
70 /* bits 7:0 - how long is the Capabilities register */
71 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
75 /* HCSPARAMS1 - hcs_params1 - bitmasks */
76 /* bits 0:7, Max Device Slots */
77 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
78 #define HCS_SLOTS_MASK 0xff
79 /* bits 8:18, Max Interrupters */
80 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
81 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
82 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84 /* HCSPARAMS2 - hcs_params2 - bitmasks */
85 /* bits 0:3, frames or uframes that SW needs to queue transactions
86 * ahead of the HW to meet periodic deadlines */
87 #define HCS_IST(p) (((p) >> 0) & 0xf)
88 /* bits 4:7, max number of Event Ring segments */
89 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
90 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
91 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
92 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94 /* HCSPARAMS3 - hcs_params3 - bitmasks */
95 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
96 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
97 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
98 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100 /* HCCPARAMS - hcc_params - bitmasks */
101 /* true: HC can use 64-bit address pointers */
102 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
103 /* true: HC can do bandwidth negotiation */
104 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
105 /* true: HC uses 64-byte Device Context structures
106 * FIXME 64-byte context structures aren't supported yet.
108 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
109 /* true: HC has port power switches */
110 #define HCC_PPC(p) ((p) & (1 << 3))
111 /* true: HC has port indicators */
112 #define HCS_INDICATOR(p) ((p) & (1 << 4))
113 /* true: HC has Light HC Reset Capability */
114 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
115 /* true: HC supports latency tolerance messaging */
116 #define HCC_LTC(p) ((p) & (1 << 6))
117 /* true: no secondary Stream ID Support */
118 #define HCC_NSS(p) ((p) & (1 << 7))
119 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
120 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
121 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
122 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124 /* db_off bitmask - bits 0:1 reserved */
125 #define DBOFF_MASK (~0x3)
127 /* run_regs_off bitmask - bits 0:4 reserved */
128 #define RTSOFF_MASK (~0x1f)
131 /* Number of registers per port */
132 #define NUM_PORT_REGS 4
135 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
136 * @command: USBCMD - xHC command register
137 * @status: USBSTS - xHC status register
138 * @page_size: This indicates the page size that the host controller
139 * supports. If bit n is set, the HC supports a page size
140 * of 2^(n+12), up to a 128MB page size.
141 * 4K is the minimum page size.
142 * @cmd_ring: CRP - 64-bit Command Ring Pointer
143 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
144 * @config_reg: CONFIG - Configure Register
145 * @port_status_base: PORTSCn - base address for Port Status and Control
146 * Each port has a Port Status and Control register,
147 * followed by a Port Power Management Status and Control
148 * register, a Port Link Info register, and a reserved
150 * @port_power_base: PORTPMSCn - base address for
151 * Port Power Management Status and Control
152 * @port_link_base: PORTLIn - base address for Port Link Info (current
153 * Link PM state and control) for USB 2.1 and USB 3.0
156 struct xhci_op_regs {
162 u32 dev_notification;
164 /* rsvd: offset 0x20-2F */
168 /* rsvd: offset 0x3C-3FF */
170 /* port 1 registers, which serve as a base address for other ports */
171 u32 port_status_base;
175 /* registers for ports 2-255 */
176 u32 reserved6[NUM_PORT_REGS*254];
179 /* USBCMD - USB command - command bitmasks */
180 /* start/stop HC execution - do not write unless HC is halted*/
181 #define CMD_RUN XHCI_CMD_RUN
182 /* Reset HC - resets internal HC state machine and all registers (except
183 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
184 * The xHCI driver must reinitialize the xHC after setting this bit.
186 #define CMD_RESET (1 << 1)
187 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188 #define CMD_EIE XHCI_CMD_EIE
189 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
190 #define CMD_HSEIE XHCI_CMD_HSEIE
191 /* bits 4:6 are reserved (and should be preserved on writes). */
192 /* light reset (port status stays unchanged) - reset completed when this is 0 */
193 #define CMD_LRESET (1 << 7)
194 /* host controller save/restore state. */
195 #define CMD_CSS (1 << 8)
196 #define CMD_CRS (1 << 9)
197 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198 #define CMD_EWE XHCI_CMD_EWE
199 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
200 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * '0' means the xHC can power it off if all ports are in the disconnect,
202 * disabled, or powered-off state.
204 #define CMD_PM_INDEX (1 << 11)
205 /* bits 12:31 are reserved (and should be preserved on writes). */
207 /* USBSTS - USB status - status bitmasks */
208 /* HC not running - set to 1 when run/stop bit is cleared. */
209 #define STS_HALT XHCI_STS_HALT
210 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
211 #define STS_FATAL (1 << 2)
212 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
213 #define STS_EINT (1 << 3)
214 /* port change detect */
215 #define STS_PORT (1 << 4)
216 /* bits 5:7 reserved and zeroed */
217 /* save state status - '1' means xHC is saving state */
218 #define STS_SAVE (1 << 8)
219 /* restore state status - '1' means xHC is restoring state */
220 #define STS_RESTORE (1 << 9)
221 /* true: save or restore error */
222 #define STS_SRE (1 << 10)
223 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
224 #define STS_CNR XHCI_STS_CNR
225 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
226 #define STS_HCE (1 << 12)
227 /* bits 13:31 reserved and should be preserved */
230 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
231 * Generate a device notification event when the HC sees a transaction with a
232 * notification type that matches a bit set in this bit field.
234 #define DEV_NOTE_MASK (0xffff)
235 #define ENABLE_DEV_NOTE(x) (1 << (x))
236 /* Most of the device notification types should only be used for debug.
237 * SW does need to pay attention to function wake notifications.
239 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
241 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
242 /* bit 0 is the command ring cycle state */
243 /* stop ring operation after completion of the currently executing command */
244 #define CMD_RING_PAUSE (1 << 1)
245 /* stop ring immediately - abort the currently executing command */
246 #define CMD_RING_ABORT (1 << 2)
247 /* true: command ring is running */
248 #define CMD_RING_RUNNING (1 << 3)
249 /* bits 4:5 reserved and should be preserved */
250 /* Command Ring pointer - bit mask for the lower 32 bits. */
251 #define CMD_RING_RSVD_BITS (0x3f)
253 /* CONFIG - Configure Register - config_reg bitmasks */
254 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255 #define MAX_DEVS(p) ((p) & 0xff)
256 /* bits 8:31 - reserved and should be preserved */
258 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
259 /* true: device connected */
260 #define PORT_CONNECT (1 << 0)
261 /* true: port enabled */
262 #define PORT_PE (1 << 1)
263 /* bit 2 reserved and zeroed */
264 /* true: port has an over-current condition */
265 #define PORT_OC (1 << 3)
266 /* true: port reset signaling asserted */
267 #define PORT_RESET (1 << 4)
268 /* Port Link State - bits 5:8
269 * A read gives the current link PM state of the port,
270 * a write with Link State Write Strobe set sets the link state.
272 #define PORT_PLS_MASK (0xf << 5)
273 #define XDEV_U0 (0x0 << 5)
274 #define XDEV_U3 (0x3 << 5)
275 #define XDEV_RESUME (0xf << 5)
276 /* true: port has power (see HCC_PPC) */
277 #define PORT_POWER (1 << 9)
278 /* bits 10:13 indicate device speed:
279 * 0 - undefined speed - port hasn't be initialized by a reset yet
286 #define DEV_SPEED_MASK (0xf << 10)
287 #define XDEV_FS (0x1 << 10)
288 #define XDEV_LS (0x2 << 10)
289 #define XDEV_HS (0x3 << 10)
290 #define XDEV_SS (0x4 << 10)
291 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
292 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
293 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
294 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
295 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
296 /* Bits 20:23 in the Slot Context are the speed for the device */
297 #define SLOT_SPEED_FS (XDEV_FS << 10)
298 #define SLOT_SPEED_LS (XDEV_LS << 10)
299 #define SLOT_SPEED_HS (XDEV_HS << 10)
300 #define SLOT_SPEED_SS (XDEV_SS << 10)
301 /* Port Indicator Control */
302 #define PORT_LED_OFF (0 << 14)
303 #define PORT_LED_AMBER (1 << 14)
304 #define PORT_LED_GREEN (2 << 14)
305 #define PORT_LED_MASK (3 << 14)
306 /* Port Link State Write Strobe - set this when changing link state */
307 #define PORT_LINK_STROBE (1 << 16)
308 /* true: connect status change */
309 #define PORT_CSC (1 << 17)
310 /* true: port enable change */
311 #define PORT_PEC (1 << 18)
312 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
313 * into an enabled state, and the device into the default state. A "warm" reset
314 * also resets the link, forcing the device through the link training sequence.
315 * SW can also look at the Port Reset register to see when warm reset is done.
317 #define PORT_WRC (1 << 19)
318 /* true: over-current change */
319 #define PORT_OCC (1 << 20)
320 /* true: reset change - 1 to 0 transition of PORT_RESET */
321 #define PORT_RC (1 << 21)
322 /* port link status change - set on some port link state transitions:
324 * ------------------------------------------------------------------------------
325 * - U3 to Resume Wakeup signaling from a device
326 * - Resume to Recovery to U0 USB 3.0 device resume
327 * - Resume to U0 USB 2.0 device resume
328 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
329 * - U3 to U0 Software resume of USB 2.0 device complete
330 * - U2 to U0 L1 resume of USB 2.1 device complete
331 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
332 * - U0 to disabled L1 entry error with USB 2.1 device
333 * - Any state to inactive Error on USB 3.0 port
335 #define PORT_PLC (1 << 22)
336 /* port configure error change - port failed to configure its link partner */
337 #define PORT_CEC (1 << 23)
338 /* bit 24 reserved */
339 /* wake on connect (enable) */
340 #define PORT_WKCONN_E (1 << 25)
341 /* wake on disconnect (enable) */
342 #define PORT_WKDISC_E (1 << 26)
343 /* wake on over-current (enable) */
344 #define PORT_WKOC_E (1 << 27)
345 /* bits 28:29 reserved */
346 /* true: device is removable - for USB 3.0 roothub emulation */
347 #define PORT_DEV_REMOVE (1 << 30)
348 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
349 #define PORT_WR (1 << 31)
351 /* We mark duplicate entries with -1 */
352 #define DUPLICATE_ENTRY ((u8)(-1))
354 /* Port Power Management Status and Control - port_power_base bitmasks */
355 /* Inactivity timer value for transitions into U1, in microseconds.
356 * Timeout can be up to 127us. 0xFF means an infinite timeout.
358 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
359 /* Inactivity timer value for transitions into U2 */
360 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
361 /* Bits 24:31 for port testing */
363 /* USB2 Protocol PORTSPMSC */
364 #define PORT_RWE (1 << 0x3)
367 * struct xhci_intr_reg - Interrupt Register Set
368 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
369 * interrupts and check for pending interrupts.
370 * @irq_control: IMOD - Interrupt Moderation Register.
371 * Used to throttle interrupts.
372 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
373 * @erst_base: ERST base address.
374 * @erst_dequeue: Event ring dequeue pointer.
376 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
377 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
378 * multiple segments of the same size. The HC places events on the ring and
379 * "updates the Cycle bit in the TRBs to indicate to software the current
380 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
381 * updates the dequeue pointer.
383 struct xhci_intr_reg {
392 /* irq_pending bitmasks */
393 #define ER_IRQ_PENDING(p) ((p) & 0x1)
394 /* bits 2:31 need to be preserved */
395 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
396 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
397 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
398 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
400 /* irq_control bitmasks */
401 /* Minimum interval between interrupts (in 250ns intervals). The interval
402 * between interrupts will be longer if there are no events on the event ring.
403 * Default is 4000 (1 ms).
405 #define ER_IRQ_INTERVAL_MASK (0xffff)
406 /* Counter used to count down the time to the next interrupt - HW use only */
407 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
409 /* erst_size bitmasks */
410 /* Preserve bits 16:31 of erst_size */
411 #define ERST_SIZE_MASK (0xffff << 16)
413 /* erst_dequeue bitmasks */
414 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
415 * where the current dequeue pointer lies. This is an optional HW hint.
417 #define ERST_DESI_MASK (0x7)
418 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
419 * a work queue (or delayed service routine)?
421 #define ERST_EHB (1 << 3)
422 #define ERST_PTR_MASK (0xf)
425 * struct xhci_run_regs
427 * MFINDEX - current microframe number
429 * Section 5.5 Host Controller Runtime Registers:
430 * "Software should read and write these registers using only Dword (32 bit)
431 * or larger accesses"
433 struct xhci_run_regs {
434 u32 microframe_index;
436 struct xhci_intr_reg ir_set[128];
440 * struct doorbell_array
442 * Bits 0 - 7: Endpoint target
444 * Bits 16 - 31: Stream ID
448 struct xhci_doorbell_array {
452 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
453 #define DB_VALUE_HOST 0x00000000
456 * struct xhci_protocol_caps
457 * @revision: major revision, minor revision, capability ID,
458 * and next capability pointer.
459 * @name_string: Four ASCII characters to say which spec this xHC
460 * follows, typically "USB ".
461 * @port_info: Port offset, count, and protocol-defined information.
463 struct xhci_protocol_caps {
469 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
470 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
471 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
474 * struct xhci_container_ctx
475 * @type: Type of context. Used to calculated offsets to contained contexts.
476 * @size: Size of the context data
477 * @bytes: The raw context data given to HW
478 * @dma: dma address of the bytes
480 * Represents either a Device or Input context. Holds a pointer to the raw
481 * memory used for the context (bytes) and dma address of it (dma).
483 struct xhci_container_ctx {
485 #define XHCI_CTX_TYPE_DEVICE 0x1
486 #define XHCI_CTX_TYPE_INPUT 0x2
495 * struct xhci_slot_ctx
496 * @dev_info: Route string, device speed, hub info, and last valid endpoint
497 * @dev_info2: Max exit latency for device number, root hub port number
498 * @tt_info: tt_info is used to construct split transaction tokens
499 * @dev_state: slot state and device address
501 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
502 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
503 * reserved at the end of the slot context for HC internal use.
505 struct xhci_slot_ctx {
510 /* offset 0x10 to 0x1f reserved for HC internal use */
514 /* dev_info bitmasks */
515 /* Route String - 0:19 */
516 #define ROUTE_STRING_MASK (0xfffff)
517 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
518 #define DEV_SPEED (0xf << 20)
519 /* bit 24 reserved */
520 /* Is this LS/FS device connected through a HS hub? - bit 25 */
521 #define DEV_MTT (0x1 << 25)
522 /* Set if the device is a hub - bit 26 */
523 #define DEV_HUB (0x1 << 26)
524 /* Index of the last valid endpoint context in this device context - 27:31 */
525 #define LAST_CTX_MASK (0x1f << 27)
526 #define LAST_CTX(p) ((p) << 27)
527 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
528 #define SLOT_FLAG (1 << 0)
529 #define EP0_FLAG (1 << 1)
531 /* dev_info2 bitmasks */
532 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
533 #define MAX_EXIT (0xffff)
534 /* Root hub port number that is needed to access the USB device */
535 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
536 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
537 /* Maximum number of ports under a hub device */
538 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
540 /* tt_info bitmasks */
542 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
543 * The Slot ID of the hub that isolates the high speed signaling from
544 * this low or full-speed device. '0' if attached to root hub port.
546 #define TT_SLOT (0xff)
548 * The number of the downstream facing port of the high-speed hub
549 * '0' if the device is not low or full speed.
551 #define TT_PORT (0xff << 8)
552 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
554 /* dev_state bitmasks */
555 /* USB device address - assigned by the HC */
556 #define DEV_ADDR_MASK (0xff)
557 /* bits 8:26 reserved */
559 #define SLOT_STATE (0x1f << 27)
560 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
565 * @ep_info: endpoint state, streams, mult, and interval information.
566 * @ep_info2: information on endpoint type, max packet size, max burst size,
567 * error count, and whether the HC will force an event for all
569 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
570 * defines one stream, this points to the endpoint transfer ring.
571 * Otherwise, it points to a stream context array, which has a
572 * ring pointer for each flow.
574 * Average TRB lengths for the endpoint ring and
575 * max payload within an Endpoint Service Interval Time (ESIT).
577 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
578 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
579 * reserved at the end of the endpoint context for HC internal use.
586 /* offset 0x14 - 0x1f reserved for HC internal use */
590 /* ep_info bitmasks */
592 * Endpoint State - bits 0:2
595 * 2 - halted due to halt condition - ok to manipulate endpoint ring
600 #define EP_STATE_MASK (0xf)
601 #define EP_STATE_DISABLED 0
602 #define EP_STATE_RUNNING 1
603 #define EP_STATE_HALTED 2
604 #define EP_STATE_STOPPED 3
605 #define EP_STATE_ERROR 4
606 /* Mult - Max number of burtst within an interval, in EP companion desc. */
607 #define EP_MULT(p) (((p) & 0x3) << 8)
608 /* bits 10:14 are Max Primary Streams */
609 /* bit 15 is Linear Stream Array */
610 /* Interval - period between requests to an endpoint - 125u increments. */
611 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
612 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
613 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
614 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
615 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
616 #define EP_HAS_LSA (1 << 15)
618 /* ep_info2 bitmasks */
620 * Force Event - generate transfer events for all TRBs for this endpoint
621 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
623 #define FORCE_EVENT (0x1)
624 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
625 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
626 #define EP_TYPE(p) ((p) << 3)
627 #define ISOC_OUT_EP 1
628 #define BULK_OUT_EP 2
635 /* bit 7 is Host Initiate Disable - for disabling stream selection */
636 #define MAX_BURST(p) (((p)&0xff) << 8)
637 #define MAX_PACKET(p) (((p)&0xffff) << 16)
638 #define MAX_PACKET_MASK (0xffff << 16)
639 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
641 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
644 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
646 /* tx_info bitmasks */
647 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
648 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
651 #define EP_CTX_CYCLE_MASK (1 << 0)
655 * struct xhci_input_control_context
656 * Input control context; see section 6.2.5.
658 * @drop_context: set the bit of the endpoint context you want to disable
659 * @add_context: set the bit of the endpoint context you want to enable
661 struct xhci_input_control_ctx {
667 /* Represents everything that is needed to issue a command on the command ring.
668 * It's useful to pre-allocate these for commands that cannot fail due to
669 * out-of-memory errors, like freeing streams.
671 struct xhci_command {
672 /* Input context for changing device state */
673 struct xhci_container_ctx *in_ctx;
675 /* If completion is null, no one is waiting on this command
676 * and the structure can be freed after the command completes.
678 struct completion *completion;
679 union xhci_trb *command_trb;
680 struct list_head cmd_list;
683 /* drop context bitmasks */
684 #define DROP_EP(x) (0x1 << x)
685 /* add context bitmasks */
686 #define ADD_EP(x) (0x1 << x)
688 struct xhci_stream_ctx {
689 /* 64-bit stream ring address, cycle state, and stream type */
691 /* offset 0x14 - 0x1f reserved for HC internal use */
695 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
696 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
697 /* Secondary stream array type, dequeue pointer is to a transfer ring */
699 /* Primary stream array type, dequeue pointer is to a transfer ring */
701 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
706 #define SCT_SSA_128 6
707 #define SCT_SSA_256 7
709 /* Assume no secondary streams for now */
710 struct xhci_stream_info {
711 struct xhci_ring **stream_rings;
712 /* Number of streams, including stream 0 (which drivers can't use) */
713 unsigned int num_streams;
714 /* The stream context array may be bigger than
715 * the number of streams the driver asked for
717 struct xhci_stream_ctx *stream_ctx_array;
718 unsigned int num_stream_ctxs;
719 dma_addr_t ctx_array_dma;
720 /* For mapping physical TRB addresses to segments in stream rings */
721 struct radix_tree_root trb_address_map;
722 struct xhci_command *free_streams_command;
725 #define SMALL_STREAM_ARRAY_SIZE 256
726 #define MEDIUM_STREAM_ARRAY_SIZE 1024
728 struct xhci_virt_ep {
729 struct xhci_ring *ring;
730 /* Related to endpoints that are configured to use stream IDs only */
731 struct xhci_stream_info *stream_info;
732 /* Temporary storage in case the configure endpoint command fails and we
733 * have to restore the device state to the previous state
735 struct xhci_ring *new_ring;
736 unsigned int ep_state;
737 #define SET_DEQ_PENDING (1 << 0)
738 #define EP_HALTED (1 << 1) /* For stall handling */
739 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
740 /* Transitioning the endpoint to using streams, don't enqueue URBs */
741 #define EP_GETTING_STREAMS (1 << 3)
742 #define EP_HAS_STREAMS (1 << 4)
743 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
744 #define EP_GETTING_NO_STREAMS (1 << 5)
745 /* ---- Related to URB cancellation ---- */
746 struct list_head cancelled_td_list;
747 /* The TRB that was last reported in a stopped endpoint ring */
748 union xhci_trb *stopped_trb;
749 struct xhci_td *stopped_td;
750 unsigned int stopped_stream;
751 /* Watchdog timer for stop endpoint command to cancel URBs */
752 struct timer_list stop_cmd_timer;
753 int stop_cmds_pending;
754 struct xhci_hcd *xhci;
755 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
756 * command. We'll need to update the ring's dequeue segment and dequeue
757 * pointer after the command completes.
759 struct xhci_segment *queued_deq_seg;
760 union xhci_trb *queued_deq_ptr;
762 * Sometimes the xHC can not process isochronous endpoint ring quickly
763 * enough, and it will miss some isoc tds on the ring and generate
764 * a Missed Service Error Event.
765 * Set skip flag when receive a Missed Service Error Event and
766 * process the missed tds on the endpoint ring.
771 struct xhci_virt_device {
772 struct usb_device *udev;
774 * Commands to the hardware are passed an "input context" that
775 * tells the hardware what to change in its data structures.
776 * The hardware will return changes in an "output context" that
777 * software must allocate for the hardware. We need to keep
778 * track of input and output contexts separately because
779 * these commands might fail and we don't trust the hardware.
781 struct xhci_container_ctx *out_ctx;
782 /* Used for addressing devices and configuration changes */
783 struct xhci_container_ctx *in_ctx;
784 /* Rings saved to ensure old alt settings can be re-instated */
785 struct xhci_ring **ring_cache;
786 int num_rings_cached;
787 /* Store xHC assigned device address */
789 #define XHCI_MAX_RINGS_CACHED 31
790 struct xhci_virt_ep eps[31];
791 struct completion cmd_completion;
792 /* Status of the last command issued for this device */
794 struct list_head cmd_list;
800 * struct xhci_device_context_array
801 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
803 struct xhci_device_context_array {
804 /* 64-bit device addresses; we only write 32-bit addresses */
805 u64 dev_context_ptrs[MAX_HC_SLOTS];
806 /* private xHCD pointers */
809 /* TODO: write function to set the 64-bit device DMA address */
811 * TODO: change this to be dynamically sized at HC mem init time since the HC
812 * might not be able to handle the maximum number of devices possible.
816 struct xhci_transfer_event {
817 /* 64-bit buffer address, or immediate data */
820 /* This field is interpreted differently based on the type of TRB */
824 /** Transfer Event bit fields **/
825 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
827 /* Completion Code - only applicable for some types of TRBs */
828 #define COMP_CODE_MASK (0xff << 24)
829 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
830 #define COMP_SUCCESS 1
831 /* Data Buffer Error */
832 #define COMP_DB_ERR 2
833 /* Babble Detected Error */
834 #define COMP_BABBLE 3
835 /* USB Transaction Error */
836 #define COMP_TX_ERR 4
837 /* TRB Error - some TRB field is invalid */
838 #define COMP_TRB_ERR 5
839 /* Stall Error - USB device is stalled */
841 /* Resource Error - HC doesn't have memory for that device configuration */
842 #define COMP_ENOMEM 7
843 /* Bandwidth Error - not enough room in schedule for this dev config */
844 #define COMP_BW_ERR 8
845 /* No Slots Available Error - HC ran out of device slots */
846 #define COMP_ENOSLOTS 9
847 /* Invalid Stream Type Error */
848 #define COMP_STREAM_ERR 10
849 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
850 #define COMP_EBADSLT 11
851 /* Endpoint Not Enabled Error */
852 #define COMP_EBADEP 12
854 #define COMP_SHORT_TX 13
855 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
856 #define COMP_UNDERRUN 14
857 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
858 #define COMP_OVERRUN 15
859 /* Virtual Function Event Ring Full Error */
860 #define COMP_VF_FULL 16
861 /* Parameter Error - Context parameter is invalid */
862 #define COMP_EINVAL 17
863 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
864 #define COMP_BW_OVER 18
865 /* Context State Error - illegal context state transition requested */
866 #define COMP_CTX_STATE 19
867 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
868 #define COMP_PING_ERR 20
869 /* Event Ring is full */
870 #define COMP_ER_FULL 21
871 /* Missed Service Error - HC couldn't service an isoc ep within interval */
872 #define COMP_MISSED_INT 23
873 /* Successfully stopped command ring */
874 #define COMP_CMD_STOP 24
875 /* Successfully aborted current command and stopped command ring */
876 #define COMP_CMD_ABORT 25
877 /* Stopped - transfer was terminated by a stop endpoint command */
879 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
880 #define COMP_STOP_INVAL 27
881 /* Control Abort Error - Debug Capability - control pipe aborted */
882 #define COMP_DBG_ABORT 28
883 /* TRB type 29 and 30 reserved */
884 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
885 #define COMP_BUFF_OVER 31
886 /* Event Lost Error - xHC has an "internal event overrun condition" */
887 #define COMP_ISSUES 32
888 /* Undefined Error - reported when other error codes don't apply */
889 #define COMP_UNKNOWN 33
890 /* Invalid Stream ID Error */
891 #define COMP_STRID_ERR 34
892 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
893 /* FIXME - check for this */
894 #define COMP_2ND_BW_ERR 35
895 /* Split Transaction Error */
896 #define COMP_SPLIT_ERR 36
898 struct xhci_link_trb {
899 /* 64-bit segment pointer*/
905 /* control bitfields */
906 #define LINK_TOGGLE (0x1<<1)
908 /* Command completion event TRB */
909 struct xhci_event_cmd {
910 /* Pointer to command TRB, or the value passed by the event data trb */
917 /* bits 16:23 are the virtual function ID */
918 /* bits 24:31 are the slot ID */
919 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
920 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
922 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
923 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
924 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
926 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
927 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
928 #define LAST_EP_INDEX 30
930 /* Set TR Dequeue Pointer command TRB fields */
931 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
932 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
935 /* Port Status Change Event TRB fields */
936 /* Port ID - bits 31:24 */
937 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
939 /* Normal TRB fields */
940 /* transfer_len bitmasks - bits 0:16 */
941 #define TRB_LEN(p) ((p) & 0x1ffff)
942 /* Interrupter Target - which MSI-X vector to target the completion event at */
943 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
944 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
946 /* Cycle bit - indicates TRB ownership by HC or HCD */
947 #define TRB_CYCLE (1<<0)
949 * Force next event data TRB to be evaluated before task switch.
950 * Used to pass OS data back after a TD completes.
952 #define TRB_ENT (1<<1)
953 /* Interrupt on short packet */
954 #define TRB_ISP (1<<2)
955 /* Set PCIe no snoop attribute */
956 #define TRB_NO_SNOOP (1<<3)
957 /* Chain multiple TRBs into a TD */
958 #define TRB_CHAIN (1<<4)
959 /* Interrupt on completion */
960 #define TRB_IOC (1<<5)
961 /* The buffer pointer contains immediate data */
962 #define TRB_IDT (1<<6)
965 /* Control transfer TRB specific fields */
966 #define TRB_DIR_IN (1<<16)
968 /* Isochronous TRB specific fields */
969 #define TRB_SIA (1<<31)
971 struct xhci_generic_trb {
976 struct xhci_link_trb link;
977 struct xhci_transfer_event trans_event;
978 struct xhci_event_cmd event_cmd;
979 struct xhci_generic_trb generic;
983 #define TRB_TYPE_BITMASK (0xfc00)
984 #define TRB_TYPE(p) ((p) << 10)
985 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
987 /* bulk, interrupt, isoc scatter/gather, and control data stage */
989 /* setup stage for control transfers */
991 /* data stage for control transfers */
993 /* status stage for control transfers */
997 /* TRB for linking ring segments */
999 #define TRB_EVENT_DATA 7
1000 /* Transfer Ring No-op (not for the command ring) */
1001 #define TRB_TR_NOOP 8
1003 /* Enable Slot Command */
1004 #define TRB_ENABLE_SLOT 9
1005 /* Disable Slot Command */
1006 #define TRB_DISABLE_SLOT 10
1007 /* Address Device Command */
1008 #define TRB_ADDR_DEV 11
1009 /* Configure Endpoint Command */
1010 #define TRB_CONFIG_EP 12
1011 /* Evaluate Context Command */
1012 #define TRB_EVAL_CONTEXT 13
1013 /* Reset Endpoint Command */
1014 #define TRB_RESET_EP 14
1015 /* Stop Transfer Ring Command */
1016 #define TRB_STOP_RING 15
1017 /* Set Transfer Ring Dequeue Pointer Command */
1018 #define TRB_SET_DEQ 16
1019 /* Reset Device Command */
1020 #define TRB_RESET_DEV 17
1021 /* Force Event Command (opt) */
1022 #define TRB_FORCE_EVENT 18
1023 /* Negotiate Bandwidth Command (opt) */
1024 #define TRB_NEG_BANDWIDTH 19
1025 /* Set Latency Tolerance Value Command (opt) */
1026 #define TRB_SET_LT 20
1027 /* Get port bandwidth Command */
1028 #define TRB_GET_BW 21
1029 /* Force Header Command - generate a transaction or link management packet */
1030 #define TRB_FORCE_HEADER 22
1031 /* No-op Command - not for transfer rings */
1032 #define TRB_CMD_NOOP 23
1033 /* TRB IDs 24-31 reserved */
1035 /* Transfer Event */
1036 #define TRB_TRANSFER 32
1037 /* Command Completion Event */
1038 #define TRB_COMPLETION 33
1039 /* Port Status Change Event */
1040 #define TRB_PORT_STATUS 34
1041 /* Bandwidth Request Event (opt) */
1042 #define TRB_BANDWIDTH_EVENT 35
1043 /* Doorbell Event (opt) */
1044 #define TRB_DOORBELL 36
1045 /* Host Controller Event */
1046 #define TRB_HC_EVENT 37
1047 /* Device Notification Event - device sent function wake notification */
1048 #define TRB_DEV_NOTE 38
1049 /* MFINDEX Wrap Event - microframe counter wrapped */
1050 #define TRB_MFINDEX_WRAP 39
1051 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1053 /* Nec vendor-specific command completion event. */
1054 #define TRB_NEC_CMD_COMP 48
1055 /* Get NEC firmware revision. */
1056 #define TRB_NEC_GET_FW 49
1058 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1059 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1062 * TRBS_PER_SEGMENT must be a multiple of 4,
1063 * since the command ring is 64-byte aligned.
1064 * It must also be greater than 16.
1066 #define TRBS_PER_SEGMENT 64
1067 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1068 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1069 #define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1070 /* SEGMENT_SHIFT should be log2(SEGMENT_SIZE).
1071 * Change this if you change TRBS_PER_SEGMENT!
1073 #define SEGMENT_SHIFT 10
1074 /* TRB buffer pointers can't cross 64KB boundaries */
1075 #define TRB_MAX_BUFF_SHIFT 16
1076 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1078 struct xhci_segment {
1079 union xhci_trb *trbs;
1080 /* private to HCD */
1081 struct xhci_segment *next;
1086 struct list_head td_list;
1087 struct list_head cancelled_td_list;
1089 struct xhci_segment *start_seg;
1090 union xhci_trb *first_trb;
1091 union xhci_trb *last_trb;
1094 struct xhci_dequeue_state {
1095 struct xhci_segment *new_deq_seg;
1096 union xhci_trb *new_deq_ptr;
1097 int new_cycle_state;
1101 struct xhci_segment *first_seg;
1102 union xhci_trb *enqueue;
1103 struct xhci_segment *enq_seg;
1104 unsigned int enq_updates;
1105 union xhci_trb *dequeue;
1106 struct xhci_segment *deq_seg;
1107 unsigned int deq_updates;
1108 struct list_head td_list;
1110 * Write the cycle state into the TRB cycle field to give ownership of
1111 * the TRB to the host controller (if we are the producer), or to check
1112 * if we own the TRB (if we are the consumer). See section 4.9.1.
1115 unsigned int stream_id;
1118 struct xhci_erst_entry {
1119 /* 64-bit event ring segment address */
1127 struct xhci_erst_entry *entries;
1128 unsigned int num_entries;
1129 /* xhci->event_ring keeps track of segment dma addresses */
1130 dma_addr_t erst_dma_addr;
1131 /* Num entries the ERST can contain */
1132 unsigned int erst_size;
1135 struct xhci_scratchpad {
1139 dma_addr_t *sp_dma_buffers;
1145 struct xhci_td *td[0];
1149 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1150 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1151 * meaning 64 ring segments.
1152 * Initial allocated size of the ERST, in number of entries */
1153 #define ERST_NUM_SEGS 1
1154 /* Initial allocated size of the ERST, in number of entries */
1155 #define ERST_SIZE 64
1156 /* Initial number of event segment rings allocated */
1157 #define ERST_ENTRIES 1
1158 /* Poll every 60 seconds */
1159 #define POLL_TIMEOUT 60
1160 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1161 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1162 /* XXX: Make these module parameters */
1176 struct xhci_bus_state {
1177 unsigned long bus_suspended;
1178 unsigned long next_statechange;
1180 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1181 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1183 u32 suspended_ports;
1184 unsigned long resume_done[USB_MAXCHILDREN];
1187 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1189 if (hcd->speed == HCD_USB3)
1195 /* There is one ehci_hci structure per controller */
1197 struct usb_hcd *main_hcd;
1198 struct usb_hcd *shared_hcd;
1199 /* glue to PCI and HCD framework */
1200 struct xhci_cap_regs __iomem *cap_regs;
1201 struct xhci_op_regs __iomem *op_regs;
1202 struct xhci_run_regs __iomem *run_regs;
1203 struct xhci_doorbell_array __iomem *dba;
1204 /* Our HCD's current interrupter register set */
1205 struct xhci_intr_reg __iomem *ir_set;
1207 /* Cached register copies of read-only HC data */
1215 /* packed release number */
1219 u8 max_interrupters;
1224 /* 4KB min, 128MB max */
1226 /* Valid values are 12 to 20, inclusive */
1230 struct msix_entry *msix_entries;
1231 /* data structures */
1232 struct xhci_device_context_array *dcbaa;
1233 struct xhci_ring *cmd_ring;
1234 unsigned int cmd_ring_reserved_trbs;
1235 struct xhci_ring *event_ring;
1236 struct xhci_erst erst;
1238 struct xhci_scratchpad *scratchpad;
1240 /* slot enabling and address device helpers */
1241 struct completion addr_dev;
1243 /* Internal mirror of the HW's dcbaa */
1244 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1247 struct dma_pool *device_pool;
1248 struct dma_pool *segment_pool;
1249 struct dma_pool *small_streams_pool;
1250 struct dma_pool *medium_streams_pool;
1252 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1253 /* Poll the rings - for debugging */
1254 struct timer_list event_ring_timer;
1257 /* Host controller watchdog timer structures */
1258 unsigned int xhc_state;
1262 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1264 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1265 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1266 * that sees this status (other than the timer that set it) should stop touching
1267 * hardware immediately. Interrupt handlers should return immediately when
1268 * they see this status (any time they drop and re-acquire xhci->lock).
1269 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1270 * putting the TD on the canceled list, etc.
1272 * There are no reports of xHCI host controllers that display this issue.
1274 #define XHCI_STATE_DYING (1 << 0)
1275 #define XHCI_STATE_HALTED (1 << 1)
1278 unsigned int quirks;
1279 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1280 #define XHCI_RESET_EP_QUIRK (1 << 1)
1281 #define XHCI_NEC_HOST (1 << 2)
1282 /* There are two roothubs to keep track of bus suspend info for */
1283 struct xhci_bus_state bus_state[2];
1284 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1286 /* Array of pointers to USB 3.0 PORTSC registers */
1287 u32 __iomem **usb3_ports;
1288 unsigned int num_usb3_ports;
1289 /* Array of pointers to USB 2.0 PORTSC registers */
1290 u32 __iomem **usb2_ports;
1291 unsigned int num_usb2_ports;
1294 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1295 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1297 return *((struct xhci_hcd **) (hcd->hcd_priv));
1300 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1302 return xhci->main_hcd;
1305 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1306 #define XHCI_DEBUG 1
1308 #define XHCI_DEBUG 0
1311 #define xhci_dbg(xhci, fmt, args...) \
1312 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1313 #define xhci_info(xhci, fmt, args...) \
1314 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1315 #define xhci_err(xhci, fmt, args...) \
1316 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1317 #define xhci_warn(xhci, fmt, args...) \
1318 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1320 /* TODO: copied from ehci.h - can be refactored? */
1321 /* xHCI spec says all registers are little endian */
1322 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1323 __u32 __iomem *regs)
1327 static inline void xhci_writel(struct xhci_hcd *xhci,
1328 const unsigned int val, __u32 __iomem *regs)
1331 "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
1337 * Registers should always be accessed with double word or quad word accesses.
1339 * Some xHCI implementations may support 64-bit address pointers. Registers
1340 * with 64-bit address pointers should be written to with dword accesses by
1341 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1342 * xHCI implementations that do not support 64-bit address pointers will ignore
1343 * the high dword, and write order is irrelevant.
1345 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1346 __u64 __iomem *regs)
1348 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1349 u64 val_lo = readl(ptr);
1350 u64 val_hi = readl(ptr + 1);
1351 return val_lo + (val_hi << 32);
1353 static inline void xhci_write_64(struct xhci_hcd *xhci,
1354 const u64 val, __u64 __iomem *regs)
1356 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1357 u32 val_lo = lower_32_bits(val);
1358 u32 val_hi = upper_32_bits(val);
1361 "`MEM_WRITE_DWORD(3'b000, 64'h%p, 64'h%0lx, 4'hf);\n",
1362 regs, (long unsigned int) val);
1363 writel(val_lo, ptr);
1364 writel(val_hi, ptr + 1);
1367 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1369 u32 temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
1370 return ((HC_VERSION(temp) == 0x95) &&
1371 (xhci->quirks & XHCI_LINK_TRB_QUIRK));
1374 /* xHCI debugging */
1375 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1376 void xhci_print_registers(struct xhci_hcd *xhci);
1377 void xhci_dbg_regs(struct xhci_hcd *xhci);
1378 void xhci_print_run_regs(struct xhci_hcd *xhci);
1379 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1380 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1381 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1382 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1383 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1384 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1385 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1386 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1387 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1388 struct xhci_container_ctx *ctx);
1389 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1390 unsigned int slot_id, unsigned int ep_index,
1391 struct xhci_virt_ep *ep);
1393 /* xHCI memory management */
1394 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1395 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1396 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1397 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1398 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1399 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1400 struct usb_device *udev);
1401 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1402 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1403 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1404 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1405 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1406 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1407 struct xhci_container_ctx *in_ctx,
1408 struct xhci_container_ctx *out_ctx,
1409 unsigned int ep_index);
1410 void xhci_slot_copy(struct xhci_hcd *xhci,
1411 struct xhci_container_ctx *in_ctx,
1412 struct xhci_container_ctx *out_ctx);
1413 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1414 struct usb_device *udev, struct usb_host_endpoint *ep,
1416 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1417 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1418 struct xhci_virt_device *virt_dev,
1419 unsigned int ep_index);
1420 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1421 unsigned int num_stream_ctxs,
1422 unsigned int num_streams, gfp_t flags);
1423 void xhci_free_stream_info(struct xhci_hcd *xhci,
1424 struct xhci_stream_info *stream_info);
1425 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1426 struct xhci_ep_ctx *ep_ctx,
1427 struct xhci_stream_info *stream_info);
1428 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1429 struct xhci_ep_ctx *ep_ctx,
1430 struct xhci_virt_ep *ep);
1431 struct xhci_ring *xhci_dma_to_transfer_ring(
1432 struct xhci_virt_ep *ep,
1434 struct xhci_ring *xhci_stream_id_to_ring(
1435 struct xhci_virt_device *dev,
1436 unsigned int ep_index,
1437 unsigned int stream_id);
1438 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1439 bool allocate_in_ctx, bool allocate_completion,
1441 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1442 void xhci_free_command(struct xhci_hcd *xhci,
1443 struct xhci_command *command);
1447 int xhci_register_pci(void);
1448 void xhci_unregister_pci(void);
1451 /* xHCI host controller glue */
1452 void xhci_quiesce(struct xhci_hcd *xhci);
1453 int xhci_halt(struct xhci_hcd *xhci);
1454 int xhci_reset(struct xhci_hcd *xhci);
1455 int xhci_init(struct usb_hcd *hcd);
1456 int xhci_run(struct usb_hcd *hcd);
1457 void xhci_stop(struct usb_hcd *hcd);
1458 void xhci_shutdown(struct usb_hcd *hcd);
1461 int xhci_suspend(struct xhci_hcd *xhci);
1462 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1464 #define xhci_suspend NULL
1465 #define xhci_resume NULL
1468 int xhci_get_frame(struct usb_hcd *hcd);
1469 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1470 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1471 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1472 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1473 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1474 struct usb_host_endpoint **eps, unsigned int num_eps,
1475 unsigned int num_streams, gfp_t mem_flags);
1476 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1477 struct usb_host_endpoint **eps, unsigned int num_eps,
1479 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1480 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1481 struct usb_tt *tt, gfp_t mem_flags);
1482 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1483 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1484 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1485 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1486 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1487 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1488 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1489 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1491 /* xHCI ring, segment, TRB, and TD functions */
1492 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1493 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1494 union xhci_trb *start_trb, union xhci_trb *end_trb,
1495 dma_addr_t suspect_dma);
1496 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1497 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1498 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1499 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1501 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1502 u32 field1, u32 field2, u32 field3, u32 field4);
1503 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1504 unsigned int ep_index, int suspend);
1505 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1506 int slot_id, unsigned int ep_index);
1507 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1508 int slot_id, unsigned int ep_index);
1509 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1510 int slot_id, unsigned int ep_index);
1511 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1512 struct urb *urb, int slot_id, unsigned int ep_index);
1513 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1514 u32 slot_id, bool command_must_succeed);
1515 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1517 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1518 unsigned int ep_index);
1519 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1520 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1521 unsigned int slot_id, unsigned int ep_index,
1522 unsigned int stream_id, struct xhci_td *cur_td,
1523 struct xhci_dequeue_state *state);
1524 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1525 unsigned int slot_id, unsigned int ep_index,
1526 unsigned int stream_id,
1527 struct xhci_dequeue_state *deq_state);
1528 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1529 struct usb_device *udev, unsigned int ep_index);
1530 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1531 unsigned int slot_id, unsigned int ep_index,
1532 struct xhci_dequeue_state *deq_state);
1533 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1534 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1535 unsigned int ep_index, unsigned int stream_id);
1537 /* xHCI roothub code */
1538 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1539 char *buf, u16 wLength);
1540 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1543 int xhci_bus_suspend(struct usb_hcd *hcd);
1544 int xhci_bus_resume(struct usb_hcd *hcd);
1546 #define xhci_bus_suspend NULL
1547 #define xhci_bus_resume NULL
1548 #endif /* CONFIG_PM */
1550 u32 xhci_port_state_to_neutral(u32 state);
1551 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1553 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1556 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1557 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1558 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1560 #endif /* __LINUX_XHCI_HCD_H */