Pileus Git - ~andy/linux/blob - drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 147 {
 148         union xhci_trb *next;
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152
 153         /* If this is not event ring, there is one more usable TRB */
 154         if (ring->type != TYPE_EVENT &&
 155                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 156                 ring->num_trbs_free++;
 157         next = ++(ring->dequeue);
 158
 159         /* Update the dequeue pointer further if that was a link TRB or we're at
 160          * the end of an event ring segment (which doesn't have link TRBS)
 161          */
 162         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 163                 if (ring->type == TYPE_EVENT && last_trb_on_last_seg(xhci,
 164                                 ring, ring->deq_seg, next)) {
 165                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 166                 }
 167                 ring->deq_seg = ring->deq_seg->next;
 168                 ring->dequeue = ring->deq_seg->trbs;
 169                 next = ring->dequeue;
 170         }
 171         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 172 }
 173
 174 /*
 175  * See Cycle bit rules. SW is the consumer for the event ring only.
 176  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 177  *
 178  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 179  * chain bit is set), then set the chain bit in all the following link TRBs.
 180  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 181  * have their chain bit cleared (so that each Link TRB is a separate TD).
 182  *
 183  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 184  * set, but other sections talk about dealing with the chain bit set.  This was
 185  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 186  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 187  *
 188  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 189  *                      prepare_transfer()?
 190  */
 191 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 192                         bool more_trbs_coming)
 193 {
 194         u32 chain;
 195         union xhci_trb *next;
 196         unsigned long long addr;
 197
 198         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 199         /* If this is not event ring, there is one less usable TRB */
 200         if (ring->type != TYPE_EVENT &&
 201                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 202                 ring->num_trbs_free--;
 203         next = ++(ring->enqueue);
 204
 205         ring->enq_updates++;
 206         /* Update the dequeue pointer further if that was a link TRB or we're at
 207          * the end of an event ring segment (which doesn't have link TRBS)
 208          */
 209         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 210                 if (ring->type != TYPE_EVENT) {
 211                         /*
 212                          * If the caller doesn't plan on enqueueing more
 213                          * TDs before ringing the doorbell, then we
 214                          * don't want to give the link TRB to the
 215                          * hardware just yet.  We'll give the link TRB
 216                          * back in prepare_ring() just before we enqueue
 217                          * the TD at the top of the ring.
 218                          */
 219                         if (!chain && !more_trbs_coming)
 220                                 break;
 221
 222                         /* If we're not dealing with 0.95 hardware or
 223                          * isoc rings on AMD 0.96 host,
 224                          * carry over the chain bit of the previous TRB
 225                          * (which may mean the chain bit is cleared).
 226                          */
 227                         if (!(ring->type == TYPE_ISOC &&
 228                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 229                                                 && !xhci_link_trb_quirk(xhci)) {
 230                                 next->link.control &=
 231                                         cpu_to_le32(~TRB_CHAIN);
 232                                 next->link.control |=
 233                                         cpu_to_le32(chain);
 234                         }
 235                         /* Give this link TRB to the hardware */
 236                         wmb();
 237                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 238
 239                         /* Toggle the cycle bit after the last ring segment. */
 240                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 241                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 242                         }
 243                 }
 244                 ring->enq_seg = ring->enq_seg->next;
 245                 ring->enqueue = ring->enq_seg->trbs;
 246                 next = ring->enqueue;
 247         }
 248         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 249 }
 250
 251 /*
 252  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 253  * above.
 254  */
 255 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 256                 unsigned int num_trbs)
 257 {
 258         if (ring->num_trbs_free >= num_trbs)
 259                 return 1;
 260
 261         return 0;
 262 }
 263
 264 /* Ring the host controller doorbell after placing a command on the ring */
 265 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 266 {
 267         xhci_dbg(xhci, "// Ding dong!\n");
 268         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 269         /* Flush PCI posted writes */
 270         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 271 }
 272
 273 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 274                 unsigned int slot_id,
 275                 unsigned int ep_index,
 276                 unsigned int stream_id)
 277 {
 278         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 279         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 280         unsigned int ep_state = ep->ep_state;
 281
 282         /* Don't ring the doorbell for this endpoint if there are pending
 283          * cancellations because we don't want to interrupt processing.
 284          * We don't want to restart any stream rings if there's a set dequeue
 285          * pointer command pending because the device can choose to start any
 286          * stream once the endpoint is on the HW schedule.
 287          * FIXME - check all the stream rings for pending cancellations.
 288          */
 289         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 290             (ep_state & EP_HALTED))
 291                 return;
 292         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 293         /* The CPU has better things to do at this point than wait for a
 294          * write-posting flush.  It'll get there soon enough.
 295          */
 296 }
 297
 298 /* Ring the doorbell for any rings with pending URBs */
 299 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 300                 unsigned int slot_id,
 301                 unsigned int ep_index)
 302 {
 303         unsigned int stream_id;
 304         struct xhci_virt_ep *ep;
 305
 306         ep = &xhci->devs[slot_id]->eps[ep_index];
 307
 308         /* A ring has pending URBs if its TD list is not empty */
 309         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 310                 if (!(list_empty(&ep->ring->td_list)))
 311                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 312                 return;
 313         }
 314
 315         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 316                         stream_id++) {
 317                 struct xhci_stream_info *stream_info = ep->stream_info;
 318                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 319                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 320                                                 stream_id);
 321         }
 322 }
 323
 324 /*
 325  * Find the segment that trb is in.  Start searching in start_seg.
 326  * If we must move past a segment that has a link TRB with a toggle cycle state
 327  * bit set, then we will toggle the value pointed at by cycle_state.
 328  */
 329 static struct xhci_segment *find_trb_seg(
 330                 struct xhci_segment *start_seg,
 331                 union xhci_trb  *trb, int *cycle_state)
 332 {
 333         struct xhci_segment *cur_seg = start_seg;
 334         struct xhci_generic_trb *generic_trb;
 335
 336         while (cur_seg->trbs > trb ||
 337                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 338                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 339                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 340                         *cycle_state ^= 0x1;
 341                 cur_seg = cur_seg->next;
 342                 if (cur_seg == start_seg)
 343                         /* Looped over the entire list.  Oops! */
 344                         return NULL;
 345         }
 346         return cur_seg;
 347 }
 348
 349
 350 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 351                 unsigned int slot_id, unsigned int ep_index,
 352                 unsigned int stream_id)
 353 {
 354         struct xhci_virt_ep *ep;
 355
 356         ep = &xhci->devs[slot_id]->eps[ep_index];
 357         /* Common case: no streams */
 358         if (!(ep->ep_state & EP_HAS_STREAMS))
 359                 return ep->ring;
 360
 361         if (stream_id == 0) {
 362                 xhci_warn(xhci,
 363                                 "WARN: Slot ID %u, ep index %u has streams, "
 364                                 "but URB has no stream ID.\n",
 365                                 slot_id, ep_index);
 366                 return NULL;
 367         }
 368
 369         if (stream_id < ep->stream_info->num_streams)
 370                 return ep->stream_info->stream_rings[stream_id];
 371
 372         xhci_warn(xhci,
 373                         "WARN: Slot ID %u, ep index %u has "
 374                         "stream IDs 1 to %u allocated, "
 375                         "but stream ID %u is requested.\n",
 376                         slot_id, ep_index,
 377                         ep->stream_info->num_streams - 1,
 378                         stream_id);
 379         return NULL;
 380 }
 381
 382 /* Get the right ring for the given URB.
 383  * If the endpoint supports streams, boundary check the URB's stream ID.
 384  * If the endpoint doesn't support streams, return the singular endpoint ring.
 385  */
 386 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 387                 struct urb *urb)
 388 {
 389         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 390                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 391 }
 392
 393 /*
 394  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 395  * Record the new state of the xHC's endpoint ring dequeue segment,
 396  * dequeue pointer, and new consumer cycle state in state.
 397  * Update our internal representation of the ring's dequeue pointer.
 398  *
 399  * We do this in three jumps:
 400  *  - First we update our new ring state to be the same as when the xHC stopped.
 401  *  - Then we traverse the ring to find the segment that contains
 402  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 403  *    any link TRBs with the toggle cycle bit set.
 404  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 405  *    if we've moved it past a link TRB with the toggle cycle bit set.
 406  *
 407  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 408  * with correct __le32 accesses they should work fine.  Only users of this are
 409  * in here.
 410  */
 411 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 412                 unsigned int slot_id, unsigned int ep_index,
 413                 unsigned int stream_id, struct xhci_td *cur_td,
 414                 struct xhci_dequeue_state *state)
 415 {
 416         struct xhci_virt_device *dev = xhci->devs[slot_id];
 417         struct xhci_ring *ep_ring;
 418         struct xhci_generic_trb *trb;
 419         struct xhci_ep_ctx *ep_ctx;
 420         dma_addr_t addr;
 421
 422         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 423                         ep_index, stream_id);
 424         if (!ep_ring) {
 425                 xhci_warn(xhci, "WARN can't find new dequeue state "
 426                                 "for invalid stream ID %u.\n",
 427                                 stream_id);
 428                 return;
 429         }
 430         state->new_cycle_state = 0;
 431         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 432         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 433                         dev->eps[ep_index].stopped_trb,
 434                         &state->new_cycle_state);
 435         if (!state->new_deq_seg) {
 436                 WARN_ON(1);
 437                 return;
 438         }
 439
 440         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 441         xhci_dbg(xhci, "Finding endpoint context\n");
 442         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 443         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 444
 445         state->new_deq_ptr = cur_td->last_trb;
 446         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 447         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 448                         state->new_deq_ptr,
 449                         &state->new_cycle_state);
 450         if (!state->new_deq_seg) {
 451                 WARN_ON(1);
 452                 return;
 453         }
 454
 455         trb = &state->new_deq_ptr->generic;
 456         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 457             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 458                 state->new_cycle_state ^= 0x1;
 459         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 460
 461         /*
 462          * If there is only one segment in a ring, find_trb_seg()'s while loop
 463          * will not run, and it will return before it has a chance to see if it
 464          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 465          * ended just before the link TRB on a one-segment ring, or if the TD
 466          * wrapped around the top of the ring, because it doesn't have the TD in
 467          * question.  Look for the one-segment case where stalled TRB's address
 468          * is greater than the new dequeue pointer address.
 469          */
 470         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 471                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 472                 state->new_cycle_state ^= 0x1;
 473         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 474
 475         /* Don't update the ring cycle state for the producer (us). */
 476         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 477                         state->new_deq_seg);
 478         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 479         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 480                         (unsigned long long) addr);
 481 }
 482
 483 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 484  * (The last TRB actually points to the ring enqueue pointer, which is not part
 485  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 486  */
 487 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 488                 struct xhci_td *cur_td, bool flip_cycle)
 489 {
 490         struct xhci_segment *cur_seg;
 491         union xhci_trb *cur_trb;
 492
 493         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 494                         true;
 495                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 496                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 497                         /* Unchain any chained Link TRBs, but
 498                          * leave the pointers intact.
 499                          */
 500                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 501                         /* Flip the cycle bit (link TRBs can't be the first
 502                          * or last TRB).
 503                          */
 504                         if (flip_cycle)
 505                                 cur_trb->generic.field[3] ^=
 506                                         cpu_to_le32(TRB_CYCLE);
 507                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 508                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 509                                         "in seg %p (0x%llx dma)\n",
 510                                         cur_trb,
 511                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 512                                         cur_seg,
 513                                         (unsigned long long)cur_seg->dma);
 514                 } else {
 515                         cur_trb->generic.field[0] = 0;
 516                         cur_trb->generic.field[1] = 0;
 517                         cur_trb->generic.field[2] = 0;
 518                         /* Preserve only the cycle bit of this TRB */
 519                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 520                         /* Flip the cycle bit except on the first or last TRB */
 521                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 522                                         cur_trb != cur_td->last_trb)
 523                                 cur_trb->generic.field[3] ^=
 524                                         cpu_to_le32(TRB_CYCLE);
 525                         cur_trb->generic.field[3] |= cpu_to_le32(
 526                                 TRB_TYPE(TRB_TR_NOOP));
 527                         xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 528                                         (unsigned long long)
 529                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 530                 }
 531                 if (cur_trb == cur_td->last_trb)
 532                         break;
 533         }
 534 }
 535
 536 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 537                 unsigned int ep_index, unsigned int stream_id,
 538                 struct xhci_segment *deq_seg,
 539                 union xhci_trb *deq_ptr, u32 cycle_state);
 540
 541 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 542                 unsigned int slot_id, unsigned int ep_index,
 543                 unsigned int stream_id,
 544                 struct xhci_dequeue_state *deq_state)
 545 {
 546         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 547
 548         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 549                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 550                         deq_state->new_deq_seg,
 551                         (unsigned long long)deq_state->new_deq_seg->dma,
 552                         deq_state->new_deq_ptr,
 553                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 554                         deq_state->new_cycle_state);
 555         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 556                         deq_state->new_deq_seg,
 557                         deq_state->new_deq_ptr,
 558                         (u32) deq_state->new_cycle_state);
 559         /* Stop the TD queueing code from ringing the doorbell until
 560          * this command completes.  The HC won't set the dequeue pointer
 561          * if the ring is running, and ringing the doorbell starts the
 562          * ring running.
 563          */
 564         ep->ep_state |= SET_DEQ_PENDING;
 565 }
 566
 567 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 568                 struct xhci_virt_ep *ep)
 569 {
 570         ep->ep_state &= ~EP_HALT_PENDING;
 571         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 572          * timer is running on another CPU, we don't decrement stop_cmds_pending
 573          * (since we didn't successfully stop the watchdog timer).
 574          */
 575         if (del_timer(&ep->stop_cmd_timer))
 576                 ep->stop_cmds_pending--;
 577 }
 578
 579 /* Must be called with xhci->lock held in interrupt context */
 580 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 581                 struct xhci_td *cur_td, int status, char *adjective)
 582 {
 583         struct usb_hcd *hcd;
 584         struct urb      *urb;
 585         struct urb_priv *urb_priv;
 586
 587         urb = cur_td->urb;
 588         urb_priv = urb->hcpriv;
 589         urb_priv->td_cnt++;
 590         hcd = bus_to_hcd(urb->dev->bus);
 591
 592         /* Only giveback urb when this is the last td in urb */
 593         if (urb_priv->td_cnt == urb_priv->length) {
 594                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 595                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 596                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 597                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 598                                         usb_amd_quirk_pll_enable();
 599                         }
 600                 }
 601                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 602
 603                 spin_unlock(&xhci->lock);
 604                 usb_hcd_giveback_urb(hcd, urb, status);
 605                 xhci_urb_free_priv(xhci, urb_priv);
 606                 spin_lock(&xhci->lock);
 607         }
 608 }
 609
 610 /*
 611  * When we get a command completion for a Stop Endpoint Command, we need to
 612  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 613  *
 614  *  1. If the HW was in the middle of processing the TD that needs to be
 615  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 616  *     in the TD with a Set Dequeue Pointer Command.
 617  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 618  *     bit cleared) so that the HW will skip over them.
 619  */
 620 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 621                 union xhci_trb *trb, struct xhci_event_cmd *event)
 622 {
 623         unsigned int slot_id;
 624         unsigned int ep_index;
 625         struct xhci_virt_device *virt_dev;
 626         struct xhci_ring *ep_ring;
 627         struct xhci_virt_ep *ep;
 628         struct list_head *entry;
 629         struct xhci_td *cur_td = NULL;
 630         struct xhci_td *last_unlinked_td;
 631
 632         struct xhci_dequeue_state deq_state;
 633
 634         if (unlikely(TRB_TO_SUSPEND_PORT(
 635                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 636                 slot_id = TRB_TO_SLOT_ID(
 637                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 638                 virt_dev = xhci->devs[slot_id];
 639                 if (virt_dev)
 640                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 641                                 event);
 642                 else
 643                         xhci_warn(xhci, "Stop endpoint command "
 644                                 "completion for disabled slot %u\n",
 645                                 slot_id);
 646                 return;
 647         }
 648
 649         memset(&deq_state, 0, sizeof(deq_state));
 650         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 651         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 652         ep = &xhci->devs[slot_id]->eps[ep_index];
 653
 654         if (list_empty(&ep->cancelled_td_list)) {
 655                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 656                 ep->stopped_td = NULL;
 657                 ep->stopped_trb = NULL;
 658                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 659                 return;
 660         }
 661
 662         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 663          * We have the xHCI lock, so nothing can modify this list until we drop
 664          * it.  We're also in the event handler, so we can't get re-interrupted
 665          * if another Stop Endpoint command completes
 666          */
 667         list_for_each(entry, &ep->cancelled_td_list) {
 668                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 669                 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 670                                 (unsigned long long)xhci_trb_virt_to_dma(
 671                                         cur_td->start_seg, cur_td->first_trb));
 672                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 673                 if (!ep_ring) {
 674                         /* This shouldn't happen unless a driver is mucking
 675                          * with the stream ID after submission.  This will
 676                          * leave the TD on the hardware ring, and the hardware
 677                          * will try to execute it, and may access a buffer
 678                          * that has already been freed.  In the best case, the
 679                          * hardware will execute it, and the event handler will
 680                          * ignore the completion event for that TD, since it was
 681                          * removed from the td_list for that endpoint.  In
 682                          * short, don't muck with the stream ID after
 683                          * submission.
 684                          */
 685                         xhci_warn(xhci, "WARN Cancelled URB %p "
 686                                         "has invalid stream ID %u.\n",
 687                                         cur_td->urb,
 688                                         cur_td->urb->stream_id);
 689                         goto remove_finished_td;
 690                 }
 691                 /*
 692                  * If we stopped on the TD we need to cancel, then we have to
 693                  * move the xHC endpoint ring dequeue pointer past this TD.
 694                  */
 695                 if (cur_td == ep->stopped_td)
 696                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 697                                         cur_td->urb->stream_id,
 698                                         cur_td, &deq_state);
 699                 else
 700                         td_to_noop(xhci, ep_ring, cur_td, false);
 701 remove_finished_td:
 702                 /*
 703                  * The event handler won't see a completion for this TD anymore,
 704                  * so remove it from the endpoint ring's TD list.  Keep it in
 705                  * the cancelled TD list for URB completion later.
 706                  */
 707                 list_del_init(&cur_td->td_list);
 708         }
 709         last_unlinked_td = cur_td;
 710         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 711
 712         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 713         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 714                 xhci_queue_new_dequeue_state(xhci,
 715                                 slot_id, ep_index,
 716                                 ep->stopped_td->urb->stream_id,
 717                                 &deq_state);
 718                 xhci_ring_cmd_db(xhci);
 719         } else {
 720                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 721                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 722         }
 723         ep->stopped_td = NULL;
 724         ep->stopped_trb = NULL;
 725
 726         /*
 727          * Drop the lock and complete the URBs in the cancelled TD list.
 728          * New TDs to be cancelled might be added to the end of the list before
 729          * we can complete all the URBs for the TDs we already unlinked.
 730          * So stop when we've completed the URB for the last TD we unlinked.
 731          */
 732         do {
 733                 cur_td = list_entry(ep->cancelled_td_list.next,
 734                                 struct xhci_td, cancelled_td_list);
 735                 list_del_init(&cur_td->cancelled_td_list);
 736
 737                 /* Clean up the cancelled URB */
 738                 /* Doesn't matter what we pass for status, since the core will
 739                  * just overwrite it (because the URB has been unlinked).
 740                  */
 741                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 742
 743                 /* Stop processing the cancelled list if the watchdog timer is
 744                  * running.
 745                  */
 746                 if (xhci->xhc_state & XHCI_STATE_DYING)
 747                         return;
 748         } while (cur_td != last_unlinked_td);
 749
 750         /* Return to the event handler with xhci->lock re-acquired */
 751 }
 752
 753 /* Watchdog timer function for when a stop endpoint command fails to complete.
 754  * In this case, we assume the host controller is broken or dying or dead.  The
 755  * host may still be completing some other events, so we have to be careful to
 756  * let the event ring handler and the URB dequeueing/enqueueing functions know
 757  * through xhci->state.
 758  *
 759  * The timer may also fire if the host takes a very long time to respond to the
 760  * command, and the stop endpoint command completion handler cannot delete the
 761  * timer before the timer function is called.  Another endpoint cancellation may
 762  * sneak in before the timer function can grab the lock, and that may queue
 763  * another stop endpoint command and add the timer back.  So we cannot use a
 764  * simple flag to say whether there is a pending stop endpoint command for a
 765  * particular endpoint.
 766  *
 767  * Instead we use a combination of that flag and a counter for the number of
 768  * pending stop endpoint commands.  If the timer is the tail end of the last
 769  * stop endpoint command, and the endpoint's command is still pending, we assume
 770  * the host is dying.
 771  */
 772 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 773 {
 774         struct xhci_hcd *xhci;
 775         struct xhci_virt_ep *ep;
 776         struct xhci_virt_ep *temp_ep;
 777         struct xhci_ring *ring;
 778         struct xhci_td *cur_td;
 779         int ret, i, j;
 780         unsigned long flags;
 781
 782         ep = (struct xhci_virt_ep *) arg;
 783         xhci = ep->xhci;
 784
 785         spin_lock_irqsave(&xhci->lock, flags);
 786
 787         ep->stop_cmds_pending--;
 788         if (xhci->xhc_state & XHCI_STATE_DYING) {
 789                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 790                                 "xHCI as DYING, exiting.\n");
 791                 spin_unlock_irqrestore(&xhci->lock, flags);
 792                 return;
 793         }
 794         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 795                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 796                                 "exiting.\n");
 797                 spin_unlock_irqrestore(&xhci->lock, flags);
 798                 return;
 799         }
 800
 801         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 802         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 803         /* Oops, HC is dead or dying or at least not responding to the stop
 804          * endpoint command.
 805          */
 806         xhci->xhc_state |= XHCI_STATE_DYING;
 807         /* Disable interrupts from the host controller and start halting it */
 808         xhci_quiesce(xhci);
 809         spin_unlock_irqrestore(&xhci->lock, flags);
 810
 811         ret = xhci_halt(xhci);
 812
 813         spin_lock_irqsave(&xhci->lock, flags);
 814         if (ret < 0) {
 815                 /* This is bad; the host is not responding to commands and it's
 816                  * not allowing itself to be halted.  At least interrupts are
 817                  * disabled. If we call usb_hc_died(), it will attempt to
 818                  * disconnect all device drivers under this host.  Those
 819                  * disconnect() methods will wait for all URBs to be unlinked,
 820                  * so we must complete them.
 821                  */
 822                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 823                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 824                 /* We could turn all TDs on the rings to no-ops.  This won't
 825                  * help if the host has cached part of the ring, and is slow if
 826                  * we want to preserve the cycle bit.  Skip it and hope the host
 827                  * doesn't touch the memory.
 828                  */
 829         }
 830         for (i = 0; i < MAX_HC_SLOTS; i++) {
 831                 if (!xhci->devs[i])
 832                         continue;
 833                 for (j = 0; j < 31; j++) {
 834                         temp_ep = &xhci->devs[i]->eps[j];
 835                         ring = temp_ep->ring;
 836                         if (!ring)
 837                                 continue;
 838                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 839                                         "ep index %u\n", i, j);
 840                         while (!list_empty(&ring->td_list)) {
 841                                 cur_td = list_first_entry(&ring->td_list,
 842                                                 struct xhci_td,
 843                                                 td_list);
 844                                 list_del_init(&cur_td->td_list);
 845                                 if (!list_empty(&cur_td->cancelled_td_list))
 846                                         list_del_init(&cur_td->cancelled_td_list);
 847                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 848                                                 -ESHUTDOWN, "killed");
 849                         }
 850                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 851                                 cur_td = list_first_entry(
 852                                                 &temp_ep->cancelled_td_list,
 853                                                 struct xhci_td,
 854                                                 cancelled_td_list);
 855                                 list_del_init(&cur_td->cancelled_td_list);
 856                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 857                                                 -ESHUTDOWN, "killed");
 858                         }
 859                 }
 860         }
 861         spin_unlock_irqrestore(&xhci->lock, flags);
 862         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 863         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 864         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 865 }
 866
 867
 868 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 869                 struct xhci_virt_device *dev,
 870                 struct xhci_ring *ep_ring,
 871                 unsigned int ep_index)
 872 {
 873         union xhci_trb *dequeue_temp;
 874         int num_trbs_free_temp;
 875         bool revert = false;
 876
 877         num_trbs_free_temp = ep_ring->num_trbs_free;
 878         dequeue_temp = ep_ring->dequeue;
 879
 880         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
 881                 /* We have more usable TRBs */
 882                 ep_ring->num_trbs_free++;
 883                 ep_ring->dequeue++;
 884                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
 885                                 ep_ring->dequeue)) {
 886                         if (ep_ring->dequeue ==
 887                                         dev->eps[ep_index].queued_deq_ptr)
 888                                 break;
 889                         ep_ring->deq_seg = ep_ring->deq_seg->next;
 890                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
 891                 }
 892                 if (ep_ring->dequeue == dequeue_temp) {
 893                         revert = true;
 894                         break;
 895                 }
 896         }
 897
 898         if (revert) {
 899                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
 900                 ep_ring->num_trbs_free = num_trbs_free_temp;
 901         }
 902 }
 903
 904 /*
 905  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 906  * we need to clear the set deq pending flag in the endpoint ring state, so that
 907  * the TD queueing code can ring the doorbell again.  We also need to ring the
 908  * endpoint doorbell to restart the ring, but only if there aren't more
 909  * cancellations pending.
 910  */
 911 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 912                 struct xhci_event_cmd *event,
 913                 union xhci_trb *trb)
 914 {
 915         unsigned int slot_id;
 916         unsigned int ep_index;
 917         unsigned int stream_id;
 918         struct xhci_ring *ep_ring;
 919         struct xhci_virt_device *dev;
 920         struct xhci_ep_ctx *ep_ctx;
 921         struct xhci_slot_ctx *slot_ctx;
 922
 923         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 924         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 925         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
 926         dev = xhci->devs[slot_id];
 927
 928         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 929         if (!ep_ring) {
 930                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 931                                 "freed stream ID %u\n",
 932                                 stream_id);
 933                 /* XXX: Harmless??? */
 934                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 935                 return;
 936         }
 937
 938         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 939         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 940
 941         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
 942                 unsigned int ep_state;
 943                 unsigned int slot_state;
 944
 945                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
 946                 case COMP_TRB_ERR:
 947                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 948                                         "of stream ID configuration\n");
 949                         break;
 950                 case COMP_CTX_STATE:
 951                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 952                                         "to incorrect slot or ep state.\n");
 953                         ep_state = le32_to_cpu(ep_ctx->ep_info);
 954                         ep_state &= EP_STATE_MASK;
 955                         slot_state = le32_to_cpu(slot_ctx->dev_state);
 956                         slot_state = GET_SLOT_STATE(slot_state);
 957                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 958                                         slot_state, ep_state);
 959                         break;
 960                 case COMP_EBADSLT:
 961                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 962                                         "slot %u was not enabled.\n", slot_id);
 963                         break;
 964                 default:
 965                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 966                                         "completion code of %u.\n",
 967                                   GET_COMP_CODE(le32_to_cpu(event->status)));
 968                         break;
 969                 }
 970                 /* OK what do we do now?  The endpoint state is hosed, and we
 971                  * should never get to this point if the synchronization between
 972                  * queueing, and endpoint state are correct.  This might happen
 973                  * if the device gets disconnected after we've finished
 974                  * cancelling URBs, which might not be an error...
 975                  */
 976         } else {
 977                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 978                          le64_to_cpu(ep_ctx->deq));
 979                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 980                                          dev->eps[ep_index].queued_deq_ptr) ==
 981                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
 982                         /* Update the ring's dequeue segment and dequeue pointer
 983                          * to reflect the new position.
 984                          */
 985                         update_ring_for_set_deq_completion(xhci, dev,
 986                                 ep_ring, ep_index);
 987                 } else {
 988                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 989                                         "Ptr command & xHCI internal state.\n");
 990                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 991                                         dev->eps[ep_index].queued_deq_seg,
 992                                         dev->eps[ep_index].queued_deq_ptr);
 993                 }
 994         }
 995
 996         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 997         dev->eps[ep_index].queued_deq_seg = NULL;
 998         dev->eps[ep_index].queued_deq_ptr = NULL;
 999         /* Restart any rings with pending URBs */
1000         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1001 }
1002
1003 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1004                 struct xhci_event_cmd *event,
1005                 union xhci_trb *trb)
1006 {
1007         int slot_id;
1008         unsigned int ep_index;
1009
1010         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1011         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1012         /* This command will only fail if the endpoint wasn't halted,
1013          * but we don't care.
1014          */
1015         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1016                  GET_COMP_CODE(le32_to_cpu(event->status)));
1017
1018         /* HW with the reset endpoint quirk needs to have a configure endpoint
1019          * command complete before the endpoint can be used.  Queue that here
1020          * because the HW can't handle two commands being queued in a row.
1021          */
1022         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1023                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1024                 xhci_queue_configure_endpoint(xhci,
1025                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1026                                 false);
1027                 xhci_ring_cmd_db(xhci);
1028         } else {
1029                 /* Clear our internal halted state and restart the ring(s) */
1030                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1031                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1032         }
1033 }
1034
1035 /* Check to see if a command in the device's command queue matches this one.
1036  * Signal the completion or free the command, and return 1.  Return 0 if the
1037  * completed command isn't at the head of the command list.
1038  */
1039 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1040                 struct xhci_virt_device *virt_dev,
1041                 struct xhci_event_cmd *event)
1042 {
1043         struct xhci_command *command;
1044
1045         if (list_empty(&virt_dev->cmd_list))
1046                 return 0;
1047
1048         command = list_entry(virt_dev->cmd_list.next,
1049                         struct xhci_command, cmd_list);
1050         if (xhci->cmd_ring->dequeue != command->command_trb)
1051                 return 0;
1052
1053         command->status = GET_COMP_CODE(le32_to_cpu(event->status));
1054         list_del(&command->cmd_list);
1055         if (command->completion)
1056                 complete(command->completion);
1057         else
1058                 xhci_free_command(xhci, command);
1059         return 1;
1060 }
1061
1062 static void handle_cmd_completion(struct xhci_hcd *xhci,
1063                 struct xhci_event_cmd *event)
1064 {
1065         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1066         u64 cmd_dma;
1067         dma_addr_t cmd_dequeue_dma;
1068         struct xhci_input_control_ctx *ctrl_ctx;
1069         struct xhci_virt_device *virt_dev;
1070         unsigned int ep_index;
1071         struct xhci_ring *ep_ring;
1072         unsigned int ep_state;
1073
1074         cmd_dma = le64_to_cpu(event->cmd_trb);
1075         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1076                         xhci->cmd_ring->dequeue);
1077         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1078         if (cmd_dequeue_dma == 0) {
1079                 xhci->error_bitmask |= 1 << 4;
1080                 return;
1081         }
1082         /* Does the DMA address match our internal dequeue pointer address? */
1083         if (cmd_dma != (u64) cmd_dequeue_dma) {
1084                 xhci->error_bitmask |= 1 << 5;
1085                 return;
1086         }
1087         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1088                 & TRB_TYPE_BITMASK) {
1089         case TRB_TYPE(TRB_ENABLE_SLOT):
1090                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1091                         xhci->slot_id = slot_id;
1092                 else
1093                         xhci->slot_id = 0;
1094                 complete(&xhci->addr_dev);
1095                 break;
1096         case TRB_TYPE(TRB_DISABLE_SLOT):
1097                 if (xhci->devs[slot_id]) {
1098                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1099                                 /* Delete default control endpoint resources */
1100                                 xhci_free_device_endpoint_resources(xhci,
1101                                                 xhci->devs[slot_id], true);
1102                         xhci_free_virt_device(xhci, slot_id);
1103                 }
1104                 break;
1105         case TRB_TYPE(TRB_CONFIG_EP):
1106                 virt_dev = xhci->devs[slot_id];
1107                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1108                         break;
1109                 /*
1110                  * Configure endpoint commands can come from the USB core
1111                  * configuration or alt setting changes, or because the HW
1112                  * needed an extra configure endpoint command after a reset
1113                  * endpoint command or streams were being configured.
1114                  * If the command was for a halted endpoint, the xHCI driver
1115                  * is not waiting on the configure endpoint command.
1116                  */
1117                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1118                                 virt_dev->in_ctx);
1119                 /* Input ctx add_flags are the endpoint index plus one */
1120                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1121                 /* A usb_set_interface() call directly after clearing a halted
1122                  * condition may race on this quirky hardware.  Not worth
1123                  * worrying about, since this is prototype hardware.  Not sure
1124                  * if this will work for streams, but streams support was
1125                  * untested on this prototype.
1126                  */
1127                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1128                                 ep_index != (unsigned int) -1 &&
1129                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1130                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1131                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1132                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1133                         if (!(ep_state & EP_HALTED))
1134                                 goto bandwidth_change;
1135                         xhci_dbg(xhci, "Completed config ep cmd - "
1136                                         "last ep index = %d, state = %d\n",
1137                                         ep_index, ep_state);
1138                         /* Clear internal halted state and restart ring(s) */
1139                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1140                                 ~EP_HALTED;
1141                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1142                         break;
1143                 }
1144 bandwidth_change:
1145                 xhci_dbg(xhci, "Completed config ep cmd\n");
1146                 xhci->devs[slot_id]->cmd_status =
1147                         GET_COMP_CODE(le32_to_cpu(event->status));
1148                 complete(&xhci->devs[slot_id]->cmd_completion);
1149                 break;
1150         case TRB_TYPE(TRB_EVAL_CONTEXT):
1151                 virt_dev = xhci->devs[slot_id];
1152                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1153                         break;
1154                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1155                 complete(&xhci->devs[slot_id]->cmd_completion);
1156                 break;
1157         case TRB_TYPE(TRB_ADDR_DEV):
1158                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1159                 complete(&xhci->addr_dev);
1160                 break;
1161         case TRB_TYPE(TRB_STOP_RING):
1162                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1163                 break;
1164         case TRB_TYPE(TRB_SET_DEQ):
1165                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1166                 break;
1167         case TRB_TYPE(TRB_CMD_NOOP):
1168                 break;
1169         case TRB_TYPE(TRB_RESET_EP):
1170                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1171                 break;
1172         case TRB_TYPE(TRB_RESET_DEV):
1173                 xhci_dbg(xhci, "Completed reset device command.\n");
1174                 slot_id = TRB_TO_SLOT_ID(
1175                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1176                 virt_dev = xhci->devs[slot_id];
1177                 if (virt_dev)
1178                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1179                 else
1180                         xhci_warn(xhci, "Reset device command completion "
1181                                         "for disabled slot %u\n", slot_id);
1182                 break;
1183         case TRB_TYPE(TRB_NEC_GET_FW):
1184                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1185                         xhci->error_bitmask |= 1 << 6;
1186                         break;
1187                 }
1188                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1189                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1190                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1191                 break;
1192         default:
1193                 /* Skip over unknown commands on the event ring */
1194                 xhci->error_bitmask |= 1 << 6;
1195                 break;
1196         }
1197         inc_deq(xhci, xhci->cmd_ring);
1198 }
1199
1200 static void handle_vendor_event(struct xhci_hcd *xhci,
1201                 union xhci_trb *event)
1202 {
1203         u32 trb_type;
1204
1205         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1206         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1207         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1208                 handle_cmd_completion(xhci, &event->event_cmd);
1209 }
1210
1211 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1212  * port registers -- USB 3.0 and USB 2.0).
1213  *
1214  * Returns a zero-based port number, which is suitable for indexing into each of
1215  * the split roothubs' port arrays and bus state arrays.
1216  * Add one to it in order to call xhci_find_slot_id_by_port.
1217  */
1218 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1219                 struct xhci_hcd *xhci, u32 port_id)
1220 {
1221         unsigned int i;
1222         unsigned int num_similar_speed_ports = 0;
1223
1224         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1225          * and usb2_ports are 0-based indexes.  Count the number of similar
1226          * speed ports, up to 1 port before this port.
1227          */
1228         for (i = 0; i < (port_id - 1); i++) {
1229                 u8 port_speed = xhci->port_array[i];
1230
1231                 /*
1232                  * Skip ports that don't have known speeds, or have duplicate
1233                  * Extended Capabilities port speed entries.
1234                  */
1235                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1236                         continue;
1237
1238                 /*
1239                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1240                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1241                  * matches the device speed, it's a similar speed port.
1242                  */
1243                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1244                         num_similar_speed_ports++;
1245         }
1246         return num_similar_speed_ports;
1247 }
1248
1249 static void handle_device_notification(struct xhci_hcd *xhci,
1250                 union xhci_trb *event)
1251 {
1252         u32 slot_id;
1253         struct usb_device *udev;
1254
1255         slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1256         if (!xhci->devs[slot_id]) {
1257                 xhci_warn(xhci, "Device Notification event for "
1258                                 "unused slot %u\n", slot_id);
1259                 return;
1260         }
1261
1262         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1263                         slot_id);
1264         udev = xhci->devs[slot_id]->udev;
1265         if (udev && udev->parent)
1266                 usb_wakeup_notification(udev->parent, udev->portnum);
1267 }
1268
1269 static void handle_port_status(struct xhci_hcd *xhci,
1270                 union xhci_trb *event)
1271 {
1272         struct usb_hcd *hcd;
1273         u32 port_id;
1274         u32 temp, temp1;
1275         int max_ports;
1276         int slot_id;
1277         unsigned int faked_port_index;
1278         u8 major_revision;
1279         struct xhci_bus_state *bus_state;
1280         __le32 __iomem **port_array;
1281         bool bogus_port_status = false;
1282
1283         /* Port status change events always have a successful completion code */
1284         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1285                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1286                 xhci->error_bitmask |= 1 << 8;
1287         }
1288         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1289         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1290
1291         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1292         if ((port_id <= 0) || (port_id > max_ports)) {
1293                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1294                 bogus_port_status = true;
1295                 goto cleanup;
1296         }
1297
1298         /* Figure out which usb_hcd this port is attached to:
1299          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1300          */
1301         major_revision = xhci->port_array[port_id - 1];
1302         if (major_revision == 0) {
1303                 xhci_warn(xhci, "Event for port %u not in "
1304                                 "Extended Capabilities, ignoring.\n",
1305                                 port_id);
1306                 bogus_port_status = true;
1307                 goto cleanup;
1308         }
1309         if (major_revision == DUPLICATE_ENTRY) {
1310                 xhci_warn(xhci, "Event for port %u duplicated in"
1311                                 "Extended Capabilities, ignoring.\n",
1312                                 port_id);
1313                 bogus_port_status = true;
1314                 goto cleanup;
1315         }
1316
1317         /*
1318          * Hardware port IDs reported by a Port Status Change Event include USB
1319          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1320          * resume event, but we first need to translate the hardware port ID
1321          * into the index into the ports on the correct split roothub, and the
1322          * correct bus_state structure.
1323          */
1324         /* Find the right roothub. */
1325         hcd = xhci_to_hcd(xhci);
1326         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1327                 hcd = xhci->shared_hcd;
1328         bus_state = &xhci->bus_state[hcd_index(hcd)];
1329         if (hcd->speed == HCD_USB3)
1330                 port_array = xhci->usb3_ports;
1331         else
1332                 port_array = xhci->usb2_ports;
1333         /* Find the faked port hub number */
1334         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1335                         port_id);
1336
1337         temp = xhci_readl(xhci, port_array[faked_port_index]);
1338         if (hcd->state == HC_STATE_SUSPENDED) {
1339                 xhci_dbg(xhci, "resume root hub\n");
1340                 usb_hcd_resume_root_hub(hcd);
1341         }
1342
1343         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1344                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1345
1346                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1347                 if (!(temp1 & CMD_RUN)) {
1348                         xhci_warn(xhci, "xHC is not running.\n");
1349                         goto cleanup;
1350                 }
1351
1352                 if (DEV_SUPERSPEED(temp)) {
1353                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1354                         /* Set a flag to say the port signaled remote wakeup,
1355                          * so we can tell the difference between the end of
1356                          * device and host initiated resume.
1357                          */
1358                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1359                         xhci_test_and_clear_bit(xhci, port_array,
1360                                         faked_port_index, PORT_PLC);
1361                         xhci_set_link_state(xhci, port_array, faked_port_index,
1362                                                 XDEV_U0);
1363                         /* Need to wait until the next link state change
1364                          * indicates the device is actually in U0.
1365                          */
1366                         bogus_port_status = true;
1367                         goto cleanup;
1368                 } else {
1369                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1370                         bus_state->resume_done[faked_port_index] = jiffies +
1371                                 msecs_to_jiffies(20);
1372                         mod_timer(&hcd->rh_timer,
1373                                   bus_state->resume_done[faked_port_index]);
1374                         /* Do the rest in GetPortStatus */
1375                 }
1376         }
1377
1378         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1379                         DEV_SUPERSPEED(temp)) {
1380                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1381                 /* We've just brought the device into U0 through either the
1382                  * Resume state after a device remote wakeup, or through the
1383                  * U3Exit state after a host-initiated resume.  If it's a device
1384                  * initiated remote wake, don't pass up the link state change,
1385                  * so the roothub behavior is consistent with external
1386                  * USB 3.0 hub behavior.
1387                  */
1388                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1389                                 faked_port_index + 1);
1390                 if (slot_id && xhci->devs[slot_id])
1391                         xhci_ring_device(xhci, slot_id);
1392                 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) {
1393                         bus_state->port_remote_wakeup &=
1394                                 ~(1 << faked_port_index);
1395                         xhci_test_and_clear_bit(xhci, port_array,
1396                                         faked_port_index, PORT_PLC);
1397                         usb_wakeup_notification(hcd->self.root_hub,
1398                                         faked_port_index + 1);
1399                         bogus_port_status = true;
1400                         goto cleanup;
1401                 }
1402         }
1403
1404         if (hcd->speed != HCD_USB3)
1405                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1406                                         PORT_PLC);
1407
1408 cleanup:
1409         /* Update event ring dequeue pointer before dropping the lock */
1410         inc_deq(xhci, xhci->event_ring);
1411
1412         /* Don't make the USB core poll the roothub if we got a bad port status
1413          * change event.  Besides, at that point we can't tell which roothub
1414          * (USB 2.0 or USB 3.0) to kick.
1415          */
1416         if (bogus_port_status)
1417                 return;
1418
1419         spin_unlock(&xhci->lock);
1420         /* Pass this up to the core */
1421         usb_hcd_poll_rh_status(hcd);
1422         spin_lock(&xhci->lock);
1423 }
1424
1425 /*
1426  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1427  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1428  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1429  * returns 0.
1430  */
1431 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1432                 union xhci_trb  *start_trb,
1433                 union xhci_trb  *end_trb,
1434                 dma_addr_t      suspect_dma)
1435 {
1436         dma_addr_t start_dma;
1437         dma_addr_t end_seg_dma;
1438         dma_addr_t end_trb_dma;
1439         struct xhci_segment *cur_seg;
1440
1441         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1442         cur_seg = start_seg;
1443
1444         do {
1445                 if (start_dma == 0)
1446                         return NULL;
1447                 /* We may get an event for a Link TRB in the middle of a TD */
1448                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1449                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1450                 /* If the end TRB isn't in this segment, this is set to 0 */
1451                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1452
1453                 if (end_trb_dma > 0) {
1454                         /* The end TRB is in this segment, so suspect should be here */
1455                         if (start_dma <= end_trb_dma) {
1456                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1457                                         return cur_seg;
1458                         } else {
1459                                 /* Case for one segment with
1460                                  * a TD wrapped around to the top
1461                                  */
1462                                 if ((suspect_dma >= start_dma &&
1463                                                         suspect_dma <= end_seg_dma) ||
1464                                                 (suspect_dma >= cur_seg->dma &&
1465                                                  suspect_dma <= end_trb_dma))
1466                                         return cur_seg;
1467                         }
1468                         return NULL;
1469                 } else {
1470                         /* Might still be somewhere in this segment */
1471                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1472                                 return cur_seg;
1473                 }
1474                 cur_seg = cur_seg->next;
1475                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1476         } while (cur_seg != start_seg);
1477
1478         return NULL;
1479 }
1480
1481 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1482                 unsigned int slot_id, unsigned int ep_index,
1483                 unsigned int stream_id,
1484                 struct xhci_td *td, union xhci_trb *event_trb)
1485 {
1486         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1487         ep->ep_state |= EP_HALTED;
1488         ep->stopped_td = td;
1489         ep->stopped_trb = event_trb;
1490         ep->stopped_stream = stream_id;
1491
1492         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1493         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1494
1495         ep->stopped_td = NULL;
1496         ep->stopped_trb = NULL;
1497         ep->stopped_stream = 0;
1498
1499         xhci_ring_cmd_db(xhci);
1500 }
1501
1502 /* Check if an error has halted the endpoint ring.  The class driver will
1503  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1504  * However, a babble and other errors also halt the endpoint ring, and the class
1505  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1506  * Ring Dequeue Pointer command manually.
1507  */
1508 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1509                 struct xhci_ep_ctx *ep_ctx,
1510                 unsigned int trb_comp_code)
1511 {
1512         /* TRB completion codes that may require a manual halt cleanup */
1513         if (trb_comp_code == COMP_TX_ERR ||
1514                         trb_comp_code == COMP_BABBLE ||
1515                         trb_comp_code == COMP_SPLIT_ERR)
1516                 /* The 0.96 spec says a babbling control endpoint
1517                  * is not halted. The 0.96 spec says it is.  Some HW
1518                  * claims to be 0.95 compliant, but it halts the control
1519                  * endpoint anyway.  Check if a babble halted the
1520                  * endpoint.
1521                  */
1522                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1523                     cpu_to_le32(EP_STATE_HALTED))
1524                         return 1;
1525
1526         return 0;
1527 }
1528
1529 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1530 {
1531         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1532                 /* Vendor defined "informational" completion code,
1533                  * treat as not-an-error.
1534                  */
1535                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1536                                 trb_comp_code);
1537                 xhci_dbg(xhci, "Treating code as success.\n");
1538                 return 1;
1539         }
1540         return 0;
1541 }
1542
1543 /*
1544  * Finish the td processing, remove the td from td list;
1545  * Return 1 if the urb can be given back.
1546  */
1547 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1548         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1549         struct xhci_virt_ep *ep, int *status, bool skip)
1550 {
1551         struct xhci_virt_device *xdev;
1552         struct xhci_ring *ep_ring;
1553         unsigned int slot_id;
1554         int ep_index;
1555         struct urb *urb = NULL;
1556         struct xhci_ep_ctx *ep_ctx;
1557         int ret = 0;
1558         struct urb_priv *urb_priv;
1559         u32 trb_comp_code;
1560
1561         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1562         xdev = xhci->devs[slot_id];
1563         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1564         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1565         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1566         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1567
1568         if (skip)
1569                 goto td_cleanup;
1570
1571         if (trb_comp_code == COMP_STOP_INVAL ||
1572                         trb_comp_code == COMP_STOP) {
1573                 /* The Endpoint Stop Command completion will take care of any
1574                  * stopped TDs.  A stopped TD may be restarted, so don't update
1575                  * the ring dequeue pointer or take this TD off any lists yet.
1576                  */
1577                 ep->stopped_td = td;
1578                 ep->stopped_trb = event_trb;
1579                 return 0;
1580         } else {
1581                 if (trb_comp_code == COMP_STALL) {
1582                         /* The transfer is completed from the driver's
1583                          * perspective, but we need to issue a set dequeue
1584                          * command for this stalled endpoint to move the dequeue
1585                          * pointer past the TD.  We can't do that here because
1586                          * the halt condition must be cleared first.  Let the
1587                          * USB class driver clear the stall later.
1588                          */
1589                         ep->stopped_td = td;
1590                         ep->stopped_trb = event_trb;
1591                         ep->stopped_stream = ep_ring->stream_id;
1592                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1593                                         ep_ctx, trb_comp_code)) {
1594                         /* Other types of errors halt the endpoint, but the
1595                          * class driver doesn't call usb_reset_endpoint() unless
1596                          * the error is -EPIPE.  Clear the halted status in the
1597                          * xHCI hardware manually.
1598                          */
1599                         xhci_cleanup_halted_endpoint(xhci,
1600                                         slot_id, ep_index, ep_ring->stream_id,
1601                                         td, event_trb);
1602                 } else {
1603                         /* Update ring dequeue pointer */
1604                         while (ep_ring->dequeue != td->last_trb)
1605                                 inc_deq(xhci, ep_ring);
1606                         inc_deq(xhci, ep_ring);
1607                 }
1608
1609 td_cleanup:
1610                 /* Clean up the endpoint's TD list */
1611                 urb = td->urb;
1612                 urb_priv = urb->hcpriv;
1613
1614                 /* Do one last check of the actual transfer length.
1615                  * If the host controller said we transferred more data than
1616                  * the buffer length, urb->actual_length will be a very big
1617                  * number (since it's unsigned).  Play it safe and say we didn't
1618                  * transfer anything.
1619                  */
1620                 if (urb->actual_length > urb->transfer_buffer_length) {
1621                         xhci_warn(xhci, "URB transfer length is wrong, "
1622                                         "xHC issue? req. len = %u, "
1623                                         "act. len = %u\n",
1624                                         urb->transfer_buffer_length,
1625                                         urb->actual_length);
1626                         urb->actual_length = 0;
1627                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1628                                 *status = -EREMOTEIO;
1629                         else
1630                                 *status = 0;
1631                 }
1632                 list_del_init(&td->td_list);
1633                 /* Was this TD slated to be cancelled but completed anyway? */
1634                 if (!list_empty(&td->cancelled_td_list))
1635                         list_del_init(&td->cancelled_td_list);
1636
1637                 urb_priv->td_cnt++;
1638                 /* Giveback the urb when all the tds are completed */
1639                 if (urb_priv->td_cnt == urb_priv->length) {
1640                         ret = 1;
1641                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1642                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1643                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1644                                         == 0) {
1645                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1646                                                 usb_amd_quirk_pll_enable();
1647                                 }
1648                         }
1649                 }
1650         }
1651
1652         return ret;
1653 }
1654
1655 /*
1656  * Process control tds, update urb status and actual_length.
1657  */
1658 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1659         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1660         struct xhci_virt_ep *ep, int *status)
1661 {
1662         struct xhci_virt_device *xdev;
1663         struct xhci_ring *ep_ring;
1664         unsigned int slot_id;
1665         int ep_index;
1666         struct xhci_ep_ctx *ep_ctx;
1667         u32 trb_comp_code;
1668
1669         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1670         xdev = xhci->devs[slot_id];
1671         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1672         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1673         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1674         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1675
1676         switch (trb_comp_code) {
1677         case COMP_SUCCESS:
1678                 if (event_trb == ep_ring->dequeue) {
1679                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1680                                         "without IOC set??\n");
1681                         *status = -ESHUTDOWN;
1682                 } else if (event_trb != td->last_trb) {
1683                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1684                                         "without IOC set??\n");
1685                         *status = -ESHUTDOWN;
1686                 } else {
1687                         *status = 0;
1688                 }
1689                 break;
1690         case COMP_SHORT_TX:
1691                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1692                         *status = -EREMOTEIO;
1693                 else
1694                         *status = 0;
1695                 break;
1696         case COMP_STOP_INVAL:
1697         case COMP_STOP:
1698                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1699         default:
1700                 if (!xhci_requires_manual_halt_cleanup(xhci,
1701                                         ep_ctx, trb_comp_code))
1702                         break;
1703                 xhci_dbg(xhci, "TRB error code %u, "
1704                                 "halted endpoint index = %u\n",
1705                                 trb_comp_code, ep_index);
1706                 /* else fall through */
1707         case COMP_STALL:
1708                 /* Did we transfer part of the data (middle) phase? */
1709                 if (event_trb != ep_ring->dequeue &&
1710                                 event_trb != td->last_trb)
1711                         td->urb->actual_length =
1712                                 td->urb->transfer_buffer_length
1713                                 - TRB_LEN(le32_to_cpu(event->transfer_len));
1714                 else
1715                         td->urb->actual_length = 0;
1716
1717                 xhci_cleanup_halted_endpoint(xhci,
1718                         slot_id, ep_index, 0, td, event_trb);
1719                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1720         }
1721         /*
1722          * Did we transfer any data, despite the errors that might have
1723          * happened?  I.e. did we get past the setup stage?
1724          */
1725         if (event_trb != ep_ring->dequeue) {
1726                 /* The event was for the status stage */
1727                 if (event_trb == td->last_trb) {
1728                         if (td->urb->actual_length != 0) {
1729                                 /* Don't overwrite a previously set error code
1730                                  */
1731                                 if ((*status == -EINPROGRESS || *status == 0) &&
1732                                                 (td->urb->transfer_flags
1733                                                  & URB_SHORT_NOT_OK))
1734                                         /* Did we already see a short data
1735                                          * stage? */
1736                                         *status = -EREMOTEIO;
1737                         } else {
1738                                 td->urb->actual_length =
1739                                         td->urb->transfer_buffer_length;
1740                         }
1741                 } else {
1742                 /* Maybe the event was for the data stage? */
1743                         td->urb->actual_length =
1744                                 td->urb->transfer_buffer_length -
1745                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1746                         xhci_dbg(xhci, "Waiting for status "
1747                                         "stage event\n");
1748                         return 0;
1749                 }
1750         }
1751
1752         return finish_td(xhci, td, event_trb, event, ep, status, false);
1753 }
1754
1755 /*
1756  * Process isochronous tds, update urb packet status and actual_length.
1757  */
1758 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1759         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1760         struct xhci_virt_ep *ep, int *status)
1761 {
1762         struct xhci_ring *ep_ring;
1763         struct urb_priv *urb_priv;
1764         int idx;
1765         int len = 0;
1766         union xhci_trb *cur_trb;
1767         struct xhci_segment *cur_seg;
1768         struct usb_iso_packet_descriptor *frame;
1769         u32 trb_comp_code;
1770         bool skip_td = false;
1771
1772         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1773         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1774         urb_priv = td->urb->hcpriv;
1775         idx = urb_priv->td_cnt;
1776         frame = &td->urb->iso_frame_desc[idx];
1777
1778         /* handle completion code */
1779         switch (trb_comp_code) {
1780         case COMP_SUCCESS:
1781                 frame->status = 0;
1782                 break;
1783         case COMP_SHORT_TX:
1784                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1785                                 -EREMOTEIO : 0;
1786                 break;
1787         case COMP_BW_OVER:
1788                 frame->status = -ECOMM;
1789                 skip_td = true;
1790                 break;
1791         case COMP_BUFF_OVER:
1792         case COMP_BABBLE:
1793                 frame->status = -EOVERFLOW;
1794                 skip_td = true;
1795                 break;
1796         case COMP_DEV_ERR:
1797         case COMP_STALL:
1798                 frame->status = -EPROTO;
1799                 skip_td = true;
1800                 break;
1801         case COMP_STOP:
1802         case COMP_STOP_INVAL:
1803                 break;
1804         default:
1805                 frame->status = -1;
1806                 break;
1807         }
1808
1809         if (trb_comp_code == COMP_SUCCESS || skip_td) {
1810                 frame->actual_length = frame->length;
1811                 td->urb->actual_length += frame->length;
1812         } else {
1813                 for (cur_trb = ep_ring->dequeue,
1814                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1815                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1816                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1817                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1818                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1819                 }
1820                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1821                         TRB_LEN(le32_to_cpu(event->transfer_len));
1822
1823                 if (trb_comp_code != COMP_STOP_INVAL) {
1824                         frame->actual_length = len;
1825                         td->urb->actual_length += len;
1826                 }
1827         }
1828
1829         return finish_td(xhci, td, event_trb, event, ep, status, false);
1830 }
1831
1832 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1833                         struct xhci_transfer_event *event,
1834                         struct xhci_virt_ep *ep, int *status)
1835 {
1836         struct xhci_ring *ep_ring;
1837         struct urb_priv *urb_priv;
1838         struct usb_iso_packet_descriptor *frame;
1839         int idx;
1840
1841         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1842         urb_priv = td->urb->hcpriv;
1843         idx = urb_priv->td_cnt;
1844         frame = &td->urb->iso_frame_desc[idx];
1845
1846         /* The transfer is partly done. */
1847         frame->status = -EXDEV;
1848
1849         /* calc actual length */
1850         frame->actual_length = 0;
1851
1852         /* Update ring dequeue pointer */
1853         while (ep_ring->dequeue != td->last_trb)
1854                 inc_deq(xhci, ep_ring);
1855         inc_deq(xhci, ep_ring);
1856
1857         return finish_td(xhci, td, NULL, event, ep, status, true);
1858 }
1859
1860 /*
1861  * Process bulk and interrupt tds, update urb status and actual_length.
1862  */
1863 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1864         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1865         struct xhci_virt_ep *ep, int *status)
1866 {
1867         struct xhci_ring *ep_ring;
1868         union xhci_trb *cur_trb;
1869         struct xhci_segment *cur_seg;
1870         u32 trb_comp_code;
1871
1872         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1873         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1874
1875         switch (trb_comp_code) {
1876         case COMP_SUCCESS:
1877                 /* Double check that the HW transferred everything. */
1878                 if (event_trb != td->last_trb) {
1879                         xhci_warn(xhci, "WARN Successful completion "
1880                                         "on short TX\n");
1881                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1882                                 *status = -EREMOTEIO;
1883                         else
1884                                 *status = 0;
1885                 } else {
1886                         *status = 0;
1887                 }
1888                 break;
1889         case COMP_SHORT_TX:
1890                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1891                         *status = -EREMOTEIO;
1892                 else
1893                         *status = 0;
1894                 break;
1895         default:
1896                 /* Others already handled above */
1897                 break;
1898         }
1899         if (trb_comp_code == COMP_SHORT_TX)
1900                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1901                                 "%d bytes untransferred\n",
1902                                 td->urb->ep->desc.bEndpointAddress,
1903                                 td->urb->transfer_buffer_length,
1904                                 TRB_LEN(le32_to_cpu(event->transfer_len)));
1905         /* Fast path - was this the last TRB in the TD for this URB? */
1906         if (event_trb == td->last_trb) {
1907                 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
1908                         td->urb->actual_length =
1909                                 td->urb->transfer_buffer_length -
1910                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1911                         if (td->urb->transfer_buffer_length <
1912                                         td->urb->actual_length) {
1913                                 xhci_warn(xhci, "HC gave bad length "
1914                                                 "of %d bytes left\n",
1915                                           TRB_LEN(le32_to_cpu(event->transfer_len)));
1916                                 td->urb->actual_length = 0;
1917                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1918                                         *status = -EREMOTEIO;
1919                                 else
1920                                         *status = 0;
1921                         }
1922                         /* Don't overwrite a previously set error code */
1923                         if (*status == -EINPROGRESS) {
1924                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1925                                         *status = -EREMOTEIO;
1926                                 else
1927                                         *status = 0;
1928                         }
1929                 } else {
1930                         td->urb->actual_length =
1931                                 td->urb->transfer_buffer_length;
1932                         /* Ignore a short packet completion if the
1933                          * untransferred length was zero.
1934                          */
1935                         if (*status == -EREMOTEIO)
1936                                 *status = 0;
1937                 }
1938         } else {
1939                 /* Slow path - walk the list, starting from the dequeue
1940                  * pointer, to get the actual length transferred.
1941                  */
1942                 td->urb->actual_length = 0;
1943                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1944                                 cur_trb != event_trb;
1945                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1946                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1947                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
1948                                 td->urb->actual_length +=
1949                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
1950                 }
1951                 /* If the ring didn't stop on a Link or No-op TRB, add
1952                  * in the actual bytes transferred from the Normal TRB
1953                  */
1954                 if (trb_comp_code != COMP_STOP_INVAL)
1955                         td->urb->actual_length +=
1956                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1957                                 TRB_LEN(le32_to_cpu(event->transfer_len));
1958         }
1959
1960         return finish_td(xhci, td, event_trb, event, ep, status, false);
1961 }
1962
1963 /*
1964  * If this function returns an error condition, it means it got a Transfer
1965  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1966  * At this point, the host controller is probably hosed and should be reset.
1967  */
1968 static int handle_tx_event(struct xhci_hcd *xhci,
1969                 struct xhci_transfer_event *event)
1970 {
1971         struct xhci_virt_device *xdev;
1972         struct xhci_virt_ep *ep;
1973         struct xhci_ring *ep_ring;
1974         unsigned int slot_id;
1975         int ep_index;
1976         struct xhci_td *td = NULL;
1977         dma_addr_t event_dma;
1978         struct xhci_segment *event_seg;
1979         union xhci_trb *event_trb;
1980         struct urb *urb = NULL;
1981         int status = -EINPROGRESS;
1982         struct urb_priv *urb_priv;
1983         struct xhci_ep_ctx *ep_ctx;
1984         struct list_head *tmp;
1985         u32 trb_comp_code;
1986         int ret = 0;
1987         int td_num = 0;
1988
1989         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1990         xdev = xhci->devs[slot_id];
1991         if (!xdev) {
1992                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1993                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
1994                          (unsigned long long) xhci_trb_virt_to_dma(
1995                                  xhci->event_ring->deq_seg,
1996                                  xhci->event_ring->dequeue),
1997                          lower_32_bits(le64_to_cpu(event->buffer)),
1998                          upper_32_bits(le64_to_cpu(event->buffer)),
1999                          le32_to_cpu(event->transfer_len),
2000                          le32_to_cpu(event->flags));
2001                 xhci_dbg(xhci, "Event ring:\n");
2002                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2003                 return -ENODEV;
2004         }
2005
2006         /* Endpoint ID is 1 based, our index is zero based */
2007         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2008         ep = &xdev->eps[ep_index];
2009         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2010         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2011         if (!ep_ring ||
2012             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2013             EP_STATE_DISABLED) {
2014                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2015                                 "or incorrect stream ring\n");
2016                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2017                          (unsigned long long) xhci_trb_virt_to_dma(
2018                                  xhci->event_ring->deq_seg,
2019                                  xhci->event_ring->dequeue),
2020                          lower_32_bits(le64_to_cpu(event->buffer)),
2021                          upper_32_bits(le64_to_cpu(event->buffer)),
2022                          le32_to_cpu(event->transfer_len),
2023                          le32_to_cpu(event->flags));
2024                 xhci_dbg(xhci, "Event ring:\n");
2025                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2026                 return -ENODEV;
2027         }
2028
2029         /* Count current td numbers if ep->skip is set */
2030         if (ep->skip) {
2031                 list_for_each(tmp, &ep_ring->td_list)
2032                         td_num++;
2033         }
2034
2035         event_dma = le64_to_cpu(event->buffer);
2036         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2037         /* Look for common error cases */
2038         switch (trb_comp_code) {
2039         /* Skip codes that require special handling depending on
2040          * transfer type
2041          */
2042         case COMP_SUCCESS:
2043         case COMP_SHORT_TX:
2044                 break;
2045         case COMP_STOP:
2046                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2047                 break;
2048         case COMP_STOP_INVAL:
2049                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2050                 break;
2051         case COMP_STALL:
2052                 xhci_dbg(xhci, "Stalled endpoint\n");
2053                 ep->ep_state |= EP_HALTED;
2054                 status = -EPIPE;
2055                 break;
2056         case COMP_TRB_ERR:
2057                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2058                 status = -EILSEQ;
2059                 break;
2060         case COMP_SPLIT_ERR:
2061         case COMP_TX_ERR:
2062                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2063                 status = -EPROTO;
2064                 break;
2065         case COMP_BABBLE:
2066                 xhci_dbg(xhci, "Babble error on endpoint\n");
2067                 status = -EOVERFLOW;
2068                 break;
2069         case COMP_DB_ERR:
2070                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2071                 status = -ENOSR;
2072                 break;
2073         case COMP_BW_OVER:
2074                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2075                 break;
2076         case COMP_BUFF_OVER:
2077                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2078                 break;
2079         case COMP_UNDERRUN:
2080                 /*
2081                  * When the Isoch ring is empty, the xHC will generate
2082                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2083                  * Underrun Event for OUT Isoch endpoint.
2084                  */
2085                 xhci_dbg(xhci, "underrun event on endpoint\n");
2086                 if (!list_empty(&ep_ring->td_list))
2087                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2088                                         "still with TDs queued?\n",
2089                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2090                                  ep_index);
2091                 goto cleanup;
2092         case COMP_OVERRUN:
2093                 xhci_dbg(xhci, "overrun event on endpoint\n");
2094                 if (!list_empty(&ep_ring->td_list))
2095                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2096                                         "still with TDs queued?\n",
2097                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2098                                  ep_index);
2099                 goto cleanup;
2100         case COMP_DEV_ERR:
2101                 xhci_warn(xhci, "WARN: detect an incompatible device");
2102                 status = -EPROTO;
2103                 break;
2104         case COMP_MISSED_INT:
2105                 /*
2106                  * When encounter missed service error, one or more isoc tds
2107                  * may be missed by xHC.
2108                  * Set skip flag of the ep_ring; Complete the missed tds as
2109                  * short transfer when process the ep_ring next time.
2110                  */
2111                 ep->skip = true;
2112                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2113                 goto cleanup;
2114         default:
2115                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2116                         status = 0;
2117                         break;
2118                 }
2119                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2120                                 "busted\n");
2121                 goto cleanup;
2122         }
2123
2124         do {
2125                 /* This TRB should be in the TD at the head of this ring's
2126                  * TD list.
2127                  */
2128                 if (list_empty(&ep_ring->td_list)) {
2129                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2130                                         "with no TDs queued?\n",
2131                                   TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2132                                   ep_index);
2133                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2134                                  (le32_to_cpu(event->flags) &
2135                                   TRB_TYPE_BITMASK)>>10);
2136                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2137                         if (ep->skip) {
2138                                 ep->skip = false;
2139                                 xhci_dbg(xhci, "td_list is empty while skip "
2140                                                 "flag set. Clear skip flag.\n");
2141                         }
2142                         ret = 0;
2143                         goto cleanup;
2144                 }
2145
2146                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2147                 if (ep->skip && td_num == 0) {
2148                         ep->skip = false;
2149                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2150                                                 "Clear skip flag.\n");
2151                         ret = 0;
2152                         goto cleanup;
2153                 }
2154
2155                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2156                 if (ep->skip)
2157                         td_num--;
2158
2159                 /* Is this a TRB in the currently executing TD? */
2160                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2161                                 td->last_trb, event_dma);
2162
2163                 /*
2164                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2165                  * is not in the current TD pointed by ep_ring->dequeue because
2166                  * that the hardware dequeue pointer still at the previous TRB
2167                  * of the current TD. The previous TRB maybe a Link TD or the
2168                  * last TRB of the previous TD. The command completion handle
2169                  * will take care the rest.
2170                  */
2171                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2172                         ret = 0;
2173                         goto cleanup;
2174                 }
2175
2176                 if (!event_seg) {
2177                         if (!ep->skip ||
2178                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2179                                 /* Some host controllers give a spurious
2180                                  * successful event after a short transfer.
2181                                  * Ignore it.
2182                                  */
2183                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2184                                                 ep_ring->last_td_was_short) {
2185                                         ep_ring->last_td_was_short = false;
2186                                         ret = 0;
2187                                         goto cleanup;
2188                                 }
2189                                 /* HC is busted, give up! */
2190                                 xhci_err(xhci,
2191                                         "ERROR Transfer event TRB DMA ptr not "
2192                                         "part of current TD\n");
2193                                 return -ESHUTDOWN;
2194                         }
2195
2196                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2197                         goto cleanup;
2198                 }
2199                 if (trb_comp_code == COMP_SHORT_TX)
2200                         ep_ring->last_td_was_short = true;
2201                 else
2202                         ep_ring->last_td_was_short = false;
2203
2204                 if (ep->skip) {
2205                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2206                         ep->skip = false;
2207                 }
2208
2209                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2210                                                 sizeof(*event_trb)];
2211                 /*
2212                  * No-op TRB should not trigger interrupts.
2213                  * If event_trb is a no-op TRB, it means the
2214                  * corresponding TD has been cancelled. Just ignore
2215                  * the TD.
2216                  */
2217                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2218                         xhci_dbg(xhci,
2219                                  "event_trb is a no-op TRB. Skip it\n");
2220                         goto cleanup;
2221                 }
2222
2223                 /* Now update the urb's actual_length and give back to
2224                  * the core
2225                  */
2226                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2227                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2228                                                  &status);
2229                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2230                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2231                                                  &status);
2232                 else
2233                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2234                                                  ep, &status);
2235
2236 cleanup:
2237                 /*
2238                  * Do not update event ring dequeue pointer if ep->skip is set.
2239                  * Will roll back to continue process missed tds.
2240                  */
2241                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2242                         inc_deq(xhci, xhci->event_ring);
2243                 }
2244
2245                 if (ret) {
2246                         urb = td->urb;
2247                         urb_priv = urb->hcpriv;
2248                         /* Leave the TD around for the reset endpoint function
2249                          * to use(but only if it's not a control endpoint,
2250                          * since we already queued the Set TR dequeue pointer
2251                          * command for stalled control endpoints).
2252                          */
2253                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2254                                 (trb_comp_code != COMP_STALL &&
2255                                         trb_comp_code != COMP_BABBLE))
2256                                 xhci_urb_free_priv(xhci, urb_priv);
2257
2258                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2259                         if ((urb->actual_length != urb->transfer_buffer_length &&
2260                                                 (urb->transfer_flags &
2261                                                  URB_SHORT_NOT_OK)) ||
2262                                         (status != 0 &&
2263                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2264                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2265                                                 "expected = %x, status = %d\n",
2266                                                 urb, urb->actual_length,
2267                                                 urb->transfer_buffer_length,
2268                                                 status);
2269                         spin_unlock(&xhci->lock);
2270                         /* EHCI, UHCI, and OHCI always unconditionally set the
2271                          * urb->status of an isochronous endpoint to 0.
2272                          */
2273                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2274                                 status = 0;
2275                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2276                         spin_lock(&xhci->lock);
2277                 }
2278
2279         /*
2280          * If ep->skip is set, it means there are missed tds on the
2281          * endpoint ring need to take care of.
2282          * Process them as short transfer until reach the td pointed by
2283          * the event.
2284          */
2285         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2286
2287         return 0;
2288 }
2289
2290 /*
2291  * This function handles all OS-owned events on the event ring.  It may drop
2292  * xhci->lock between event processing (e.g. to pass up port status changes).
2293  * Returns >0 for "possibly more events to process" (caller should call again),
2294  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2295  */
2296 static int xhci_handle_event(struct xhci_hcd *xhci)
2297 {
2298         union xhci_trb *event;
2299         int update_ptrs = 1;
2300         int ret;
2301
2302         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2303                 xhci->error_bitmask |= 1 << 1;
2304                 return 0;
2305         }
2306
2307         event = xhci->event_ring->dequeue;
2308         /* Does the HC or OS own the TRB? */
2309         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2310             xhci->event_ring->cycle_state) {
2311                 xhci->error_bitmask |= 1 << 2;
2312                 return 0;
2313         }
2314
2315         /*
2316          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2317          * speculative reads of the event's flags/data below.
2318          */
2319         rmb();
2320         /* FIXME: Handle more event types. */
2321         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2322         case TRB_TYPE(TRB_COMPLETION):
2323                 handle_cmd_completion(xhci, &event->event_cmd);
2324                 break;
2325         case TRB_TYPE(TRB_PORT_STATUS):
2326                 handle_port_status(xhci, event);
2327                 update_ptrs = 0;
2328                 break;
2329         case TRB_TYPE(TRB_TRANSFER):
2330                 ret = handle_tx_event(xhci, &event->trans_event);
2331                 if (ret < 0)
2332                         xhci->error_bitmask |= 1 << 9;
2333                 else
2334                         update_ptrs = 0;
2335                 break;
2336         case TRB_TYPE(TRB_DEV_NOTE):
2337                 handle_device_notification(xhci, event);
2338                 break;
2339         default:
2340                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2341                     TRB_TYPE(48))
2342                         handle_vendor_event(xhci, event);
2343                 else
2344                         xhci->error_bitmask |= 1 << 3;
2345         }
2346         /* Any of the above functions may drop and re-acquire the lock, so check
2347          * to make sure a watchdog timer didn't mark the host as non-responsive.
2348          */
2349         if (xhci->xhc_state & XHCI_STATE_DYING) {
2350                 xhci_dbg(xhci, "xHCI host dying, returning from "
2351                                 "event handler.\n");
2352                 return 0;
2353         }
2354
2355         if (update_ptrs)
2356                 /* Update SW event ring dequeue pointer */
2357                 inc_deq(xhci, xhci->event_ring);
2358
2359         /* Are there more items on the event ring?  Caller will call us again to
2360          * check.
2361          */
2362         return 1;
2363 }
2364
2365 /*
2366  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2367  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2368  * indicators of an event TRB error, but we check the status *first* to be safe.
2369  */
2370 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2371 {
2372         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2373         u32 status;
2374         union xhci_trb *trb;
2375         u64 temp_64;
2376         union xhci_trb *event_ring_deq;
2377         dma_addr_t deq;
2378
2379         spin_lock(&xhci->lock);
2380         trb = xhci->event_ring->dequeue;
2381         /* Check if the xHC generated the interrupt, or the irq is shared */
2382         status = xhci_readl(xhci, &xhci->op_regs->status);
2383         if (status == 0xffffffff)
2384                 goto hw_died;
2385
2386         if (!(status & STS_EINT)) {
2387                 spin_unlock(&xhci->lock);
2388                 return IRQ_NONE;
2389         }
2390         if (status & STS_FATAL) {
2391                 xhci_warn(xhci, "WARNING: Host System Error\n");
2392                 xhci_halt(xhci);
2393 hw_died:
2394                 spin_unlock(&xhci->lock);
2395                 return -ESHUTDOWN;
2396         }
2397
2398         /*
2399          * Clear the op reg interrupt status first,
2400          * so we can receive interrupts from other MSI-X interrupters.
2401          * Write 1 to clear the interrupt status.
2402          */
2403         status |= STS_EINT;
2404         xhci_writel(xhci, status, &xhci->op_regs->status);
2405         /* FIXME when MSI-X is supported and there are multiple vectors */
2406         /* Clear the MSI-X event interrupt status */
2407
2408         if (hcd->irq) {
2409                 u32 irq_pending;
2410                 /* Acknowledge the PCI interrupt */
2411                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2412                 irq_pending |= 0x3;
2413                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2414         }
2415
2416         if (xhci->xhc_state & XHCI_STATE_DYING) {
2417                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2418                                 "Shouldn't IRQs be disabled?\n");
2419                 /* Clear the event handler busy flag (RW1C);
2420                  * the event ring should be empty.
2421                  */
2422                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2423                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2424                                 &xhci->ir_set->erst_dequeue);
2425                 spin_unlock(&xhci->lock);
2426
2427                 return IRQ_HANDLED;
2428         }
2429
2430         event_ring_deq = xhci->event_ring->dequeue;
2431         /* FIXME this should be a delayed service routine
2432          * that clears the EHB.
2433          */
2434         while (xhci_handle_event(xhci) > 0) {}
2435
2436         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2437         /* If necessary, update the HW's version of the event ring deq ptr. */
2438         if (event_ring_deq != xhci->event_ring->dequeue) {
2439                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2440                                 xhci->event_ring->dequeue);
2441                 if (deq == 0)
2442                         xhci_warn(xhci, "WARN something wrong with SW event "
2443                                         "ring dequeue ptr.\n");
2444                 /* Update HC event ring dequeue pointer */
2445                 temp_64 &= ERST_PTR_MASK;
2446                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2447         }
2448
2449         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2450         temp_64 |= ERST_EHB;
2451         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2452
2453         spin_unlock(&xhci->lock);
2454
2455         return IRQ_HANDLED;
2456 }
2457
2458 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2459 {
2460         return xhci_irq(hcd);
2461 }
2462
2463 /****           Endpoint Ring Operations        ****/
2464
2465 /*
2466  * Generic function for queueing a TRB on a ring.
2467  * The caller must have checked to make sure there's room on the ring.
2468  *
2469  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2470  *                      prepare_transfer()?
2471  */
2472 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2473                 bool more_trbs_coming,
2474                 u32 field1, u32 field2, u32 field3, u32 field4)
2475 {
2476         struct xhci_generic_trb *trb;
2477
2478         trb = &ring->enqueue->generic;
2479         trb->field[0] = cpu_to_le32(field1);
2480         trb->field[1] = cpu_to_le32(field2);
2481         trb->field[2] = cpu_to_le32(field3);
2482         trb->field[3] = cpu_to_le32(field4);
2483         inc_enq(xhci, ring, more_trbs_coming);
2484 }
2485
2486 /*
2487  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2488  * FIXME allocate segments if the ring is full.
2489  */
2490 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2491                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2492 {
2493         unsigned int num_trbs_needed;
2494
2495         /* Make sure the endpoint has been added to xHC schedule */
2496         switch (ep_state) {
2497         case EP_STATE_DISABLED:
2498                 /*
2499                  * USB core changed config/interfaces without notifying us,
2500                  * or hardware is reporting the wrong state.
2501                  */
2502                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2503                 return -ENOENT;
2504         case EP_STATE_ERROR:
2505                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2506                 /* FIXME event handling code for error needs to clear it */
2507                 /* XXX not sure if this should be -ENOENT or not */
2508                 return -EINVAL;
2509         case EP_STATE_HALTED:
2510                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2511         case EP_STATE_STOPPED:
2512         case EP_STATE_RUNNING:
2513                 break;
2514         default:
2515                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2516                 /*
2517                  * FIXME issue Configure Endpoint command to try to get the HC
2518                  * back into a known state.
2519                  */
2520                 return -EINVAL;
2521         }
2522
2523         while (1) {
2524                 if (room_on_ring(xhci, ep_ring, num_trbs))
2525                         break;
2526
2527                 if (ep_ring == xhci->cmd_ring) {
2528                         xhci_err(xhci, "Do not support expand command ring\n");
2529                         return -ENOMEM;
2530                 }
2531
2532                 if (ep_ring->enq_seg == ep_ring->deq_seg &&
2533                                 ep_ring->dequeue > ep_ring->enqueue) {
2534                         xhci_err(xhci, "Can not expand the ring while dequeue "
2535                                 "pointer has not passed the link TRB\n");
2536                         return -ENOMEM;
2537                 }
2538
2539                 xhci_dbg(xhci, "ERROR no room on ep ring, "
2540                                         "try ring expansion\n");
2541                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2542                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2543                                         mem_flags)) {
2544                         xhci_err(xhci, "Ring expansion failed\n");
2545                         return -ENOMEM;
2546                 }
2547         };
2548
2549         if (enqueue_is_link_trb(ep_ring)) {
2550                 struct xhci_ring *ring = ep_ring;
2551                 union xhci_trb *next;
2552
2553                 next = ring->enqueue;
2554
2555                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2556                         /* If we're not dealing with 0.95 hardware or isoc rings
2557                          * on AMD 0.96 host, clear the chain bit.
2558                          */
2559                         if (!xhci_link_trb_quirk(xhci) &&
2560                                         !(ring->type == TYPE_ISOC &&
2561                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
2562                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2563                         else
2564                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2565
2566                         wmb();
2567                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2568
2569                         /* Toggle the cycle bit after the last ring segment. */
2570                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2571                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2572                         }
2573                         ring->enq_seg = ring->enq_seg->next;
2574                         ring->enqueue = ring->enq_seg->trbs;
2575                         next = ring->enqueue;
2576                 }
2577         }
2578
2579         return 0;
2580 }
2581
2582 static int prepare_transfer(struct xhci_hcd *xhci,
2583                 struct xhci_virt_device *xdev,
2584                 unsigned int ep_index,
2585                 unsigned int stream_id,
2586                 unsigned int num_trbs,
2587                 struct urb *urb,
2588                 unsigned int td_index,
2589                 gfp_t mem_flags)
2590 {
2591         int ret;
2592         struct urb_priv *urb_priv;
2593         struct xhci_td  *td;
2594         struct xhci_ring *ep_ring;
2595         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2596
2597         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2598         if (!ep_ring) {
2599                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2600                                 stream_id);
2601                 return -EINVAL;
2602         }
2603
2604         ret = prepare_ring(xhci, ep_ring,
2605                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2606                            num_trbs, mem_flags);
2607         if (ret)
2608                 return ret;
2609
2610         urb_priv = urb->hcpriv;
2611         td = urb_priv->td[td_index];
2612
2613         INIT_LIST_HEAD(&td->td_list);
2614         INIT_LIST_HEAD(&td->cancelled_td_list);
2615
2616         if (td_index == 0) {
2617                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2618                 if (unlikely(ret))
2619                         return ret;
2620         }
2621
2622         td->urb = urb;
2623         /* Add this TD to the tail of the endpoint ring's TD list */
2624         list_add_tail(&td->td_list, &ep_ring->td_list);
2625         td->start_seg = ep_ring->enq_seg;
2626         td->first_trb = ep_ring->enqueue;
2627
2628         urb_priv->td[td_index] = td;
2629
2630         return 0;
2631 }
2632
2633 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2634 {
2635         int num_sgs, num_trbs, running_total, temp, i;
2636         struct scatterlist *sg;
2637
2638         sg = NULL;
2639         num_sgs = urb->num_mapped_sgs;
2640         temp = urb->transfer_buffer_length;
2641
2642         num_trbs = 0;
2643         for_each_sg(urb->sg, sg, num_sgs, i) {
2644                 unsigned int len = sg_dma_len(sg);
2645
2646                 /* Scatter gather list entries may cross 64KB boundaries */
2647                 running_total = TRB_MAX_BUFF_SIZE -
2648                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2649                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2650                 if (running_total != 0)
2651                         num_trbs++;
2652
2653                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2654                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2655                         num_trbs++;
2656                         running_total += TRB_MAX_BUFF_SIZE;
2657                 }
2658                 len = min_t(int, len, temp);
2659                 temp -= len;
2660                 if (temp == 0)
2661                         break;
2662         }
2663         return num_trbs;
2664 }
2665
2666 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2667 {
2668         if (num_trbs != 0)
2669                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2670                                 "TRBs, %d left\n", __func__,
2671                                 urb->ep->desc.bEndpointAddress, num_trbs);
2672         if (running_total != urb->transfer_buffer_length)
2673                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2674                                 "queued %#x (%d), asked for %#x (%d)\n",
2675                                 __func__,
2676                                 urb->ep->desc.bEndpointAddress,
2677                                 running_total, running_total,
2678                                 urb->transfer_buffer_length,
2679                                 urb->transfer_buffer_length);
2680 }
2681
2682 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2683                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2684                 struct xhci_generic_trb *start_trb)
2685 {
2686         /*
2687          * Pass all the TRBs to the hardware at once and make sure this write
2688          * isn't reordered.
2689          */
2690         wmb();
2691         if (start_cycle)
2692                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2693         else
2694                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2695         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2696 }
2697
2698 /*
2699  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2700  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2701  * (comprised of sg list entries) can take several service intervals to
2702  * transmit.
2703  */
2704 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2705                 struct urb *urb, int slot_id, unsigned int ep_index)
2706 {
2707         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2708                         xhci->devs[slot_id]->out_ctx, ep_index);
2709         int xhci_interval;
2710         int ep_interval;
2711
2712         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2713         ep_interval = urb->interval;
2714         /* Convert to microframes */
2715         if (urb->dev->speed == USB_SPEED_LOW ||
2716                         urb->dev->speed == USB_SPEED_FULL)
2717                 ep_interval *= 8;
2718         /* FIXME change this to a warning and a suggestion to use the new API
2719          * to set the polling interval (once the API is added).
2720          */
2721         if (xhci_interval != ep_interval) {
2722                 if (printk_ratelimit())
2723                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2724                                         " (%d microframe%s) than xHCI "
2725                                         "(%d microframe%s)\n",
2726                                         ep_interval,
2727                                         ep_interval == 1 ? "" : "s",
2728                                         xhci_interval,
2729                                         xhci_interval == 1 ? "" : "s");
2730                 urb->interval = xhci_interval;
2731                 /* Convert back to frames for LS/FS devices */
2732                 if (urb->dev->speed == USB_SPEED_LOW ||
2733                                 urb->dev->speed == USB_SPEED_FULL)
2734                         urb->interval /= 8;
2735         }
2736         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2737 }
2738
2739 /*
2740  * The TD size is the number of bytes remaining in the TD (including this TRB),
2741  * right shifted by 10.
2742  * It must fit in bits 21:17, so it can't be bigger than 31.
2743  */
2744 static u32 xhci_td_remainder(unsigned int remainder)
2745 {
2746         u32 max = (1 << (21 - 17 + 1)) - 1;
2747
2748         if ((remainder >> 10) >= max)
2749                 return max << 17;
2750         else
2751                 return (remainder >> 10) << 17;
2752 }
2753
2754 /*
2755  * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2756  * the TD (*not* including this TRB).
2757  *
2758  * Total TD packet count = total_packet_count =
2759  *     roundup(TD size in bytes / wMaxPacketSize)
2760  *
2761  * Packets transferred up to and including this TRB = packets_transferred =
2762  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2763  *
2764  * TD size = total_packet_count - packets_transferred
2765  *
2766  * It must fit in bits 21:17, so it can't be bigger than 31.
2767  */
2768
2769 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2770                 unsigned int total_packet_count, struct urb *urb)
2771 {
2772         int packets_transferred;
2773
2774         /* One TRB with a zero-length data packet. */
2775         if (running_total == 0 && trb_buff_len == 0)
2776                 return 0;
2777
2778         /* All the TRB queueing functions don't count the current TRB in
2779          * running_total.
2780          */
2781         packets_transferred = (running_total + trb_buff_len) /
2782                 usb_endpoint_maxp(&urb->ep->desc);
2783
2784         return xhci_td_remainder(total_packet_count - packets_transferred);
2785 }
2786
2787 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2788                 struct urb *urb, int slot_id, unsigned int ep_index)
2789 {
2790         struct xhci_ring *ep_ring;
2791         unsigned int num_trbs;
2792         struct urb_priv *urb_priv;
2793         struct xhci_td *td;
2794         struct scatterlist *sg;
2795         int num_sgs;
2796         int trb_buff_len, this_sg_len, running_total;
2797         unsigned int total_packet_count;
2798         bool first_trb;
2799         u64 addr;
2800         bool more_trbs_coming;
2801
2802         struct xhci_generic_trb *start_trb;
2803         int start_cycle;
2804
2805         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2806         if (!ep_ring)
2807                 return -EINVAL;
2808
2809         num_trbs = count_sg_trbs_needed(xhci, urb);
2810         num_sgs = urb->num_mapped_sgs;
2811         total_packet_count = roundup(urb->transfer_buffer_length,
2812                         usb_endpoint_maxp(&urb->ep->desc));
2813
2814         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2815                         ep_index, urb->stream_id,
2816                         num_trbs, urb, 0, mem_flags);
2817         if (trb_buff_len < 0)
2818                 return trb_buff_len;
2819
2820         urb_priv = urb->hcpriv;
2821         td = urb_priv->td[0];
2822
2823         /*
2824          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2825          * until we've finished creating all the other TRBs.  The ring's cycle
2826          * state may change as we enqueue the other TRBs, so save it too.
2827          */
2828         start_trb = &ep_ring->enqueue->generic;
2829         start_cycle = ep_ring->cycle_state;
2830
2831         running_total = 0;
2832         /*
2833          * How much data is in the first TRB?
2834          *
2835          * There are three forces at work for TRB buffer pointers and lengths:
2836          * 1. We don't want to walk off the end of this sg-list entry buffer.
2837          * 2. The transfer length that the driver requested may be smaller than
2838          *    the amount of memory allocated for this scatter-gather list.
2839          * 3. TRBs buffers can't cross 64KB boundaries.
2840          */
2841         sg = urb->sg;
2842         addr = (u64) sg_dma_address(sg);
2843         this_sg_len = sg_dma_len(sg);
2844         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
2845         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2846         if (trb_buff_len > urb->transfer_buffer_length)
2847                 trb_buff_len = urb->transfer_buffer_length;
2848
2849         first_trb = true;
2850         /* Queue the first TRB, even if it's zero-length */
2851         do {
2852                 u32 field = 0;
2853                 u32 length_field = 0;
2854                 u32 remainder = 0;
2855
2856                 /* Don't change the cycle bit of the first TRB until later */
2857                 if (first_trb) {
2858                         first_trb = false;
2859                         if (start_cycle == 0)
2860                                 field |= 0x1;
2861                 } else
2862                         field |= ep_ring->cycle_state;
2863
2864                 /* Chain all the TRBs together; clear the chain bit in the last
2865                  * TRB to indicate it's the last TRB in the chain.
2866                  */
2867                 if (num_trbs > 1) {
2868                         field |= TRB_CHAIN;
2869                 } else {
2870                         /* FIXME - add check for ZERO_PACKET flag before this */
2871                         td->last_trb = ep_ring->enqueue;
2872                         field |= TRB_IOC;
2873                 }
2874
2875                 /* Only set interrupt on short packet for IN endpoints */
2876                 if (usb_urb_dir_in(urb))
2877                         field |= TRB_ISP;
2878
2879                 if (TRB_MAX_BUFF_SIZE -
2880                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
2881                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2882                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2883                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2884                                         (unsigned int) addr + trb_buff_len);
2885                 }
2886
2887                 /* Set the TRB length, TD size, and interrupter fields. */
2888                 if (xhci->hci_version < 0x100) {
2889                         remainder = xhci_td_remainder(
2890                                         urb->transfer_buffer_length -
2891                                         running_total);
2892                 } else {
2893                         remainder = xhci_v1_0_td_remainder(running_total,
2894                                         trb_buff_len, total_packet_count, urb);
2895                 }
2896                 length_field = TRB_LEN(trb_buff_len) |
2897                         remainder |
2898                         TRB_INTR_TARGET(0);
2899
2900                 if (num_trbs > 1)
2901                         more_trbs_coming = true;
2902                 else
2903                         more_trbs_coming = false;
2904                 queue_trb(xhci, ep_ring, more_trbs_coming,
2905                                 lower_32_bits(addr),
2906                                 upper_32_bits(addr),
2907                                 length_field,
2908                                 field | TRB_TYPE(TRB_NORMAL));
2909                 --num_trbs;
2910                 running_total += trb_buff_len;
2911
2912                 /* Calculate length for next transfer --
2913                  * Are we done queueing all the TRBs for this sg entry?
2914                  */
2915                 this_sg_len -= trb_buff_len;
2916                 if (this_sg_len == 0) {
2917                         --num_sgs;
2918                         if (num_sgs == 0)
2919                                 break;
2920                         sg = sg_next(sg);
2921                         addr = (u64) sg_dma_address(sg);
2922                         this_sg_len = sg_dma_len(sg);
2923                 } else {
2924                         addr += trb_buff_len;
2925                 }
2926
2927                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2928                         (addr & (TRB_MAX_BUFF_SIZE - 1));
2929                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2930                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2931                         trb_buff_len =
2932                                 urb->transfer_buffer_length - running_total;
2933         } while (running_total < urb->transfer_buffer_length);
2934
2935         check_trb_math(urb, num_trbs, running_total);
2936         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2937                         start_cycle, start_trb);
2938         return 0;
2939 }
2940
2941 /* This is very similar to what ehci-q.c qtd_fill() does */
2942 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2943                 struct urb *urb, int slot_id, unsigned int ep_index)
2944 {
2945         struct xhci_ring *ep_ring;
2946         struct urb_priv *urb_priv;
2947         struct xhci_td *td;
2948         int num_trbs;
2949         struct xhci_generic_trb *start_trb;
2950         bool first_trb;
2951         bool more_trbs_coming;
2952         int start_cycle;
2953         u32 field, length_field;
2954
2955         int running_total, trb_buff_len, ret;
2956         unsigned int total_packet_count;
2957         u64 addr;
2958
2959         if (urb->num_sgs)
2960                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2961
2962         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2963         if (!ep_ring)
2964                 return -EINVAL;
2965
2966         num_trbs = 0;
2967         /* How much data is (potentially) left before the 64KB boundary? */
2968         running_total = TRB_MAX_BUFF_SIZE -
2969                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2970         running_total &= TRB_MAX_BUFF_SIZE - 1;
2971
2972         /* If there's some data on this 64KB chunk, or we have to send a
2973          * zero-length transfer, we need at least one TRB
2974          */
2975         if (running_total != 0 || urb->transfer_buffer_length == 0)
2976                 num_trbs++;
2977         /* How many more 64KB chunks to transfer, how many more TRBs? */
2978         while (running_total < urb->transfer_buffer_length) {
2979                 num_trbs++;
2980                 running_total += TRB_MAX_BUFF_SIZE;
2981         }
2982         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2983
2984         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2985                         ep_index, urb->stream_id,
2986                         num_trbs, urb, 0, mem_flags);
2987         if (ret < 0)
2988                 return ret;
2989
2990         urb_priv = urb->hcpriv;
2991         td = urb_priv->td[0];
2992
2993         /*
2994          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2995          * until we've finished creating all the other TRBs.  The ring's cycle
2996          * state may change as we enqueue the other TRBs, so save it too.
2997          */
2998         start_trb = &ep_ring->enqueue->generic;
2999         start_cycle = ep_ring->cycle_state;
3000
3001         running_total = 0;
3002         total_packet_count = roundup(urb->transfer_buffer_length,
3003                         usb_endpoint_maxp(&urb->ep->desc));
3004         /* How much data is in the first TRB? */
3005         addr = (u64) urb->transfer_dma;
3006         trb_buff_len = TRB_MAX_BUFF_SIZE -
3007                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3008         if (trb_buff_len > urb->transfer_buffer_length)
3009                 trb_buff_len = urb->transfer_buffer_length;
3010
3011         first_trb = true;
3012
3013         /* Queue the first TRB, even if it's zero-length */
3014         do {
3015                 u32 remainder = 0;
3016                 field = 0;
3017
3018                 /* Don't change the cycle bit of the first TRB until later */
3019                 if (first_trb) {
3020                         first_trb = false;
3021                         if (start_cycle == 0)
3022                                 field |= 0x1;
3023                 } else
3024                         field |= ep_ring->cycle_state;
3025
3026                 /* Chain all the TRBs together; clear the chain bit in the last
3027                  * TRB to indicate it's the last TRB in the chain.
3028                  */
3029                 if (num_trbs > 1) {
3030                         field |= TRB_CHAIN;
3031                 } else {
3032                         /* FIXME - add check for ZERO_PACKET flag before this */
3033                         td->last_trb = ep_ring->enqueue;
3034                         field |= TRB_IOC;
3035                 }
3036
3037                 /* Only set interrupt on short packet for IN endpoints */
3038                 if (usb_urb_dir_in(urb))
3039                         field |= TRB_ISP;
3040
3041                 /* Set the TRB length, TD size, and interrupter fields. */
3042                 if (xhci->hci_version < 0x100) {
3043                         remainder = xhci_td_remainder(
3044                                         urb->transfer_buffer_length -
3045                                         running_total);
3046                 } else {
3047                         remainder = xhci_v1_0_td_remainder(running_total,
3048                                         trb_buff_len, total_packet_count, urb);
3049                 }
3050                 length_field = TRB_LEN(trb_buff_len) |
3051                         remainder |
3052                         TRB_INTR_TARGET(0);
3053
3054                 if (num_trbs > 1)
3055                         more_trbs_coming = true;
3056                 else
3057                         more_trbs_coming = false;
3058                 queue_trb(xhci, ep_ring, more_trbs_coming,
3059                                 lower_32_bits(addr),
3060                                 upper_32_bits(addr),
3061                                 length_field,
3062                                 field | TRB_TYPE(TRB_NORMAL));
3063                 --num_trbs;
3064                 running_total += trb_buff_len;
3065
3066                 /* Calculate length for next transfer */
3067                 addr += trb_buff_len;
3068                 trb_buff_len = urb->transfer_buffer_length - running_total;
3069                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3070                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3071         } while (running_total < urb->transfer_buffer_length);
3072
3073         check_trb_math(urb, num_trbs, running_total);
3074         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3075                         start_cycle, start_trb);
3076         return 0;
3077 }
3078
3079 /* Caller must have locked xhci->lock */
3080 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3081                 struct urb *urb, int slot_id, unsigned int ep_index)
3082 {
3083         struct xhci_ring *ep_ring;
3084         int num_trbs;
3085         int ret;
3086         struct usb_ctrlrequest *setup;
3087         struct xhci_generic_trb *start_trb;
3088         int start_cycle;
3089         u32 field, length_field;
3090         struct urb_priv *urb_priv;
3091         struct xhci_td *td;
3092
3093         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3094         if (!ep_ring)
3095                 return -EINVAL;
3096
3097         /*
3098          * Need to copy setup packet into setup TRB, so we can't use the setup
3099          * DMA address.
3100          */
3101         if (!urb->setup_packet)
3102                 return -EINVAL;
3103
3104         /* 1 TRB for setup, 1 for status */
3105         num_trbs = 2;
3106         /*
3107          * Don't need to check if we need additional event data and normal TRBs,
3108          * since data in control transfers will never get bigger than 16MB
3109          * XXX: can we get a buffer that crosses 64KB boundaries?
3110          */
3111         if (urb->transfer_buffer_length > 0)
3112                 num_trbs++;
3113         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3114                         ep_index, urb->stream_id,
3115                         num_trbs, urb, 0, mem_flags);
3116         if (ret < 0)
3117                 return ret;
3118
3119         urb_priv = urb->hcpriv;
3120         td = urb_priv->td[0];
3121
3122         /*
3123          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3124          * until we've finished creating all the other TRBs.  The ring's cycle
3125          * state may change as we enqueue the other TRBs, so save it too.
3126          */
3127         start_trb = &ep_ring->enqueue->generic;
3128         start_cycle = ep_ring->cycle_state;
3129
3130         /* Queue setup TRB - see section 6.4.1.2.1 */
3131         /* FIXME better way to translate setup_packet into two u32 fields? */
3132         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3133         field = 0;
3134         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3135         if (start_cycle == 0)
3136                 field |= 0x1;
3137
3138         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3139         if (xhci->hci_version == 0x100) {
3140                 if (urb->transfer_buffer_length > 0) {
3141                         if (setup->bRequestType & USB_DIR_IN)
3142                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3143                         else
3144                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3145                 }
3146         }
3147
3148         queue_trb(xhci, ep_ring, true,
3149                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3150                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3151                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3152                   /* Immediate data in pointer */
3153                   field);
3154
3155         /* If there's data, queue data TRBs */
3156         /* Only set interrupt on short packet for IN endpoints */
3157         if (usb_urb_dir_in(urb))
3158                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3159         else
3160                 field = TRB_TYPE(TRB_DATA);
3161
3162         length_field = TRB_LEN(urb->transfer_buffer_length) |
3163                 xhci_td_remainder(urb->transfer_buffer_length) |
3164                 TRB_INTR_TARGET(0);
3165         if (urb->transfer_buffer_length > 0) {
3166                 if (setup->bRequestType & USB_DIR_IN)
3167                         field |= TRB_DIR_IN;
3168                 queue_trb(xhci, ep_ring, true,
3169                                 lower_32_bits(urb->transfer_dma),
3170                                 upper_32_bits(urb->transfer_dma),
3171                                 length_field,
3172                                 field | ep_ring->cycle_state);
3173         }
3174
3175         /* Save the DMA address of the last TRB in the TD */
3176         td->last_trb = ep_ring->enqueue;
3177
3178         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3179         /* If the device sent data, the status stage is an OUT transfer */
3180         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3181                 field = 0;
3182         else
3183                 field = TRB_DIR_IN;
3184         queue_trb(xhci, ep_ring, false,
3185                         0,
3186                         0,
3187                         TRB_INTR_TARGET(0),
3188                         /* Event on completion */
3189                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3190
3191         giveback_first_trb(xhci, slot_id, ep_index, 0,
3192                         start_cycle, start_trb);
3193         return 0;
3194 }
3195
3196 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3197                 struct urb *urb, int i)
3198 {
3199         int num_trbs = 0;
3200         u64 addr, td_len;
3201
3202         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3203         td_len = urb->iso_frame_desc[i].length;
3204
3205         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3206                         TRB_MAX_BUFF_SIZE);
3207         if (num_trbs == 0)
3208                 num_trbs++;
3209
3210         return num_trbs;
3211 }
3212
3213 /*
3214  * The transfer burst count field of the isochronous TRB defines the number of
3215  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3216  * devices can burst up to bMaxBurst number of packets per service interval.
3217  * This field is zero based, meaning a value of zero in the field means one
3218  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3219  * zero.  Only xHCI 1.0 host controllers support this field.
3220  */
3221 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3222                 struct usb_device *udev,
3223                 struct urb *urb, unsigned int total_packet_count)
3224 {
3225         unsigned int max_burst;
3226
3227         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3228                 return 0;
3229
3230         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3231         return roundup(total_packet_count, max_burst + 1) - 1;
3232 }
3233
3234 /*
3235  * Returns the number of packets in the last "burst" of packets.  This field is
3236  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3237  * the last burst packet count is equal to the total number of packets in the
3238  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3239  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3240  * contain 1 to (bMaxBurst + 1) packets.
3241  */
3242 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3243                 struct usb_device *udev,
3244                 struct urb *urb, unsigned int total_packet_count)
3245 {
3246         unsigned int max_burst;
3247         unsigned int residue;
3248
3249         if (xhci->hci_version < 0x100)
3250                 return 0;
3251
3252         switch (udev->speed) {
3253         case USB_SPEED_SUPER:
3254                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3255                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3256                 residue = total_packet_count % (max_burst + 1);
3257                 /* If residue is zero, the last burst contains (max_burst + 1)
3258                  * number of packets, but the TLBPC field is zero-based.
3259                  */
3260                 if (residue == 0)
3261                         return max_burst;
3262                 return residue - 1;
3263         default:
3264                 if (total_packet_count == 0)
3265                         return 0;
3266                 return total_packet_count - 1;
3267         }
3268 }
3269
3270 /* This is for isoc transfer */
3271 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3272                 struct urb *urb, int slot_id, unsigned int ep_index)
3273 {
3274         struct xhci_ring *ep_ring;
3275         struct urb_priv *urb_priv;
3276         struct xhci_td *td;
3277         int num_tds, trbs_per_td;
3278         struct xhci_generic_trb *start_trb;
3279         bool first_trb;
3280         int start_cycle;
3281         u32 field, length_field;
3282         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3283         u64 start_addr, addr;
3284         int i, j;
3285         bool more_trbs_coming;
3286
3287         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3288
3289         num_tds = urb->number_of_packets;
3290         if (num_tds < 1) {
3291                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3292                 return -EINVAL;
3293         }
3294
3295         start_addr = (u64) urb->transfer_dma;
3296         start_trb = &ep_ring->enqueue->generic;
3297         start_cycle = ep_ring->cycle_state;
3298
3299         urb_priv = urb->hcpriv;
3300         /* Queue the first TRB, even if it's zero-length */
3301         for (i = 0; i < num_tds; i++) {
3302                 unsigned int total_packet_count;
3303                 unsigned int burst_count;
3304                 unsigned int residue;
3305
3306                 first_trb = true;
3307                 running_total = 0;
3308                 addr = start_addr + urb->iso_frame_desc[i].offset;
3309                 td_len = urb->iso_frame_desc[i].length;
3310                 td_remain_len = td_len;
3311                 total_packet_count = roundup(td_len,
3312                                 usb_endpoint_maxp(&urb->ep->desc));
3313                 /* A zero-length transfer still involves at least one packet. */
3314                 if (total_packet_count == 0)
3315                         total_packet_count++;
3316                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3317                                 total_packet_count);
3318                 residue = xhci_get_last_burst_packet_count(xhci,
3319                                 urb->dev, urb, total_packet_count);
3320
3321                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3322
3323                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3324                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3325                 if (ret < 0) {
3326                         if (i == 0)
3327                                 return ret;
3328                         goto cleanup;
3329                 }
3330
3331                 td = urb_priv->td[i];
3332                 for (j = 0; j < trbs_per_td; j++) {
3333                         u32 remainder = 0;
3334                         field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
3335
3336                         if (first_trb) {
3337                                 /* Queue the isoc TRB */
3338                                 field |= TRB_TYPE(TRB_ISOC);
3339                                 /* Assume URB_ISO_ASAP is set */
3340                                 field |= TRB_SIA;
3341                                 if (i == 0) {
3342                                         if (start_cycle == 0)
3343                                                 field |= 0x1;
3344                                 } else
3345                                         field |= ep_ring->cycle_state;
3346                                 first_trb = false;
3347                         } else {
3348                                 /* Queue other normal TRBs */
3349                                 field |= TRB_TYPE(TRB_NORMAL);
3350                                 field |= ep_ring->cycle_state;
3351                         }
3352
3353                         /* Only set interrupt on short packet for IN EPs */
3354                         if (usb_urb_dir_in(urb))
3355                                 field |= TRB_ISP;
3356
3357                         /* Chain all the TRBs together; clear the chain bit in
3358                          * the last TRB to indicate it's the last TRB in the
3359                          * chain.
3360                          */
3361                         if (j < trbs_per_td - 1) {
3362                                 field |= TRB_CHAIN;
3363                                 more_trbs_coming = true;
3364                         } else {
3365                                 td->last_trb = ep_ring->enqueue;
3366                                 field |= TRB_IOC;
3367                                 if (xhci->hci_version == 0x100) {
3368                                         /* Set BEI bit except for the last td */
3369                                         if (i < num_tds - 1)
3370                                                 field |= TRB_BEI;
3371                                 }
3372                                 more_trbs_coming = false;
3373                         }
3374
3375                         /* Calculate TRB length */
3376                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3377                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3378                         if (trb_buff_len > td_remain_len)
3379                                 trb_buff_len = td_remain_len;
3380
3381                         /* Set the TRB length, TD size, & interrupter fields. */
3382                         if (xhci->hci_version < 0x100) {
3383                                 remainder = xhci_td_remainder(
3384                                                 td_len - running_total);
3385                         } else {
3386                                 remainder = xhci_v1_0_td_remainder(
3387                                                 running_total, trb_buff_len,
3388                                                 total_packet_count, urb);
3389                         }
3390                         length_field = TRB_LEN(trb_buff_len) |
3391                                 remainder |
3392                                 TRB_INTR_TARGET(0);
3393
3394                         queue_trb(xhci, ep_ring, more_trbs_coming,
3395                                 lower_32_bits(addr),
3396                                 upper_32_bits(addr),
3397                                 length_field,
3398                                 field);
3399                         running_total += trb_buff_len;
3400
3401                         addr += trb_buff_len;
3402                         td_remain_len -= trb_buff_len;
3403                 }
3404
3405                 /* Check TD length */
3406                 if (running_total != td_len) {
3407                         xhci_err(xhci, "ISOC TD length unmatch\n");
3408                         ret = -EINVAL;
3409                         goto cleanup;
3410                 }
3411         }
3412
3413         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3414                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3415                         usb_amd_quirk_pll_disable();
3416         }
3417         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3418
3419         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3420                         start_cycle, start_trb);
3421         return 0;
3422 cleanup:
3423         /* Clean up a partially enqueued isoc transfer. */
3424
3425         for (i--; i >= 0; i--)
3426                 list_del_init(&urb_priv->td[i]->td_list);
3427
3428         /* Use the first TD as a temporary variable to turn the TDs we've queued
3429          * into No-ops with a software-owned cycle bit. That way the hardware
3430          * won't accidentally start executing bogus TDs when we partially
3431          * overwrite them.  td->first_trb and td->start_seg are already set.
3432          */
3433         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3434         /* Every TRB except the first & last will have its cycle bit flipped. */
3435         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3436
3437         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3438         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3439         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3440         ep_ring->cycle_state = start_cycle;
3441         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3442         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3443         return ret;
3444 }
3445
3446 /*
3447  * Check transfer ring to guarantee there is enough room for the urb.
3448  * Update ISO URB start_frame and interval.
3449  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3450  * update the urb->start_frame by now.
3451  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3452  */
3453 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3454                 struct urb *urb, int slot_id, unsigned int ep_index)
3455 {
3456         struct xhci_virt_device *xdev;
3457         struct xhci_ring *ep_ring;
3458         struct xhci_ep_ctx *ep_ctx;
3459         int start_frame;
3460         int xhci_interval;
3461         int ep_interval;
3462         int num_tds, num_trbs, i;
3463         int ret;
3464
3465         xdev = xhci->devs[slot_id];
3466         ep_ring = xdev->eps[ep_index].ring;
3467         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3468
3469         num_trbs = 0;
3470         num_tds = urb->number_of_packets;
3471         for (i = 0; i < num_tds; i++)
3472                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3473
3474         /* Check the ring to guarantee there is enough room for the whole urb.
3475          * Do not insert any td of the urb to the ring if the check failed.
3476          */
3477         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3478                            num_trbs, mem_flags);
3479         if (ret)
3480                 return ret;
3481
3482         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3483         start_frame &= 0x3fff;
3484
3485         urb->start_frame = start_frame;
3486         if (urb->dev->speed == USB_SPEED_LOW ||
3487                         urb->dev->speed == USB_SPEED_FULL)
3488                 urb->start_frame >>= 3;
3489
3490         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3491         ep_interval = urb->interval;
3492         /* Convert to microframes */
3493         if (urb->dev->speed == USB_SPEED_LOW ||
3494                         urb->dev->speed == USB_SPEED_FULL)
3495                 ep_interval *= 8;
3496         /* FIXME change this to a warning and a suggestion to use the new API
3497          * to set the polling interval (once the API is added).
3498          */
3499         if (xhci_interval != ep_interval) {
3500                 if (printk_ratelimit())
3501                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3502                                         " (%d microframe%s) than xHCI "
3503                                         "(%d microframe%s)\n",
3504                                         ep_interval,
3505                                         ep_interval == 1 ? "" : "s",
3506                                         xhci_interval,
3507                                         xhci_interval == 1 ? "" : "s");
3508                 urb->interval = xhci_interval;
3509                 /* Convert back to frames for LS/FS devices */
3510                 if (urb->dev->speed == USB_SPEED_LOW ||
3511                                 urb->dev->speed == USB_SPEED_FULL)
3512                         urb->interval /= 8;
3513         }
3514         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3515
3516         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3517 }
3518
3519 /****           Command Ring Operations         ****/
3520
3521 /* Generic function for queueing a command TRB on the command ring.
3522  * Check to make sure there's room on the command ring for one command TRB.
3523  * Also check that there's room reserved for commands that must not fail.
3524  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3525  * then only check for the number of reserved spots.
3526  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3527  * because the command event handler may want to resubmit a failed command.
3528  */
3529 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3530                 u32 field3, u32 field4, bool command_must_succeed)
3531 {
3532         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3533         int ret;
3534
3535         if (!command_must_succeed)
3536                 reserved_trbs++;
3537
3538         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3539                         reserved_trbs, GFP_ATOMIC);
3540         if (ret < 0) {
3541                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3542                 if (command_must_succeed)
3543                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3544                                         "unfailable commands failed.\n");
3545                 return ret;
3546         }
3547         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3548                         field4 | xhci->cmd_ring->cycle_state);
3549         return 0;
3550 }
3551
3552 /* Queue a slot enable or disable request on the command ring */
3553 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3554 {
3555         return queue_command(xhci, 0, 0, 0,
3556                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3557 }
3558
3559 /* Queue an address device command TRB */
3560 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3561                 u32 slot_id)
3562 {
3563         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3564                         upper_32_bits(in_ctx_ptr), 0,
3565                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3566                         false);
3567 }
3568
3569 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3570                 u32 field1, u32 field2, u32 field3, u32 field4)
3571 {
3572         return queue_command(xhci, field1, field2, field3, field4, false);
3573 }
3574
3575 /* Queue a reset device command TRB */
3576 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3577 {
3578         return queue_command(xhci, 0, 0, 0,
3579                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3580                         false);
3581 }
3582
3583 /* Queue a configure endpoint command TRB */
3584 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3585                 u32 slot_id, bool command_must_succeed)
3586 {
3587         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3588                         upper_32_bits(in_ctx_ptr), 0,
3589                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3590                         command_must_succeed);
3591 }
3592
3593 /* Queue an evaluate context command TRB */
3594 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3595                 u32 slot_id)
3596 {
3597         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3598                         upper_32_bits(in_ctx_ptr), 0,
3599                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3600                         false);
3601 }
3602
3603 /*
3604  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3605  * activity on an endpoint that is about to be suspended.
3606  */
3607 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3608                 unsigned int ep_index, int suspend)
3609 {
3610         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3611         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3612         u32 type = TRB_TYPE(TRB_STOP_RING);
3613         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3614
3615         return queue_command(xhci, 0, 0, 0,
3616                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3617 }
3618
3619 /* Set Transfer Ring Dequeue Pointer command.
3620  * This should not be used for endpoints that have streams enabled.
3621  */
3622 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3623                 unsigned int ep_index, unsigned int stream_id,
3624                 struct xhci_segment *deq_seg,
3625                 union xhci_trb *deq_ptr, u32 cycle_state)
3626 {
3627         dma_addr_t addr;
3628         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3629         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3630         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3631         u32 type = TRB_TYPE(TRB_SET_DEQ);
3632         struct xhci_virt_ep *ep;
3633
3634         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3635         if (addr == 0) {
3636                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3637                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3638                                 deq_seg, deq_ptr);
3639                 return 0;
3640         }
3641         ep = &xhci->devs[slot_id]->eps[ep_index];
3642         if ((ep->ep_state & SET_DEQ_PENDING)) {
3643                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3644                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3645                 return 0;
3646         }
3647         ep->queued_deq_seg = deq_seg;
3648         ep->queued_deq_ptr = deq_ptr;
3649         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3650                         upper_32_bits(addr), trb_stream_id,
3651                         trb_slot_id | trb_ep_index | type, false);
3652 }
3653
3654 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3655                 unsigned int ep_index)
3656 {
3657         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3658         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3659         u32 type = TRB_TYPE(TRB_RESET_EP);
3660
3661         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3662                         false);
3663 }