Pileus Git - ~andy/linux/blob - drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset > TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return trb->link.control & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
 117 }
 118
 119 static inline int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         union xhci_trb *next = ++(ring->dequeue);
 149         unsigned long long addr;
 150
 151         ring->deq_updates++;
 152         /* Update the dequeue pointer further if that was a link TRB or we're at
 153          * the end of an event ring segment (which doesn't have link TRBS)
 154          */
 155         while (last_trb(xhci, ring, ring->deq_seg, next)) {
 156                 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
 157                         ring->cycle_state = (ring->cycle_state ? 0 : 1);
 158                         if (!in_interrupt())
 159                                 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 160                                                 ring,
 161                                                 (unsigned int) ring->cycle_state);
 162                 }
 163                 ring->deq_seg = ring->deq_seg->next;
 164                 ring->dequeue = ring->deq_seg->trbs;
 165                 next = ring->dequeue;
 166         }
 167         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 168         if (ring == xhci->event_ring)
 169                 xhci_dbg(xhci, "Event ring deq = 0x%llx (DMA)\n", addr);
 170         else if (ring == xhci->cmd_ring)
 171                 xhci_dbg(xhci, "Command ring deq = 0x%llx (DMA)\n", addr);
 172         else
 173                 xhci_dbg(xhci, "Ring deq = 0x%llx (DMA)\n", addr);
 174 }
 175
 176 /*
 177  * See Cycle bit rules. SW is the consumer for the event ring only.
 178  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 179  *
 180  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 181  * chain bit is set), then set the chain bit in all the following link TRBs.
 182  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 183  * have their chain bit cleared (so that each Link TRB is a separate TD).
 184  *
 185  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 186  * set, but other sections talk about dealing with the chain bit set.  This was
 187  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 188  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 189  *
 190  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 191  *                      prepare_transfer()?
 192  */
 193 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 194                 bool consumer, bool more_trbs_coming)
 195 {
 196         u32 chain;
 197         union xhci_trb *next;
 198         unsigned long long addr;
 199
 200         chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
 201         next = ++(ring->enqueue);
 202
 203         ring->enq_updates++;
 204         /* Update the dequeue pointer further if that was a link TRB or we're at
 205          * the end of an event ring segment (which doesn't have link TRBS)
 206          */
 207         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 208                 if (!consumer) {
 209                         if (ring != xhci->event_ring) {
 210                                 /*
 211                                  * If the caller doesn't plan on enqueueing more
 212                                  * TDs before ringing the doorbell, then we
 213                                  * don't want to give the link TRB to the
 214                                  * hardware just yet.  We'll give the link TRB
 215                                  * back in prepare_ring() just before we enqueue
 216                                  * the TD at the top of the ring.
 217                                  */
 218                                 if (!chain && !more_trbs_coming)
 219                                         break;
 220
 221                                 /* If we're not dealing with 0.95 hardware,
 222                                  * carry over the chain bit of the previous TRB
 223                                  * (which may mean the chain bit is cleared).
 224                                  */
 225                                 if (!xhci_link_trb_quirk(xhci)) {
 226                                         next->link.control &= ~TRB_CHAIN;
 227                                         next->link.control |= chain;
 228                                 }
 229                                 /* Give this link TRB to the hardware */
 230                                 wmb();
 231                                 next->link.control ^= TRB_CYCLE;
 232                         }
 233                         /* Toggle the cycle bit after the last ring segment. */
 234                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 235                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 236                                 if (!in_interrupt())
 237                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 238                                                         ring,
 239                                                         (unsigned int) ring->cycle_state);
 240                         }
 241                 }
 242                 ring->enq_seg = ring->enq_seg->next;
 243                 ring->enqueue = ring->enq_seg->trbs;
 244                 next = ring->enqueue;
 245         }
 246         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 247         if (ring == xhci->event_ring)
 248                 xhci_dbg(xhci, "Event ring enq = 0x%llx (DMA)\n", addr);
 249         else if (ring == xhci->cmd_ring)
 250                 xhci_dbg(xhci, "Command ring enq = 0x%llx (DMA)\n", addr);
 251         else
 252                 xhci_dbg(xhci, "Ring enq = 0x%llx (DMA)\n", addr);
 253 }
 254
 255 /*
 256  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 257  * above.
 258  * FIXME: this would be simpler and faster if we just kept track of the number
 259  * of free TRBs in a ring.
 260  */
 261 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 262                 unsigned int num_trbs)
 263 {
 264         int i;
 265         union xhci_trb *enq = ring->enqueue;
 266         struct xhci_segment *enq_seg = ring->enq_seg;
 267         struct xhci_segment *cur_seg;
 268         unsigned int left_on_ring;
 269
 270         /* If we are currently pointing to a link TRB, advance the
 271          * enqueue pointer before checking for space */
 272         while (last_trb(xhci, ring, enq_seg, enq)) {
 273                 enq_seg = enq_seg->next;
 274                 enq = enq_seg->trbs;
 275         }
 276
 277         /* Check if ring is empty */
 278         if (enq == ring->dequeue) {
 279                 /* Can't use link trbs */
 280                 left_on_ring = TRBS_PER_SEGMENT - 1;
 281                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 282                                 cur_seg = cur_seg->next)
 283                         left_on_ring += TRBS_PER_SEGMENT - 1;
 284
 285                 /* Always need one TRB free in the ring. */
 286                 left_on_ring -= 1;
 287                 if (num_trbs > left_on_ring) {
 288                         xhci_warn(xhci, "Not enough room on ring; "
 289                                         "need %u TRBs, %u TRBs left\n",
 290                                         num_trbs, left_on_ring);
 291                         return 0;
 292                 }
 293                 return 1;
 294         }
 295         /* Make sure there's an extra empty TRB available */
 296         for (i = 0; i <= num_trbs; ++i) {
 297                 if (enq == ring->dequeue)
 298                         return 0;
 299                 enq++;
 300                 while (last_trb(xhci, ring, enq_seg, enq)) {
 301                         enq_seg = enq_seg->next;
 302                         enq = enq_seg->trbs;
 303                 }
 304         }
 305         return 1;
 306 }
 307
 308 /* Ring the host controller doorbell after placing a command on the ring */
 309 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 310 {
 311         xhci_dbg(xhci, "// Ding dong!\n");
 312         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 313         /* Flush PCI posted writes */
 314         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 315 }
 316
 317 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 318                 unsigned int slot_id,
 319                 unsigned int ep_index,
 320                 unsigned int stream_id)
 321 {
 322         __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 323         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 324         unsigned int ep_state = ep->ep_state;
 325
 326         /* Don't ring the doorbell for this endpoint if there are pending
 327          * cancellations because we don't want to interrupt processing.
 328          * We don't want to restart any stream rings if there's a set dequeue
 329          * pointer command pending because the device can choose to start any
 330          * stream once the endpoint is on the HW schedule.
 331          * FIXME - check all the stream rings for pending cancellations.
 332          */
 333         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 334             (ep_state & EP_HALTED))
 335                 return;
 336         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 337         /* The CPU has better things to do at this point than wait for a
 338          * write-posting flush.  It'll get there soon enough.
 339          */
 340 }
 341
 342 /* Ring the doorbell for any rings with pending URBs */
 343 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 344                 unsigned int slot_id,
 345                 unsigned int ep_index)
 346 {
 347         unsigned int stream_id;
 348         struct xhci_virt_ep *ep;
 349
 350         ep = &xhci->devs[slot_id]->eps[ep_index];
 351
 352         /* A ring has pending URBs if its TD list is not empty */
 353         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 354                 if (!(list_empty(&ep->ring->td_list)))
 355                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 356                 return;
 357         }
 358
 359         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 360                         stream_id++) {
 361                 struct xhci_stream_info *stream_info = ep->stream_info;
 362                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 363                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 364                                                 stream_id);
 365         }
 366 }
 367
 368 /*
 369  * Find the segment that trb is in.  Start searching in start_seg.
 370  * If we must move past a segment that has a link TRB with a toggle cycle state
 371  * bit set, then we will toggle the value pointed at by cycle_state.
 372  */
 373 static struct xhci_segment *find_trb_seg(
 374                 struct xhci_segment *start_seg,
 375                 union xhci_trb  *trb, int *cycle_state)
 376 {
 377         struct xhci_segment *cur_seg = start_seg;
 378         struct xhci_generic_trb *generic_trb;
 379
 380         while (cur_seg->trbs > trb ||
 381                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 382                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 383                 if ((generic_trb->field[3] & TRB_TYPE_BITMASK) ==
 384                                 TRB_TYPE(TRB_LINK) &&
 385                                 (generic_trb->field[3] & LINK_TOGGLE))
 386                         *cycle_state = ~(*cycle_state) & 0x1;
 387                 cur_seg = cur_seg->next;
 388                 if (cur_seg == start_seg)
 389                         /* Looped over the entire list.  Oops! */
 390                         return NULL;
 391         }
 392         return cur_seg;
 393 }
 394
 395
 396 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 397                 unsigned int slot_id, unsigned int ep_index,
 398                 unsigned int stream_id)
 399 {
 400         struct xhci_virt_ep *ep;
 401
 402         ep = &xhci->devs[slot_id]->eps[ep_index];
 403         /* Common case: no streams */
 404         if (!(ep->ep_state & EP_HAS_STREAMS))
 405                 return ep->ring;
 406
 407         if (stream_id == 0) {
 408                 xhci_warn(xhci,
 409                                 "WARN: Slot ID %u, ep index %u has streams, "
 410                                 "but URB has no stream ID.\n",
 411                                 slot_id, ep_index);
 412                 return NULL;
 413         }
 414
 415         if (stream_id < ep->stream_info->num_streams)
 416                 return ep->stream_info->stream_rings[stream_id];
 417
 418         xhci_warn(xhci,
 419                         "WARN: Slot ID %u, ep index %u has "
 420                         "stream IDs 1 to %u allocated, "
 421                         "but stream ID %u is requested.\n",
 422                         slot_id, ep_index,
 423                         ep->stream_info->num_streams - 1,
 424                         stream_id);
 425         return NULL;
 426 }
 427
 428 /* Get the right ring for the given URB.
 429  * If the endpoint supports streams, boundary check the URB's stream ID.
 430  * If the endpoint doesn't support streams, return the singular endpoint ring.
 431  */
 432 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 433                 struct urb *urb)
 434 {
 435         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 436                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 437 }
 438
 439 /*
 440  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 441  * Record the new state of the xHC's endpoint ring dequeue segment,
 442  * dequeue pointer, and new consumer cycle state in state.
 443  * Update our internal representation of the ring's dequeue pointer.
 444  *
 445  * We do this in three jumps:
 446  *  - First we update our new ring state to be the same as when the xHC stopped.
 447  *  - Then we traverse the ring to find the segment that contains
 448  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 449  *    any link TRBs with the toggle cycle bit set.
 450  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 451  *    if we've moved it past a link TRB with the toggle cycle bit set.
 452  */
 453 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 454                 unsigned int slot_id, unsigned int ep_index,
 455                 unsigned int stream_id, struct xhci_td *cur_td,
 456                 struct xhci_dequeue_state *state)
 457 {
 458         struct xhci_virt_device *dev = xhci->devs[slot_id];
 459         struct xhci_ring *ep_ring;
 460         struct xhci_generic_trb *trb;
 461         struct xhci_ep_ctx *ep_ctx;
 462         dma_addr_t addr;
 463
 464         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 465                         ep_index, stream_id);
 466         if (!ep_ring) {
 467                 xhci_warn(xhci, "WARN can't find new dequeue state "
 468                                 "for invalid stream ID %u.\n",
 469                                 stream_id);
 470                 return;
 471         }
 472         state->new_cycle_state = 0;
 473         xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 474         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 475                         dev->eps[ep_index].stopped_trb,
 476                         &state->new_cycle_state);
 477         if (!state->new_deq_seg)
 478                 BUG();
 479         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 480         xhci_dbg(xhci, "Finding endpoint context\n");
 481         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 482         state->new_cycle_state = 0x1 & ep_ctx->deq;
 483
 484         state->new_deq_ptr = cur_td->last_trb;
 485         xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 486         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 487                         state->new_deq_ptr,
 488                         &state->new_cycle_state);
 489         if (!state->new_deq_seg)
 490                 BUG();
 491
 492         trb = &state->new_deq_ptr->generic;
 493         if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
 494                                 (trb->field[3] & LINK_TOGGLE))
 495                 state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
 496         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 497
 498         /* Don't update the ring cycle state for the producer (us). */
 499         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 500                         state->new_deq_seg);
 501         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 502         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 503                         (unsigned long long) addr);
 504 }
 505
 506 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 507                 struct xhci_td *cur_td)
 508 {
 509         struct xhci_segment *cur_seg;
 510         union xhci_trb *cur_trb;
 511
 512         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 513                         true;
 514                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 515                 if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
 516                                 TRB_TYPE(TRB_LINK)) {
 517                         /* Unchain any chained Link TRBs, but
 518                          * leave the pointers intact.
 519                          */
 520                         cur_trb->generic.field[3] &= ~TRB_CHAIN;
 521                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 522                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 523                                         "in seg %p (0x%llx dma)\n",
 524                                         cur_trb,
 525                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 526                                         cur_seg,
 527                                         (unsigned long long)cur_seg->dma);
 528                 } else {
 529                         cur_trb->generic.field[0] = 0;
 530                         cur_trb->generic.field[1] = 0;
 531                         cur_trb->generic.field[2] = 0;
 532                         /* Preserve only the cycle bit of this TRB */
 533                         cur_trb->generic.field[3] &= TRB_CYCLE;
 534                         cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
 535                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 536                                         "in seg %p (0x%llx dma)\n",
 537                                         cur_trb,
 538                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 539                                         cur_seg,
 540                                         (unsigned long long)cur_seg->dma);
 541                 }
 542                 if (cur_trb == cur_td->last_trb)
 543                         break;
 544         }
 545 }
 546
 547 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 548                 unsigned int ep_index, unsigned int stream_id,
 549                 struct xhci_segment *deq_seg,
 550                 union xhci_trb *deq_ptr, u32 cycle_state);
 551
 552 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 553                 unsigned int slot_id, unsigned int ep_index,
 554                 unsigned int stream_id,
 555                 struct xhci_dequeue_state *deq_state)
 556 {
 557         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 558
 559         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 560                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 561                         deq_state->new_deq_seg,
 562                         (unsigned long long)deq_state->new_deq_seg->dma,
 563                         deq_state->new_deq_ptr,
 564                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 565                         deq_state->new_cycle_state);
 566         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 567                         deq_state->new_deq_seg,
 568                         deq_state->new_deq_ptr,
 569                         (u32) deq_state->new_cycle_state);
 570         /* Stop the TD queueing code from ringing the doorbell until
 571          * this command completes.  The HC won't set the dequeue pointer
 572          * if the ring is running, and ringing the doorbell starts the
 573          * ring running.
 574          */
 575         ep->ep_state |= SET_DEQ_PENDING;
 576 }
 577
 578 static inline void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 579                 struct xhci_virt_ep *ep)
 580 {
 581         ep->ep_state &= ~EP_HALT_PENDING;
 582         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 583          * timer is running on another CPU, we don't decrement stop_cmds_pending
 584          * (since we didn't successfully stop the watchdog timer).
 585          */
 586         if (del_timer(&ep->stop_cmd_timer))
 587                 ep->stop_cmds_pending--;
 588 }
 589
 590 /* Must be called with xhci->lock held in interrupt context */
 591 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 592                 struct xhci_td *cur_td, int status, char *adjective)
 593 {
 594         struct usb_hcd *hcd;
 595         struct urb      *urb;
 596         struct urb_priv *urb_priv;
 597
 598         urb = cur_td->urb;
 599         urb_priv = urb->hcpriv;
 600         urb_priv->td_cnt++;
 601         hcd = bus_to_hcd(urb->dev->bus);
 602
 603         /* Only giveback urb when this is the last td in urb */
 604         if (urb_priv->td_cnt == urb_priv->length) {
 605                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 606                 xhci_dbg(xhci, "Giveback %s URB %p\n", adjective, urb);
 607
 608                 spin_unlock(&xhci->lock);
 609                 usb_hcd_giveback_urb(hcd, urb, status);
 610                 xhci_urb_free_priv(xhci, urb_priv);
 611                 spin_lock(&xhci->lock);
 612                 xhci_dbg(xhci, "%s URB given back\n", adjective);
 613         }
 614 }
 615
 616 /*
 617  * When we get a command completion for a Stop Endpoint Command, we need to
 618  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 619  *
 620  *  1. If the HW was in the middle of processing the TD that needs to be
 621  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 622  *     in the TD with a Set Dequeue Pointer Command.
 623  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 624  *     bit cleared) so that the HW will skip over them.
 625  */
 626 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 627                 union xhci_trb *trb, struct xhci_event_cmd *event)
 628 {
 629         unsigned int slot_id;
 630         unsigned int ep_index;
 631         struct xhci_virt_device *virt_dev;
 632         struct xhci_ring *ep_ring;
 633         struct xhci_virt_ep *ep;
 634         struct list_head *entry;
 635         struct xhci_td *cur_td = NULL;
 636         struct xhci_td *last_unlinked_td;
 637
 638         struct xhci_dequeue_state deq_state;
 639
 640         if (unlikely(TRB_TO_SUSPEND_PORT(
 641                         xhci->cmd_ring->dequeue->generic.field[3]))) {
 642                 slot_id = TRB_TO_SLOT_ID(
 643                         xhci->cmd_ring->dequeue->generic.field[3]);
 644                 virt_dev = xhci->devs[slot_id];
 645                 if (virt_dev)
 646                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 647                                 event);
 648                 else
 649                         xhci_warn(xhci, "Stop endpoint command "
 650                                 "completion for disabled slot %u\n",
 651                                 slot_id);
 652                 return;
 653         }
 654
 655         memset(&deq_state, 0, sizeof(deq_state));
 656         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 657         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 658         ep = &xhci->devs[slot_id]->eps[ep_index];
 659
 660         if (list_empty(&ep->cancelled_td_list)) {
 661                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 662                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 663                 return;
 664         }
 665
 666         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 667          * We have the xHCI lock, so nothing can modify this list until we drop
 668          * it.  We're also in the event handler, so we can't get re-interrupted
 669          * if another Stop Endpoint command completes
 670          */
 671         list_for_each(entry, &ep->cancelled_td_list) {
 672                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 673                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 674                                 cur_td->first_trb,
 675                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 676                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 677                 if (!ep_ring) {
 678                         /* This shouldn't happen unless a driver is mucking
 679                          * with the stream ID after submission.  This will
 680                          * leave the TD on the hardware ring, and the hardware
 681                          * will try to execute it, and may access a buffer
 682                          * that has already been freed.  In the best case, the
 683                          * hardware will execute it, and the event handler will
 684                          * ignore the completion event for that TD, since it was
 685                          * removed from the td_list for that endpoint.  In
 686                          * short, don't muck with the stream ID after
 687                          * submission.
 688                          */
 689                         xhci_warn(xhci, "WARN Cancelled URB %p "
 690                                         "has invalid stream ID %u.\n",
 691                                         cur_td->urb,
 692                                         cur_td->urb->stream_id);
 693                         goto remove_finished_td;
 694                 }
 695                 /*
 696                  * If we stopped on the TD we need to cancel, then we have to
 697                  * move the xHC endpoint ring dequeue pointer past this TD.
 698                  */
 699                 if (cur_td == ep->stopped_td)
 700                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 701                                         cur_td->urb->stream_id,
 702                                         cur_td, &deq_state);
 703                 else
 704                         td_to_noop(xhci, ep_ring, cur_td);
 705 remove_finished_td:
 706                 /*
 707                  * The event handler won't see a completion for this TD anymore,
 708                  * so remove it from the endpoint ring's TD list.  Keep it in
 709                  * the cancelled TD list for URB completion later.
 710                  */
 711                 list_del(&cur_td->td_list);
 712         }
 713         last_unlinked_td = cur_td;
 714         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 715
 716         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 717         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 718                 xhci_queue_new_dequeue_state(xhci,
 719                                 slot_id, ep_index,
 720                                 ep->stopped_td->urb->stream_id,
 721                                 &deq_state);
 722                 xhci_ring_cmd_db(xhci);
 723         } else {
 724                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 725                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 726         }
 727         ep->stopped_td = NULL;
 728         ep->stopped_trb = NULL;
 729
 730         /*
 731          * Drop the lock and complete the URBs in the cancelled TD list.
 732          * New TDs to be cancelled might be added to the end of the list before
 733          * we can complete all the URBs for the TDs we already unlinked.
 734          * So stop when we've completed the URB for the last TD we unlinked.
 735          */
 736         do {
 737                 cur_td = list_entry(ep->cancelled_td_list.next,
 738                                 struct xhci_td, cancelled_td_list);
 739                 list_del(&cur_td->cancelled_td_list);
 740
 741                 /* Clean up the cancelled URB */
 742                 /* Doesn't matter what we pass for status, since the core will
 743                  * just overwrite it (because the URB has been unlinked).
 744                  */
 745                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 746
 747                 /* Stop processing the cancelled list if the watchdog timer is
 748                  * running.
 749                  */
 750                 if (xhci->xhc_state & XHCI_STATE_DYING)
 751                         return;
 752         } while (cur_td != last_unlinked_td);
 753
 754         /* Return to the event handler with xhci->lock re-acquired */
 755 }
 756
 757 /* Watchdog timer function for when a stop endpoint command fails to complete.
 758  * In this case, we assume the host controller is broken or dying or dead.  The
 759  * host may still be completing some other events, so we have to be careful to
 760  * let the event ring handler and the URB dequeueing/enqueueing functions know
 761  * through xhci->state.
 762  *
 763  * The timer may also fire if the host takes a very long time to respond to the
 764  * command, and the stop endpoint command completion handler cannot delete the
 765  * timer before the timer function is called.  Another endpoint cancellation may
 766  * sneak in before the timer function can grab the lock, and that may queue
 767  * another stop endpoint command and add the timer back.  So we cannot use a
 768  * simple flag to say whether there is a pending stop endpoint command for a
 769  * particular endpoint.
 770  *
 771  * Instead we use a combination of that flag and a counter for the number of
 772  * pending stop endpoint commands.  If the timer is the tail end of the last
 773  * stop endpoint command, and the endpoint's command is still pending, we assume
 774  * the host is dying.
 775  */
 776 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 777 {
 778         struct xhci_hcd *xhci;
 779         struct xhci_virt_ep *ep;
 780         struct xhci_virt_ep *temp_ep;
 781         struct xhci_ring *ring;
 782         struct xhci_td *cur_td;
 783         int ret, i, j;
 784
 785         ep = (struct xhci_virt_ep *) arg;
 786         xhci = ep->xhci;
 787
 788         spin_lock(&xhci->lock);
 789
 790         ep->stop_cmds_pending--;
 791         if (xhci->xhc_state & XHCI_STATE_DYING) {
 792                 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 793                                 "xHCI as DYING, exiting.\n");
 794                 spin_unlock(&xhci->lock);
 795                 return;
 796         }
 797         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 798                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 799                                 "exiting.\n");
 800                 spin_unlock(&xhci->lock);
 801                 return;
 802         }
 803
 804         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 805         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 806         /* Oops, HC is dead or dying or at least not responding to the stop
 807          * endpoint command.
 808          */
 809         xhci->xhc_state |= XHCI_STATE_DYING;
 810         /* Disable interrupts from the host controller and start halting it */
 811         xhci_quiesce(xhci);
 812         spin_unlock(&xhci->lock);
 813
 814         ret = xhci_halt(xhci);
 815
 816         spin_lock(&xhci->lock);
 817         if (ret < 0) {
 818                 /* This is bad; the host is not responding to commands and it's
 819                  * not allowing itself to be halted.  At least interrupts are
 820                  * disabled. If we call usb_hc_died(), it will attempt to
 821                  * disconnect all device drivers under this host.  Those
 822                  * disconnect() methods will wait for all URBs to be unlinked,
 823                  * so we must complete them.
 824                  */
 825                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 826                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 827                 /* We could turn all TDs on the rings to no-ops.  This won't
 828                  * help if the host has cached part of the ring, and is slow if
 829                  * we want to preserve the cycle bit.  Skip it and hope the host
 830                  * doesn't touch the memory.
 831                  */
 832         }
 833         for (i = 0; i < MAX_HC_SLOTS; i++) {
 834                 if (!xhci->devs[i])
 835                         continue;
 836                 for (j = 0; j < 31; j++) {
 837                         temp_ep = &xhci->devs[i]->eps[j];
 838                         ring = temp_ep->ring;
 839                         if (!ring)
 840                                 continue;
 841                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 842                                         "ep index %u\n", i, j);
 843                         while (!list_empty(&ring->td_list)) {
 844                                 cur_td = list_first_entry(&ring->td_list,
 845                                                 struct xhci_td,
 846                                                 td_list);
 847                                 list_del(&cur_td->td_list);
 848                                 if (!list_empty(&cur_td->cancelled_td_list))
 849                                         list_del(&cur_td->cancelled_td_list);
 850                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 851                                                 -ESHUTDOWN, "killed");
 852                         }
 853                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 854                                 cur_td = list_first_entry(
 855                                                 &temp_ep->cancelled_td_list,
 856                                                 struct xhci_td,
 857                                                 cancelled_td_list);
 858                                 list_del(&cur_td->cancelled_td_list);
 859                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 860                                                 -ESHUTDOWN, "killed");
 861                         }
 862                 }
 863         }
 864         spin_unlock(&xhci->lock);
 865         xhci_dbg(xhci, "Calling usb_hc_died()\n");
 866         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 867         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 868 }
 869
 870 /*
 871  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
 872  * we need to clear the set deq pending flag in the endpoint ring state, so that
 873  * the TD queueing code can ring the doorbell again.  We also need to ring the
 874  * endpoint doorbell to restart the ring, but only if there aren't more
 875  * cancellations pending.
 876  */
 877 static void handle_set_deq_completion(struct xhci_hcd *xhci,
 878                 struct xhci_event_cmd *event,
 879                 union xhci_trb *trb)
 880 {
 881         unsigned int slot_id;
 882         unsigned int ep_index;
 883         unsigned int stream_id;
 884         struct xhci_ring *ep_ring;
 885         struct xhci_virt_device *dev;
 886         struct xhci_ep_ctx *ep_ctx;
 887         struct xhci_slot_ctx *slot_ctx;
 888
 889         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 890         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 891         stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
 892         dev = xhci->devs[slot_id];
 893
 894         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
 895         if (!ep_ring) {
 896                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
 897                                 "freed stream ID %u\n",
 898                                 stream_id);
 899                 /* XXX: Harmless??? */
 900                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 901                 return;
 902         }
 903
 904         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 905         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
 906
 907         if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
 908                 unsigned int ep_state;
 909                 unsigned int slot_state;
 910
 911                 switch (GET_COMP_CODE(event->status)) {
 912                 case COMP_TRB_ERR:
 913                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
 914                                         "of stream ID configuration\n");
 915                         break;
 916                 case COMP_CTX_STATE:
 917                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
 918                                         "to incorrect slot or ep state.\n");
 919                         ep_state = ep_ctx->ep_info;
 920                         ep_state &= EP_STATE_MASK;
 921                         slot_state = slot_ctx->dev_state;
 922                         slot_state = GET_SLOT_STATE(slot_state);
 923                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
 924                                         slot_state, ep_state);
 925                         break;
 926                 case COMP_EBADSLT:
 927                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
 928                                         "slot %u was not enabled.\n", slot_id);
 929                         break;
 930                 default:
 931                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
 932                                         "completion code of %u.\n",
 933                                         GET_COMP_CODE(event->status));
 934                         break;
 935                 }
 936                 /* OK what do we do now?  The endpoint state is hosed, and we
 937                  * should never get to this point if the synchronization between
 938                  * queueing, and endpoint state are correct.  This might happen
 939                  * if the device gets disconnected after we've finished
 940                  * cancelling URBs, which might not be an error...
 941                  */
 942         } else {
 943                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
 944                                 ep_ctx->deq);
 945                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
 946                                         dev->eps[ep_index].queued_deq_ptr) ==
 947                                 (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
 948                         /* Update the ring's dequeue segment and dequeue pointer
 949                          * to reflect the new position.
 950                          */
 951                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
 952                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
 953                 } else {
 954                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
 955                                         "Ptr command & xHCI internal state.\n");
 956                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
 957                                         dev->eps[ep_index].queued_deq_seg,
 958                                         dev->eps[ep_index].queued_deq_ptr);
 959                 }
 960         }
 961
 962         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
 963         dev->eps[ep_index].queued_deq_seg = NULL;
 964         dev->eps[ep_index].queued_deq_ptr = NULL;
 965         /* Restart any rings with pending URBs */
 966         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 967 }
 968
 969 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
 970                 struct xhci_event_cmd *event,
 971                 union xhci_trb *trb)
 972 {
 973         int slot_id;
 974         unsigned int ep_index;
 975
 976         slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
 977         ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
 978         /* This command will only fail if the endpoint wasn't halted,
 979          * but we don't care.
 980          */
 981         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
 982                         (unsigned int) GET_COMP_CODE(event->status));
 983
 984         /* HW with the reset endpoint quirk needs to have a configure endpoint
 985          * command complete before the endpoint can be used.  Queue that here
 986          * because the HW can't handle two commands being queued in a row.
 987          */
 988         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
 989                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
 990                 xhci_queue_configure_endpoint(xhci,
 991                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
 992                                 false);
 993                 xhci_ring_cmd_db(xhci);
 994         } else {
 995                 /* Clear our internal halted state and restart the ring(s) */
 996                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
 997                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 998         }
 999 }
1000
1001 /* Check to see if a command in the device's command queue matches this one.
1002  * Signal the completion or free the command, and return 1.  Return 0 if the
1003  * completed command isn't at the head of the command list.
1004  */
1005 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1006                 struct xhci_virt_device *virt_dev,
1007                 struct xhci_event_cmd *event)
1008 {
1009         struct xhci_command *command;
1010
1011         if (list_empty(&virt_dev->cmd_list))
1012                 return 0;
1013
1014         command = list_entry(virt_dev->cmd_list.next,
1015                         struct xhci_command, cmd_list);
1016         if (xhci->cmd_ring->dequeue != command->command_trb)
1017                 return 0;
1018
1019         command->status =
1020                 GET_COMP_CODE(event->status);
1021         list_del(&command->cmd_list);
1022         if (command->completion)
1023                 complete(command->completion);
1024         else
1025                 xhci_free_command(xhci, command);
1026         return 1;
1027 }
1028
1029 static void handle_cmd_completion(struct xhci_hcd *xhci,
1030                 struct xhci_event_cmd *event)
1031 {
1032         int slot_id = TRB_TO_SLOT_ID(event->flags);
1033         u64 cmd_dma;
1034         dma_addr_t cmd_dequeue_dma;
1035         struct xhci_input_control_ctx *ctrl_ctx;
1036         struct xhci_virt_device *virt_dev;
1037         unsigned int ep_index;
1038         struct xhci_ring *ep_ring;
1039         unsigned int ep_state;
1040
1041         cmd_dma = event->cmd_trb;
1042         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1043                         xhci->cmd_ring->dequeue);
1044         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1045         if (cmd_dequeue_dma == 0) {
1046                 xhci->error_bitmask |= 1 << 4;
1047                 return;
1048         }
1049         /* Does the DMA address match our internal dequeue pointer address? */
1050         if (cmd_dma != (u64) cmd_dequeue_dma) {
1051                 xhci->error_bitmask |= 1 << 5;
1052                 return;
1053         }
1054         switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
1055         case TRB_TYPE(TRB_ENABLE_SLOT):
1056                 if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
1057                         xhci->slot_id = slot_id;
1058                 else
1059                         xhci->slot_id = 0;
1060                 complete(&xhci->addr_dev);
1061                 break;
1062         case TRB_TYPE(TRB_DISABLE_SLOT):
1063                 if (xhci->devs[slot_id])
1064                         xhci_free_virt_device(xhci, slot_id);
1065                 break;
1066         case TRB_TYPE(TRB_CONFIG_EP):
1067                 virt_dev = xhci->devs[slot_id];
1068                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1069                         break;
1070                 /*
1071                  * Configure endpoint commands can come from the USB core
1072                  * configuration or alt setting changes, or because the HW
1073                  * needed an extra configure endpoint command after a reset
1074                  * endpoint command or streams were being configured.
1075                  * If the command was for a halted endpoint, the xHCI driver
1076                  * is not waiting on the configure endpoint command.
1077                  */
1078                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1079                                 virt_dev->in_ctx);
1080                 /* Input ctx add_flags are the endpoint index plus one */
1081                 ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
1082                 /* A usb_set_interface() call directly after clearing a halted
1083                  * condition may race on this quirky hardware.  Not worth
1084                  * worrying about, since this is prototype hardware.  Not sure
1085                  * if this will work for streams, but streams support was
1086                  * untested on this prototype.
1087                  */
1088                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1089                                 ep_index != (unsigned int) -1 &&
1090                                 ctrl_ctx->add_flags - SLOT_FLAG ==
1091                                         ctrl_ctx->drop_flags) {
1092                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1093                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1094                         if (!(ep_state & EP_HALTED))
1095                                 goto bandwidth_change;
1096                         xhci_dbg(xhci, "Completed config ep cmd - "
1097                                         "last ep index = %d, state = %d\n",
1098                                         ep_index, ep_state);
1099                         /* Clear internal halted state and restart ring(s) */
1100                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1101                                 ~EP_HALTED;
1102                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1103                         break;
1104                 }
1105 bandwidth_change:
1106                 xhci_dbg(xhci, "Completed config ep cmd\n");
1107                 xhci->devs[slot_id]->cmd_status =
1108                         GET_COMP_CODE(event->status);
1109                 complete(&xhci->devs[slot_id]->cmd_completion);
1110                 break;
1111         case TRB_TYPE(TRB_EVAL_CONTEXT):
1112                 virt_dev = xhci->devs[slot_id];
1113                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1114                         break;
1115                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1116                 complete(&xhci->devs[slot_id]->cmd_completion);
1117                 break;
1118         case TRB_TYPE(TRB_ADDR_DEV):
1119                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
1120                 complete(&xhci->addr_dev);
1121                 break;
1122         case TRB_TYPE(TRB_STOP_RING):
1123                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1124                 break;
1125         case TRB_TYPE(TRB_SET_DEQ):
1126                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1127                 break;
1128         case TRB_TYPE(TRB_CMD_NOOP):
1129                 break;
1130         case TRB_TYPE(TRB_RESET_EP):
1131                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1132                 break;
1133         case TRB_TYPE(TRB_RESET_DEV):
1134                 xhci_dbg(xhci, "Completed reset device command.\n");
1135                 slot_id = TRB_TO_SLOT_ID(
1136                                 xhci->cmd_ring->dequeue->generic.field[3]);
1137                 virt_dev = xhci->devs[slot_id];
1138                 if (virt_dev)
1139                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1140                 else
1141                         xhci_warn(xhci, "Reset device command completion "
1142                                         "for disabled slot %u\n", slot_id);
1143                 break;
1144         case TRB_TYPE(TRB_NEC_GET_FW):
1145                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1146                         xhci->error_bitmask |= 1 << 6;
1147                         break;
1148                 }
1149                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1150                                 NEC_FW_MAJOR(event->status),
1151                                 NEC_FW_MINOR(event->status));
1152                 break;
1153         default:
1154                 /* Skip over unknown commands on the event ring */
1155                 xhci->error_bitmask |= 1 << 6;
1156                 break;
1157         }
1158         inc_deq(xhci, xhci->cmd_ring, false);
1159 }
1160
1161 static void handle_vendor_event(struct xhci_hcd *xhci,
1162                 union xhci_trb *event)
1163 {
1164         u32 trb_type;
1165
1166         trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
1167         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1168         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1169                 handle_cmd_completion(xhci, &event->event_cmd);
1170 }
1171
1172 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1173  * port registers -- USB 3.0 and USB 2.0).
1174  *
1175  * Returns a zero-based port number, which is suitable for indexing into each of
1176  * the split roothubs' port arrays and bus state arrays.
1177  */
1178 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1179                 struct xhci_hcd *xhci, u32 port_id)
1180 {
1181         unsigned int i;
1182         unsigned int num_similar_speed_ports = 0;
1183
1184         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1185          * and usb2_ports are 0-based indexes.  Count the number of similar
1186          * speed ports, up to 1 port before this port.
1187          */
1188         for (i = 0; i < (port_id - 1); i++) {
1189                 u8 port_speed = xhci->port_array[i];
1190
1191                 /*
1192                  * Skip ports that don't have known speeds, or have duplicate
1193                  * Extended Capabilities port speed entries.
1194                  */
1195                 if (port_speed == 0 || port_speed == -1)
1196                         continue;
1197
1198                 /*
1199                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1200                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1201                  * matches the device speed, it's a similar speed port.
1202                  */
1203                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1204                         num_similar_speed_ports++;
1205         }
1206         return num_similar_speed_ports;
1207 }
1208
1209 static void handle_port_status(struct xhci_hcd *xhci,
1210                 union xhci_trb *event)
1211 {
1212         struct usb_hcd *hcd;
1213         u32 port_id;
1214         u32 temp, temp1;
1215         int max_ports;
1216         int slot_id;
1217         unsigned int faked_port_index;
1218         u8 major_revision;
1219         struct xhci_bus_state *bus_state;
1220         u32 __iomem **port_array;
1221
1222         /* Port status change events always have a successful completion code */
1223         if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
1224                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1225                 xhci->error_bitmask |= 1 << 8;
1226         }
1227         port_id = GET_PORT_ID(event->generic.field[0]);
1228         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1229
1230         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1231         if ((port_id <= 0) || (port_id > max_ports)) {
1232                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1233                 goto cleanup;
1234         }
1235
1236         /* Figure out which usb_hcd this port is attached to:
1237          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1238          */
1239         major_revision = xhci->port_array[port_id - 1];
1240         if (major_revision == 0) {
1241                 xhci_warn(xhci, "Event for port %u not in "
1242                                 "Extended Capabilities, ignoring.\n",
1243                                 port_id);
1244                 goto cleanup;
1245         }
1246         if (major_revision == (u8) -1) {
1247                 xhci_warn(xhci, "Event for port %u duplicated in"
1248                                 "Extended Capabilities, ignoring.\n",
1249                                 port_id);
1250                 goto cleanup;
1251         }
1252
1253         /*
1254          * Hardware port IDs reported by a Port Status Change Event include USB
1255          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1256          * resume event, but we first need to translate the hardware port ID
1257          * into the index into the ports on the correct split roothub, and the
1258          * correct bus_state structure.
1259          */
1260         /* Find the right roothub. */
1261         hcd = xhci_to_hcd(xhci);
1262         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1263                 hcd = xhci->shared_hcd;
1264         bus_state = &xhci->bus_state[hcd_index(hcd)];
1265         if (hcd->speed == HCD_USB3)
1266                 port_array = xhci->usb3_ports;
1267         else
1268                 port_array = xhci->usb2_ports;
1269         /* Find the faked port hub number */
1270         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1271                         port_id);
1272
1273         temp = xhci_readl(xhci, port_array[faked_port_index]);
1274         if (hcd->state == HC_STATE_SUSPENDED) {
1275                 xhci_dbg(xhci, "resume root hub\n");
1276                 usb_hcd_resume_root_hub(hcd);
1277         }
1278
1279         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1280                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1281
1282                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1283                 if (!(temp1 & CMD_RUN)) {
1284                         xhci_warn(xhci, "xHC is not running.\n");
1285                         goto cleanup;
1286                 }
1287
1288                 if (DEV_SUPERSPEED(temp)) {
1289                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1290                         temp = xhci_port_state_to_neutral(temp);
1291                         temp &= ~PORT_PLS_MASK;
1292                         temp |= PORT_LINK_STROBE | XDEV_U0;
1293                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1294                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1295                                         faked_port_index);
1296                         if (!slot_id) {
1297                                 xhci_dbg(xhci, "slot_id is zero\n");
1298                                 goto cleanup;
1299                         }
1300                         xhci_ring_device(xhci, slot_id);
1301                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1302                         /* Clear PORT_PLC */
1303                         temp = xhci_readl(xhci, port_array[faked_port_index]);
1304                         temp = xhci_port_state_to_neutral(temp);
1305                         temp |= PORT_PLC;
1306                         xhci_writel(xhci, temp, port_array[faked_port_index]);
1307                 } else {
1308                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1309                         bus_state->resume_done[faked_port_index] = jiffies +
1310                                 msecs_to_jiffies(20);
1311                         mod_timer(&hcd->rh_timer,
1312                                   bus_state->resume_done[faked_port_index]);
1313                         /* Do the rest in GetPortStatus */
1314                 }
1315         }
1316
1317 cleanup:
1318         /* Update event ring dequeue pointer before dropping the lock */
1319         inc_deq(xhci, xhci->event_ring, true);
1320
1321         spin_unlock(&xhci->lock);
1322         /* Pass this up to the core */
1323         usb_hcd_poll_rh_status(hcd);
1324         spin_lock(&xhci->lock);
1325 }
1326
1327 /*
1328  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1329  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1330  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1331  * returns 0.
1332  */
1333 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1334                 union xhci_trb  *start_trb,
1335                 union xhci_trb  *end_trb,
1336                 dma_addr_t      suspect_dma)
1337 {
1338         dma_addr_t start_dma;
1339         dma_addr_t end_seg_dma;
1340         dma_addr_t end_trb_dma;
1341         struct xhci_segment *cur_seg;
1342
1343         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1344         cur_seg = start_seg;
1345
1346         do {
1347                 if (start_dma == 0)
1348                         return NULL;
1349                 /* We may get an event for a Link TRB in the middle of a TD */
1350                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1351                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1352                 /* If the end TRB isn't in this segment, this is set to 0 */
1353                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1354
1355                 if (end_trb_dma > 0) {
1356                         /* The end TRB is in this segment, so suspect should be here */
1357                         if (start_dma <= end_trb_dma) {
1358                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1359                                         return cur_seg;
1360                         } else {
1361                                 /* Case for one segment with
1362                                  * a TD wrapped around to the top
1363                                  */
1364                                 if ((suspect_dma >= start_dma &&
1365                                                         suspect_dma <= end_seg_dma) ||
1366                                                 (suspect_dma >= cur_seg->dma &&
1367                                                  suspect_dma <= end_trb_dma))
1368                                         return cur_seg;
1369                         }
1370                         return NULL;
1371                 } else {
1372                         /* Might still be somewhere in this segment */
1373                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1374                                 return cur_seg;
1375                 }
1376                 cur_seg = cur_seg->next;
1377                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1378         } while (cur_seg != start_seg);
1379
1380         return NULL;
1381 }
1382
1383 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1384                 unsigned int slot_id, unsigned int ep_index,
1385                 unsigned int stream_id,
1386                 struct xhci_td *td, union xhci_trb *event_trb)
1387 {
1388         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1389         ep->ep_state |= EP_HALTED;
1390         ep->stopped_td = td;
1391         ep->stopped_trb = event_trb;
1392         ep->stopped_stream = stream_id;
1393
1394         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1395         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1396
1397         ep->stopped_td = NULL;
1398         ep->stopped_trb = NULL;
1399         ep->stopped_stream = 0;
1400
1401         xhci_ring_cmd_db(xhci);
1402 }
1403
1404 /* Check if an error has halted the endpoint ring.  The class driver will
1405  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1406  * However, a babble and other errors also halt the endpoint ring, and the class
1407  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1408  * Ring Dequeue Pointer command manually.
1409  */
1410 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1411                 struct xhci_ep_ctx *ep_ctx,
1412                 unsigned int trb_comp_code)
1413 {
1414         /* TRB completion codes that may require a manual halt cleanup */
1415         if (trb_comp_code == COMP_TX_ERR ||
1416                         trb_comp_code == COMP_BABBLE ||
1417                         trb_comp_code == COMP_SPLIT_ERR)
1418                 /* The 0.96 spec says a babbling control endpoint
1419                  * is not halted. The 0.96 spec says it is.  Some HW
1420                  * claims to be 0.95 compliant, but it halts the control
1421                  * endpoint anyway.  Check if a babble halted the
1422                  * endpoint.
1423                  */
1424                 if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
1425                         return 1;
1426
1427         return 0;
1428 }
1429
1430 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1431 {
1432         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1433                 /* Vendor defined "informational" completion code,
1434                  * treat as not-an-error.
1435                  */
1436                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1437                                 trb_comp_code);
1438                 xhci_dbg(xhci, "Treating code as success.\n");
1439                 return 1;
1440         }
1441         return 0;
1442 }
1443
1444 /*
1445  * Finish the td processing, remove the td from td list;
1446  * Return 1 if the urb can be given back.
1447  */
1448 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1449         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1450         struct xhci_virt_ep *ep, int *status, bool skip)
1451 {
1452         struct xhci_virt_device *xdev;
1453         struct xhci_ring *ep_ring;
1454         unsigned int slot_id;
1455         int ep_index;
1456         struct urb *urb = NULL;
1457         struct xhci_ep_ctx *ep_ctx;
1458         int ret = 0;
1459         struct urb_priv *urb_priv;
1460         u32 trb_comp_code;
1461
1462         slot_id = TRB_TO_SLOT_ID(event->flags);
1463         xdev = xhci->devs[slot_id];
1464         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1465         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1466         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1467         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1468
1469         if (skip)
1470                 goto td_cleanup;
1471
1472         if (trb_comp_code == COMP_STOP_INVAL ||
1473                         trb_comp_code == COMP_STOP) {
1474                 /* The Endpoint Stop Command completion will take care of any
1475                  * stopped TDs.  A stopped TD may be restarted, so don't update
1476                  * the ring dequeue pointer or take this TD off any lists yet.
1477                  */
1478                 ep->stopped_td = td;
1479                 ep->stopped_trb = event_trb;
1480                 return 0;
1481         } else {
1482                 if (trb_comp_code == COMP_STALL) {
1483                         /* The transfer is completed from the driver's
1484                          * perspective, but we need to issue a set dequeue
1485                          * command for this stalled endpoint to move the dequeue
1486                          * pointer past the TD.  We can't do that here because
1487                          * the halt condition must be cleared first.  Let the
1488                          * USB class driver clear the stall later.
1489                          */
1490                         ep->stopped_td = td;
1491                         ep->stopped_trb = event_trb;
1492                         ep->stopped_stream = ep_ring->stream_id;
1493                 } else if (xhci_requires_manual_halt_cleanup(xhci,
1494                                         ep_ctx, trb_comp_code)) {
1495                         /* Other types of errors halt the endpoint, but the
1496                          * class driver doesn't call usb_reset_endpoint() unless
1497                          * the error is -EPIPE.  Clear the halted status in the
1498                          * xHCI hardware manually.
1499                          */
1500                         xhci_cleanup_halted_endpoint(xhci,
1501                                         slot_id, ep_index, ep_ring->stream_id,
1502                                         td, event_trb);
1503                 } else {
1504                         /* Update ring dequeue pointer */
1505                         while (ep_ring->dequeue != td->last_trb)
1506                                 inc_deq(xhci, ep_ring, false);
1507                         inc_deq(xhci, ep_ring, false);
1508                 }
1509
1510 td_cleanup:
1511                 /* Clean up the endpoint's TD list */
1512                 urb = td->urb;
1513                 urb_priv = urb->hcpriv;
1514
1515                 /* Do one last check of the actual transfer length.
1516                  * If the host controller said we transferred more data than
1517                  * the buffer length, urb->actual_length will be a very big
1518                  * number (since it's unsigned).  Play it safe and say we didn't
1519                  * transfer anything.
1520                  */
1521                 if (urb->actual_length > urb->transfer_buffer_length) {
1522                         xhci_warn(xhci, "URB transfer length is wrong, "
1523                                         "xHC issue? req. len = %u, "
1524                                         "act. len = %u\n",
1525                                         urb->transfer_buffer_length,
1526                                         urb->actual_length);
1527                         urb->actual_length = 0;
1528                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1529                                 *status = -EREMOTEIO;
1530                         else
1531                                 *status = 0;
1532                 }
1533                 list_del(&td->td_list);
1534                 /* Was this TD slated to be cancelled but completed anyway? */
1535                 if (!list_empty(&td->cancelled_td_list))
1536                         list_del(&td->cancelled_td_list);
1537
1538                 urb_priv->td_cnt++;
1539                 /* Giveback the urb when all the tds are completed */
1540                 if (urb_priv->td_cnt == urb_priv->length)
1541                         ret = 1;
1542         }
1543
1544         return ret;
1545 }
1546
1547 /*
1548  * Process control tds, update urb status and actual_length.
1549  */
1550 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1551         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1552         struct xhci_virt_ep *ep, int *status)
1553 {
1554         struct xhci_virt_device *xdev;
1555         struct xhci_ring *ep_ring;
1556         unsigned int slot_id;
1557         int ep_index;
1558         struct xhci_ep_ctx *ep_ctx;
1559         u32 trb_comp_code;
1560
1561         slot_id = TRB_TO_SLOT_ID(event->flags);
1562         xdev = xhci->devs[slot_id];
1563         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1564         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1565         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1566         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1567
1568         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1569         switch (trb_comp_code) {
1570         case COMP_SUCCESS:
1571                 if (event_trb == ep_ring->dequeue) {
1572                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1573                                         "without IOC set??\n");
1574                         *status = -ESHUTDOWN;
1575                 } else if (event_trb != td->last_trb) {
1576                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1577                                         "without IOC set??\n");
1578                         *status = -ESHUTDOWN;
1579                 } else {
1580                         xhci_dbg(xhci, "Successful control transfer!\n");
1581                         *status = 0;
1582                 }
1583                 break;
1584         case COMP_SHORT_TX:
1585                 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1586                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1587                         *status = -EREMOTEIO;
1588                 else
1589                         *status = 0;
1590                 break;
1591         default:
1592                 if (!xhci_requires_manual_halt_cleanup(xhci,
1593                                         ep_ctx, trb_comp_code))
1594                         break;
1595                 xhci_dbg(xhci, "TRB error code %u, "
1596                                 "halted endpoint index = %u\n",
1597                                 trb_comp_code, ep_index);
1598                 /* else fall through */
1599         case COMP_STALL:
1600                 /* Did we transfer part of the data (middle) phase? */
1601                 if (event_trb != ep_ring->dequeue &&
1602                                 event_trb != td->last_trb)
1603                         td->urb->actual_length =
1604                                 td->urb->transfer_buffer_length
1605                                 - TRB_LEN(event->transfer_len);
1606                 else
1607                         td->urb->actual_length = 0;
1608
1609                 xhci_cleanup_halted_endpoint(xhci,
1610                         slot_id, ep_index, 0, td, event_trb);
1611                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1612         }
1613         /*
1614          * Did we transfer any data, despite the errors that might have
1615          * happened?  I.e. did we get past the setup stage?
1616          */
1617         if (event_trb != ep_ring->dequeue) {
1618                 /* The event was for the status stage */
1619                 if (event_trb == td->last_trb) {
1620                         if (td->urb->actual_length != 0) {
1621                                 /* Don't overwrite a previously set error code
1622                                  */
1623                                 if ((*status == -EINPROGRESS || *status == 0) &&
1624                                                 (td->urb->transfer_flags
1625                                                  & URB_SHORT_NOT_OK))
1626                                         /* Did we already see a short data
1627                                          * stage? */
1628                                         *status = -EREMOTEIO;
1629                         } else {
1630                                 td->urb->actual_length =
1631                                         td->urb->transfer_buffer_length;
1632                         }
1633                 } else {
1634                 /* Maybe the event was for the data stage? */
1635                         if (trb_comp_code != COMP_STOP_INVAL) {
1636                                 /* We didn't stop on a link TRB in the middle */
1637                                 td->urb->actual_length =
1638                                         td->urb->transfer_buffer_length -
1639                                         TRB_LEN(event->transfer_len);
1640                                 xhci_dbg(xhci, "Waiting for status "
1641                                                 "stage event\n");
1642                                 return 0;
1643                         }
1644                 }
1645         }
1646
1647         return finish_td(xhci, td, event_trb, event, ep, status, false);
1648 }
1649
1650 /*
1651  * Process isochronous tds, update urb packet status and actual_length.
1652  */
1653 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1654         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1655         struct xhci_virt_ep *ep, int *status)
1656 {
1657         struct xhci_ring *ep_ring;
1658         struct urb_priv *urb_priv;
1659         int idx;
1660         int len = 0;
1661         int skip_td = 0;
1662         union xhci_trb *cur_trb;
1663         struct xhci_segment *cur_seg;
1664         u32 trb_comp_code;
1665
1666         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1667         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1668         urb_priv = td->urb->hcpriv;
1669         idx = urb_priv->td_cnt;
1670
1671         if (ep->skip) {
1672                 /* The transfer is partly done */
1673                 *status = -EXDEV;
1674                 td->urb->iso_frame_desc[idx].status = -EXDEV;
1675         } else {
1676                 /* handle completion code */
1677                 switch (trb_comp_code) {
1678                 case COMP_SUCCESS:
1679                         td->urb->iso_frame_desc[idx].status = 0;
1680                         xhci_dbg(xhci, "Successful isoc transfer!\n");
1681                         break;
1682                 case COMP_SHORT_TX:
1683                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1684                                 td->urb->iso_frame_desc[idx].status =
1685                                          -EREMOTEIO;
1686                         else
1687                                 td->urb->iso_frame_desc[idx].status = 0;
1688                         break;
1689                 case COMP_BW_OVER:
1690                         td->urb->iso_frame_desc[idx].status = -ECOMM;
1691                         skip_td = 1;
1692                         break;
1693                 case COMP_BUFF_OVER:
1694                 case COMP_BABBLE:
1695                         td->urb->iso_frame_desc[idx].status = -EOVERFLOW;
1696                         skip_td = 1;
1697                         break;
1698                 case COMP_STALL:
1699                         td->urb->iso_frame_desc[idx].status = -EPROTO;
1700                         skip_td = 1;
1701                         break;
1702                 case COMP_STOP:
1703                 case COMP_STOP_INVAL:
1704                         break;
1705                 default:
1706                         td->urb->iso_frame_desc[idx].status = -1;
1707                         break;
1708                 }
1709         }
1710
1711         /* calc actual length */
1712         if (ep->skip) {
1713                 td->urb->iso_frame_desc[idx].actual_length = 0;
1714                 /* Update ring dequeue pointer */
1715                 while (ep_ring->dequeue != td->last_trb)
1716                         inc_deq(xhci, ep_ring, false);
1717                 inc_deq(xhci, ep_ring, false);
1718                 return finish_td(xhci, td, event_trb, event, ep, status, true);
1719         }
1720
1721         if (trb_comp_code == COMP_SUCCESS || skip_td == 1) {
1722                 td->urb->iso_frame_desc[idx].actual_length =
1723                         td->urb->iso_frame_desc[idx].length;
1724                 td->urb->actual_length +=
1725                         td->urb->iso_frame_desc[idx].length;
1726         } else {
1727                 for (cur_trb = ep_ring->dequeue,
1728                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1729                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1730                         if ((cur_trb->generic.field[3] &
1731                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1732                             (cur_trb->generic.field[3] &
1733                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1734                                 len +=
1735                                     TRB_LEN(cur_trb->generic.field[2]);
1736                 }
1737                 len += TRB_LEN(cur_trb->generic.field[2]) -
1738                         TRB_LEN(event->transfer_len);
1739
1740                 if (trb_comp_code != COMP_STOP_INVAL) {
1741                         td->urb->iso_frame_desc[idx].actual_length = len;
1742                         td->urb->actual_length += len;
1743                 }
1744         }
1745
1746         if ((idx == urb_priv->length - 1) && *status == -EINPROGRESS)
1747                 *status = 0;
1748
1749         return finish_td(xhci, td, event_trb, event, ep, status, false);
1750 }
1751
1752 /*
1753  * Process bulk and interrupt tds, update urb status and actual_length.
1754  */
1755 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1756         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1757         struct xhci_virt_ep *ep, int *status)
1758 {
1759         struct xhci_ring *ep_ring;
1760         union xhci_trb *cur_trb;
1761         struct xhci_segment *cur_seg;
1762         u32 trb_comp_code;
1763
1764         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1765         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1766
1767         switch (trb_comp_code) {
1768         case COMP_SUCCESS:
1769                 /* Double check that the HW transferred everything. */
1770                 if (event_trb != td->last_trb) {
1771                         xhci_warn(xhci, "WARN Successful completion "
1772                                         "on short TX\n");
1773                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1774                                 *status = -EREMOTEIO;
1775                         else
1776                                 *status = 0;
1777                 } else {
1778                         if (usb_endpoint_xfer_bulk(&td->urb->ep->desc))
1779                                 xhci_dbg(xhci, "Successful bulk "
1780                                                 "transfer!\n");
1781                         else
1782                                 xhci_dbg(xhci, "Successful interrupt "
1783                                                 "transfer!\n");
1784                         *status = 0;
1785                 }
1786                 break;
1787         case COMP_SHORT_TX:
1788                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1789                         *status = -EREMOTEIO;
1790                 else
1791                         *status = 0;
1792                 break;
1793         default:
1794                 /* Others already handled above */
1795                 break;
1796         }
1797         xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1798                         "%d bytes untransferred\n",
1799                         td->urb->ep->desc.bEndpointAddress,
1800                         td->urb->transfer_buffer_length,
1801                         TRB_LEN(event->transfer_len));
1802         /* Fast path - was this the last TRB in the TD for this URB? */
1803         if (event_trb == td->last_trb) {
1804                 if (TRB_LEN(event->transfer_len) != 0) {
1805                         td->urb->actual_length =
1806                                 td->urb->transfer_buffer_length -
1807                                 TRB_LEN(event->transfer_len);
1808                         if (td->urb->transfer_buffer_length <
1809                                         td->urb->actual_length) {
1810                                 xhci_warn(xhci, "HC gave bad length "
1811                                                 "of %d bytes left\n",
1812                                                 TRB_LEN(event->transfer_len));
1813                                 td->urb->actual_length = 0;
1814                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1815                                         *status = -EREMOTEIO;
1816                                 else
1817                                         *status = 0;
1818                         }
1819                         /* Don't overwrite a previously set error code */
1820                         if (*status == -EINPROGRESS) {
1821                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1822                                         *status = -EREMOTEIO;
1823                                 else
1824                                         *status = 0;
1825                         }
1826                 } else {
1827                         td->urb->actual_length =
1828                                 td->urb->transfer_buffer_length;
1829                         /* Ignore a short packet completion if the
1830                          * untransferred length was zero.
1831                          */
1832                         if (*status == -EREMOTEIO)
1833                                 *status = 0;
1834                 }
1835         } else {
1836                 /* Slow path - walk the list, starting from the dequeue
1837                  * pointer, to get the actual length transferred.
1838                  */
1839                 td->urb->actual_length = 0;
1840                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1841                                 cur_trb != event_trb;
1842                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
1843                         if ((cur_trb->generic.field[3] &
1844                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
1845                             (cur_trb->generic.field[3] &
1846                          TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
1847                                 td->urb->actual_length +=
1848                                         TRB_LEN(cur_trb->generic.field[2]);
1849                 }
1850                 /* If the ring didn't stop on a Link or No-op TRB, add
1851                  * in the actual bytes transferred from the Normal TRB
1852                  */
1853                 if (trb_comp_code != COMP_STOP_INVAL)
1854                         td->urb->actual_length +=
1855                                 TRB_LEN(cur_trb->generic.field[2]) -
1856                                 TRB_LEN(event->transfer_len);
1857         }
1858
1859         return finish_td(xhci, td, event_trb, event, ep, status, false);
1860 }
1861
1862 /*
1863  * If this function returns an error condition, it means it got a Transfer
1864  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1865  * At this point, the host controller is probably hosed and should be reset.
1866  */
1867 static int handle_tx_event(struct xhci_hcd *xhci,
1868                 struct xhci_transfer_event *event)
1869 {
1870         struct xhci_virt_device *xdev;
1871         struct xhci_virt_ep *ep;
1872         struct xhci_ring *ep_ring;
1873         unsigned int slot_id;
1874         int ep_index;
1875         struct xhci_td *td = NULL;
1876         dma_addr_t event_dma;
1877         struct xhci_segment *event_seg;
1878         union xhci_trb *event_trb;
1879         struct urb *urb = NULL;
1880         int status = -EINPROGRESS;
1881         struct urb_priv *urb_priv;
1882         struct xhci_ep_ctx *ep_ctx;
1883         u32 trb_comp_code;
1884         int ret = 0;
1885
1886         slot_id = TRB_TO_SLOT_ID(event->flags);
1887         xdev = xhci->devs[slot_id];
1888         if (!xdev) {
1889                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1890                 return -ENODEV;
1891         }
1892
1893         /* Endpoint ID is 1 based, our index is zero based */
1894         ep_index = TRB_TO_EP_ID(event->flags) - 1;
1895         xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
1896         ep = &xdev->eps[ep_index];
1897         ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
1898         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1899         if (!ep_ring ||
1900                 (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
1901                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1902                                 "or incorrect stream ring\n");
1903                 return -ENODEV;
1904         }
1905
1906         event_dma = event->buffer;
1907         trb_comp_code = GET_COMP_CODE(event->transfer_len);
1908         /* Look for common error cases */
1909         switch (trb_comp_code) {
1910         /* Skip codes that require special handling depending on
1911          * transfer type
1912          */
1913         case COMP_SUCCESS:
1914         case COMP_SHORT_TX:
1915                 break;
1916         case COMP_STOP:
1917                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1918                 break;
1919         case COMP_STOP_INVAL:
1920                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1921                 break;
1922         case COMP_STALL:
1923                 xhci_warn(xhci, "WARN: Stalled endpoint\n");
1924                 ep->ep_state |= EP_HALTED;
1925                 status = -EPIPE;
1926                 break;
1927         case COMP_TRB_ERR:
1928                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1929                 status = -EILSEQ;
1930                 break;
1931         case COMP_SPLIT_ERR:
1932         case COMP_TX_ERR:
1933                 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1934                 status = -EPROTO;
1935                 break;
1936         case COMP_BABBLE:
1937                 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1938                 status = -EOVERFLOW;
1939                 break;
1940         case COMP_DB_ERR:
1941                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1942                 status = -ENOSR;
1943                 break;
1944         case COMP_BW_OVER:
1945                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
1946                 break;
1947         case COMP_BUFF_OVER:
1948                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
1949                 break;
1950         case COMP_UNDERRUN:
1951                 /*
1952                  * When the Isoch ring is empty, the xHC will generate
1953                  * a Ring Overrun Event for IN Isoch endpoint or Ring
1954                  * Underrun Event for OUT Isoch endpoint.
1955                  */
1956                 xhci_dbg(xhci, "underrun event on endpoint\n");
1957                 if (!list_empty(&ep_ring->td_list))
1958                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
1959                                         "still with TDs queued?\n",
1960                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1961                 goto cleanup;
1962         case COMP_OVERRUN:
1963                 xhci_dbg(xhci, "overrun event on endpoint\n");
1964                 if (!list_empty(&ep_ring->td_list))
1965                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
1966                                         "still with TDs queued?\n",
1967                                 TRB_TO_SLOT_ID(event->flags), ep_index);
1968                 goto cleanup;
1969         case COMP_MISSED_INT:
1970                 /*
1971                  * When encounter missed service error, one or more isoc tds
1972                  * may be missed by xHC.
1973                  * Set skip flag of the ep_ring; Complete the missed tds as
1974                  * short transfer when process the ep_ring next time.
1975                  */
1976                 ep->skip = true;
1977                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
1978                 goto cleanup;
1979         default:
1980                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
1981                         status = 0;
1982                         break;
1983                 }
1984                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
1985                                 "busted\n");
1986                 goto cleanup;
1987         }
1988
1989         do {
1990                 /* This TRB should be in the TD at the head of this ring's
1991                  * TD list.
1992                  */
1993                 if (list_empty(&ep_ring->td_list)) {
1994                         xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
1995                                         "with no TDs queued?\n",
1996                                   TRB_TO_SLOT_ID(event->flags), ep_index);
1997                         xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
1998                           (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
1999                         xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2000                         if (ep->skip) {
2001                                 ep->skip = false;
2002                                 xhci_dbg(xhci, "td_list is empty while skip "
2003                                                 "flag set. Clear skip flag.\n");
2004                         }
2005                         ret = 0;
2006                         goto cleanup;
2007                 }
2008
2009                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2010                 /* Is this a TRB in the currently executing TD? */
2011                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2012                                 td->last_trb, event_dma);
2013                 if (event_seg && ep->skip) {
2014                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2015                         ep->skip = false;
2016                 }
2017                 if (!event_seg &&
2018                    (!ep->skip || !usb_endpoint_xfer_isoc(&td->urb->ep->desc))) {
2019                         /* HC is busted, give up! */
2020                         xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not "
2021                                         "part of current TD\n");
2022                         return -ESHUTDOWN;
2023                 }
2024
2025                 if (event_seg) {
2026                         event_trb = &event_seg->trbs[(event_dma -
2027                                          event_seg->dma) / sizeof(*event_trb)];
2028                         /*
2029                          * No-op TRB should not trigger interrupts.
2030                          * If event_trb is a no-op TRB, it means the
2031                          * corresponding TD has been cancelled. Just ignore
2032                          * the TD.
2033                          */
2034                         if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
2035                                          == TRB_TYPE(TRB_TR_NOOP)) {
2036                                 xhci_dbg(xhci, "event_trb is a no-op TRB. "
2037                                                 "Skip it\n");
2038                                 goto cleanup;
2039                         }
2040                 }
2041
2042                 /* Now update the urb's actual_length and give back to
2043                  * the core
2044                  */
2045                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2046                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2047                                                  &status);
2048                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2049                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2050                                                  &status);
2051                 else
2052                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2053                                                  ep, &status);
2054
2055 cleanup:
2056                 /*
2057                  * Do not update event ring dequeue pointer if ep->skip is set.
2058                  * Will roll back to continue process missed tds.
2059                  */
2060                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2061                         inc_deq(xhci, xhci->event_ring, true);
2062                 }
2063
2064                 if (ret) {
2065                         urb = td->urb;
2066                         urb_priv = urb->hcpriv;
2067                         /* Leave the TD around for the reset endpoint function
2068                          * to use(but only if it's not a control endpoint,
2069                          * since we already queued the Set TR dequeue pointer
2070                          * command for stalled control endpoints).
2071                          */
2072                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2073                                 (trb_comp_code != COMP_STALL &&
2074                                         trb_comp_code != COMP_BABBLE))
2075                                 xhci_urb_free_priv(xhci, urb_priv);
2076
2077                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2078                         xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2079                                         "status = %d\n",
2080                                         urb, urb->actual_length, status);
2081                         spin_unlock(&xhci->lock);
2082                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2083                         spin_lock(&xhci->lock);
2084                 }
2085
2086         /*
2087          * If ep->skip is set, it means there are missed tds on the
2088          * endpoint ring need to take care of.
2089          * Process them as short transfer until reach the td pointed by
2090          * the event.
2091          */
2092         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2093
2094         return 0;
2095 }
2096
2097 /*
2098  * This function handles all OS-owned events on the event ring.  It may drop
2099  * xhci->lock between event processing (e.g. to pass up port status changes).
2100  */
2101 static void xhci_handle_event(struct xhci_hcd *xhci)
2102 {
2103         union xhci_trb *event;
2104         int update_ptrs = 1;
2105         int ret;
2106
2107         xhci_dbg(xhci, "In %s\n", __func__);
2108         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2109                 xhci->error_bitmask |= 1 << 1;
2110                 return;
2111         }
2112
2113         event = xhci->event_ring->dequeue;
2114         /* Does the HC or OS own the TRB? */
2115         if ((event->event_cmd.flags & TRB_CYCLE) !=
2116                         xhci->event_ring->cycle_state) {
2117                 xhci->error_bitmask |= 1 << 2;
2118                 return;
2119         }
2120         xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
2121
2122         /* FIXME: Handle more event types. */
2123         switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
2124         case TRB_TYPE(TRB_COMPLETION):
2125                 xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
2126                 handle_cmd_completion(xhci, &event->event_cmd);
2127                 xhci_dbg(xhci, "%s - returned from handle_cmd_completion\n", __func__);
2128                 break;
2129         case TRB_TYPE(TRB_PORT_STATUS):
2130                 xhci_dbg(xhci, "%s - calling handle_port_status\n", __func__);
2131                 handle_port_status(xhci, event);
2132                 xhci_dbg(xhci, "%s - returned from handle_port_status\n", __func__);
2133                 update_ptrs = 0;
2134                 break;
2135         case TRB_TYPE(TRB_TRANSFER):
2136                 xhci_dbg(xhci, "%s - calling handle_tx_event\n", __func__);
2137                 ret = handle_tx_event(xhci, &event->trans_event);
2138                 xhci_dbg(xhci, "%s - returned from handle_tx_event\n", __func__);
2139                 if (ret < 0)
2140                         xhci->error_bitmask |= 1 << 9;
2141                 else
2142                         update_ptrs = 0;
2143                 break;
2144         default:
2145                 if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
2146                         handle_vendor_event(xhci, event);
2147                 else
2148                         xhci->error_bitmask |= 1 << 3;
2149         }
2150         /* Any of the above functions may drop and re-acquire the lock, so check
2151          * to make sure a watchdog timer didn't mark the host as non-responsive.
2152          */
2153         if (xhci->xhc_state & XHCI_STATE_DYING) {
2154                 xhci_dbg(xhci, "xHCI host dying, returning from "
2155                                 "event handler.\n");
2156                 return;
2157         }
2158
2159         if (update_ptrs)
2160                 /* Update SW event ring dequeue pointer */
2161                 inc_deq(xhci, xhci->event_ring, true);
2162
2163         /* Are there more items on the event ring? */
2164         xhci_handle_event(xhci);
2165 }
2166
2167 /*
2168  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2169  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2170  * indicators of an event TRB error, but we check the status *first* to be safe.
2171  */
2172 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2173 {
2174         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2175         u32 status;
2176         union xhci_trb *trb;
2177         u64 temp_64;
2178         union xhci_trb *event_ring_deq;
2179         dma_addr_t deq;
2180
2181         spin_lock(&xhci->lock);
2182         trb = xhci->event_ring->dequeue;
2183         /* Check if the xHC generated the interrupt, or the irq is shared */
2184         status = xhci_readl(xhci, &xhci->op_regs->status);
2185         if (status == 0xffffffff)
2186                 goto hw_died;
2187
2188         if (!(status & STS_EINT)) {
2189                 spin_unlock(&xhci->lock);
2190                 return IRQ_NONE;
2191         }
2192         xhci_dbg(xhci, "op reg status = %08x\n", status);
2193         xhci_dbg(xhci, "Event ring dequeue ptr:\n");
2194         xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
2195                         (unsigned long long)
2196                         xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
2197                         lower_32_bits(trb->link.segment_ptr),
2198                         upper_32_bits(trb->link.segment_ptr),
2199                         (unsigned int) trb->link.intr_target,
2200                         (unsigned int) trb->link.control);
2201
2202         if (status & STS_FATAL) {
2203                 xhci_warn(xhci, "WARNING: Host System Error\n");
2204                 xhci_halt(xhci);
2205 hw_died:
2206                 spin_unlock(&xhci->lock);
2207                 return -ESHUTDOWN;
2208         }
2209
2210         /*
2211          * Clear the op reg interrupt status first,
2212          * so we can receive interrupts from other MSI-X interrupters.
2213          * Write 1 to clear the interrupt status.
2214          */
2215         status |= STS_EINT;
2216         xhci_writel(xhci, status, &xhci->op_regs->status);
2217         /* FIXME when MSI-X is supported and there are multiple vectors */
2218         /* Clear the MSI-X event interrupt status */
2219
2220         if (hcd->irq != -1) {
2221                 u32 irq_pending;
2222                 /* Acknowledge the PCI interrupt */
2223                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2224                 irq_pending |= 0x3;
2225                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2226         }
2227
2228         if (xhci->xhc_state & XHCI_STATE_DYING) {
2229                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2230                                 "Shouldn't IRQs be disabled?\n");
2231                 /* Clear the event handler busy flag (RW1C);
2232                  * the event ring should be empty.
2233                  */
2234                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2235                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2236                                 &xhci->ir_set->erst_dequeue);
2237                 spin_unlock(&xhci->lock);
2238
2239                 return IRQ_HANDLED;
2240         }
2241
2242         event_ring_deq = xhci->event_ring->dequeue;
2243         /* FIXME this should be a delayed service routine
2244          * that clears the EHB.
2245          */
2246         xhci_handle_event(xhci);
2247
2248         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2249         /* If necessary, update the HW's version of the event ring deq ptr. */
2250         if (event_ring_deq != xhci->event_ring->dequeue) {
2251                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2252                                 xhci->event_ring->dequeue);
2253                 if (deq == 0)
2254                         xhci_warn(xhci, "WARN something wrong with SW event "
2255                                         "ring dequeue ptr.\n");
2256                 /* Update HC event ring dequeue pointer */
2257                 temp_64 &= ERST_PTR_MASK;
2258                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2259         }
2260
2261         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2262         temp_64 |= ERST_EHB;
2263         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2264
2265         spin_unlock(&xhci->lock);
2266
2267         return IRQ_HANDLED;
2268 }
2269
2270 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2271 {
2272         irqreturn_t ret;
2273         struct xhci_hcd *xhci;
2274
2275         xhci = hcd_to_xhci(hcd);
2276         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2277         if (xhci->shared_hcd)
2278                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2279
2280         ret = xhci_irq(hcd);
2281
2282         return ret;
2283 }
2284
2285 /****           Endpoint Ring Operations        ****/
2286
2287 /*
2288  * Generic function for queueing a TRB on a ring.
2289  * The caller must have checked to make sure there's room on the ring.
2290  *
2291  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2292  *                      prepare_transfer()?
2293  */
2294 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2295                 bool consumer, bool more_trbs_coming,
2296                 u32 field1, u32 field2, u32 field3, u32 field4)
2297 {
2298         struct xhci_generic_trb *trb;
2299
2300         trb = &ring->enqueue->generic;
2301         trb->field[0] = field1;
2302         trb->field[1] = field2;
2303         trb->field[2] = field3;
2304         trb->field[3] = field4;
2305         inc_enq(xhci, ring, consumer, more_trbs_coming);
2306 }
2307
2308 /*
2309  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2310  * FIXME allocate segments if the ring is full.
2311  */
2312 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2313                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2314 {
2315         /* Make sure the endpoint has been added to xHC schedule */
2316         xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
2317         switch (ep_state) {
2318         case EP_STATE_DISABLED:
2319                 /*
2320                  * USB core changed config/interfaces without notifying us,
2321                  * or hardware is reporting the wrong state.
2322                  */
2323                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2324                 return -ENOENT;
2325         case EP_STATE_ERROR:
2326                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2327                 /* FIXME event handling code for error needs to clear it */
2328                 /* XXX not sure if this should be -ENOENT or not */
2329                 return -EINVAL;
2330         case EP_STATE_HALTED:
2331                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2332         case EP_STATE_STOPPED:
2333         case EP_STATE_RUNNING:
2334                 break;
2335         default:
2336                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2337                 /*
2338                  * FIXME issue Configure Endpoint command to try to get the HC
2339                  * back into a known state.
2340                  */
2341                 return -EINVAL;
2342         }
2343         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2344                 /* FIXME allocate more room */
2345                 xhci_err(xhci, "ERROR no room on ep ring\n");
2346                 return -ENOMEM;
2347         }
2348
2349         if (enqueue_is_link_trb(ep_ring)) {
2350                 struct xhci_ring *ring = ep_ring;
2351                 union xhci_trb *next;
2352
2353                 xhci_dbg(xhci, "prepare_ring: pointing to link trb\n");
2354                 next = ring->enqueue;
2355
2356                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2357
2358                         /* If we're not dealing with 0.95 hardware,
2359                          * clear the chain bit.
2360                          */
2361                         if (!xhci_link_trb_quirk(xhci))
2362                                 next->link.control &= ~TRB_CHAIN;
2363                         else
2364                                 next->link.control |= TRB_CHAIN;
2365
2366                         wmb();
2367                         next->link.control ^= (u32) TRB_CYCLE;
2368
2369                         /* Toggle the cycle bit after the last ring segment. */
2370                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2371                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2372                                 if (!in_interrupt()) {
2373                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2374                                                 "state for ring %p = %i\n",
2375                                                 ring, (unsigned int)ring->cycle_state);
2376                                 }
2377                         }
2378                         ring->enq_seg = ring->enq_seg->next;
2379                         ring->enqueue = ring->enq_seg->trbs;
2380                         next = ring->enqueue;
2381                 }
2382         }
2383
2384         return 0;
2385 }
2386
2387 static int prepare_transfer(struct xhci_hcd *xhci,
2388                 struct xhci_virt_device *xdev,
2389                 unsigned int ep_index,
2390                 unsigned int stream_id,
2391                 unsigned int num_trbs,
2392                 struct urb *urb,
2393                 unsigned int td_index,
2394                 gfp_t mem_flags)
2395 {
2396         int ret;
2397         struct urb_priv *urb_priv;
2398         struct xhci_td  *td;
2399         struct xhci_ring *ep_ring;
2400         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2401
2402         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2403         if (!ep_ring) {
2404                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2405                                 stream_id);
2406                 return -EINVAL;
2407         }
2408
2409         ret = prepare_ring(xhci, ep_ring,
2410                         ep_ctx->ep_info & EP_STATE_MASK,
2411                         num_trbs, mem_flags);
2412         if (ret)
2413                 return ret;
2414
2415         urb_priv = urb->hcpriv;
2416         td = urb_priv->td[td_index];
2417
2418         INIT_LIST_HEAD(&td->td_list);
2419         INIT_LIST_HEAD(&td->cancelled_td_list);
2420
2421         if (td_index == 0) {
2422                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2423                 if (unlikely(ret)) {
2424                         xhci_urb_free_priv(xhci, urb_priv);
2425                         urb->hcpriv = NULL;
2426                         return ret;
2427                 }
2428         }
2429
2430         td->urb = urb;
2431         /* Add this TD to the tail of the endpoint ring's TD list */
2432         list_add_tail(&td->td_list, &ep_ring->td_list);
2433         td->start_seg = ep_ring->enq_seg;
2434         td->first_trb = ep_ring->enqueue;
2435
2436         urb_priv->td[td_index] = td;
2437
2438         return 0;
2439 }
2440
2441 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2442 {
2443         int num_sgs, num_trbs, running_total, temp, i;
2444         struct scatterlist *sg;
2445
2446         sg = NULL;
2447         num_sgs = urb->num_sgs;
2448         temp = urb->transfer_buffer_length;
2449
2450         xhci_dbg(xhci, "count sg list trbs: \n");
2451         num_trbs = 0;
2452         for_each_sg(urb->sg, sg, num_sgs, i) {
2453                 unsigned int previous_total_trbs = num_trbs;
2454                 unsigned int len = sg_dma_len(sg);
2455
2456                 /* Scatter gather list entries may cross 64KB boundaries */
2457                 running_total = TRB_MAX_BUFF_SIZE -
2458                         (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2459                 if (running_total != 0)
2460                         num_trbs++;
2461
2462                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2463                 while (running_total < sg_dma_len(sg)) {
2464                         num_trbs++;
2465                         running_total += TRB_MAX_BUFF_SIZE;
2466                 }
2467                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2468                                 i, (unsigned long long)sg_dma_address(sg),
2469                                 len, len, num_trbs - previous_total_trbs);
2470
2471                 len = min_t(int, len, temp);
2472                 temp -= len;
2473                 if (temp == 0)
2474                         break;
2475         }
2476         xhci_dbg(xhci, "\n");
2477         if (!in_interrupt())
2478                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2479                                 "num_trbs = %d\n",
2480                                 urb->ep->desc.bEndpointAddress,
2481                                 urb->transfer_buffer_length,
2482                                 num_trbs);
2483         return num_trbs;
2484 }
2485
2486 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2487 {
2488         if (num_trbs != 0)
2489                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2490                                 "TRBs, %d left\n", __func__,
2491                                 urb->ep->desc.bEndpointAddress, num_trbs);
2492         if (running_total != urb->transfer_buffer_length)
2493                 dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2494                                 "queued %#x (%d), asked for %#x (%d)\n",
2495                                 __func__,
2496                                 urb->ep->desc.bEndpointAddress,
2497                                 running_total, running_total,
2498                                 urb->transfer_buffer_length,
2499                                 urb->transfer_buffer_length);
2500 }
2501
2502 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2503                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2504                 struct xhci_generic_trb *start_trb)
2505 {
2506         /*
2507          * Pass all the TRBs to the hardware at once and make sure this write
2508          * isn't reordered.
2509          */
2510         wmb();
2511         if (start_cycle)
2512                 start_trb->field[3] |= start_cycle;
2513         else
2514                 start_trb->field[3] &= ~0x1;
2515         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2516 }
2517
2518 /*
2519  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2520  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2521  * (comprised of sg list entries) can take several service intervals to
2522  * transmit.
2523  */
2524 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2525                 struct urb *urb, int slot_id, unsigned int ep_index)
2526 {
2527         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2528                         xhci->devs[slot_id]->out_ctx, ep_index);
2529         int xhci_interval;
2530         int ep_interval;
2531
2532         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
2533         ep_interval = urb->interval;
2534         /* Convert to microframes */
2535         if (urb->dev->speed == USB_SPEED_LOW ||
2536                         urb->dev->speed == USB_SPEED_FULL)
2537                 ep_interval *= 8;
2538         /* FIXME change this to a warning and a suggestion to use the new API
2539          * to set the polling interval (once the API is added).
2540          */
2541         if (xhci_interval != ep_interval) {
2542                 if (printk_ratelimit())
2543                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
2544                                         " (%d microframe%s) than xHCI "
2545                                         "(%d microframe%s)\n",
2546                                         ep_interval,
2547                                         ep_interval == 1 ? "" : "s",
2548                                         xhci_interval,
2549                                         xhci_interval == 1 ? "" : "s");
2550                 urb->interval = xhci_interval;
2551                 /* Convert back to frames for LS/FS devices */
2552                 if (urb->dev->speed == USB_SPEED_LOW ||
2553                                 urb->dev->speed == USB_SPEED_FULL)
2554                         urb->interval /= 8;
2555         }
2556         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2557 }
2558
2559 /*
2560  * The TD size is the number of bytes remaining in the TD (including this TRB),
2561  * right shifted by 10.
2562  * It must fit in bits 21:17, so it can't be bigger than 31.
2563  */
2564 static u32 xhci_td_remainder(unsigned int remainder)
2565 {
2566         u32 max = (1 << (21 - 17 + 1)) - 1;
2567
2568         if ((remainder >> 10) >= max)
2569                 return max << 17;
2570         else
2571                 return (remainder >> 10) << 17;
2572 }
2573
2574 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2575                 struct urb *urb, int slot_id, unsigned int ep_index)
2576 {
2577         struct xhci_ring *ep_ring;
2578         unsigned int num_trbs;
2579         struct urb_priv *urb_priv;
2580         struct xhci_td *td;
2581         struct scatterlist *sg;
2582         int num_sgs;
2583         int trb_buff_len, this_sg_len, running_total;
2584         bool first_trb;
2585         u64 addr;
2586         bool more_trbs_coming;
2587
2588         struct xhci_generic_trb *start_trb;
2589         int start_cycle;
2590
2591         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2592         if (!ep_ring)
2593                 return -EINVAL;
2594
2595         num_trbs = count_sg_trbs_needed(xhci, urb);
2596         num_sgs = urb->num_sgs;
2597
2598         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
2599                         ep_index, urb->stream_id,
2600                         num_trbs, urb, 0, mem_flags);
2601         if (trb_buff_len < 0)
2602                 return trb_buff_len;
2603
2604         urb_priv = urb->hcpriv;
2605         td = urb_priv->td[0];
2606
2607         /*
2608          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2609          * until we've finished creating all the other TRBs.  The ring's cycle
2610          * state may change as we enqueue the other TRBs, so save it too.
2611          */
2612         start_trb = &ep_ring->enqueue->generic;
2613         start_cycle = ep_ring->cycle_state;
2614
2615         running_total = 0;
2616         /*
2617          * How much data is in the first TRB?
2618          *
2619          * There are three forces at work for TRB buffer pointers and lengths:
2620          * 1. We don't want to walk off the end of this sg-list entry buffer.
2621          * 2. The transfer length that the driver requested may be smaller than
2622          *    the amount of memory allocated for this scatter-gather list.
2623          * 3. TRBs buffers can't cross 64KB boundaries.
2624          */
2625         sg = urb->sg;
2626         addr = (u64) sg_dma_address(sg);
2627         this_sg_len = sg_dma_len(sg);
2628         trb_buff_len = TRB_MAX_BUFF_SIZE -
2629                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2630         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2631         if (trb_buff_len > urb->transfer_buffer_length)
2632                 trb_buff_len = urb->transfer_buffer_length;
2633         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2634                         trb_buff_len);
2635
2636         first_trb = true;
2637         /* Queue the first TRB, even if it's zero-length */
2638         do {
2639                 u32 field = 0;
2640                 u32 length_field = 0;
2641                 u32 remainder = 0;
2642
2643                 /* Don't change the cycle bit of the first TRB until later */
2644                 if (first_trb) {
2645                         first_trb = false;
2646                         if (start_cycle == 0)
2647                                 field |= 0x1;
2648                 } else
2649                         field |= ep_ring->cycle_state;
2650
2651                 /* Chain all the TRBs together; clear the chain bit in the last
2652                  * TRB to indicate it's the last TRB in the chain.
2653                  */
2654                 if (num_trbs > 1) {
2655                         field |= TRB_CHAIN;
2656                 } else {
2657                         /* FIXME - add check for ZERO_PACKET flag before this */
2658                         td->last_trb = ep_ring->enqueue;
2659                         field |= TRB_IOC;
2660                 }
2661                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2662                                 "64KB boundary at %#x, end dma = %#x\n",
2663                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
2664                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2665                                 (unsigned int) addr + trb_buff_len);
2666                 if (TRB_MAX_BUFF_SIZE -
2667                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
2668                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2669                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2670                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2671                                         (unsigned int) addr + trb_buff_len);
2672                 }
2673                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2674                                 running_total) ;
2675                 length_field = TRB_LEN(trb_buff_len) |
2676                         remainder |
2677                         TRB_INTR_TARGET(0);
2678                 if (num_trbs > 1)
2679                         more_trbs_coming = true;
2680                 else
2681                         more_trbs_coming = false;
2682                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2683                                 lower_32_bits(addr),
2684                                 upper_32_bits(addr),
2685                                 length_field,
2686                                 /* We always want to know if the TRB was short,
2687                                  * or we won't get an event when it completes.
2688                                  * (Unless we use event data TRBs, which are a
2689                                  * waste of space and HC resources.)
2690                                  */
2691                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2692                 --num_trbs;
2693                 running_total += trb_buff_len;
2694
2695                 /* Calculate length for next transfer --
2696                  * Are we done queueing all the TRBs for this sg entry?
2697                  */
2698                 this_sg_len -= trb_buff_len;
2699                 if (this_sg_len == 0) {
2700                         --num_sgs;
2701                         if (num_sgs == 0)
2702                                 break;
2703                         sg = sg_next(sg);
2704                         addr = (u64) sg_dma_address(sg);
2705                         this_sg_len = sg_dma_len(sg);
2706                 } else {
2707                         addr += trb_buff_len;
2708                 }
2709
2710                 trb_buff_len = TRB_MAX_BUFF_SIZE -
2711                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2712                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2713                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2714                         trb_buff_len =
2715                                 urb->transfer_buffer_length - running_total;
2716         } while (running_total < urb->transfer_buffer_length);
2717
2718         check_trb_math(urb, num_trbs, running_total);
2719         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2720                         start_cycle, start_trb);
2721         return 0;
2722 }
2723
2724 /* This is very similar to what ehci-q.c qtd_fill() does */
2725 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2726                 struct urb *urb, int slot_id, unsigned int ep_index)
2727 {
2728         struct xhci_ring *ep_ring;
2729         struct urb_priv *urb_priv;
2730         struct xhci_td *td;
2731         int num_trbs;
2732         struct xhci_generic_trb *start_trb;
2733         bool first_trb;
2734         bool more_trbs_coming;
2735         int start_cycle;
2736         u32 field, length_field;
2737
2738         int running_total, trb_buff_len, ret;
2739         u64 addr;
2740
2741         if (urb->num_sgs)
2742                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2743
2744         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2745         if (!ep_ring)
2746                 return -EINVAL;
2747
2748         num_trbs = 0;
2749         /* How much data is (potentially) left before the 64KB boundary? */
2750         running_total = TRB_MAX_BUFF_SIZE -
2751                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2752
2753         /* If there's some data on this 64KB chunk, or we have to send a
2754          * zero-length transfer, we need at least one TRB
2755          */
2756         if (running_total != 0 || urb->transfer_buffer_length == 0)
2757                 num_trbs++;
2758         /* How many more 64KB chunks to transfer, how many more TRBs? */
2759         while (running_total < urb->transfer_buffer_length) {
2760                 num_trbs++;
2761                 running_total += TRB_MAX_BUFF_SIZE;
2762         }
2763         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2764
2765         if (!in_interrupt())
2766                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2767                                 "addr = %#llx, num_trbs = %d\n",
2768                                 urb->ep->desc.bEndpointAddress,
2769                                 urb->transfer_buffer_length,
2770                                 urb->transfer_buffer_length,
2771                                 (unsigned long long)urb->transfer_dma,
2772                                 num_trbs);
2773
2774         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2775                         ep_index, urb->stream_id,
2776                         num_trbs, urb, 0, mem_flags);
2777         if (ret < 0)
2778                 return ret;
2779
2780         urb_priv = urb->hcpriv;
2781         td = urb_priv->td[0];
2782
2783         /*
2784          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2785          * until we've finished creating all the other TRBs.  The ring's cycle
2786          * state may change as we enqueue the other TRBs, so save it too.
2787          */
2788         start_trb = &ep_ring->enqueue->generic;
2789         start_cycle = ep_ring->cycle_state;
2790
2791         running_total = 0;
2792         /* How much data is in the first TRB? */
2793         addr = (u64) urb->transfer_dma;
2794         trb_buff_len = TRB_MAX_BUFF_SIZE -
2795                 (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2796         if (urb->transfer_buffer_length < trb_buff_len)
2797                 trb_buff_len = urb->transfer_buffer_length;
2798
2799         first_trb = true;
2800
2801         /* Queue the first TRB, even if it's zero-length */
2802         do {
2803                 u32 remainder = 0;
2804                 field = 0;
2805
2806                 /* Don't change the cycle bit of the first TRB until later */
2807                 if (first_trb) {
2808                         first_trb = false;
2809                         if (start_cycle == 0)
2810                                 field |= 0x1;
2811                 } else
2812                         field |= ep_ring->cycle_state;
2813
2814                 /* Chain all the TRBs together; clear the chain bit in the last
2815                  * TRB to indicate it's the last TRB in the chain.
2816                  */
2817                 if (num_trbs > 1) {
2818                         field |= TRB_CHAIN;
2819                 } else {
2820                         /* FIXME - add check for ZERO_PACKET flag before this */
2821                         td->last_trb = ep_ring->enqueue;
2822                         field |= TRB_IOC;
2823                 }
2824                 remainder = xhci_td_remainder(urb->transfer_buffer_length -
2825                                 running_total);
2826                 length_field = TRB_LEN(trb_buff_len) |
2827                         remainder |
2828                         TRB_INTR_TARGET(0);
2829                 if (num_trbs > 1)
2830                         more_trbs_coming = true;
2831                 else
2832                         more_trbs_coming = false;
2833                 queue_trb(xhci, ep_ring, false, more_trbs_coming,
2834                                 lower_32_bits(addr),
2835                                 upper_32_bits(addr),
2836                                 length_field,
2837                                 /* We always want to know if the TRB was short,
2838                                  * or we won't get an event when it completes.
2839                                  * (Unless we use event data TRBs, which are a
2840                                  * waste of space and HC resources.)
2841                                  */
2842                                 field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
2843                 --num_trbs;
2844                 running_total += trb_buff_len;
2845
2846                 /* Calculate length for next transfer */
2847                 addr += trb_buff_len;
2848                 trb_buff_len = urb->transfer_buffer_length - running_total;
2849                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
2850                         trb_buff_len = TRB_MAX_BUFF_SIZE;
2851         } while (running_total < urb->transfer_buffer_length);
2852
2853         check_trb_math(urb, num_trbs, running_total);
2854         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
2855                         start_cycle, start_trb);
2856         return 0;
2857 }
2858
2859 /* Caller must have locked xhci->lock */
2860 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2861                 struct urb *urb, int slot_id, unsigned int ep_index)
2862 {
2863         struct xhci_ring *ep_ring;
2864         int num_trbs;
2865         int ret;
2866         struct usb_ctrlrequest *setup;
2867         struct xhci_generic_trb *start_trb;
2868         int start_cycle;
2869         u32 field, length_field;
2870         struct urb_priv *urb_priv;
2871         struct xhci_td *td;
2872
2873         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2874         if (!ep_ring)
2875                 return -EINVAL;
2876
2877         /*
2878          * Need to copy setup packet into setup TRB, so we can't use the setup
2879          * DMA address.
2880          */
2881         if (!urb->setup_packet)
2882                 return -EINVAL;
2883
2884         if (!in_interrupt())
2885                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
2886                                 slot_id, ep_index);
2887         /* 1 TRB for setup, 1 for status */
2888         num_trbs = 2;
2889         /*
2890          * Don't need to check if we need additional event data and normal TRBs,
2891          * since data in control transfers will never get bigger than 16MB
2892          * XXX: can we get a buffer that crosses 64KB boundaries?
2893          */
2894         if (urb->transfer_buffer_length > 0)
2895                 num_trbs++;
2896         ret = prepare_transfer(xhci, xhci->devs[slot_id],
2897                         ep_index, urb->stream_id,
2898                         num_trbs, urb, 0, mem_flags);
2899         if (ret < 0)
2900                 return ret;
2901
2902         urb_priv = urb->hcpriv;
2903         td = urb_priv->td[0];
2904
2905         /*
2906          * Don't give the first TRB to the hardware (by toggling the cycle bit)
2907          * until we've finished creating all the other TRBs.  The ring's cycle
2908          * state may change as we enqueue the other TRBs, so save it too.
2909          */
2910         start_trb = &ep_ring->enqueue->generic;
2911         start_cycle = ep_ring->cycle_state;
2912
2913         /* Queue setup TRB - see section 6.4.1.2.1 */
2914         /* FIXME better way to translate setup_packet into two u32 fields? */
2915         setup = (struct usb_ctrlrequest *) urb->setup_packet;
2916         field = 0;
2917         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
2918         if (start_cycle == 0)
2919                 field |= 0x1;
2920         queue_trb(xhci, ep_ring, false, true,
2921                         /* FIXME endianness is probably going to bite my ass here. */
2922                         setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
2923                         setup->wIndex | setup->wLength << 16,
2924                         TRB_LEN(8) | TRB_INTR_TARGET(0),
2925                         /* Immediate data in pointer */
2926                         field);
2927
2928         /* If there's data, queue data TRBs */
2929         field = 0;
2930         length_field = TRB_LEN(urb->transfer_buffer_length) |
2931                 xhci_td_remainder(urb->transfer_buffer_length) |
2932                 TRB_INTR_TARGET(0);
2933         if (urb->transfer_buffer_length > 0) {
2934                 if (setup->bRequestType & USB_DIR_IN)
2935                         field |= TRB_DIR_IN;
2936                 queue_trb(xhci, ep_ring, false, true,
2937                                 lower_32_bits(urb->transfer_dma),
2938                                 upper_32_bits(urb->transfer_dma),
2939                                 length_field,
2940                                 /* Event on short tx */
2941                                 field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
2942         }
2943
2944         /* Save the DMA address of the last TRB in the TD */
2945         td->last_trb = ep_ring->enqueue;
2946
2947         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
2948         /* If the device sent data, the status stage is an OUT transfer */
2949         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
2950                 field = 0;
2951         else
2952                 field = TRB_DIR_IN;
2953         queue_trb(xhci, ep_ring, false, false,
2954                         0,
2955                         0,
2956                         TRB_INTR_TARGET(0),
2957                         /* Event on completion */
2958                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
2959
2960         giveback_first_trb(xhci, slot_id, ep_index, 0,
2961                         start_cycle, start_trb);
2962         return 0;
2963 }
2964
2965 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
2966                 struct urb *urb, int i)
2967 {
2968         int num_trbs = 0;
2969         u64 addr, td_len, running_total;
2970
2971         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2972         td_len = urb->iso_frame_desc[i].length;
2973
2974         running_total = TRB_MAX_BUFF_SIZE -
2975                         (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
2976         if (running_total != 0)
2977                 num_trbs++;
2978
2979         while (running_total < td_len) {
2980                 num_trbs++;
2981                 running_total += TRB_MAX_BUFF_SIZE;
2982         }
2983
2984         return num_trbs;
2985 }
2986
2987 /* This is for isoc transfer */
2988 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2989                 struct urb *urb, int slot_id, unsigned int ep_index)
2990 {
2991         struct xhci_ring *ep_ring;
2992         struct urb_priv *urb_priv;
2993         struct xhci_td *td;
2994         int num_tds, trbs_per_td;
2995         struct xhci_generic_trb *start_trb;
2996         bool first_trb;
2997         int start_cycle;
2998         u32 field, length_field;
2999         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3000         u64 start_addr, addr;
3001         int i, j;
3002         bool more_trbs_coming;
3003
3004         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3005
3006         num_tds = urb->number_of_packets;
3007         if (num_tds < 1) {
3008                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3009                 return -EINVAL;
3010         }
3011
3012         if (!in_interrupt())
3013                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3014                                 " addr = %#llx, num_tds = %d\n",
3015                                 urb->ep->desc.bEndpointAddress,
3016                                 urb->transfer_buffer_length,
3017                                 urb->transfer_buffer_length,
3018                                 (unsigned long long)urb->transfer_dma,
3019                                 num_tds);
3020
3021         start_addr = (u64) urb->transfer_dma;
3022         start_trb = &ep_ring->enqueue->generic;
3023         start_cycle = ep_ring->cycle_state;
3024
3025         /* Queue the first TRB, even if it's zero-length */
3026         for (i = 0; i < num_tds; i++) {
3027                 first_trb = true;
3028
3029                 running_total = 0;
3030                 addr = start_addr + urb->iso_frame_desc[i].offset;
3031                 td_len = urb->iso_frame_desc[i].length;
3032                 td_remain_len = td_len;
3033
3034                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3035
3036                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3037                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3038                 if (ret < 0)
3039                         return ret;
3040
3041                 urb_priv = urb->hcpriv;
3042                 td = urb_priv->td[i];
3043
3044                 for (j = 0; j < trbs_per_td; j++) {
3045                         u32 remainder = 0;
3046                         field = 0;
3047
3048                         if (first_trb) {
3049                                 /* Queue the isoc TRB */
3050                                 field |= TRB_TYPE(TRB_ISOC);
3051                                 /* Assume URB_ISO_ASAP is set */
3052                                 field |= TRB_SIA;
3053                                 if (i == 0) {
3054                                         if (start_cycle == 0)
3055                                                 field |= 0x1;
3056                                 } else
3057                                         field |= ep_ring->cycle_state;
3058                                 first_trb = false;
3059                         } else {
3060                                 /* Queue other normal TRBs */
3061                                 field |= TRB_TYPE(TRB_NORMAL);
3062                                 field |= ep_ring->cycle_state;
3063                         }
3064
3065                         /* Chain all the TRBs together; clear the chain bit in
3066                          * the last TRB to indicate it's the last TRB in the
3067                          * chain.
3068                          */
3069                         if (j < trbs_per_td - 1) {
3070                                 field |= TRB_CHAIN;
3071                                 more_trbs_coming = true;
3072                         } else {
3073                                 td->last_trb = ep_ring->enqueue;
3074                                 field |= TRB_IOC;
3075                                 more_trbs_coming = false;
3076                         }
3077
3078                         /* Calculate TRB length */
3079                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3080                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3081                         if (trb_buff_len > td_remain_len)
3082                                 trb_buff_len = td_remain_len;
3083
3084                         remainder = xhci_td_remainder(td_len - running_total);
3085                         length_field = TRB_LEN(trb_buff_len) |
3086                                 remainder |
3087                                 TRB_INTR_TARGET(0);
3088                         queue_trb(xhci, ep_ring, false, more_trbs_coming,
3089                                 lower_32_bits(addr),
3090                                 upper_32_bits(addr),
3091                                 length_field,
3092                                 /* We always want to know if the TRB was short,
3093                                  * or we won't get an event when it completes.
3094                                  * (Unless we use event data TRBs, which are a
3095                                  * waste of space and HC resources.)
3096                                  */
3097                                 field | TRB_ISP);
3098                         running_total += trb_buff_len;
3099
3100                         addr += trb_buff_len;
3101                         td_remain_len -= trb_buff_len;
3102                 }
3103
3104                 /* Check TD length */
3105                 if (running_total != td_len) {
3106                         xhci_err(xhci, "ISOC TD length unmatch\n");
3107                         return -EINVAL;
3108                 }
3109         }
3110
3111         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3112                         start_cycle, start_trb);
3113         return 0;
3114 }
3115
3116 /*
3117  * Check transfer ring to guarantee there is enough room for the urb.
3118  * Update ISO URB start_frame and interval.
3119  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3120  * update the urb->start_frame by now.
3121  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3122  */
3123 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3124                 struct urb *urb, int slot_id, unsigned int ep_index)
3125 {
3126         struct xhci_virt_device *xdev;
3127         struct xhci_ring *ep_ring;
3128         struct xhci_ep_ctx *ep_ctx;
3129         int start_frame;
3130         int xhci_interval;
3131         int ep_interval;
3132         int num_tds, num_trbs, i;
3133         int ret;
3134
3135         xdev = xhci->devs[slot_id];
3136         ep_ring = xdev->eps[ep_index].ring;
3137         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3138
3139         num_trbs = 0;
3140         num_tds = urb->number_of_packets;
3141         for (i = 0; i < num_tds; i++)
3142                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3143
3144         /* Check the ring to guarantee there is enough room for the whole urb.
3145          * Do not insert any td of the urb to the ring if the check failed.
3146          */
3147         ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
3148                                 num_trbs, mem_flags);
3149         if (ret)
3150                 return ret;
3151
3152         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3153         start_frame &= 0x3fff;
3154
3155         urb->start_frame = start_frame;
3156         if (urb->dev->speed == USB_SPEED_LOW ||
3157                         urb->dev->speed == USB_SPEED_FULL)
3158                 urb->start_frame >>= 3;
3159
3160         xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
3161         ep_interval = urb->interval;
3162         /* Convert to microframes */
3163         if (urb->dev->speed == USB_SPEED_LOW ||
3164                         urb->dev->speed == USB_SPEED_FULL)
3165                 ep_interval *= 8;
3166         /* FIXME change this to a warning and a suggestion to use the new API
3167          * to set the polling interval (once the API is added).
3168          */
3169         if (xhci_interval != ep_interval) {
3170                 if (printk_ratelimit())
3171                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3172                                         " (%d microframe%s) than xHCI "
3173                                         "(%d microframe%s)\n",
3174                                         ep_interval,
3175                                         ep_interval == 1 ? "" : "s",
3176                                         xhci_interval,
3177                                         xhci_interval == 1 ? "" : "s");
3178                 urb->interval = xhci_interval;
3179                 /* Convert back to frames for LS/FS devices */
3180                 if (urb->dev->speed == USB_SPEED_LOW ||
3181                                 urb->dev->speed == USB_SPEED_FULL)
3182                         urb->interval /= 8;
3183         }
3184         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3185 }
3186
3187 /****           Command Ring Operations         ****/
3188
3189 /* Generic function for queueing a command TRB on the command ring.
3190  * Check to make sure there's room on the command ring for one command TRB.
3191  * Also check that there's room reserved for commands that must not fail.
3192  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3193  * then only check for the number of reserved spots.
3194  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3195  * because the command event handler may want to resubmit a failed command.
3196  */
3197 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3198                 u32 field3, u32 field4, bool command_must_succeed)
3199 {
3200         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3201         int ret;
3202
3203         if (!command_must_succeed)
3204                 reserved_trbs++;
3205
3206         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3207                         reserved_trbs, GFP_ATOMIC);
3208         if (ret < 0) {
3209                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3210                 if (command_must_succeed)
3211                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3212                                         "unfailable commands failed.\n");
3213                 return ret;
3214         }
3215         queue_trb(xhci, xhci->cmd_ring, false, false, field1, field2, field3,
3216                         field4 | xhci->cmd_ring->cycle_state);
3217         return 0;
3218 }
3219
3220 /* Queue a slot enable or disable request on the command ring */
3221 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3222 {
3223         return queue_command(xhci, 0, 0, 0,
3224                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3225 }
3226
3227 /* Queue an address device command TRB */
3228 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3229                 u32 slot_id)
3230 {
3231         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3232                         upper_32_bits(in_ctx_ptr), 0,
3233                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3234                         false);
3235 }
3236
3237 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3238                 u32 field1, u32 field2, u32 field3, u32 field4)
3239 {
3240         return queue_command(xhci, field1, field2, field3, field4, false);
3241 }
3242
3243 /* Queue a reset device command TRB */
3244 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3245 {
3246         return queue_command(xhci, 0, 0, 0,
3247                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3248                         false);
3249 }
3250
3251 /* Queue a configure endpoint command TRB */
3252 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3253                 u32 slot_id, bool command_must_succeed)
3254 {
3255         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3256                         upper_32_bits(in_ctx_ptr), 0,
3257                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3258                         command_must_succeed);
3259 }
3260
3261 /* Queue an evaluate context command TRB */
3262 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3263                 u32 slot_id)
3264 {
3265         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3266                         upper_32_bits(in_ctx_ptr), 0,
3267                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3268                         false);
3269 }
3270
3271 /*
3272  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3273  * activity on an endpoint that is about to be suspended.
3274  */
3275 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3276                 unsigned int ep_index, int suspend)
3277 {
3278         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3279         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3280         u32 type = TRB_TYPE(TRB_STOP_RING);
3281         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3282
3283         return queue_command(xhci, 0, 0, 0,
3284                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3285 }
3286
3287 /* Set Transfer Ring Dequeue Pointer command.
3288  * This should not be used for endpoints that have streams enabled.
3289  */
3290 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3291                 unsigned int ep_index, unsigned int stream_id,
3292                 struct xhci_segment *deq_seg,
3293                 union xhci_trb *deq_ptr, u32 cycle_state)
3294 {
3295         dma_addr_t addr;
3296         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3297         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3298         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3299         u32 type = TRB_TYPE(TRB_SET_DEQ);
3300         struct xhci_virt_ep *ep;
3301
3302         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3303         if (addr == 0) {
3304                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3305                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3306                                 deq_seg, deq_ptr);
3307                 return 0;
3308         }
3309         ep = &xhci->devs[slot_id]->eps[ep_index];
3310         if ((ep->ep_state & SET_DEQ_PENDING)) {
3311                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3312                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3313                 return 0;
3314         }
3315         ep->queued_deq_seg = deq_seg;
3316         ep->queued_deq_ptr = deq_ptr;
3317         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3318                         upper_32_bits(addr), trb_stream_id,
3319                         trb_slot_id | trb_ep_index | type, false);
3320 }
3321
3322 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3323                 unsigned int ep_index)
3324 {
3325         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3326         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3327         u32 type = TRB_TYPE(TRB_RESET_EP);
3328
3329         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3330                         false);
3331 }