2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
28 /* Device for a quirk */
29 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
30 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 static const char hcd_name[] = "xhci_hcd";
34 /* called after powerup, by probe or system-pm "wakeup" */
35 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
38 * TODO: Implement finding debug ports later.
39 * TODO: see if there are any quirks that need to be added to handle
40 * new extended capabilities.
43 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
44 if (!pci_set_mwi(pdev))
45 xhci_dbg(xhci, "MWI active\n");
47 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
51 /* called during probe() after chip reset completes */
52 static int xhci_pci_setup(struct usb_hcd *hcd)
54 struct xhci_hcd *xhci;
55 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
59 hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
61 if (usb_hcd_is_primary_hcd(hcd)) {
62 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
65 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
67 /* Mark the first roothub as being USB 2.0.
68 * The xHCI driver will register the USB 3.0 roothub.
70 hcd->speed = HCD_USB2;
71 hcd->self.root_hub->speed = USB_SPEED_HIGH;
73 * USB 2.0 roothub under xHCI has an integrated TT,
74 * (rate matching hub) as opposed to having an OHCI/UHCI
75 * companion controller.
79 /* xHCI private pointer was set in xhci_pci_probe for the second
82 xhci = hcd_to_xhci(hcd);
83 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
84 if (HCC_64BIT_ADDR(temp)) {
85 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
86 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
88 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
93 xhci->cap_regs = hcd->regs;
94 xhci->op_regs = hcd->regs +
95 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
96 xhci->run_regs = hcd->regs +
97 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
98 /* Cache read-only capability registers */
99 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
100 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
101 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
102 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
103 xhci->hci_version = HC_VERSION(xhci->hcc_params);
104 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
105 xhci_print_registers(xhci);
107 /* Look for vendor-specific quirks */
108 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
109 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
110 pdev->revision == 0x0) {
111 xhci->quirks |= XHCI_RESET_EP_QUIRK;
112 xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
113 " endpoint cmd after reset endpoint\n");
115 if (pdev->vendor == PCI_VENDOR_ID_NEC)
116 xhci->quirks |= XHCI_NEC_HOST;
119 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
120 xhci->quirks |= XHCI_AMD_PLL_FIX;
121 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
122 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
123 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
124 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
125 xhci->limit_active_eps = 64;
128 /* Make sure the HC is halted. */
129 retval = xhci_halt(xhci);
133 xhci_dbg(xhci, "Resetting HCD\n");
134 /* Reset the internal HC memory state and registers. */
135 retval = xhci_reset(xhci);
138 xhci_dbg(xhci, "Reset complete\n");
140 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
141 if (HCC_64BIT_ADDR(temp)) {
142 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
143 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
145 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
148 xhci_dbg(xhci, "Calling HCD init\n");
149 /* Initialize HCD and host controller data structures. */
150 retval = xhci_init(hcd);
153 xhci_dbg(xhci, "Called HCD init\n");
155 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
156 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
158 /* Find any debug ports */
159 retval = xhci_pci_reinit(xhci, pdev);
169 * We need to register our own PCI probe function (instead of the USB core's
170 * function) in order to create a second roothub under xHCI.
172 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
175 struct xhci_hcd *xhci;
176 struct hc_driver *driver;
179 driver = (struct hc_driver *)id->driver_data;
180 /* Register the USB 2.0 roothub.
181 * FIXME: USB core must know to register the USB 2.0 roothub first.
182 * This is sort of silly, because we could just set the HCD driver flags
183 * to say USB 2.0, but I'm not sure what the implications would be in
184 * the other parts of the HCD code.
186 retval = usb_hcd_pci_probe(dev, id);
191 /* USB 2.0 roothub is stored in the PCI device now. */
192 hcd = dev_get_drvdata(&dev->dev);
193 xhci = hcd_to_xhci(hcd);
194 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
196 if (!xhci->shared_hcd) {
198 goto dealloc_usb2_hcd;
201 /* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
202 * is called by usb_add_hcd().
204 *((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
206 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
207 IRQF_DISABLED | IRQF_SHARED);
210 /* Roothub already marked as USB 3.0 speed */
214 usb_put_hcd(xhci->shared_hcd);
216 usb_hcd_pci_remove(dev);
220 static void xhci_pci_remove(struct pci_dev *dev)
222 struct xhci_hcd *xhci;
224 xhci = hcd_to_xhci(pci_get_drvdata(dev));
225 if (xhci->shared_hcd) {
226 usb_remove_hcd(xhci->shared_hcd);
227 usb_put_hcd(xhci->shared_hcd);
229 usb_hcd_pci_remove(dev);
234 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
236 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
239 if (hcd->state != HC_STATE_SUSPENDED ||
240 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
243 retval = xhci_suspend(xhci);
248 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
250 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
251 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
254 /* The BIOS on systems with the Intel Panther Point chipset may or may
255 * not support xHCI natively. That means that during system resume, it
256 * may switch the ports back to EHCI so that users can use their
257 * keyboard to select a kernel from GRUB after resume from hibernate.
259 * The BIOS is supposed to remember whether the OS had xHCI ports
260 * enabled before resume, and switch the ports back to xHCI when the
261 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
264 * Unconditionally switch the ports back to xHCI after a system resume.
265 * We can't tell whether the EHCI or xHCI controller will be resumed
266 * first, so we have to do the port switchover in both drivers. Writing
267 * a '1' to the port switchover registers should have no effect if the
268 * port was already switched over.
270 if (usb_is_intel_switchable_xhci(pdev))
271 usb_enable_xhci_ports(pdev);
273 retval = xhci_resume(xhci, hibernated);
276 #endif /* CONFIG_PM */
278 static const struct hc_driver xhci_pci_hc_driver = {
279 .description = hcd_name,
280 .product_desc = "xHCI Host Controller",
281 .hcd_priv_size = sizeof(struct xhci_hcd *),
284 * generic hardware linkage
287 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
290 * basic lifecycle operations
292 .reset = xhci_pci_setup,
295 .pci_suspend = xhci_pci_suspend,
296 .pci_resume = xhci_pci_resume,
299 .shutdown = xhci_shutdown,
302 * managing i/o requests and associated device resources
304 .urb_enqueue = xhci_urb_enqueue,
305 .urb_dequeue = xhci_urb_dequeue,
306 .alloc_dev = xhci_alloc_dev,
307 .free_dev = xhci_free_dev,
308 .alloc_streams = xhci_alloc_streams,
309 .free_streams = xhci_free_streams,
310 .add_endpoint = xhci_add_endpoint,
311 .drop_endpoint = xhci_drop_endpoint,
312 .endpoint_reset = xhci_endpoint_reset,
313 .check_bandwidth = xhci_check_bandwidth,
314 .reset_bandwidth = xhci_reset_bandwidth,
315 .address_device = xhci_address_device,
316 .update_hub_device = xhci_update_hub_device,
317 .reset_device = xhci_discover_or_reset_device,
322 .get_frame_number = xhci_get_frame,
324 /* Root hub support */
325 .hub_control = xhci_hub_control,
326 .hub_status_data = xhci_hub_status_data,
327 .bus_suspend = xhci_bus_suspend,
328 .bus_resume = xhci_bus_resume,
331 /*-------------------------------------------------------------------------*/
333 /* PCI driver selection metadata; PCI hotplugging uses this */
334 static const struct pci_device_id pci_ids[] = { {
335 /* handle any USB 3.0 xHCI controller */
336 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
337 .driver_data = (unsigned long) &xhci_pci_hc_driver,
339 { /* end: all zeroes */ }
341 MODULE_DEVICE_TABLE(pci, pci_ids);
343 /* pci driver glue; this is a "new style" PCI driver module */
344 static struct pci_driver xhci_pci_driver = {
345 .name = (char *) hcd_name,
348 .probe = xhci_pci_probe,
349 .remove = xhci_pci_remove,
350 /* suspend and resume implemented later */
352 .shutdown = usb_hcd_pci_shutdown,
353 #ifdef CONFIG_PM_SLEEP
355 .pm = &usb_hcd_pci_pm_ops
360 int xhci_register_pci(void)
362 return pci_register_driver(&xhci_pci_driver);
365 void xhci_unregister_pci(void)
367 pci_unregister_driver(&xhci_pci_driver);