Pileus Git - ~andy/linux/blob - drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  38 {
  39         struct xhci_segment *seg;
  40         dma_addr_t      dma;
  41
  42         seg = kzalloc(sizeof *seg, flags);
  43         if (!seg)
  44                 return NULL;
  45
  46         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  47         if (!seg->trbs) {
  48                 kfree(seg);
  49                 return NULL;
  50         }
  51
  52         memset(seg->trbs, 0, SEGMENT_SIZE);
  53         seg->dma = dma;
  54         seg->next = NULL;
  55
  56         return seg;
  57 }
  58
  59 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  60 {
  61         if (seg->trbs) {
  62                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  63                 seg->trbs = NULL;
  64         }
  65         kfree(seg);
  66 }
  67
  68 /*
  69  * Make the prev segment point to the next segment.
  70  *
  71  * Change the last TRB in the prev segment to be a Link TRB which points to the
  72  * DMA address of the next segment.  The caller needs to set any Link TRB
  73  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  74  */
  75 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  76                 struct xhci_segment *next, bool link_trbs, bool isoc)
  77 {
  78         u32 val;
  79
  80         if (!prev || !next)
  81                 return;
  82         prev->next = next;
  83         if (link_trbs) {
  84                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  85                         cpu_to_le64(next->dma);
  86
  87                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  88                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  89                 val &= ~TRB_TYPE_BITMASK;
  90                 val |= TRB_TYPE(TRB_LINK);
  91                 /* Always set the chain bit with 0.95 hardware */
  92                 /* Set chain bit for isoc rings on AMD 0.96 host */
  93                 if (xhci_link_trb_quirk(xhci) ||
  94                                 (isoc && (xhci->quirks & XHCI_AMD_0x96_HOST)))
  95                         val |= TRB_CHAIN;
  96                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
  97         }
  98 }
  99
 100 /* XXX: Do we need the hcd structure in all these functions? */
 101 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 102 {
 103         struct xhci_segment *seg;
 104         struct xhci_segment *first_seg;
 105
 106         if (!ring)
 107                 return;
 108         if (ring->first_seg) {
 109                 first_seg = ring->first_seg;
 110                 seg = first_seg->next;
 111                 while (seg != first_seg) {
 112                         struct xhci_segment *next = seg->next;
 113                         xhci_segment_free(xhci, seg);
 114                         seg = next;
 115                 }
 116                 xhci_segment_free(xhci, first_seg);
 117                 ring->first_seg = NULL;
 118         }
 119         kfree(ring);
 120 }
 121
 122 static void xhci_initialize_ring_info(struct xhci_ring *ring)
 123 {
 124         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 125         ring->enqueue = ring->first_seg->trbs;
 126         ring->enq_seg = ring->first_seg;
 127         ring->dequeue = ring->enqueue;
 128         ring->deq_seg = ring->first_seg;
 129         /* The ring is initialized to 0. The producer must write 1 to the cycle
 130          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 131          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 132          */
 133         ring->cycle_state = 1;
 134         /* Not necessary for new rings, but needed for re-initialized rings */
 135         ring->enq_updates = 0;
 136         ring->deq_updates = 0;
 137 }
 138
 139 /**
 140  * Create a new ring with zero or more segments.
 141  *
 142  * Link each segment together into a ring.
 143  * Set the end flag and the cycle toggle bit on the last segment.
 144  * See section 4.9.1 and figures 15 and 16.
 145  */
 146 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 147                 unsigned int num_segs, bool link_trbs, bool isoc, gfp_t flags)
 148 {
 149         struct xhci_ring        *ring;
 150         struct xhci_segment     *prev;
 151
 152         ring = kzalloc(sizeof *(ring), flags);
 153         if (!ring)
 154                 return NULL;
 155
 156         INIT_LIST_HEAD(&ring->td_list);
 157         if (num_segs == 0)
 158                 return ring;
 159
 160         ring->first_seg = xhci_segment_alloc(xhci, flags);
 161         if (!ring->first_seg)
 162                 goto fail;
 163         num_segs--;
 164
 165         prev = ring->first_seg;
 166         while (num_segs > 0) {
 167                 struct xhci_segment     *next;
 168
 169                 next = xhci_segment_alloc(xhci, flags);
 170                 if (!next)
 171                         goto fail;
 172                 xhci_link_segments(xhci, prev, next, link_trbs, isoc);
 173
 174                 prev = next;
 175                 num_segs--;
 176         }
 177         xhci_link_segments(xhci, prev, ring->first_seg, link_trbs, isoc);
 178
 179         if (link_trbs) {
 180                 /* See section 4.9.2.1 and 6.4.4.1 */
 181                 prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
 182                         cpu_to_le32(LINK_TOGGLE);
 183         }
 184         xhci_initialize_ring_info(ring);
 185         return ring;
 186
 187 fail:
 188         xhci_ring_free(xhci, ring);
 189         return NULL;
 190 }
 191
 192 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 193                 struct xhci_virt_device *virt_dev,
 194                 unsigned int ep_index)
 195 {
 196         int rings_cached;
 197
 198         rings_cached = virt_dev->num_rings_cached;
 199         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 200                 virt_dev->ring_cache[rings_cached] =
 201                         virt_dev->eps[ep_index].ring;
 202                 virt_dev->num_rings_cached++;
 203                 xhci_dbg(xhci, "Cached old ring, "
 204                                 "%d ring%s cached\n",
 205                                 virt_dev->num_rings_cached,
 206                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 207         } else {
 208                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 209                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 210                                 "freeing ring\n",
 211                                 virt_dev->num_rings_cached);
 212         }
 213         virt_dev->eps[ep_index].ring = NULL;
 214 }
 215
 216 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 217  * pointers to the beginning of the ring.
 218  */
 219 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 220                 struct xhci_ring *ring, bool isoc)
 221 {
 222         struct xhci_segment     *seg = ring->first_seg;
 223         do {
 224                 memset(seg->trbs, 0,
 225                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 226                 /* All endpoint rings have link TRBs */
 227                 xhci_link_segments(xhci, seg, seg->next, 1, isoc);
 228                 seg = seg->next;
 229         } while (seg != ring->first_seg);
 230         xhci_initialize_ring_info(ring);
 231         /* td list should be empty since all URBs have been cancelled,
 232          * but just in case...
 233          */
 234         INIT_LIST_HEAD(&ring->td_list);
 235 }
 236
 237 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 238
 239 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 240                                                     int type, gfp_t flags)
 241 {
 242         struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
 243         if (!ctx)
 244                 return NULL;
 245
 246         BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
 247         ctx->type = type;
 248         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 249         if (type == XHCI_CTX_TYPE_INPUT)
 250                 ctx->size += CTX_SIZE(xhci->hcc_params);
 251
 252         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 253         memset(ctx->bytes, 0, ctx->size);
 254         return ctx;
 255 }
 256
 257 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 258                              struct xhci_container_ctx *ctx)
 259 {
 260         if (!ctx)
 261                 return;
 262         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 263         kfree(ctx);
 264 }
 265
 266 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 267                                               struct xhci_container_ctx *ctx)
 268 {
 269         BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
 270         return (struct xhci_input_control_ctx *)ctx->bytes;
 271 }
 272
 273 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 274                                         struct xhci_container_ctx *ctx)
 275 {
 276         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 277                 return (struct xhci_slot_ctx *)ctx->bytes;
 278
 279         return (struct xhci_slot_ctx *)
 280                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 281 }
 282
 283 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 284                                     struct xhci_container_ctx *ctx,
 285                                     unsigned int ep_index)
 286 {
 287         /* increment ep index by offset of start of ep ctx array */
 288         ep_index++;
 289         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 290                 ep_index++;
 291
 292         return (struct xhci_ep_ctx *)
 293                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 294 }
 295
 296
 297 /***************** Streams structures manipulation *************************/
 298
 299 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 300                 unsigned int num_stream_ctxs,
 301                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 302 {
 303         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 304
 305         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 306                 dma_free_coherent(&pdev->dev,
 307                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 308                                 stream_ctx, dma);
 309         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 310                 return dma_pool_free(xhci->small_streams_pool,
 311                                 stream_ctx, dma);
 312         else
 313                 return dma_pool_free(xhci->medium_streams_pool,
 314                                 stream_ctx, dma);
 315 }
 316
 317 /*
 318  * The stream context array for each endpoint with bulk streams enabled can
 319  * vary in size, based on:
 320  *  - how many streams the endpoint supports,
 321  *  - the maximum primary stream array size the host controller supports,
 322  *  - and how many streams the device driver asks for.
 323  *
 324  * The stream context array must be a power of 2, and can be as small as
 325  * 64 bytes or as large as 1MB.
 326  */
 327 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 328                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 329                 gfp_t mem_flags)
 330 {
 331         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 332
 333         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 334                 return dma_alloc_coherent(&pdev->dev,
 335                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 336                                 dma, mem_flags);
 337         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 338                 return dma_pool_alloc(xhci->small_streams_pool,
 339                                 mem_flags, dma);
 340         else
 341                 return dma_pool_alloc(xhci->medium_streams_pool,
 342                                 mem_flags, dma);
 343 }
 344
 345 struct xhci_ring *xhci_dma_to_transfer_ring(
 346                 struct xhci_virt_ep *ep,
 347                 u64 address)
 348 {
 349         if (ep->ep_state & EP_HAS_STREAMS)
 350                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 351                                 address >> SEGMENT_SHIFT);
 352         return ep->ring;
 353 }
 354
 355 /* Only use this when you know stream_info is valid */
 356 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 357 static struct xhci_ring *dma_to_stream_ring(
 358                 struct xhci_stream_info *stream_info,
 359                 u64 address)
 360 {
 361         return radix_tree_lookup(&stream_info->trb_address_map,
 362                         address >> SEGMENT_SHIFT);
 363 }
 364 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 365
 366 struct xhci_ring *xhci_stream_id_to_ring(
 367                 struct xhci_virt_device *dev,
 368                 unsigned int ep_index,
 369                 unsigned int stream_id)
 370 {
 371         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 372
 373         if (stream_id == 0)
 374                 return ep->ring;
 375         if (!ep->stream_info)
 376                 return NULL;
 377
 378         if (stream_id > ep->stream_info->num_streams)
 379                 return NULL;
 380         return ep->stream_info->stream_rings[stream_id];
 381 }
 382
 383 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 384 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 385                 unsigned int num_streams,
 386                 struct xhci_stream_info *stream_info)
 387 {
 388         u32 cur_stream;
 389         struct xhci_ring *cur_ring;
 390         u64 addr;
 391
 392         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 393                 struct xhci_ring *mapped_ring;
 394                 int trb_size = sizeof(union xhci_trb);
 395
 396                 cur_ring = stream_info->stream_rings[cur_stream];
 397                 for (addr = cur_ring->first_seg->dma;
 398                                 addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
 399                                 addr += trb_size) {
 400                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 401                         if (cur_ring != mapped_ring) {
 402                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 403                                                 "didn't map to stream ID %u; "
 404                                                 "mapped to ring %p\n",
 405                                                 (unsigned long long) addr,
 406                                                 cur_stream,
 407                                                 mapped_ring);
 408                                 return -EINVAL;
 409                         }
 410                 }
 411                 /* One TRB after the end of the ring segment shouldn't return a
 412                  * pointer to the current ring (although it may be a part of a
 413                  * different ring).
 414                  */
 415                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 416                 if (mapped_ring != cur_ring) {
 417                         /* One TRB before should also fail */
 418                         addr = cur_ring->first_seg->dma - trb_size;
 419                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 420                 }
 421                 if (mapped_ring == cur_ring) {
 422                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 423                                         "mapped to valid stream ID %u; "
 424                                         "mapped ring = %p\n",
 425                                         (unsigned long long) addr,
 426                                         cur_stream,
 427                                         mapped_ring);
 428                         return -EINVAL;
 429                 }
 430         }
 431         return 0;
 432 }
 433 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 434
 435 /*
 436  * Change an endpoint's internal structure so it supports stream IDs.  The
 437  * number of requested streams includes stream 0, which cannot be used by device
 438  * drivers.
 439  *
 440  * The number of stream contexts in the stream context array may be bigger than
 441  * the number of streams the driver wants to use.  This is because the number of
 442  * stream context array entries must be a power of two.
 443  *
 444  * We need a radix tree for mapping physical addresses of TRBs to which stream
 445  * ID they belong to.  We need to do this because the host controller won't tell
 446  * us which stream ring the TRB came from.  We could store the stream ID in an
 447  * event data TRB, but that doesn't help us for the cancellation case, since the
 448  * endpoint may stop before it reaches that event data TRB.
 449  *
 450  * The radix tree maps the upper portion of the TRB DMA address to a ring
 451  * segment that has the same upper portion of DMA addresses.  For example, say I
 452  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 453  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 454  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 455  * pass the radix tree a key to get the right stream ID:
 456  *
 457  *      0x10c90fff >> 10 = 0x43243
 458  *      0x10c912c0 >> 10 = 0x43244
 459  *      0x10c91400 >> 10 = 0x43245
 460  *
 461  * Obviously, only those TRBs with DMA addresses that are within the segment
 462  * will make the radix tree return the stream ID for that ring.
 463  *
 464  * Caveats for the radix tree:
 465  *
 466  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 467  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 468  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 469  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 470  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 471  * extended systems (where the DMA address can be bigger than 32-bits),
 472  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 473  */
 474 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 475                 unsigned int num_stream_ctxs,
 476                 unsigned int num_streams, gfp_t mem_flags)
 477 {
 478         struct xhci_stream_info *stream_info;
 479         u32 cur_stream;
 480         struct xhci_ring *cur_ring;
 481         unsigned long key;
 482         u64 addr;
 483         int ret;
 484
 485         xhci_dbg(xhci, "Allocating %u streams and %u "
 486                         "stream context array entries.\n",
 487                         num_streams, num_stream_ctxs);
 488         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 489                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 490                 return NULL;
 491         }
 492         xhci->cmd_ring_reserved_trbs++;
 493
 494         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 495         if (!stream_info)
 496                 goto cleanup_trbs;
 497
 498         stream_info->num_streams = num_streams;
 499         stream_info->num_stream_ctxs = num_stream_ctxs;
 500
 501         /* Initialize the array of virtual pointers to stream rings. */
 502         stream_info->stream_rings = kzalloc(
 503                         sizeof(struct xhci_ring *)*num_streams,
 504                         mem_flags);
 505         if (!stream_info->stream_rings)
 506                 goto cleanup_info;
 507
 508         /* Initialize the array of DMA addresses for stream rings for the HW. */
 509         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 510                         num_stream_ctxs, &stream_info->ctx_array_dma,
 511                         mem_flags);
 512         if (!stream_info->stream_ctx_array)
 513                 goto cleanup_ctx;
 514         memset(stream_info->stream_ctx_array, 0,
 515                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 516
 517         /* Allocate everything needed to free the stream rings later */
 518         stream_info->free_streams_command =
 519                 xhci_alloc_command(xhci, true, true, mem_flags);
 520         if (!stream_info->free_streams_command)
 521                 goto cleanup_ctx;
 522
 523         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 524
 525         /* Allocate rings for all the streams that the driver will use,
 526          * and add their segment DMA addresses to the radix tree.
 527          * Stream 0 is reserved.
 528          */
 529         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 530                 stream_info->stream_rings[cur_stream] =
 531                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
 532                 cur_ring = stream_info->stream_rings[cur_stream];
 533                 if (!cur_ring)
 534                         goto cleanup_rings;
 535                 cur_ring->stream_id = cur_stream;
 536                 /* Set deq ptr, cycle bit, and stream context type */
 537                 addr = cur_ring->first_seg->dma |
 538                         SCT_FOR_CTX(SCT_PRI_TR) |
 539                         cur_ring->cycle_state;
 540                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 541                         cpu_to_le64(addr);
 542                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 543                                 cur_stream, (unsigned long long) addr);
 544
 545                 key = (unsigned long)
 546                         (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
 547                 ret = radix_tree_insert(&stream_info->trb_address_map,
 548                                 key, cur_ring);
 549                 if (ret) {
 550                         xhci_ring_free(xhci, cur_ring);
 551                         stream_info->stream_rings[cur_stream] = NULL;
 552                         goto cleanup_rings;
 553                 }
 554         }
 555         /* Leave the other unused stream ring pointers in the stream context
 556          * array initialized to zero.  This will cause the xHC to give us an
 557          * error if the device asks for a stream ID we don't have setup (if it
 558          * was any other way, the host controller would assume the ring is
 559          * "empty" and wait forever for data to be queued to that stream ID).
 560          */
 561 #if XHCI_DEBUG
 562         /* Do a little test on the radix tree to make sure it returns the
 563          * correct values.
 564          */
 565         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 566                 goto cleanup_rings;
 567 #endif
 568
 569         return stream_info;
 570
 571 cleanup_rings:
 572         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 573                 cur_ring = stream_info->stream_rings[cur_stream];
 574                 if (cur_ring) {
 575                         addr = cur_ring->first_seg->dma;
 576                         radix_tree_delete(&stream_info->trb_address_map,
 577                                         addr >> SEGMENT_SHIFT);
 578                         xhci_ring_free(xhci, cur_ring);
 579                         stream_info->stream_rings[cur_stream] = NULL;
 580                 }
 581         }
 582         xhci_free_command(xhci, stream_info->free_streams_command);
 583 cleanup_ctx:
 584         kfree(stream_info->stream_rings);
 585 cleanup_info:
 586         kfree(stream_info);
 587 cleanup_trbs:
 588         xhci->cmd_ring_reserved_trbs--;
 589         return NULL;
 590 }
 591 /*
 592  * Sets the MaxPStreams field and the Linear Stream Array field.
 593  * Sets the dequeue pointer to the stream context array.
 594  */
 595 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 596                 struct xhci_ep_ctx *ep_ctx,
 597                 struct xhci_stream_info *stream_info)
 598 {
 599         u32 max_primary_streams;
 600         /* MaxPStreams is the number of stream context array entries, not the
 601          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 602          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 603          */
 604         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 605         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 606                         1 << (max_primary_streams + 1));
 607         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 608         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 609                                        | EP_HAS_LSA);
 610         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 611 }
 612
 613 /*
 614  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 615  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 616  * not at the beginning of the ring).
 617  */
 618 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 619                 struct xhci_ep_ctx *ep_ctx,
 620                 struct xhci_virt_ep *ep)
 621 {
 622         dma_addr_t addr;
 623         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 624         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 625         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 626 }
 627
 628 /* Frees all stream contexts associated with the endpoint,
 629  *
 630  * Caller should fix the endpoint context streams fields.
 631  */
 632 void xhci_free_stream_info(struct xhci_hcd *xhci,
 633                 struct xhci_stream_info *stream_info)
 634 {
 635         int cur_stream;
 636         struct xhci_ring *cur_ring;
 637         dma_addr_t addr;
 638
 639         if (!stream_info)
 640                 return;
 641
 642         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 643                         cur_stream++) {
 644                 cur_ring = stream_info->stream_rings[cur_stream];
 645                 if (cur_ring) {
 646                         addr = cur_ring->first_seg->dma;
 647                         radix_tree_delete(&stream_info->trb_address_map,
 648                                         addr >> SEGMENT_SHIFT);
 649                         xhci_ring_free(xhci, cur_ring);
 650                         stream_info->stream_rings[cur_stream] = NULL;
 651                 }
 652         }
 653         xhci_free_command(xhci, stream_info->free_streams_command);
 654         xhci->cmd_ring_reserved_trbs--;
 655         if (stream_info->stream_ctx_array)
 656                 xhci_free_stream_ctx(xhci,
 657                                 stream_info->num_stream_ctxs,
 658                                 stream_info->stream_ctx_array,
 659                                 stream_info->ctx_array_dma);
 660
 661         if (stream_info)
 662                 kfree(stream_info->stream_rings);
 663         kfree(stream_info);
 664 }
 665
 666
 667 /***************** Device context manipulation *************************/
 668
 669 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 670                 struct xhci_virt_ep *ep)
 671 {
 672         init_timer(&ep->stop_cmd_timer);
 673         ep->stop_cmd_timer.data = (unsigned long) ep;
 674         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 675         ep->xhci = xhci;
 676 }
 677
 678 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 679                 struct xhci_virt_device *virt_dev,
 680                 int slot_id)
 681 {
 682         struct list_head *tt;
 683         struct list_head *tt_list_head;
 684         struct list_head *tt_next;
 685         struct xhci_tt_bw_info *tt_info;
 686
 687         /* If the device never made it past the Set Address stage,
 688          * it may not have the real_port set correctly.
 689          */
 690         if (virt_dev->real_port == 0 ||
 691                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 692                 xhci_dbg(xhci, "Bad real port.\n");
 693                 return;
 694         }
 695
 696         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 697         if (list_empty(tt_list_head))
 698                 return;
 699
 700         list_for_each(tt, tt_list_head) {
 701                 tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
 702                 if (tt_info->slot_id == slot_id)
 703                         break;
 704         }
 705         /* Cautionary measure in case the hub was disconnected before we
 706          * stored the TT information.
 707          */
 708         if (tt_info->slot_id != slot_id)
 709                 return;
 710
 711         tt_next = tt->next;
 712         tt_info = list_entry(tt, struct xhci_tt_bw_info,
 713                         tt_list);
 714         /* Multi-TT hubs will have more than one entry */
 715         do {
 716                 list_del(tt);
 717                 kfree(tt_info);
 718                 tt = tt_next;
 719                 if (list_empty(tt_list_head))
 720                         break;
 721                 tt_next = tt->next;
 722                 tt_info = list_entry(tt, struct xhci_tt_bw_info,
 723                                 tt_list);
 724         } while (tt_info->slot_id == slot_id);
 725 }
 726
 727 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 728                 struct xhci_virt_device *virt_dev,
 729                 struct usb_device *hdev,
 730                 struct usb_tt *tt, gfp_t mem_flags)
 731 {
 732         struct xhci_tt_bw_info          *tt_info;
 733         unsigned int                    num_ports;
 734         int                             i, j;
 735
 736         if (!tt->multi)
 737                 num_ports = 1;
 738         else
 739                 num_ports = hdev->maxchild;
 740
 741         for (i = 0; i < num_ports; i++, tt_info++) {
 742                 struct xhci_interval_bw_table *bw_table;
 743
 744                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 745                 if (!tt_info)
 746                         goto free_tts;
 747                 INIT_LIST_HEAD(&tt_info->tt_list);
 748                 list_add(&tt_info->tt_list,
 749                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 750                 tt_info->slot_id = virt_dev->udev->slot_id;
 751                 if (tt->multi)
 752                         tt_info->ttport = i+1;
 753                 bw_table = &tt_info->bw_table;
 754                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 755                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 756         }
 757         return 0;
 758
 759 free_tts:
 760         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 761         return -ENOMEM;
 762 }
 763
 764
 765 /* All the xhci_tds in the ring's TD list should be freed at this point.
 766  * Should be called with xhci->lock held if there is any chance the TT lists
 767  * will be manipulated by the configure endpoint, allocate device, or update
 768  * hub functions while this function is removing the TT entries from the list.
 769  */
 770 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 771 {
 772         struct xhci_virt_device *dev;
 773         int i;
 774         int old_active_eps = 0;
 775
 776         /* Slot ID 0 is reserved */
 777         if (slot_id == 0 || !xhci->devs[slot_id])
 778                 return;
 779
 780         dev = xhci->devs[slot_id];
 781         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 782         if (!dev)
 783                 return;
 784
 785         if (dev->tt_info)
 786                 old_active_eps = dev->tt_info->active_eps;
 787
 788         for (i = 0; i < 31; ++i) {
 789                 if (dev->eps[i].ring)
 790                         xhci_ring_free(xhci, dev->eps[i].ring);
 791                 if (dev->eps[i].stream_info)
 792                         xhci_free_stream_info(xhci,
 793                                         dev->eps[i].stream_info);
 794                 /* Endpoints on the TT/root port lists should have been removed
 795                  * when usb_disable_device() was called for the device.
 796                  * We can't drop them anyway, because the udev might have gone
 797                  * away by this point, and we can't tell what speed it was.
 798                  */
 799                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 800                         xhci_warn(xhci, "Slot %u endpoint %u "
 801                                         "not removed from BW list!\n",
 802                                         slot_id, i);
 803         }
 804         /* If this is a hub, free the TT(s) from the TT list */
 805         xhci_free_tt_info(xhci, dev, slot_id);
 806         /* If necessary, update the number of active TTs on this root port */
 807         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 808
 809         if (dev->ring_cache) {
 810                 for (i = 0; i < dev->num_rings_cached; i++)
 811                         xhci_ring_free(xhci, dev->ring_cache[i]);
 812                 kfree(dev->ring_cache);
 813         }
 814
 815         if (dev->in_ctx)
 816                 xhci_free_container_ctx(xhci, dev->in_ctx);
 817         if (dev->out_ctx)
 818                 xhci_free_container_ctx(xhci, dev->out_ctx);
 819
 820         kfree(xhci->devs[slot_id]);
 821         xhci->devs[slot_id] = NULL;
 822 }
 823
 824 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 825                 struct usb_device *udev, gfp_t flags)
 826 {
 827         struct xhci_virt_device *dev;
 828         int i;
 829
 830         /* Slot ID 0 is reserved */
 831         if (slot_id == 0 || xhci->devs[slot_id]) {
 832                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 833                 return 0;
 834         }
 835
 836         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 837         if (!xhci->devs[slot_id])
 838                 return 0;
 839         dev = xhci->devs[slot_id];
 840
 841         /* Allocate the (output) device context that will be used in the HC. */
 842         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 843         if (!dev->out_ctx)
 844                 goto fail;
 845
 846         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 847                         (unsigned long long)dev->out_ctx->dma);
 848
 849         /* Allocate the (input) device context for address device command */
 850         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 851         if (!dev->in_ctx)
 852                 goto fail;
 853
 854         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 855                         (unsigned long long)dev->in_ctx->dma);
 856
 857         /* Initialize the cancellation list and watchdog timers for each ep */
 858         for (i = 0; i < 31; i++) {
 859                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 860                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 861                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 862         }
 863
 864         /* Allocate endpoint 0 ring */
 865         dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, false, flags);
 866         if (!dev->eps[0].ring)
 867                 goto fail;
 868
 869         /* Allocate pointers to the ring cache */
 870         dev->ring_cache = kzalloc(
 871                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 872                         flags);
 873         if (!dev->ring_cache)
 874                 goto fail;
 875         dev->num_rings_cached = 0;
 876
 877         init_completion(&dev->cmd_completion);
 878         INIT_LIST_HEAD(&dev->cmd_list);
 879         dev->udev = udev;
 880
 881         /* Point to output device context in dcbaa. */
 882         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 883         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 884                  slot_id,
 885                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 886                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 887
 888         return 1;
 889 fail:
 890         xhci_free_virt_device(xhci, slot_id);
 891         return 0;
 892 }
 893
 894 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
 895                 struct usb_device *udev)
 896 {
 897         struct xhci_virt_device *virt_dev;
 898         struct xhci_ep_ctx      *ep0_ctx;
 899         struct xhci_ring        *ep_ring;
 900
 901         virt_dev = xhci->devs[udev->slot_id];
 902         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
 903         ep_ring = virt_dev->eps[0].ring;
 904         /*
 905          * FIXME we don't keep track of the dequeue pointer very well after a
 906          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
 907          * host to our enqueue pointer.  This should only be called after a
 908          * configured device has reset, so all control transfers should have
 909          * been completed or cancelled before the reset.
 910          */
 911         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
 912                                                         ep_ring->enqueue)
 913                                    | ep_ring->cycle_state);
 914 }
 915
 916 /*
 917  * The xHCI roothub may have ports of differing speeds in any order in the port
 918  * status registers.  xhci->port_array provides an array of the port speed for
 919  * each offset into the port status registers.
 920  *
 921  * The xHCI hardware wants to know the roothub port number that the USB device
 922  * is attached to (or the roothub port its ancestor hub is attached to).  All we
 923  * know is the index of that port under either the USB 2.0 or the USB 3.0
 924  * roothub, but that doesn't give us the real index into the HW port status
 925  * registers.  Scan through the xHCI roothub port array, looking for the Nth
 926  * entry of the correct port speed.  Return the port number of that entry.
 927  */
 928 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
 929                 struct usb_device *udev)
 930 {
 931         struct usb_device *top_dev;
 932         unsigned int num_similar_speed_ports;
 933         unsigned int faked_port_num;
 934         int i;
 935
 936         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
 937                         top_dev = top_dev->parent)
 938                 /* Found device below root hub */;
 939         faked_port_num = top_dev->portnum;
 940         for (i = 0, num_similar_speed_ports = 0;
 941                         i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
 942                 u8 port_speed = xhci->port_array[i];
 943
 944                 /*
 945                  * Skip ports that don't have known speeds, or have duplicate
 946                  * Extended Capabilities port speed entries.
 947                  */
 948                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
 949                         continue;
 950
 951                 /*
 952                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
 953                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
 954                  * matches the device speed, it's a similar speed port.
 955                  */
 956                 if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
 957                         num_similar_speed_ports++;
 958                 if (num_similar_speed_ports == faked_port_num)
 959                         /* Roothub ports are numbered from 1 to N */
 960                         return i+1;
 961         }
 962         return 0;
 963 }
 964
 965 /* Setup an xHCI virtual device for a Set Address command */
 966 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
 967 {
 968         struct xhci_virt_device *dev;
 969         struct xhci_ep_ctx      *ep0_ctx;
 970         struct xhci_slot_ctx    *slot_ctx;
 971         u32                     port_num;
 972         struct usb_device *top_dev;
 973
 974         dev = xhci->devs[udev->slot_id];
 975         /* Slot ID 0 is reserved */
 976         if (udev->slot_id == 0 || !dev) {
 977                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
 978                                 udev->slot_id);
 979                 return -EINVAL;
 980         }
 981         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
 982         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
 983
 984         /* 3) Only the control endpoint is valid - one endpoint context */
 985         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
 986         switch (udev->speed) {
 987         case USB_SPEED_SUPER:
 988                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
 989                 break;
 990         case USB_SPEED_HIGH:
 991                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
 992                 break;
 993         case USB_SPEED_FULL:
 994                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
 995                 break;
 996         case USB_SPEED_LOW:
 997                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
 998                 break;
 999         case USB_SPEED_WIRELESS:
1000                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1001                 return -EINVAL;
1002                 break;
1003         default:
1004                 /* Speed was set earlier, this shouldn't happen. */
1005                 BUG();
1006         }
1007         /* Find the root hub port this device is under */
1008         port_num = xhci_find_real_port_number(xhci, udev);
1009         if (!port_num)
1010                 return -EINVAL;
1011         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1012         /* Set the port number in the virtual_device to the faked port number */
1013         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1014                         top_dev = top_dev->parent)
1015                 /* Found device below root hub */;
1016         dev->fake_port = top_dev->portnum;
1017         dev->real_port = port_num;
1018         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1019         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1020
1021         /* Find the right bandwidth table that this device will be a part of.
1022          * If this is a full speed device attached directly to a root port (or a
1023          * decendent of one), it counts as a primary bandwidth domain, not a
1024          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1025          * will never be created for the HS root hub.
1026          */
1027         if (!udev->tt || !udev->tt->hub->parent) {
1028                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1029         } else {
1030                 struct xhci_root_port_bw_info *rh_bw;
1031                 struct xhci_tt_bw_info *tt_bw;
1032
1033                 rh_bw = &xhci->rh_bw[port_num - 1];
1034                 /* Find the right TT. */
1035                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1036                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1037                                 continue;
1038
1039                         if (!dev->udev->tt->multi ||
1040                                         (udev->tt->multi &&
1041                                          tt_bw->ttport == dev->udev->ttport)) {
1042                                 dev->bw_table = &tt_bw->bw_table;
1043                                 dev->tt_info = tt_bw;
1044                                 break;
1045                         }
1046                 }
1047                 if (!dev->tt_info)
1048                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1049         }
1050
1051         /* Is this a LS/FS device under an external HS hub? */
1052         if (udev->tt && udev->tt->hub->parent) {
1053                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1054                                                 (udev->ttport << 8));
1055                 if (udev->tt->multi)
1056                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1057         }
1058         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1059         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1060
1061         /* Step 4 - ring already allocated */
1062         /* Step 5 */
1063         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1064         /*
1065          * XXX: Not sure about wireless USB devices.
1066          */
1067         switch (udev->speed) {
1068         case USB_SPEED_SUPER:
1069                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1070                 break;
1071         case USB_SPEED_HIGH:
1072         /* USB core guesses at a 64-byte max packet first for FS devices */
1073         case USB_SPEED_FULL:
1074                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1075                 break;
1076         case USB_SPEED_LOW:
1077                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1078                 break;
1079         case USB_SPEED_WIRELESS:
1080                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1081                 return -EINVAL;
1082                 break;
1083         default:
1084                 /* New speed? */
1085                 BUG();
1086         }
1087         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1088         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1089
1090         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1091                                    dev->eps[0].ring->cycle_state);
1092
1093         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1094
1095         return 0;
1096 }
1097
1098 /*
1099  * Convert interval expressed as 2^(bInterval - 1) == interval into
1100  * straight exponent value 2^n == interval.
1101  *
1102  */
1103 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1104                 struct usb_host_endpoint *ep)
1105 {
1106         unsigned int interval;
1107
1108         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1109         if (interval != ep->desc.bInterval - 1)
1110                 dev_warn(&udev->dev,
1111                          "ep %#x - rounding interval to %d %sframes\n",
1112                          ep->desc.bEndpointAddress,
1113                          1 << interval,
1114                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1115
1116         if (udev->speed == USB_SPEED_FULL) {
1117                 /*
1118                  * Full speed isoc endpoints specify interval in frames,
1119                  * not microframes. We are using microframes everywhere,
1120                  * so adjust accordingly.
1121                  */
1122                 interval += 3;  /* 1 frame = 2^3 uframes */
1123         }
1124
1125         return interval;
1126 }
1127
1128 /*
1129  * Convert bInterval expressed in frames (in 1-255 range) to exponent of
1130  * microframes, rounded down to nearest power of 2.
1131  */
1132 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1133                 struct usb_host_endpoint *ep)
1134 {
1135         unsigned int interval;
1136
1137         interval = fls(8 * ep->desc.bInterval) - 1;
1138         interval = clamp_val(interval, 3, 10);
1139         if ((1 << interval) != 8 * ep->desc.bInterval)
1140                 dev_warn(&udev->dev,
1141                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1142                          ep->desc.bEndpointAddress,
1143                          1 << interval,
1144                          8 * ep->desc.bInterval);
1145
1146         return interval;
1147 }
1148
1149 /* Return the polling or NAK interval.
1150  *
1151  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1152  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1153  *
1154  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1155  * is set to 0.
1156  */
1157 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1158                 struct usb_host_endpoint *ep)
1159 {
1160         unsigned int interval = 0;
1161
1162         switch (udev->speed) {
1163         case USB_SPEED_HIGH:
1164                 /* Max NAK rate */
1165                 if (usb_endpoint_xfer_control(&ep->desc) ||
1166                     usb_endpoint_xfer_bulk(&ep->desc)) {
1167                         interval = ep->desc.bInterval;
1168                         break;
1169                 }
1170                 /* Fall through - SS and HS isoc/int have same decoding */
1171
1172         case USB_SPEED_SUPER:
1173                 if (usb_endpoint_xfer_int(&ep->desc) ||
1174                     usb_endpoint_xfer_isoc(&ep->desc)) {
1175                         interval = xhci_parse_exponent_interval(udev, ep);
1176                 }
1177                 break;
1178
1179         case USB_SPEED_FULL:
1180                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1181                         interval = xhci_parse_exponent_interval(udev, ep);
1182                         break;
1183                 }
1184                 /*
1185                  * Fall through for interrupt endpoint interval decoding
1186                  * since it uses the same rules as low speed interrupt
1187                  * endpoints.
1188                  */
1189
1190         case USB_SPEED_LOW:
1191                 if (usb_endpoint_xfer_int(&ep->desc) ||
1192                     usb_endpoint_xfer_isoc(&ep->desc)) {
1193
1194                         interval = xhci_parse_frame_interval(udev, ep);
1195                 }
1196                 break;
1197
1198         default:
1199                 BUG();
1200         }
1201         return EP_INTERVAL(interval);
1202 }
1203
1204 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1205  * High speed endpoint descriptors can define "the number of additional
1206  * transaction opportunities per microframe", but that goes in the Max Burst
1207  * endpoint context field.
1208  */
1209 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1210                 struct usb_host_endpoint *ep)
1211 {
1212         if (udev->speed != USB_SPEED_SUPER ||
1213                         !usb_endpoint_xfer_isoc(&ep->desc))
1214                 return 0;
1215         return ep->ss_ep_comp.bmAttributes;
1216 }
1217
1218 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1219                 struct usb_host_endpoint *ep)
1220 {
1221         int in;
1222         u32 type;
1223
1224         in = usb_endpoint_dir_in(&ep->desc);
1225         if (usb_endpoint_xfer_control(&ep->desc)) {
1226                 type = EP_TYPE(CTRL_EP);
1227         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1228                 if (in)
1229                         type = EP_TYPE(BULK_IN_EP);
1230                 else
1231                         type = EP_TYPE(BULK_OUT_EP);
1232         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1233                 if (in)
1234                         type = EP_TYPE(ISOC_IN_EP);
1235                 else
1236                         type = EP_TYPE(ISOC_OUT_EP);
1237         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1238                 if (in)
1239                         type = EP_TYPE(INT_IN_EP);
1240                 else
1241                         type = EP_TYPE(INT_OUT_EP);
1242         } else {
1243                 BUG();
1244         }
1245         return type;
1246 }
1247
1248 /* Return the maximum endpoint service interval time (ESIT) payload.
1249  * Basically, this is the maxpacket size, multiplied by the burst size
1250  * and mult size.
1251  */
1252 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1253                 struct usb_device *udev,
1254                 struct usb_host_endpoint *ep)
1255 {
1256         int max_burst;
1257         int max_packet;
1258
1259         /* Only applies for interrupt or isochronous endpoints */
1260         if (usb_endpoint_xfer_control(&ep->desc) ||
1261                         usb_endpoint_xfer_bulk(&ep->desc))
1262                 return 0;
1263
1264         if (udev->speed == USB_SPEED_SUPER)
1265                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1266
1267         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1268         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1269         /* A 0 in max burst means 1 transfer per ESIT */
1270         return max_packet * (max_burst + 1);
1271 }
1272
1273 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1274  * Drivers will have to call usb_alloc_streams() to do that.
1275  */
1276 int xhci_endpoint_init(struct xhci_hcd *xhci,
1277                 struct xhci_virt_device *virt_dev,
1278                 struct usb_device *udev,
1279                 struct usb_host_endpoint *ep,
1280                 gfp_t mem_flags)
1281 {
1282         unsigned int ep_index;
1283         struct xhci_ep_ctx *ep_ctx;
1284         struct xhci_ring *ep_ring;
1285         unsigned int max_packet;
1286         unsigned int max_burst;
1287         u32 max_esit_payload;
1288
1289         ep_index = xhci_get_endpoint_index(&ep->desc);
1290         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1291
1292         /* Set up the endpoint ring */
1293         /*
1294          * Isochronous endpoint ring needs bigger size because one isoc URB
1295          * carries multiple packets and it will insert multiple tds to the
1296          * ring.
1297          * This should be replaced with dynamic ring resizing in the future.
1298          */
1299         if (usb_endpoint_xfer_isoc(&ep->desc))
1300                 virt_dev->eps[ep_index].new_ring =
1301                         xhci_ring_alloc(xhci, 8, true, true, mem_flags);
1302         else
1303                 virt_dev->eps[ep_index].new_ring =
1304                         xhci_ring_alloc(xhci, 1, true, false, mem_flags);
1305         if (!virt_dev->eps[ep_index].new_ring) {
1306                 /* Attempt to use the ring cache */
1307                 if (virt_dev->num_rings_cached == 0)
1308                         return -ENOMEM;
1309                 virt_dev->eps[ep_index].new_ring =
1310                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1311                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1312                 virt_dev->num_rings_cached--;
1313                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1314                         usb_endpoint_xfer_isoc(&ep->desc) ? true : false);
1315         }
1316         virt_dev->eps[ep_index].skip = false;
1317         ep_ring = virt_dev->eps[ep_index].new_ring;
1318         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1319
1320         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1321                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1322
1323         /* FIXME dig Mult and streams info out of ep companion desc */
1324
1325         /* Allow 3 retries for everything but isoc;
1326          * CErr shall be set to 0 for Isoch endpoints.
1327          */
1328         if (!usb_endpoint_xfer_isoc(&ep->desc))
1329                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1330         else
1331                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1332
1333         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1334
1335         /* Set the max packet size and max burst */
1336         switch (udev->speed) {
1337         case USB_SPEED_SUPER:
1338                 max_packet = usb_endpoint_maxp(&ep->desc);
1339                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1340                 /* dig out max burst from ep companion desc */
1341                 max_packet = ep->ss_ep_comp.bMaxBurst;
1342                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
1343                 break;
1344         case USB_SPEED_HIGH:
1345                 /* bits 11:12 specify the number of additional transaction
1346                  * opportunities per microframe (USB 2.0, section 9.6.6)
1347                  */
1348                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1349                                 usb_endpoint_xfer_int(&ep->desc)) {
1350                         max_burst = (usb_endpoint_maxp(&ep->desc)
1351                                      & 0x1800) >> 11;
1352                         ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
1353                 }
1354                 /* Fall through */
1355         case USB_SPEED_FULL:
1356         case USB_SPEED_LOW:
1357                 max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1358                 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
1359                 break;
1360         default:
1361                 BUG();
1362         }
1363         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1364         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1365
1366         /*
1367          * XXX no idea how to calculate the average TRB buffer length for bulk
1368          * endpoints, as the driver gives us no clue how big each scatter gather
1369          * list entry (or buffer) is going to be.
1370          *
1371          * For isochronous and interrupt endpoints, we set it to the max
1372          * available, until we have new API in the USB core to allow drivers to
1373          * declare how much bandwidth they actually need.
1374          *
1375          * Normally, it would be calculated by taking the total of the buffer
1376          * lengths in the TD and then dividing by the number of TRBs in a TD,
1377          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1378          * use Event Data TRBs, and we don't chain in a link TRB on short
1379          * transfers, we're basically dividing by 1.
1380          *
1381          * xHCI 1.0 specification indicates that the Average TRB Length should
1382          * be set to 8 for control endpoints.
1383          */
1384         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1385                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1386         else
1387                 ep_ctx->tx_info |=
1388                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1389
1390         /* FIXME Debug endpoint context */
1391         return 0;
1392 }
1393
1394 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1395                 struct xhci_virt_device *virt_dev,
1396                 struct usb_host_endpoint *ep)
1397 {
1398         unsigned int ep_index;
1399         struct xhci_ep_ctx *ep_ctx;
1400
1401         ep_index = xhci_get_endpoint_index(&ep->desc);
1402         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1403
1404         ep_ctx->ep_info = 0;
1405         ep_ctx->ep_info2 = 0;
1406         ep_ctx->deq = 0;
1407         ep_ctx->tx_info = 0;
1408         /* Don't free the endpoint ring until the set interface or configuration
1409          * request succeeds.
1410          */
1411 }
1412
1413 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1414 {
1415         bw_info->ep_interval = 0;
1416         bw_info->mult = 0;
1417         bw_info->num_packets = 0;
1418         bw_info->max_packet_size = 0;
1419         bw_info->type = 0;
1420         bw_info->max_esit_payload = 0;
1421 }
1422
1423 void xhci_update_bw_info(struct xhci_hcd *xhci,
1424                 struct xhci_container_ctx *in_ctx,
1425                 struct xhci_input_control_ctx *ctrl_ctx,
1426                 struct xhci_virt_device *virt_dev)
1427 {
1428         struct xhci_bw_info *bw_info;
1429         struct xhci_ep_ctx *ep_ctx;
1430         unsigned int ep_type;
1431         int i;
1432
1433         for (i = 1; i < 31; ++i) {
1434                 bw_info = &virt_dev->eps[i].bw_info;
1435
1436                 /* We can't tell what endpoint type is being dropped, but
1437                  * unconditionally clearing the bandwidth info for non-periodic
1438                  * endpoints should be harmless because the info will never be
1439                  * set in the first place.
1440                  */
1441                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1442                         /* Dropped endpoint */
1443                         xhci_clear_endpoint_bw_info(bw_info);
1444                         continue;
1445                 }
1446
1447                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1448                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1449                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1450
1451                         /* Ignore non-periodic endpoints */
1452                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1453                                         ep_type != ISOC_IN_EP &&
1454                                         ep_type != INT_IN_EP)
1455                                 continue;
1456
1457                         /* Added or changed endpoint */
1458                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1459                                         le32_to_cpu(ep_ctx->ep_info));
1460                         /* Number of packets and mult are zero-based in the
1461                          * input context, but we want one-based for the
1462                          * interval table.
1463                          */
1464                         bw_info->mult = CTX_TO_EP_MULT(
1465                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1466                         bw_info->num_packets = CTX_TO_MAX_BURST(
1467                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1468                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1469                                         le32_to_cpu(ep_ctx->ep_info2));
1470                         bw_info->type = ep_type;
1471                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1472                                         le32_to_cpu(ep_ctx->tx_info));
1473                 }
1474         }
1475 }
1476
1477 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1478  * Useful when you want to change one particular aspect of the endpoint and then
1479  * issue a configure endpoint command.
1480  */
1481 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1482                 struct xhci_container_ctx *in_ctx,
1483                 struct xhci_container_ctx *out_ctx,
1484                 unsigned int ep_index)
1485 {
1486         struct xhci_ep_ctx *out_ep_ctx;
1487         struct xhci_ep_ctx *in_ep_ctx;
1488
1489         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1490         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1491
1492         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1493         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1494         in_ep_ctx->deq = out_ep_ctx->deq;
1495         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1496 }
1497
1498 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1499  * Useful when you want to change one particular aspect of the endpoint and then
1500  * issue a configure endpoint command.  Only the context entries field matters,
1501  * but we'll copy the whole thing anyway.
1502  */
1503 void xhci_slot_copy(struct xhci_hcd *xhci,
1504                 struct xhci_container_ctx *in_ctx,
1505                 struct xhci_container_ctx *out_ctx)
1506 {
1507         struct xhci_slot_ctx *in_slot_ctx;
1508         struct xhci_slot_ctx *out_slot_ctx;
1509
1510         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1511         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1512
1513         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1514         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1515         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1516         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1517 }
1518
1519 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1520 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1521 {
1522         int i;
1523         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1524         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1525
1526         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1527
1528         if (!num_sp)
1529                 return 0;
1530
1531         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1532         if (!xhci->scratchpad)
1533                 goto fail_sp;
1534
1535         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1536                                      num_sp * sizeof(u64),
1537                                      &xhci->scratchpad->sp_dma, flags);
1538         if (!xhci->scratchpad->sp_array)
1539                 goto fail_sp2;
1540
1541         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1542         if (!xhci->scratchpad->sp_buffers)
1543                 goto fail_sp3;
1544
1545         xhci->scratchpad->sp_dma_buffers =
1546                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1547
1548         if (!xhci->scratchpad->sp_dma_buffers)
1549                 goto fail_sp4;
1550
1551         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1552         for (i = 0; i < num_sp; i++) {
1553                 dma_addr_t dma;
1554                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1555                                 flags);
1556                 if (!buf)
1557                         goto fail_sp5;
1558
1559                 xhci->scratchpad->sp_array[i] = dma;
1560                 xhci->scratchpad->sp_buffers[i] = buf;
1561                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1562         }
1563
1564         return 0;
1565
1566  fail_sp5:
1567         for (i = i - 1; i >= 0; i--) {
1568                 dma_free_coherent(dev, xhci->page_size,
1569                                     xhci->scratchpad->sp_buffers[i],
1570                                     xhci->scratchpad->sp_dma_buffers[i]);
1571         }
1572         kfree(xhci->scratchpad->sp_dma_buffers);
1573
1574  fail_sp4:
1575         kfree(xhci->scratchpad->sp_buffers);
1576
1577  fail_sp3:
1578         dma_free_coherent(dev, num_sp * sizeof(u64),
1579                             xhci->scratchpad->sp_array,
1580                             xhci->scratchpad->sp_dma);
1581
1582  fail_sp2:
1583         kfree(xhci->scratchpad);
1584         xhci->scratchpad = NULL;
1585
1586  fail_sp:
1587         return -ENOMEM;
1588 }
1589
1590 static void scratchpad_free(struct xhci_hcd *xhci)
1591 {
1592         int num_sp;
1593         int i;
1594         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1595
1596         if (!xhci->scratchpad)
1597                 return;
1598
1599         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1600
1601         for (i = 0; i < num_sp; i++) {
1602                 dma_free_coherent(&pdev->dev, xhci->page_size,
1603                                     xhci->scratchpad->sp_buffers[i],
1604                                     xhci->scratchpad->sp_dma_buffers[i]);
1605         }
1606         kfree(xhci->scratchpad->sp_dma_buffers);
1607         kfree(xhci->scratchpad->sp_buffers);
1608         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1609                             xhci->scratchpad->sp_array,
1610                             xhci->scratchpad->sp_dma);
1611         kfree(xhci->scratchpad);
1612         xhci->scratchpad = NULL;
1613 }
1614
1615 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1616                 bool allocate_in_ctx, bool allocate_completion,
1617                 gfp_t mem_flags)
1618 {
1619         struct xhci_command *command;
1620
1621         command = kzalloc(sizeof(*command), mem_flags);
1622         if (!command)
1623                 return NULL;
1624
1625         if (allocate_in_ctx) {
1626                 command->in_ctx =
1627                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1628                                         mem_flags);
1629                 if (!command->in_ctx) {
1630                         kfree(command);
1631                         return NULL;
1632                 }
1633         }
1634
1635         if (allocate_completion) {
1636                 command->completion =
1637                         kzalloc(sizeof(struct completion), mem_flags);
1638                 if (!command->completion) {
1639                         xhci_free_container_ctx(xhci, command->in_ctx);
1640                         kfree(command);
1641                         return NULL;
1642                 }
1643                 init_completion(command->completion);
1644         }
1645
1646         command->status = 0;
1647         INIT_LIST_HEAD(&command->cmd_list);
1648         return command;
1649 }
1650
1651 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1652 {
1653         if (urb_priv) {
1654                 kfree(urb_priv->td[0]);
1655                 kfree(urb_priv);
1656         }
1657 }
1658
1659 void xhci_free_command(struct xhci_hcd *xhci,
1660                 struct xhci_command *command)
1661 {
1662         xhci_free_container_ctx(xhci,
1663                         command->in_ctx);
1664         kfree(command->completion);
1665         kfree(command);
1666 }
1667
1668 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1669 {
1670         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1671         struct dev_info *dev_info, *next;
1672         unsigned long   flags;
1673         int size;
1674         int i;
1675
1676         /* Free the Event Ring Segment Table and the actual Event Ring */
1677         if (xhci->ir_set) {
1678                 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
1679                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
1680                 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
1681         }
1682         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1683         if (xhci->erst.entries)
1684                 dma_free_coherent(&pdev->dev, size,
1685                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1686         xhci->erst.entries = NULL;
1687         xhci_dbg(xhci, "Freed ERST\n");
1688         if (xhci->event_ring)
1689                 xhci_ring_free(xhci, xhci->event_ring);
1690         xhci->event_ring = NULL;
1691         xhci_dbg(xhci, "Freed event ring\n");
1692
1693         xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
1694         if (xhci->cmd_ring)
1695                 xhci_ring_free(xhci, xhci->cmd_ring);
1696         xhci->cmd_ring = NULL;
1697         xhci_dbg(xhci, "Freed command ring\n");
1698
1699         for (i = 1; i < MAX_HC_SLOTS; ++i)
1700                 xhci_free_virt_device(xhci, i);
1701
1702         if (xhci->segment_pool)
1703                 dma_pool_destroy(xhci->segment_pool);
1704         xhci->segment_pool = NULL;
1705         xhci_dbg(xhci, "Freed segment pool\n");
1706
1707         if (xhci->device_pool)
1708                 dma_pool_destroy(xhci->device_pool);
1709         xhci->device_pool = NULL;
1710         xhci_dbg(xhci, "Freed device context pool\n");
1711
1712         if (xhci->small_streams_pool)
1713                 dma_pool_destroy(xhci->small_streams_pool);
1714         xhci->small_streams_pool = NULL;
1715         xhci_dbg(xhci, "Freed small stream array pool\n");
1716
1717         if (xhci->medium_streams_pool)
1718                 dma_pool_destroy(xhci->medium_streams_pool);
1719         xhci->medium_streams_pool = NULL;
1720         xhci_dbg(xhci, "Freed medium stream array pool\n");
1721
1722         xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
1723         if (xhci->dcbaa)
1724                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1725                                 xhci->dcbaa, xhci->dcbaa->dma);
1726         xhci->dcbaa = NULL;
1727
1728         scratchpad_free(xhci);
1729
1730         spin_lock_irqsave(&xhci->lock, flags);
1731         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1732                 list_del(&dev_info->list);
1733                 kfree(dev_info);
1734         }
1735         spin_unlock_irqrestore(&xhci->lock, flags);
1736
1737         xhci->num_usb2_ports = 0;
1738         xhci->num_usb3_ports = 0;
1739         kfree(xhci->usb2_ports);
1740         kfree(xhci->usb3_ports);
1741         kfree(xhci->port_array);
1742         kfree(xhci->rh_bw);
1743
1744         xhci->page_size = 0;
1745         xhci->page_shift = 0;
1746         xhci->bus_state[0].bus_suspended = 0;
1747         xhci->bus_state[1].bus_suspended = 0;
1748 }
1749
1750 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1751                 struct xhci_segment *input_seg,
1752                 union xhci_trb *start_trb,
1753                 union xhci_trb *end_trb,
1754                 dma_addr_t input_dma,
1755                 struct xhci_segment *result_seg,
1756                 char *test_name, int test_number)
1757 {
1758         unsigned long long start_dma;
1759         unsigned long long end_dma;
1760         struct xhci_segment *seg;
1761
1762         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1763         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1764
1765         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1766         if (seg != result_seg) {
1767                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1768                                 test_name, test_number);
1769                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1770                                 "input DMA 0x%llx\n",
1771                                 input_seg,
1772                                 (unsigned long long) input_dma);
1773                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1774                                 "ending TRB %p (0x%llx DMA)\n",
1775                                 start_trb, start_dma,
1776                                 end_trb, end_dma);
1777                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1778                                 result_seg, seg);
1779                 return -1;
1780         }
1781         return 0;
1782 }
1783
1784 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1785 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1786 {
1787         struct {
1788                 dma_addr_t              input_dma;
1789                 struct xhci_segment     *result_seg;
1790         } simple_test_vector [] = {
1791                 /* A zeroed DMA field should fail */
1792                 { 0, NULL },
1793                 /* One TRB before the ring start should fail */
1794                 { xhci->event_ring->first_seg->dma - 16, NULL },
1795                 /* One byte before the ring start should fail */
1796                 { xhci->event_ring->first_seg->dma - 1, NULL },
1797                 /* Starting TRB should succeed */
1798                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1799                 /* Ending TRB should succeed */
1800                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1801                         xhci->event_ring->first_seg },
1802                 /* One byte after the ring end should fail */
1803                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1804                 /* One TRB after the ring end should fail */
1805                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1806                 /* An address of all ones should fail */
1807                 { (dma_addr_t) (~0), NULL },
1808         };
1809         struct {
1810                 struct xhci_segment     *input_seg;
1811                 union xhci_trb          *start_trb;
1812                 union xhci_trb          *end_trb;
1813                 dma_addr_t              input_dma;
1814                 struct xhci_segment     *result_seg;
1815         } complex_test_vector [] = {
1816                 /* Test feeding a valid DMA address from a different ring */
1817                 {       .input_seg = xhci->event_ring->first_seg,
1818                         .start_trb = xhci->event_ring->first_seg->trbs,
1819                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1820                         .input_dma = xhci->cmd_ring->first_seg->dma,
1821                         .result_seg = NULL,
1822                 },
1823                 /* Test feeding a valid end TRB from a different ring */
1824                 {       .input_seg = xhci->event_ring->first_seg,
1825                         .start_trb = xhci->event_ring->first_seg->trbs,
1826                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1827                         .input_dma = xhci->cmd_ring->first_seg->dma,
1828                         .result_seg = NULL,
1829                 },
1830                 /* Test feeding a valid start and end TRB from a different ring */
1831                 {       .input_seg = xhci->event_ring->first_seg,
1832                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1833                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1834                         .input_dma = xhci->cmd_ring->first_seg->dma,
1835                         .result_seg = NULL,
1836                 },
1837                 /* TRB in this ring, but after this TD */
1838                 {       .input_seg = xhci->event_ring->first_seg,
1839                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1840                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1841                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1842                         .result_seg = NULL,
1843                 },
1844                 /* TRB in this ring, but before this TD */
1845                 {       .input_seg = xhci->event_ring->first_seg,
1846                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1847                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1848                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1849                         .result_seg = NULL,
1850                 },
1851                 /* TRB in this ring, but after this wrapped TD */
1852                 {       .input_seg = xhci->event_ring->first_seg,
1853                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1854                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1855                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1856                         .result_seg = NULL,
1857                 },
1858                 /* TRB in this ring, but before this wrapped TD */
1859                 {       .input_seg = xhci->event_ring->first_seg,
1860                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1861                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1862                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1863                         .result_seg = NULL,
1864                 },
1865                 /* TRB not in this ring, and we have a wrapped TD */
1866                 {       .input_seg = xhci->event_ring->first_seg,
1867                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1868                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1869                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1870                         .result_seg = NULL,
1871                 },
1872         };
1873
1874         unsigned int num_tests;
1875         int i, ret;
1876
1877         num_tests = ARRAY_SIZE(simple_test_vector);
1878         for (i = 0; i < num_tests; i++) {
1879                 ret = xhci_test_trb_in_td(xhci,
1880                                 xhci->event_ring->first_seg,
1881                                 xhci->event_ring->first_seg->trbs,
1882                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1883                                 simple_test_vector[i].input_dma,
1884                                 simple_test_vector[i].result_seg,
1885                                 "Simple", i);
1886                 if (ret < 0)
1887                         return ret;
1888         }
1889
1890         num_tests = ARRAY_SIZE(complex_test_vector);
1891         for (i = 0; i < num_tests; i++) {
1892                 ret = xhci_test_trb_in_td(xhci,
1893                                 complex_test_vector[i].input_seg,
1894                                 complex_test_vector[i].start_trb,
1895                                 complex_test_vector[i].end_trb,
1896                                 complex_test_vector[i].input_dma,
1897                                 complex_test_vector[i].result_seg,
1898                                 "Complex", i);
1899                 if (ret < 0)
1900                         return ret;
1901         }
1902         xhci_dbg(xhci, "TRB math tests passed.\n");
1903         return 0;
1904 }
1905
1906 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
1907 {
1908         u64 temp;
1909         dma_addr_t deq;
1910
1911         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
1912                         xhci->event_ring->dequeue);
1913         if (deq == 0 && !in_interrupt())
1914                 xhci_warn(xhci, "WARN something wrong with SW event ring "
1915                                 "dequeue ptr.\n");
1916         /* Update HC event ring dequeue pointer */
1917         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
1918         temp &= ERST_PTR_MASK;
1919         /* Don't clear the EHB bit (which is RW1C) because
1920          * there might be more events to service.
1921          */
1922         temp &= ~ERST_EHB;
1923         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
1924                         "preserving EHB bit\n");
1925         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
1926                         &xhci->ir_set->erst_dequeue);
1927 }
1928
1929 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
1930                 __le32 __iomem *addr, u8 major_revision)
1931 {
1932         u32 temp, port_offset, port_count;
1933         int i;
1934
1935         if (major_revision > 0x03) {
1936                 xhci_warn(xhci, "Ignoring unknown port speed, "
1937                                 "Ext Cap %p, revision = 0x%x\n",
1938                                 addr, major_revision);
1939                 /* Ignoring port protocol we can't understand. FIXME */
1940                 return;
1941         }
1942
1943         /* Port offset and count in the third dword, see section 7.2 */
1944         temp = xhci_readl(xhci, addr + 2);
1945         port_offset = XHCI_EXT_PORT_OFF(temp);
1946         port_count = XHCI_EXT_PORT_COUNT(temp);
1947         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
1948                         "count = %u, revision = 0x%x\n",
1949                         addr, port_offset, port_count, major_revision);
1950         /* Port count includes the current port offset */
1951         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
1952                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
1953                 return;
1954
1955         /* Check the host's USB2 LPM capability */
1956         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
1957                         (temp & XHCI_L1C)) {
1958                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
1959                 xhci->sw_lpm_support = 1;
1960         }
1961
1962         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
1963                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
1964                 xhci->sw_lpm_support = 1;
1965                 if (temp & XHCI_HLC) {
1966                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
1967                         xhci->hw_lpm_support = 1;
1968                 }
1969         }
1970
1971         port_offset--;
1972         for (i = port_offset; i < (port_offset + port_count); i++) {
1973                 /* Duplicate entry.  Ignore the port if the revisions differ. */
1974                 if (xhci->port_array[i] != 0) {
1975                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
1976                                         " port %u\n", addr, i);
1977                         xhci_warn(xhci, "Port was marked as USB %u, "
1978                                         "duplicated as USB %u\n",
1979                                         xhci->port_array[i], major_revision);
1980                         /* Only adjust the roothub port counts if we haven't
1981                          * found a similar duplicate.
1982                          */
1983                         if (xhci->port_array[i] != major_revision &&
1984                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
1985                                 if (xhci->port_array[i] == 0x03)
1986                                         xhci->num_usb3_ports--;
1987                                 else
1988                                         xhci->num_usb2_ports--;
1989                                 xhci->port_array[i] = DUPLICATE_ENTRY;
1990                         }
1991                         /* FIXME: Should we disable the port? */
1992                         continue;
1993                 }
1994                 xhci->port_array[i] = major_revision;
1995                 if (major_revision == 0x03)
1996                         xhci->num_usb3_ports++;
1997                 else
1998                         xhci->num_usb2_ports++;
1999         }
2000         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2001 }
2002
2003 /*
2004  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2005  * specify what speeds each port is supposed to be.  We can't count on the port
2006  * speed bits in the PORTSC register being correct until a device is connected,
2007  * but we need to set up the two fake roothubs with the correct number of USB
2008  * 3.0 and USB 2.0 ports at host controller initialization time.
2009  */
2010 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2011 {
2012         __le32 __iomem *addr;
2013         u32 offset;
2014         unsigned int num_ports;
2015         int i, j, port_index;
2016
2017         addr = &xhci->cap_regs->hcc_params;
2018         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2019         if (offset == 0) {
2020                 xhci_err(xhci, "No Extended Capability registers, "
2021                                 "unable to set up roothub.\n");
2022                 return -ENODEV;
2023         }
2024
2025         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2026         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2027         if (!xhci->port_array)
2028                 return -ENOMEM;
2029
2030         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2031         if (!xhci->rh_bw)
2032                 return -ENOMEM;
2033         for (i = 0; i < num_ports; i++) {
2034                 struct xhci_interval_bw_table *bw_table;
2035
2036                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2037                 bw_table = &xhci->rh_bw[i].bw_table;
2038                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2039                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2040         }
2041
2042         /*
2043          * For whatever reason, the first capability offset is from the
2044          * capability register base, not from the HCCPARAMS register.
2045          * See section 5.3.6 for offset calculation.
2046          */
2047         addr = &xhci->cap_regs->hc_capbase + offset;
2048         while (1) {
2049                 u32 cap_id;
2050
2051                 cap_id = xhci_readl(xhci, addr);
2052                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2053                         xhci_add_in_port(xhci, num_ports, addr,
2054                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id));
2055                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2056                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2057                                 == num_ports)
2058                         break;
2059                 /*
2060                  * Once you're into the Extended Capabilities, the offset is
2061                  * always relative to the register holding the offset.
2062                  */
2063                 addr += offset;
2064         }
2065
2066         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2067                 xhci_warn(xhci, "No ports on the roothubs?\n");
2068                 return -ENODEV;
2069         }
2070         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2071                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2072
2073         /* Place limits on the number of roothub ports so that the hub
2074          * descriptors aren't longer than the USB core will allocate.
2075          */
2076         if (xhci->num_usb3_ports > 15) {
2077                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2078                 xhci->num_usb3_ports = 15;
2079         }
2080         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2081                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2082                                 USB_MAXCHILDREN);
2083                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2084         }
2085
2086         /*
2087          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2088          * Not sure how the USB core will handle a hub with no ports...
2089          */
2090         if (xhci->num_usb2_ports) {
2091                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2092                                 xhci->num_usb2_ports, flags);
2093                 if (!xhci->usb2_ports)
2094                         return -ENOMEM;
2095
2096                 port_index = 0;
2097                 for (i = 0; i < num_ports; i++) {
2098                         if (xhci->port_array[i] == 0x03 ||
2099                                         xhci->port_array[i] == 0 ||
2100                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2101                                 continue;
2102
2103                         xhci->usb2_ports[port_index] =
2104                                 &xhci->op_regs->port_status_base +
2105                                 NUM_PORT_REGS*i;
2106                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2107                                         "addr = %p\n", i,
2108                                         xhci->usb2_ports[port_index]);
2109                         port_index++;
2110                         if (port_index == xhci->num_usb2_ports)
2111                                 break;
2112                 }
2113         }
2114         if (xhci->num_usb3_ports) {
2115                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2116                                 xhci->num_usb3_ports, flags);
2117                 if (!xhci->usb3_ports)
2118                         return -ENOMEM;
2119
2120                 port_index = 0;
2121                 for (i = 0; i < num_ports; i++)
2122                         if (xhci->port_array[i] == 0x03) {
2123                                 xhci->usb3_ports[port_index] =
2124                                         &xhci->op_regs->port_status_base +
2125                                         NUM_PORT_REGS*i;
2126                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2127                                                 "addr = %p\n", i,
2128                                                 xhci->usb3_ports[port_index]);
2129                                 port_index++;
2130                                 if (port_index == xhci->num_usb3_ports)
2131                                         break;
2132                         }
2133         }
2134         return 0;
2135 }
2136
2137 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2138 {
2139         dma_addr_t      dma;
2140         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2141         unsigned int    val, val2;
2142         u64             val_64;
2143         struct xhci_segment     *seg;
2144         u32 page_size;
2145         int i;
2146
2147         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2148         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2149         for (i = 0; i < 16; i++) {
2150                 if ((0x1 & page_size) != 0)
2151                         break;
2152                 page_size = page_size >> 1;
2153         }
2154         if (i < 16)
2155                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2156         else
2157                 xhci_warn(xhci, "WARN: no supported page size\n");
2158         /* Use 4K pages, since that's common and the minimum the HC supports */
2159         xhci->page_shift = 12;
2160         xhci->page_size = 1 << xhci->page_shift;
2161         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2162
2163         /*
2164          * Program the Number of Device Slots Enabled field in the CONFIG
2165          * register with the max value of slots the HC can handle.
2166          */
2167         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2168         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2169                         (unsigned int) val);
2170         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2171         val |= (val2 & ~HCS_SLOTS_MASK);
2172         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2173                         (unsigned int) val);
2174         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2175
2176         /*
2177          * Section 5.4.8 - doorbell array must be
2178          * "physically contiguous and 64-byte (cache line) aligned".
2179          */
2180         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2181                         GFP_KERNEL);
2182         if (!xhci->dcbaa)
2183                 goto fail;
2184         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2185         xhci->dcbaa->dma = dma;
2186         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2187                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2188         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2189
2190         /*
2191          * Initialize the ring segment pool.  The ring must be a contiguous
2192          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2193          * however, the command ring segment needs 64-byte aligned segments,
2194          * so we pick the greater alignment need.
2195          */
2196         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2197                         SEGMENT_SIZE, 64, xhci->page_size);
2198
2199         /* See Table 46 and Note on Figure 55 */
2200         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2201                         2112, 64, xhci->page_size);
2202         if (!xhci->segment_pool || !xhci->device_pool)
2203                 goto fail;
2204
2205         /* Linear stream context arrays don't have any boundary restrictions,
2206          * and only need to be 16-byte aligned.
2207          */
2208         xhci->small_streams_pool =
2209                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2210                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2211         xhci->medium_streams_pool =
2212                 dma_pool_create("xHCI 1KB stream ctx arrays",
2213                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2214         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2215          * will be allocated with dma_alloc_coherent()
2216          */
2217
2218         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2219                 goto fail;
2220
2221         /* Set up the command ring to have one segments for now. */
2222         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, false, flags);
2223         if (!xhci->cmd_ring)
2224                 goto fail;
2225         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2226         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2227                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2228
2229         /* Set the address in the Command Ring Control register */
2230         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2231         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2232                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2233                 xhci->cmd_ring->cycle_state;
2234         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2235         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2236         xhci_dbg_cmd_ptrs(xhci);
2237
2238         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2239         val &= DBOFF_MASK;
2240         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2241                         " from cap regs base addr\n", val);
2242         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2243         xhci_dbg_regs(xhci);
2244         xhci_print_run_regs(xhci);
2245         /* Set ir_set to interrupt register set 0 */
2246         xhci->ir_set = &xhci->run_regs->ir_set[0];
2247
2248         /*
2249          * Event ring setup: Allocate a normal ring, but also setup
2250          * the event ring segment table (ERST).  Section 4.9.3.
2251          */
2252         xhci_dbg(xhci, "// Allocating event ring\n");
2253         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, false,
2254                                                 flags);
2255         if (!xhci->event_ring)
2256                 goto fail;
2257         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2258                 goto fail;
2259
2260         xhci->erst.entries = dma_alloc_coherent(dev,
2261                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2262                         GFP_KERNEL);
2263         if (!xhci->erst.entries)
2264                 goto fail;
2265         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2266                         (unsigned long long)dma);
2267
2268         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2269         xhci->erst.num_entries = ERST_NUM_SEGS;
2270         xhci->erst.erst_dma_addr = dma;
2271         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2272                         xhci->erst.num_entries,
2273                         xhci->erst.entries,
2274                         (unsigned long long)xhci->erst.erst_dma_addr);
2275
2276         /* set ring base address and size for each segment table entry */
2277         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2278                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2279                 entry->seg_addr = cpu_to_le64(seg->dma);
2280                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2281                 entry->rsvd = 0;
2282                 seg = seg->next;
2283         }
2284
2285         /* set ERST count with the number of entries in the segment table */
2286         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2287         val &= ERST_SIZE_MASK;
2288         val |= ERST_NUM_SEGS;
2289         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2290                         val);
2291         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2292
2293         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2294         /* set the segment table base address */
2295         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2296                         (unsigned long long)xhci->erst.erst_dma_addr);
2297         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2298         val_64 &= ERST_PTR_MASK;
2299         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2300         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2301
2302         /* Set the event ring dequeue address */
2303         xhci_set_hc_event_deq(xhci);
2304         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2305         xhci_print_ir_set(xhci, 0);
2306
2307         /*
2308          * XXX: Might need to set the Interrupter Moderation Register to
2309          * something other than the default (~1ms minimum between interrupts).
2310          * See section 5.5.1.2.
2311          */
2312         init_completion(&xhci->addr_dev);
2313         for (i = 0; i < MAX_HC_SLOTS; ++i)
2314                 xhci->devs[i] = NULL;
2315         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2316                 xhci->bus_state[0].resume_done[i] = 0;
2317                 xhci->bus_state[1].resume_done[i] = 0;
2318         }
2319
2320         if (scratchpad_alloc(xhci, flags))
2321                 goto fail;
2322         if (xhci_setup_port_arrays(xhci, flags))
2323                 goto fail;
2324
2325         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2326
2327         return 0;
2328
2329 fail:
2330         xhci_warn(xhci, "Couldn't initialize memory\n");
2331         xhci_mem_cleanup(xhci);
2332         return -ENOMEM;
2333 }