Pileus Git - ~andy/linux/blob - drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/gfp.h>
  24 #include <asm/unaligned.h>
  25
  26 #include "xhci.h"
  27 #include "xhci-trace.h"
  28
  29 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  30 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  31                          PORT_RC | PORT_PLC | PORT_PE)
  32
  33 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  34 static u8 usb_bos_descriptor [] = {
  35         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  36         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  37         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  38         0x1,                            /*  __u8 bNumDeviceCaps */
  39         /* First device capability */
  40         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  41         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  42         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  43         0x00,                           /* bmAttributes, LTM off by default */
  44         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  45         0x03,                           /* bFunctionalitySupport,
  46                                            USB 3.0 speed only */
  47         0x00,                           /* bU1DevExitLat, set later. */
  48         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  49 };
  50
  51
  52 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  53                 struct usb_hub_descriptor *desc, int ports)
  54 {
  55         u16 temp;
  56
  57         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  58         desc->bHubContrCurrent = 0;
  59
  60         desc->bNbrPorts = ports;
  61         temp = 0;
  62         /* Bits 1:0 - support per-port power switching, or power always on */
  63         if (HCC_PPC(xhci->hcc_params))
  64                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  65         else
  66                 temp |= HUB_CHAR_NO_LPSM;
  67         /* Bit  2 - root hubs are not part of a compound device */
  68         /* Bits 4:3 - individual port over current protection */
  69         temp |= HUB_CHAR_INDV_PORT_OCPM;
  70         /* Bits 6:5 - no TTs in root ports */
  71         /* Bit  7 - no port indicators */
  72         desc->wHubCharacteristics = cpu_to_le16(temp);
  73 }
  74
  75 /* Fill in the USB 2.0 roothub descriptor */
  76 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  77                 struct usb_hub_descriptor *desc)
  78 {
  79         int ports;
  80         u16 temp;
  81         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  82         u32 portsc;
  83         unsigned int i;
  84
  85         ports = xhci->num_usb2_ports;
  86
  87         xhci_common_hub_descriptor(xhci, desc, ports);
  88         desc->bDescriptorType = USB_DT_HUB;
  89         temp = 1 + (ports / 8);
  90         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  91
  92         /* The Device Removable bits are reported on a byte granularity.
  93          * If the port doesn't exist within that byte, the bit is set to 0.
  94          */
  95         memset(port_removable, 0, sizeof(port_removable));
  96         for (i = 0; i < ports; i++) {
  97                 portsc = readl(xhci->usb2_ports[i]);
  98                 /* If a device is removable, PORTSC reports a 0, same as in the
  99                  * hub descriptor DeviceRemovable bits.
 100                  */
 101                 if (portsc & PORT_DEV_REMOVE)
 102                         /* This math is hairy because bit 0 of DeviceRemovable
 103                          * is reserved, and bit 1 is for port 1, etc.
 104                          */
 105                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 106         }
 107
 108         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 109          * ports on it.  The USB 2.0 specification says that there are two
 110          * variable length fields at the end of the hub descriptor:
 111          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 112          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 113          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 114          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 115          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 116          * set of ports that actually exist.
 117          */
 118         memset(desc->u.hs.DeviceRemovable, 0xff,
 119                         sizeof(desc->u.hs.DeviceRemovable));
 120         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 121                         sizeof(desc->u.hs.PortPwrCtrlMask));
 122
 123         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 124                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 125                                 sizeof(__u8));
 126 }
 127
 128 /* Fill in the USB 3.0 roothub descriptor */
 129 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 130                 struct usb_hub_descriptor *desc)
 131 {
 132         int ports;
 133         u16 port_removable;
 134         u32 portsc;
 135         unsigned int i;
 136
 137         ports = xhci->num_usb3_ports;
 138         xhci_common_hub_descriptor(xhci, desc, ports);
 139         desc->bDescriptorType = USB_DT_SS_HUB;
 140         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 141
 142         /* header decode latency should be zero for roothubs,
 143          * see section 4.23.5.2.
 144          */
 145         desc->u.ss.bHubHdrDecLat = 0;
 146         desc->u.ss.wHubDelay = 0;
 147
 148         port_removable = 0;
 149         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 150         for (i = 0; i < ports; i++) {
 151                 portsc = readl(xhci->usb3_ports[i]);
 152                 if (portsc & PORT_DEV_REMOVE)
 153                         port_removable |= 1 << (i + 1);
 154         }
 155
 156         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 157 }
 158
 159 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 160                 struct usb_hub_descriptor *desc)
 161 {
 162
 163         if (hcd->speed == HCD_USB3)
 164                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 165         else
 166                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 167
 168 }
 169
 170 static unsigned int xhci_port_speed(unsigned int port_status)
 171 {
 172         if (DEV_LOWSPEED(port_status))
 173                 return USB_PORT_STAT_LOW_SPEED;
 174         if (DEV_HIGHSPEED(port_status))
 175                 return USB_PORT_STAT_HIGH_SPEED;
 176         /*
 177          * FIXME: Yes, we should check for full speed, but the core uses that as
 178          * a default in portspeed() in usb/core/hub.c (which is the only place
 179          * USB_PORT_STAT_*_SPEED is used).
 180          */
 181         return 0;
 182 }
 183
 184 /*
 185  * These bits are Read Only (RO) and should be saved and written to the
 186  * registers: 0, 3, 10:13, 30
 187  * connect status, over-current status, port speed, and device removable.
 188  * connect status and port speed are also sticky - meaning they're in
 189  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 190  */
 191 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 192 /*
 193  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 194  * bits 5:8, 9, 14:15, 25:27
 195  * link state, port power, port indicator state, "wake on" enable state
 196  */
 197 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 198 /*
 199  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 200  * bit 4 (port reset)
 201  */
 202 #define XHCI_PORT_RW1S  ((1<<4))
 203 /*
 204  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 205  * bits 1, 17, 18, 19, 20, 21, 22, 23
 206  * port enable/disable, and
 207  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 208  * over-current, reset, link state, and L1 change
 209  */
 210 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 211 /*
 212  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 213  * latched in
 214  */
 215 #define XHCI_PORT_RW    ((1<<16))
 216 /*
 217  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 218  * bits 2, 24, 28:31
 219  */
 220 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 221
 222 /*
 223  * Given a port state, this function returns a value that would result in the
 224  * port being in the same state, if the value was written to the port status
 225  * control register.
 226  * Save Read Only (RO) bits and save read/write bits where
 227  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 228  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 229  */
 230 u32 xhci_port_state_to_neutral(u32 state)
 231 {
 232         /* Save read-only status and port state */
 233         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 234 }
 235
 236 /*
 237  * find slot id based on port number.
 238  * @port: The one-based port number from one of the two split roothubs.
 239  */
 240 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 241                 u16 port)
 242 {
 243         int slot_id;
 244         int i;
 245         enum usb_device_speed speed;
 246
 247         slot_id = 0;
 248         for (i = 0; i < MAX_HC_SLOTS; i++) {
 249                 if (!xhci->devs[i])
 250                         continue;
 251                 speed = xhci->devs[i]->udev->speed;
 252                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 253                                 && xhci->devs[i]->fake_port == port) {
 254                         slot_id = i;
 255                         break;
 256                 }
 257         }
 258
 259         return slot_id;
 260 }
 261
 262 /*
 263  * Stop device
 264  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 265  * to complete.
 266  * suspend will set to 1, if suspend bit need to set in command.
 267  */
 268 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 269 {
 270         struct xhci_virt_device *virt_dev;
 271         struct xhci_command *cmd;
 272         unsigned long flags;
 273         int timeleft;
 274         int ret;
 275         int i;
 276
 277         ret = 0;
 278         virt_dev = xhci->devs[slot_id];
 279         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 280         if (!cmd) {
 281                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 282                 return -ENOMEM;
 283         }
 284
 285         spin_lock_irqsave(&xhci->lock, flags);
 286         for (i = LAST_EP_INDEX; i > 0; i--) {
 287                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
 288                         xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
 289         }
 290         cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
 291         list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
 292         xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
 293         xhci_ring_cmd_db(xhci);
 294         spin_unlock_irqrestore(&xhci->lock, flags);
 295
 296         /* Wait for last stop endpoint command to finish */
 297         timeleft = wait_for_completion_interruptible_timeout(
 298                         cmd->completion,
 299                         XHCI_CMD_DEFAULT_TIMEOUT);
 300         if (timeleft <= 0) {
 301                 xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
 302                                 timeleft == 0 ? "Timeout" : "Signal");
 303                 spin_lock_irqsave(&xhci->lock, flags);
 304                 /* The timeout might have raced with the event ring handler, so
 305                  * only delete from the list if the item isn't poisoned.
 306                  */
 307                 if (cmd->cmd_list.next != LIST_POISON1)
 308                         list_del(&cmd->cmd_list);
 309                 spin_unlock_irqrestore(&xhci->lock, flags);
 310                 ret = -ETIME;
 311                 goto command_cleanup;
 312         }
 313
 314 command_cleanup:
 315         xhci_free_command(xhci, cmd);
 316         return ret;
 317 }
 318
 319 /*
 320  * Ring device, it rings the all doorbells unconditionally.
 321  */
 322 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 323 {
 324         int i;
 325
 326         for (i = 0; i < LAST_EP_INDEX + 1; i++)
 327                 if (xhci->devs[slot_id]->eps[i].ring &&
 328                     xhci->devs[slot_id]->eps[i].ring->dequeue)
 329                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 330
 331         return;
 332 }
 333
 334 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 335                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 336 {
 337         /* Don't allow the USB core to disable SuperSpeed ports. */
 338         if (hcd->speed == HCD_USB3) {
 339                 xhci_dbg(xhci, "Ignoring request to disable "
 340                                 "SuperSpeed port.\n");
 341                 return;
 342         }
 343
 344         /* Write 1 to disable the port */
 345         writel(port_status | PORT_PE, addr);
 346         port_status = readl(addr);
 347         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 348                         wIndex, port_status);
 349 }
 350
 351 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 352                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 353 {
 354         char *port_change_bit;
 355         u32 status;
 356
 357         switch (wValue) {
 358         case USB_PORT_FEAT_C_RESET:
 359                 status = PORT_RC;
 360                 port_change_bit = "reset";
 361                 break;
 362         case USB_PORT_FEAT_C_BH_PORT_RESET:
 363                 status = PORT_WRC;
 364                 port_change_bit = "warm(BH) reset";
 365                 break;
 366         case USB_PORT_FEAT_C_CONNECTION:
 367                 status = PORT_CSC;
 368                 port_change_bit = "connect";
 369                 break;
 370         case USB_PORT_FEAT_C_OVER_CURRENT:
 371                 status = PORT_OCC;
 372                 port_change_bit = "over-current";
 373                 break;
 374         case USB_PORT_FEAT_C_ENABLE:
 375                 status = PORT_PEC;
 376                 port_change_bit = "enable/disable";
 377                 break;
 378         case USB_PORT_FEAT_C_SUSPEND:
 379                 status = PORT_PLC;
 380                 port_change_bit = "suspend/resume";
 381                 break;
 382         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 383                 status = PORT_PLC;
 384                 port_change_bit = "link state";
 385                 break;
 386         default:
 387                 /* Should never happen */
 388                 return;
 389         }
 390         /* Change bits are all write 1 to clear */
 391         writel(port_status | status, addr);
 392         port_status = readl(addr);
 393         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 394                         port_change_bit, wIndex, port_status);
 395 }
 396
 397 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 398 {
 399         int max_ports;
 400         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 401
 402         if (hcd->speed == HCD_USB3) {
 403                 max_ports = xhci->num_usb3_ports;
 404                 *port_array = xhci->usb3_ports;
 405         } else {
 406                 max_ports = xhci->num_usb2_ports;
 407                 *port_array = xhci->usb2_ports;
 408         }
 409
 410         return max_ports;
 411 }
 412
 413 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 414                                 int port_id, u32 link_state)
 415 {
 416         u32 temp;
 417
 418         temp = readl(port_array[port_id]);
 419         temp = xhci_port_state_to_neutral(temp);
 420         temp &= ~PORT_PLS_MASK;
 421         temp |= PORT_LINK_STROBE | link_state;
 422         writel(temp, port_array[port_id]);
 423 }
 424
 425 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 426                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 427 {
 428         u32 temp;
 429
 430         temp = readl(port_array[port_id]);
 431         temp = xhci_port_state_to_neutral(temp);
 432
 433         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 434                 temp |= PORT_WKCONN_E;
 435         else
 436                 temp &= ~PORT_WKCONN_E;
 437
 438         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 439                 temp |= PORT_WKDISC_E;
 440         else
 441                 temp &= ~PORT_WKDISC_E;
 442
 443         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 444                 temp |= PORT_WKOC_E;
 445         else
 446                 temp &= ~PORT_WKOC_E;
 447
 448         writel(temp, port_array[port_id]);
 449 }
 450
 451 /* Test and clear port RWC bit */
 452 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 453                                 int port_id, u32 port_bit)
 454 {
 455         u32 temp;
 456
 457         temp = readl(port_array[port_id]);
 458         if (temp & port_bit) {
 459                 temp = xhci_port_state_to_neutral(temp);
 460                 temp |= port_bit;
 461                 writel(temp, port_array[port_id]);
 462         }
 463 }
 464
 465 /* Updates Link Status for USB 2.1 port */
 466 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 467 {
 468         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 469                 *status |= USB_PORT_STAT_L1;
 470 }
 471
 472 /* Updates Link Status for super Speed port */
 473 static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
 474 {
 475         u32 pls = status_reg & PORT_PLS_MASK;
 476
 477         /* resume state is a xHCI internal state.
 478          * Do not report it to usb core.
 479          */
 480         if (pls == XDEV_RESUME)
 481                 return;
 482
 483         /* When the CAS bit is set then warm reset
 484          * should be performed on port
 485          */
 486         if (status_reg & PORT_CAS) {
 487                 /* The CAS bit can be set while the port is
 488                  * in any link state.
 489                  * Only roothubs have CAS bit, so we
 490                  * pretend to be in compliance mode
 491                  * unless we're already in compliance
 492                  * or the inactive state.
 493                  */
 494                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 495                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 496                         pls = USB_SS_PORT_LS_COMP_MOD;
 497                 }
 498                 /* Return also connection bit -
 499                  * hub state machine resets port
 500                  * when this bit is set.
 501                  */
 502                 pls |= USB_PORT_STAT_CONNECTION;
 503         } else {
 504                 /*
 505                  * If CAS bit isn't set but the Port is already at
 506                  * Compliance Mode, fake a connection so the USB core
 507                  * notices the Compliance state and resets the port.
 508                  * This resolves an issue generated by the SN65LVPE502CP
 509                  * in which sometimes the port enters compliance mode
 510                  * caused by a delay on the host-device negotiation.
 511                  */
 512                 if (pls == USB_SS_PORT_LS_COMP_MOD)
 513                         pls |= USB_PORT_STAT_CONNECTION;
 514         }
 515
 516         /* update status field */
 517         *status |= pls;
 518 }
 519
 520 /*
 521  * Function for Compliance Mode Quirk.
 522  *
 523  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 524  * the compliance mode timer is deleted. A port won't enter
 525  * compliance mode if it has previously entered U0.
 526  */
 527 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 528                                     u16 wIndex)
 529 {
 530         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 531         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 532
 533         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 534                 return;
 535
 536         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 537                 xhci->port_status_u0 |= 1 << wIndex;
 538                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 539                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 540                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 541                                 "All USB3 ports have entered U0 already!");
 542                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 543                                 "Compliance Mode Recovery Timer Deleted.");
 544                 }
 545         }
 546 }
 547
 548 /*
 549  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 550  * 3.0 hubs use.
 551  *
 552  * Possible side effects:
 553  *  - Mark a port as being done with device resume,
 554  *    and ring the endpoint doorbells.
 555  *  - Stop the Synopsys redriver Compliance Mode polling.
 556  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 557  */
 558 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 559                 struct xhci_bus_state *bus_state,
 560                 __le32 __iomem **port_array,
 561                 u16 wIndex, u32 raw_port_status,
 562                 unsigned long flags)
 563         __releases(&xhci->lock)
 564         __acquires(&xhci->lock)
 565 {
 566         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 567         u32 status = 0;
 568         int slot_id;
 569
 570         /* wPortChange bits */
 571         if (raw_port_status & PORT_CSC)
 572                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 573         if (raw_port_status & PORT_PEC)
 574                 status |= USB_PORT_STAT_C_ENABLE << 16;
 575         if ((raw_port_status & PORT_OCC))
 576                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 577         if ((raw_port_status & PORT_RC))
 578                 status |= USB_PORT_STAT_C_RESET << 16;
 579         /* USB3.0 only */
 580         if (hcd->speed == HCD_USB3) {
 581                 if ((raw_port_status & PORT_PLC))
 582                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 583                 if ((raw_port_status & PORT_WRC))
 584                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 585         }
 586
 587         if (hcd->speed != HCD_USB3) {
 588                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 589                                 && (raw_port_status & PORT_POWER))
 590                         status |= USB_PORT_STAT_SUSPEND;
 591         }
 592         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 593                         !DEV_SUPERSPEED(raw_port_status)) {
 594                 if ((raw_port_status & PORT_RESET) ||
 595                                 !(raw_port_status & PORT_PE))
 596                         return 0xffffffff;
 597                 if (time_after_eq(jiffies,
 598                                         bus_state->resume_done[wIndex])) {
 599                         int time_left;
 600
 601                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 602                                         wIndex + 1);
 603                         bus_state->resume_done[wIndex] = 0;
 604                         clear_bit(wIndex, &bus_state->resuming_ports);
 605
 606                         set_bit(wIndex, &bus_state->rexit_ports);
 607                         xhci_set_link_state(xhci, port_array, wIndex,
 608                                         XDEV_U0);
 609
 610                         spin_unlock_irqrestore(&xhci->lock, flags);
 611                         time_left = wait_for_completion_timeout(
 612                                         &bus_state->rexit_done[wIndex],
 613                                         msecs_to_jiffies(
 614                                                 XHCI_MAX_REXIT_TIMEOUT));
 615                         spin_lock_irqsave(&xhci->lock, flags);
 616
 617                         if (time_left) {
 618                                 slot_id = xhci_find_slot_id_by_port(hcd,
 619                                                 xhci, wIndex + 1);
 620                                 if (!slot_id) {
 621                                         xhci_dbg(xhci, "slot_id is zero\n");
 622                                         return 0xffffffff;
 623                                 }
 624                                 xhci_ring_device(xhci, slot_id);
 625                         } else {
 626                                 int port_status = readl(port_array[wIndex]);
 627                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 628                                                 XHCI_MAX_REXIT_TIMEOUT,
 629                                                 port_status);
 630                                 status |= USB_PORT_STAT_SUSPEND;
 631                                 clear_bit(wIndex, &bus_state->rexit_ports);
 632                         }
 633
 634                         bus_state->port_c_suspend |= 1 << wIndex;
 635                         bus_state->suspended_ports &= ~(1 << wIndex);
 636                 } else {
 637                         /*
 638                          * The resume has been signaling for less than
 639                          * 20ms. Report the port status as SUSPEND,
 640                          * let the usbcore check port status again
 641                          * and clear resume signaling later.
 642                          */
 643                         status |= USB_PORT_STAT_SUSPEND;
 644                 }
 645         }
 646         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
 647                         && (raw_port_status & PORT_POWER)
 648                         && (bus_state->suspended_ports & (1 << wIndex))) {
 649                 bus_state->suspended_ports &= ~(1 << wIndex);
 650                 if (hcd->speed != HCD_USB3)
 651                         bus_state->port_c_suspend |= 1 << wIndex;
 652         }
 653         if (raw_port_status & PORT_CONNECT) {
 654                 status |= USB_PORT_STAT_CONNECTION;
 655                 status |= xhci_port_speed(raw_port_status);
 656         }
 657         if (raw_port_status & PORT_PE)
 658                 status |= USB_PORT_STAT_ENABLE;
 659         if (raw_port_status & PORT_OC)
 660                 status |= USB_PORT_STAT_OVERCURRENT;
 661         if (raw_port_status & PORT_RESET)
 662                 status |= USB_PORT_STAT_RESET;
 663         if (raw_port_status & PORT_POWER) {
 664                 if (hcd->speed == HCD_USB3)
 665                         status |= USB_SS_PORT_STAT_POWER;
 666                 else
 667                         status |= USB_PORT_STAT_POWER;
 668         }
 669         /* Update Port Link State */
 670         if (hcd->speed == HCD_USB3) {
 671                 xhci_hub_report_usb3_link_state(&status, raw_port_status);
 672                 /*
 673                  * Verify if all USB3 Ports Have entered U0 already.
 674                  * Delete Compliance Mode Timer if so.
 675                  */
 676                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 677         } else {
 678                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 679         }
 680         if (bus_state->port_c_suspend & (1 << wIndex))
 681                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 682
 683         return status;
 684 }
 685
 686 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 687                 u16 wIndex, char *buf, u16 wLength)
 688 {
 689         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 690         int max_ports;
 691         unsigned long flags;
 692         u32 temp, status;
 693         int retval = 0;
 694         __le32 __iomem **port_array;
 695         int slot_id;
 696         struct xhci_bus_state *bus_state;
 697         u16 link_state = 0;
 698         u16 wake_mask = 0;
 699         u16 timeout = 0;
 700
 701         max_ports = xhci_get_ports(hcd, &port_array);
 702         bus_state = &xhci->bus_state[hcd_index(hcd)];
 703
 704         spin_lock_irqsave(&xhci->lock, flags);
 705         switch (typeReq) {
 706         case GetHubStatus:
 707                 /* No power source, over-current reported per port */
 708                 memset(buf, 0, 4);
 709                 break;
 710         case GetHubDescriptor:
 711                 /* Check to make sure userspace is asking for the USB 3.0 hub
 712                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 713                  * endpoint, like external hubs do.
 714                  */
 715                 if (hcd->speed == HCD_USB3 &&
 716                                 (wLength < USB_DT_SS_HUB_SIZE ||
 717                                  wValue != (USB_DT_SS_HUB << 8))) {
 718                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 719                                         "USB 3.0 roothub.\n");
 720                         goto error;
 721                 }
 722                 xhci_hub_descriptor(hcd, xhci,
 723                                 (struct usb_hub_descriptor *) buf);
 724                 break;
 725         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 726                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 727                         goto error;
 728
 729                 if (hcd->speed != HCD_USB3)
 730                         goto error;
 731
 732                 /* Set the U1 and U2 exit latencies. */
 733                 memcpy(buf, &usb_bos_descriptor,
 734                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 735                 temp = readl(&xhci->cap_regs->hcs_params3);
 736                 buf[12] = HCS_U1_LATENCY(temp);
 737                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 738
 739                 /* Indicate whether the host has LTM support. */
 740                 temp = readl(&xhci->cap_regs->hcc_params);
 741                 if (HCC_LTC(temp))
 742                         buf[8] |= USB_LTM_SUPPORT;
 743
 744                 spin_unlock_irqrestore(&xhci->lock, flags);
 745                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 746         case GetPortStatus:
 747                 if (!wIndex || wIndex > max_ports)
 748                         goto error;
 749                 wIndex--;
 750                 temp = readl(port_array[wIndex]);
 751                 if (temp == 0xffffffff) {
 752                         retval = -ENODEV;
 753                         break;
 754                 }
 755                 status = xhci_get_port_status(hcd, bus_state, port_array,
 756                                 wIndex, temp, flags);
 757                 if (status == 0xffffffff)
 758                         goto error;
 759
 760                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 761                                 wIndex, temp);
 762                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 763
 764                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 765                 break;
 766         case SetPortFeature:
 767                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 768                         link_state = (wIndex & 0xff00) >> 3;
 769                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 770                         wake_mask = wIndex & 0xff00;
 771                 /* The MSB of wIndex is the U1/U2 timeout */
 772                 timeout = (wIndex & 0xff00) >> 8;
 773                 wIndex &= 0xff;
 774                 if (!wIndex || wIndex > max_ports)
 775                         goto error;
 776                 wIndex--;
 777                 temp = readl(port_array[wIndex]);
 778                 if (temp == 0xffffffff) {
 779                         retval = -ENODEV;
 780                         break;
 781                 }
 782                 temp = xhci_port_state_to_neutral(temp);
 783                 /* FIXME: What new port features do we need to support? */
 784                 switch (wValue) {
 785                 case USB_PORT_FEAT_SUSPEND:
 786                         temp = readl(port_array[wIndex]);
 787                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 788                                 /* Resume the port to U0 first */
 789                                 xhci_set_link_state(xhci, port_array, wIndex,
 790                                                         XDEV_U0);
 791                                 spin_unlock_irqrestore(&xhci->lock, flags);
 792                                 msleep(10);
 793                                 spin_lock_irqsave(&xhci->lock, flags);
 794                         }
 795                         /* In spec software should not attempt to suspend
 796                          * a port unless the port reports that it is in the
 797                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 798                          */
 799                         temp = readl(port_array[wIndex]);
 800                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 801                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 802                                 xhci_warn(xhci, "USB core suspending device "
 803                                           "not in U0/U1/U2.\n");
 804                                 goto error;
 805                         }
 806
 807                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 808                                         wIndex + 1);
 809                         if (!slot_id) {
 810                                 xhci_warn(xhci, "slot_id is zero\n");
 811                                 goto error;
 812                         }
 813                         /* unlock to execute stop endpoint commands */
 814                         spin_unlock_irqrestore(&xhci->lock, flags);
 815                         xhci_stop_device(xhci, slot_id, 1);
 816                         spin_lock_irqsave(&xhci->lock, flags);
 817
 818                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 819
 820                         spin_unlock_irqrestore(&xhci->lock, flags);
 821                         msleep(10); /* wait device to enter */
 822                         spin_lock_irqsave(&xhci->lock, flags);
 823
 824                         temp = readl(port_array[wIndex]);
 825                         bus_state->suspended_ports |= 1 << wIndex;
 826                         break;
 827                 case USB_PORT_FEAT_LINK_STATE:
 828                         temp = readl(port_array[wIndex]);
 829
 830                         /* Disable port */
 831                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
 832                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
 833                                 temp = xhci_port_state_to_neutral(temp);
 834                                 /*
 835                                  * Clear all change bits, so that we get a new
 836                                  * connection event.
 837                                  */
 838                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
 839                                         PORT_OCC | PORT_RC | PORT_PLC |
 840                                         PORT_CEC;
 841                                 writel(temp | PORT_PE, port_array[wIndex]);
 842                                 temp = readl(port_array[wIndex]);
 843                                 break;
 844                         }
 845
 846                         /* Put link in RxDetect (enable port) */
 847                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
 848                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
 849                                 xhci_set_link_state(xhci, port_array, wIndex,
 850                                                 link_state);
 851                                 temp = readl(port_array[wIndex]);
 852                                 break;
 853                         }
 854
 855                         /* Software should not attempt to set
 856                          * port link state above '3' (U3) and the port
 857                          * must be enabled.
 858                          */
 859                         if ((temp & PORT_PE) == 0 ||
 860                                 (link_state > USB_SS_PORT_LS_U3)) {
 861                                 xhci_warn(xhci, "Cannot set link state.\n");
 862                                 goto error;
 863                         }
 864
 865                         if (link_state == USB_SS_PORT_LS_U3) {
 866                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 867                                                 wIndex + 1);
 868                                 if (slot_id) {
 869                                         /* unlock to execute stop endpoint
 870                                          * commands */
 871                                         spin_unlock_irqrestore(&xhci->lock,
 872                                                                 flags);
 873                                         xhci_stop_device(xhci, slot_id, 1);
 874                                         spin_lock_irqsave(&xhci->lock, flags);
 875                                 }
 876                         }
 877
 878                         xhci_set_link_state(xhci, port_array, wIndex,
 879                                                 link_state);
 880
 881                         spin_unlock_irqrestore(&xhci->lock, flags);
 882                         msleep(20); /* wait device to enter */
 883                         spin_lock_irqsave(&xhci->lock, flags);
 884
 885                         temp = readl(port_array[wIndex]);
 886                         if (link_state == USB_SS_PORT_LS_U3)
 887                                 bus_state->suspended_ports |= 1 << wIndex;
 888                         break;
 889                 case USB_PORT_FEAT_POWER:
 890                         /*
 891                          * Turn on ports, even if there isn't per-port switching.
 892                          * HC will report connect events even before this is set.
 893                          * However, khubd will ignore the roothub events until
 894                          * the roothub is registered.
 895                          */
 896                         writel(temp | PORT_POWER, port_array[wIndex]);
 897
 898                         temp = readl(port_array[wIndex]);
 899                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 900
 901                         spin_unlock_irqrestore(&xhci->lock, flags);
 902                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 903                                         wIndex);
 904                         if (temp)
 905                                 usb_acpi_set_power_state(hcd->self.root_hub,
 906                                                 wIndex, true);
 907                         spin_lock_irqsave(&xhci->lock, flags);
 908                         break;
 909                 case USB_PORT_FEAT_RESET:
 910                         temp = (temp | PORT_RESET);
 911                         writel(temp, port_array[wIndex]);
 912
 913                         temp = readl(port_array[wIndex]);
 914                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 915                         break;
 916                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 917                         xhci_set_remote_wake_mask(xhci, port_array,
 918                                         wIndex, wake_mask);
 919                         temp = readl(port_array[wIndex]);
 920                         xhci_dbg(xhci, "set port remote wake mask, "
 921                                         "actual port %d status  = 0x%x\n",
 922                                         wIndex, temp);
 923                         break;
 924                 case USB_PORT_FEAT_BH_PORT_RESET:
 925                         temp |= PORT_WR;
 926                         writel(temp, port_array[wIndex]);
 927
 928                         temp = readl(port_array[wIndex]);
 929                         break;
 930                 case USB_PORT_FEAT_U1_TIMEOUT:
 931                         if (hcd->speed != HCD_USB3)
 932                                 goto error;
 933                         temp = readl(port_array[wIndex] + PORTPMSC);
 934                         temp &= ~PORT_U1_TIMEOUT_MASK;
 935                         temp |= PORT_U1_TIMEOUT(timeout);
 936                         writel(temp, port_array[wIndex] + PORTPMSC);
 937                         break;
 938                 case USB_PORT_FEAT_U2_TIMEOUT:
 939                         if (hcd->speed != HCD_USB3)
 940                                 goto error;
 941                         temp = readl(port_array[wIndex] + PORTPMSC);
 942                         temp &= ~PORT_U2_TIMEOUT_MASK;
 943                         temp |= PORT_U2_TIMEOUT(timeout);
 944                         writel(temp, port_array[wIndex] + PORTPMSC);
 945                         break;
 946                 default:
 947                         goto error;
 948                 }
 949                 /* unblock any posted writes */
 950                 temp = readl(port_array[wIndex]);
 951                 break;
 952         case ClearPortFeature:
 953                 if (!wIndex || wIndex > max_ports)
 954                         goto error;
 955                 wIndex--;
 956                 temp = readl(port_array[wIndex]);
 957                 if (temp == 0xffffffff) {
 958                         retval = -ENODEV;
 959                         break;
 960                 }
 961                 /* FIXME: What new port features do we need to support? */
 962                 temp = xhci_port_state_to_neutral(temp);
 963                 switch (wValue) {
 964                 case USB_PORT_FEAT_SUSPEND:
 965                         temp = readl(port_array[wIndex]);
 966                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 967                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 968                         if (temp & PORT_RESET)
 969                                 goto error;
 970                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 971                                 if ((temp & PORT_PE) == 0)
 972                                         goto error;
 973
 974                                 xhci_set_link_state(xhci, port_array, wIndex,
 975                                                         XDEV_RESUME);
 976                                 spin_unlock_irqrestore(&xhci->lock, flags);
 977                                 msleep(20);
 978                                 spin_lock_irqsave(&xhci->lock, flags);
 979                                 xhci_set_link_state(xhci, port_array, wIndex,
 980                                                         XDEV_U0);
 981                         }
 982                         bus_state->port_c_suspend |= 1 << wIndex;
 983
 984                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 985                                         wIndex + 1);
 986                         if (!slot_id) {
 987                                 xhci_dbg(xhci, "slot_id is zero\n");
 988                                 goto error;
 989                         }
 990                         xhci_ring_device(xhci, slot_id);
 991                         break;
 992                 case USB_PORT_FEAT_C_SUSPEND:
 993                         bus_state->port_c_suspend &= ~(1 << wIndex);
 994                 case USB_PORT_FEAT_C_RESET:
 995                 case USB_PORT_FEAT_C_BH_PORT_RESET:
 996                 case USB_PORT_FEAT_C_CONNECTION:
 997                 case USB_PORT_FEAT_C_OVER_CURRENT:
 998                 case USB_PORT_FEAT_C_ENABLE:
 999                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1000                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1001                                         port_array[wIndex], temp);
1002                         break;
1003                 case USB_PORT_FEAT_ENABLE:
1004                         xhci_disable_port(hcd, xhci, wIndex,
1005                                         port_array[wIndex], temp);
1006                         break;
1007                 case USB_PORT_FEAT_POWER:
1008                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1009
1010                         spin_unlock_irqrestore(&xhci->lock, flags);
1011                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1012                                         wIndex);
1013                         if (temp)
1014                                 usb_acpi_set_power_state(hcd->self.root_hub,
1015                                                 wIndex, false);
1016                         spin_lock_irqsave(&xhci->lock, flags);
1017                         break;
1018                 default:
1019                         goto error;
1020                 }
1021                 break;
1022         default:
1023 error:
1024                 /* "stall" on error */
1025                 retval = -EPIPE;
1026         }
1027         spin_unlock_irqrestore(&xhci->lock, flags);
1028         return retval;
1029 }
1030
1031 /*
1032  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1033  * Ports are 0-indexed from the HCD point of view,
1034  * and 1-indexed from the USB core pointer of view.
1035  *
1036  * Note that the status change bits will be cleared as soon as a port status
1037  * change event is generated, so we use the saved status from that event.
1038  */
1039 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1040 {
1041         unsigned long flags;
1042         u32 temp, status;
1043         u32 mask;
1044         int i, retval;
1045         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1046         int max_ports;
1047         __le32 __iomem **port_array;
1048         struct xhci_bus_state *bus_state;
1049         bool reset_change = false;
1050
1051         max_ports = xhci_get_ports(hcd, &port_array);
1052         bus_state = &xhci->bus_state[hcd_index(hcd)];
1053
1054         /* Initial status is no changes */
1055         retval = (max_ports + 8) / 8;
1056         memset(buf, 0, retval);
1057
1058         /*
1059          * Inform the usbcore about resume-in-progress by returning
1060          * a non-zero value even if there are no status changes.
1061          */
1062         status = bus_state->resuming_ports;
1063
1064         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1065
1066         spin_lock_irqsave(&xhci->lock, flags);
1067         /* For each port, did anything change?  If so, set that bit in buf. */
1068         for (i = 0; i < max_ports; i++) {
1069                 temp = readl(port_array[i]);
1070                 if (temp == 0xffffffff) {
1071                         retval = -ENODEV;
1072                         break;
1073                 }
1074                 if ((temp & mask) != 0 ||
1075                         (bus_state->port_c_suspend & 1 << i) ||
1076                         (bus_state->resume_done[i] && time_after_eq(
1077                             jiffies, bus_state->resume_done[i]))) {
1078                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1079                         status = 1;
1080                 }
1081                 if ((temp & PORT_RC))
1082                         reset_change = true;
1083         }
1084         if (!status && !reset_change) {
1085                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1086                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1087         }
1088         spin_unlock_irqrestore(&xhci->lock, flags);
1089         return status ? retval : 0;
1090 }
1091
1092 #ifdef CONFIG_PM
1093
1094 int xhci_bus_suspend(struct usb_hcd *hcd)
1095 {
1096         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1097         int max_ports, port_index;
1098         __le32 __iomem **port_array;
1099         struct xhci_bus_state *bus_state;
1100         unsigned long flags;
1101
1102         max_ports = xhci_get_ports(hcd, &port_array);
1103         bus_state = &xhci->bus_state[hcd_index(hcd)];
1104
1105         spin_lock_irqsave(&xhci->lock, flags);
1106
1107         if (hcd->self.root_hub->do_remote_wakeup) {
1108                 if (bus_state->resuming_ports) {
1109                         spin_unlock_irqrestore(&xhci->lock, flags);
1110                         xhci_dbg(xhci, "suspend failed because "
1111                                                 "a port is resuming\n");
1112                         return -EBUSY;
1113                 }
1114         }
1115
1116         port_index = max_ports;
1117         bus_state->bus_suspended = 0;
1118         while (port_index--) {
1119                 /* suspend the port if the port is not suspended */
1120                 u32 t1, t2;
1121                 int slot_id;
1122
1123                 t1 = readl(port_array[port_index]);
1124                 t2 = xhci_port_state_to_neutral(t1);
1125
1126                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1127                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1128                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1129                                         port_index + 1);
1130                         if (slot_id) {
1131                                 spin_unlock_irqrestore(&xhci->lock, flags);
1132                                 xhci_stop_device(xhci, slot_id, 1);
1133                                 spin_lock_irqsave(&xhci->lock, flags);
1134                         }
1135                         t2 &= ~PORT_PLS_MASK;
1136                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1137                         set_bit(port_index, &bus_state->bus_suspended);
1138                 }
1139                 /* USB core sets remote wake mask for USB 3.0 hubs,
1140                  * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1141                  * is enabled, so also enable remote wake here.
1142                  */
1143                 if (hcd->self.root_hub->do_remote_wakeup) {
1144                         if (t1 & PORT_CONNECT) {
1145                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1146                                 t2 &= ~PORT_WKCONN_E;
1147                         } else {
1148                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1149                                 t2 &= ~PORT_WKDISC_E;
1150                         }
1151                 } else
1152                         t2 &= ~PORT_WAKE_BITS;
1153
1154                 t1 = xhci_port_state_to_neutral(t1);
1155                 if (t1 != t2)
1156                         writel(t2, port_array[port_index]);
1157         }
1158         hcd->state = HC_STATE_SUSPENDED;
1159         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1160         spin_unlock_irqrestore(&xhci->lock, flags);
1161         return 0;
1162 }
1163
1164 int xhci_bus_resume(struct usb_hcd *hcd)
1165 {
1166         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1167         int max_ports, port_index;
1168         __le32 __iomem **port_array;
1169         struct xhci_bus_state *bus_state;
1170         u32 temp;
1171         unsigned long flags;
1172
1173         max_ports = xhci_get_ports(hcd, &port_array);
1174         bus_state = &xhci->bus_state[hcd_index(hcd)];
1175
1176         if (time_before(jiffies, bus_state->next_statechange))
1177                 msleep(5);
1178
1179         spin_lock_irqsave(&xhci->lock, flags);
1180         if (!HCD_HW_ACCESSIBLE(hcd)) {
1181                 spin_unlock_irqrestore(&xhci->lock, flags);
1182                 return -ESHUTDOWN;
1183         }
1184
1185         /* delay the irqs */
1186         temp = readl(&xhci->op_regs->command);
1187         temp &= ~CMD_EIE;
1188         writel(temp, &xhci->op_regs->command);
1189
1190         port_index = max_ports;
1191         while (port_index--) {
1192                 /* Check whether need resume ports. If needed
1193                    resume port and disable remote wakeup */
1194                 u32 temp;
1195                 int slot_id;
1196
1197                 temp = readl(port_array[port_index]);
1198                 if (DEV_SUPERSPEED(temp))
1199                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1200                 else
1201                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1202                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1203                     (temp & PORT_PLS_MASK)) {
1204                         if (DEV_SUPERSPEED(temp)) {
1205                                 xhci_set_link_state(xhci, port_array,
1206                                                         port_index, XDEV_U0);
1207                         } else {
1208                                 xhci_set_link_state(xhci, port_array,
1209                                                 port_index, XDEV_RESUME);
1210
1211                                 spin_unlock_irqrestore(&xhci->lock, flags);
1212                                 msleep(20);
1213                                 spin_lock_irqsave(&xhci->lock, flags);
1214
1215                                 xhci_set_link_state(xhci, port_array,
1216                                                         port_index, XDEV_U0);
1217                         }
1218                         /* wait for the port to enter U0 and report port link
1219                          * state change.
1220                          */
1221                         spin_unlock_irqrestore(&xhci->lock, flags);
1222                         msleep(20);
1223                         spin_lock_irqsave(&xhci->lock, flags);
1224
1225                         /* Clear PLC */
1226                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1227                                                 PORT_PLC);
1228
1229                         slot_id = xhci_find_slot_id_by_port(hcd,
1230                                         xhci, port_index + 1);
1231                         if (slot_id)
1232                                 xhci_ring_device(xhci, slot_id);
1233                 } else
1234                         writel(temp, port_array[port_index]);
1235         }
1236
1237         (void) readl(&xhci->op_regs->command);
1238
1239         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1240         /* re-enable irqs */
1241         temp = readl(&xhci->op_regs->command);
1242         temp |= CMD_EIE;
1243         writel(temp, &xhci->op_regs->command);
1244         temp = readl(&xhci->op_regs->command);
1245
1246         spin_unlock_irqrestore(&xhci->lock, flags);
1247         return 0;
1248 }
1249
1250 #endif  /* CONFIG_PM */