1 #ifndef __LINUX_UHCI_HCD_H
2 #define __LINUX_UHCI_HCD_H
4 #include <linux/list.h>
7 #define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8 #define PIPE_DEVEP_MASK 0x0007ff00
12 * Universal Host Controller Interface data structures and defines
15 /* Command register */
17 #define USBCMD_RS 0x0001 /* Run/Stop */
18 #define USBCMD_HCRESET 0x0002 /* Host reset */
19 #define USBCMD_GRESET 0x0004 /* Global reset */
20 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
21 #define USBCMD_FGR 0x0010 /* Force Global Resume */
22 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
23 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
24 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
28 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
29 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
30 #define USBSTS_RD 0x0004 /* Resume Detect */
31 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
32 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
33 * the schedule is buggy */
34 #define USBSTS_HCH 0x0020 /* HC Halted */
36 /* Interrupt enable register */
38 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
39 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
40 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
41 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
44 #define USBFLBASEADD 8
46 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
48 /* USB port status and control registers */
51 #define USBPORTSC_CCS 0x0001 /* Current Connect Status
52 * ("device present") */
53 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
54 #define USBPORTSC_PE 0x0004 /* Port Enable */
55 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
56 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
57 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
58 #define USBPORTSC_RD 0x0040 /* Resume Detect */
59 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
60 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
61 #define USBPORTSC_PR 0x0200 /* Port Reset */
62 /* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
63 #define USBPORTSC_OC 0x0400 /* Over Current condition */
64 #define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
65 #define USBPORTSC_SUSP 0x1000 /* Suspend */
66 #define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
67 #define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
68 #define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
70 /* PCI legacy support register */
71 #define USBLEGSUP 0xc0
72 #define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
73 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
74 #define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
76 /* PCI Intel-specific resume-enable register */
77 #define USBRES_INTEL 0xc4
78 #define USBPORT1EN 0x01
79 #define USBPORT2EN 0x02
81 #define UHCI_PTR_BITS cpu_to_le32(0x000F)
82 #define UHCI_PTR_TERM cpu_to_le32(0x0001)
83 #define UHCI_PTR_QH cpu_to_le32(0x0002)
84 #define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
85 #define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
87 #define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
88 #define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
89 #define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
91 #define MAX_PHASE 32 /* Periodic scheduling length */
93 /* When no queues need Full-Speed Bandwidth Reclamation,
94 * delay this long before turning FSBR off */
95 #define FSBR_OFF_DELAY msecs_to_jiffies(10)
97 /* If a queue hasn't advanced after this much time, assume it is stuck */
98 #define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
106 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
107 * with each endpoint, and qh->element (updated by the HC) is either:
108 * - the next unprocessed TD in the endpoint's queue, or
109 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
111 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
112 * can easily splice a QH for some endpoint into the schedule at the right
113 * place. Then qh->element is UHCI_PTR_TERM.
115 * In the schedule, qh->link maintains a list of QHs seen by the HC:
116 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
118 * qh->node is the software equivalent of qh->link. The differences
119 * are that the software list is doubly-linked and QHs in the UNLINKING
120 * state are on the software list but not the hardware schedule.
122 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
123 * but they never get added to the hardware schedule.
125 #define QH_STATE_IDLE 1 /* QH is not being used */
126 #define QH_STATE_UNLINKING 2 /* QH has been removed from the
127 * schedule but the hardware may
128 * still be using it */
129 #define QH_STATE_ACTIVE 3 /* QH is on the schedule */
132 /* Hardware fields */
133 __le32 link; /* Next QH in the schedule */
134 __le32 element; /* Queue element (TD) pointer */
136 /* Software fields */
137 dma_addr_t dma_handle;
139 struct list_head node; /* Node in the list of QHs */
140 struct usb_host_endpoint *hep; /* Endpoint information */
141 struct usb_device *udev;
142 struct list_head queue; /* Queue of urbps for this QH */
143 struct uhci_td *dummy_td; /* Dummy TD to end the queue */
144 struct uhci_td *post_td; /* Last TD completed */
146 struct usb_iso_packet_descriptor *iso_packet_desc;
147 /* Next urb->iso_frame_desc entry */
148 unsigned long advance_jiffies; /* Time of last queue advance */
149 unsigned int unlink_frame; /* When the QH was unlinked */
150 unsigned int period; /* For Interrupt and Isochronous QHs */
151 short phase; /* Between 0 and period-1 */
152 short load; /* Periodic time requirement, in us */
153 unsigned int iso_frame; /* Frame # for iso_packet_desc */
155 int state; /* QH_STATE_xxx; see above */
156 int type; /* Queue type (control, bulk, etc) */
157 int skel; /* Skeleton queue number */
159 unsigned int initial_toggle:1; /* Endpoint's current toggle value */
160 unsigned int needs_fixup:1; /* Must fix the TD toggle values */
161 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */
162 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */
163 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has
165 } __attribute__((aligned(16)));
168 * We need a special accessor for the element pointer because it is
169 * subject to asynchronous updates by the controller.
171 #define qh_element(qh) ACCESS_ONCE((qh)->element)
173 #define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle))
177 * Transfer Descriptors
183 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
184 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
185 #define TD_CTRL_C_ERR_SHIFT 27
186 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
187 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
188 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
189 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
190 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
191 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
192 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
193 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
194 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
195 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
196 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
198 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
199 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
202 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
203 #define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
204 #define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
205 TD_CTRL_ACTLEN_MASK) /* 1-based */
208 * for TD <info>: (a.k.a. Token)
210 #define td_token(td) le32_to_cpu((td)->token)
211 #define TD_TOKEN_DEVADDR_SHIFT 8
212 #define TD_TOKEN_TOGGLE_SHIFT 19
213 #define TD_TOKEN_TOGGLE (1 << 19)
214 #define TD_TOKEN_EXPLEN_SHIFT 21
215 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
216 #define TD_TOKEN_PID_MASK 0xFF
218 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
219 TD_TOKEN_EXPLEN_SHIFT)
221 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
222 1) & TD_TOKEN_EXPLEN_MASK)
223 #define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
224 #define uhci_endpoint(token) (((token) >> 15) & 0xf)
225 #define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
226 #define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
227 #define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
228 #define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
229 #define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
232 * The documentation says "4 words for hardware, 4 words for software".
234 * That's silly, the hardware doesn't care. The hardware only cares that
235 * the hardware words are 16-byte aligned, and we can have any amount of
236 * sw space after the TD entry.
238 * td->link points to either another TD (not necessarily for the same urb or
239 * even the same endpoint), or nothing (PTR_TERM), or a QH.
242 /* Hardware fields */
248 /* Software fields */
249 dma_addr_t dma_handle;
251 struct list_head list;
253 int frame; /* for iso: what frame? */
254 struct list_head fl_list;
255 } __attribute__((aligned(16)));
258 * We need a special accessor for the control/status word because it is
259 * subject to asynchronous updates by the controller.
261 #define td_status(td) le32_to_cpu(ACCESS_ONCE((td)->status))
263 #define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle))
267 * Skeleton Queue Headers
271 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
272 * automatic queuing. To make it easy to insert entries into the schedule,
273 * we have a skeleton of QHs for each predefined Interrupt latency.
274 * Asynchronous QHs (low-speed control, full-speed control, and bulk)
275 * go onto the period-1 interrupt list, since they all get accessed on
278 * When we want to add a new QH, we add it to the list starting from the
279 * appropriate skeleton QH. For instance, the schedule can look like this:
287 * skel int1 + async QH
288 * dev 5 low-speed control QH
292 * There is a special terminating QH used to keep full-speed bandwidth
293 * reclamation active when no full-speed control or bulk QHs are linked
294 * into the schedule. It has an inactive TD (to work around a PIIX bug,
295 * see the Intel errata) and it points back to itself.
297 * There's a special skeleton QH for Isochronous QHs which never appears
298 * on the schedule. Isochronous TDs go on the schedule before the
299 * the skeleton QHs. The hardware accesses them directly rather than
300 * through their QH, which is used only for bookkeeping purposes.
301 * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
302 * it doesn't use them either. And the spec says that queues never
303 * advance on an error completion status, which makes them totally
304 * unsuitable for Isochronous transfers.
306 * There's also a special skeleton QH used for QHs which are in the process
307 * of unlinking and so may still be in use by the hardware. It too never
308 * appears on the schedule.
311 #define UHCI_NUM_SKELQH 11
312 #define SKEL_UNLINK 0
313 #define skel_unlink_qh skelqh[SKEL_UNLINK]
315 #define skel_iso_qh skelqh[SKEL_ISO]
316 /* int128, int64, ..., int1 = 2, 3, ..., 9 */
317 #define SKEL_INDEX(exponent) (9 - exponent)
319 #define skel_async_qh skelqh[SKEL_ASYNC]
321 #define skel_term_qh skelqh[SKEL_TERM]
323 /* The following entries refer to sublists of skel_async_qh */
324 #define SKEL_LS_CONTROL 20
325 #define SKEL_FS_CONTROL 21
326 #define SKEL_FSBR SKEL_FS_CONTROL
330 * The UHCI controller and root hub
334 * States for the root hub:
336 * To prevent "bouncing" in the presence of electrical noise,
337 * when there are no devices attached we delay for 1 second in the
338 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
340 * (Note that the AUTO_STOPPED state won't be necessary once the hub
341 * driver learns to autosuspend.)
344 /* In the following states the HC must be halted.
345 * These two must come first. */
349 UHCI_RH_AUTO_STOPPED,
352 /* In this state the HC changes from running to halted,
353 * so it can legally appear either way. */
356 /* In the following states it's an error if the HC is halted.
357 * These two must come last. */
358 UHCI_RH_RUNNING, /* The normal state */
359 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
363 * The full UHCI controller information:
368 struct dentry *dentry;
370 /* Grabbed from PCI */
371 unsigned long io_addr;
373 /* Used when registers are memory mapped */
376 struct dma_pool *qh_pool;
377 struct dma_pool *td_pool;
379 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
380 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */
381 struct uhci_qh *next_qh; /* Next QH to scan */
385 dma_addr_t frame_dma_handle; /* Hardware frame list */
387 void **frame_cpu; /* CPU's frame list */
389 enum uhci_rh_state rh_state;
390 unsigned long auto_stop_time; /* When to AUTO_STOP */
392 unsigned int frame_number; /* As of last check */
393 unsigned int is_stopped;
394 #define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
395 unsigned int last_iso_frame; /* Frame of last scan */
396 unsigned int cur_iso_frame; /* Frame for current scan */
398 unsigned int scan_in_progress:1; /* Schedule scan is running */
399 unsigned int need_rescan:1; /* Redo the schedule scan */
400 unsigned int dead:1; /* Controller has died */
401 unsigned int RD_enable:1; /* Suspended root hub with
402 Resume-Detect interrupts
404 unsigned int is_initialized:1; /* Data structure is usable */
405 unsigned int fsbr_is_on:1; /* FSBR is turned on */
406 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */
407 unsigned int fsbr_expiring:1; /* FSBR is timing out */
409 struct timer_list fsbr_timer; /* For turning off FBSR */
412 unsigned int oc_low:1; /* OverCurrent bit active low */
413 unsigned int wait_for_hp:1; /* Wait for HP port reset */
414 unsigned int big_endian_mmio:1; /* Big endian registers */
416 /* Support for port suspend/resume/reset */
417 unsigned long port_c_suspend; /* Bit-arrays of ports */
418 unsigned long resuming_ports;
419 unsigned long ports_timeout; /* Time to stop signalling */
421 struct list_head idle_qh_list; /* Where the idle QHs live */
423 int rh_numports; /* Number of root-hub ports */
425 wait_queue_head_t waitqh; /* endpoint_disable waiters */
426 int num_waiting; /* Number of waiters */
428 int total_load; /* Sum of array values */
429 short load[MAX_PHASE]; /* Periodic allocations */
431 /* Reset host controller */
432 void (*reset_hc) (struct uhci_hcd *uhci);
433 int (*check_and_reset_hc) (struct uhci_hcd *uhci);
434 /* configure_hc should perform arch specific settings, if needed */
435 void (*configure_hc) (struct uhci_hcd *uhci);
436 /* Check for broken resume detect interrupts */
437 int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
438 /* Check for broken global suspend */
439 int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
442 /* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
443 static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
445 return (struct uhci_hcd *) (hcd->hcd_priv);
447 static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
449 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
452 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
454 /* Utility macro for comparing frame numbers */
455 #define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
459 * Private per-URB data
462 struct list_head node; /* Node in the QH's urbp list */
466 struct uhci_qh *qh; /* QH for this URB */
467 struct list_head td_list;
469 unsigned fsbr:1; /* URB wants FSBR */
473 /* Some special IDs */
475 #define PCI_VENDOR_ID_GENESYS 0x17a0
476 #define PCI_DEVICE_ID_GL880S_UHCI 0x8083
479 * Functions used to access controller registers. The UCHI spec says that host
480 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
481 * we use memory mapped registers.
484 #ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
485 /* Support PCI only */
486 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
488 return inl(uhci->io_addr + reg);
491 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
493 outl(val, uhci->io_addr + reg);
496 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
498 return inw(uhci->io_addr + reg);
501 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
503 outw(val, uhci->io_addr + reg);
506 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
508 return inb(uhci->io_addr + reg);
511 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
513 outb(val, uhci->io_addr + reg);
517 /* Support non-PCI host controllers */
519 /* Support PCI and non-PCI host controllers */
520 #define uhci_has_pci_registers(u) ((u)->io_addr != 0)
522 /* Support non-PCI host controllers only */
523 #define uhci_has_pci_registers(u) 0
526 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
527 /* Support (non-PCI) big endian host controllers */
528 #define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
530 #define uhci_big_endian_mmio(u) 0
533 static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
535 if (uhci_has_pci_registers(uhci))
536 return inl(uhci->io_addr + reg);
537 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
538 else if (uhci_big_endian_mmio(uhci))
539 return readl_be(uhci->regs + reg);
542 return readl(uhci->regs + reg);
545 static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
547 if (uhci_has_pci_registers(uhci))
548 outl(val, uhci->io_addr + reg);
549 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
550 else if (uhci_big_endian_mmio(uhci))
551 writel_be(val, uhci->regs + reg);
554 writel(val, uhci->regs + reg);
557 static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
559 if (uhci_has_pci_registers(uhci))
560 return inw(uhci->io_addr + reg);
561 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
562 else if (uhci_big_endian_mmio(uhci))
563 return readw_be(uhci->regs + reg);
566 return readw(uhci->regs + reg);
569 static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
571 if (uhci_has_pci_registers(uhci))
572 outw(val, uhci->io_addr + reg);
573 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
574 else if (uhci_big_endian_mmio(uhci))
575 writew_be(val, uhci->regs + reg);
578 writew(val, uhci->regs + reg);
581 static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
583 if (uhci_has_pci_registers(uhci))
584 return inb(uhci->io_addr + reg);
585 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
586 else if (uhci_big_endian_mmio(uhci))
587 return readb_be(uhci->regs + reg);
590 return readb(uhci->regs + reg);
593 static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
595 if (uhci_has_pci_registers(uhci))
596 outb(val, uhci->io_addr + reg);
597 #ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
598 else if (uhci_big_endian_mmio(uhci))
599 writeb_be(val, uhci->regs + reg);
602 writeb(val, uhci->regs + reg);
604 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */