2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
18 * Intel documents this fairly well, and as far as I know there
19 * are no royalties or anything like that, but even so there are
20 * people who decided that they want to do the same thing in a
21 * completely different way.
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/slab.h>
32 #include <linux/errno.h>
33 #include <linux/unistd.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/debugfs.h>
38 #include <linux/dmapool.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/usb.h>
41 #include <linux/usb/hcd.h>
42 #include <linux/bitops.h>
43 #include <linux/dmi.h>
45 #include <asm/uaccess.h>
48 #include <asm/system.h>
55 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, \
56 Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, \
58 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
60 /* for flakey hardware, ignore overcurrent indicators */
62 module_param(ignore_oc, bool, S_IRUGO);
63 MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications");
66 * debug = 0, no debugging messages
67 * debug = 1, dump failed URBs except for stalls
68 * debug = 2, dump all failed URBs (including stalls)
69 * show all queues in /sys/kernel/debug/uhci/[pci_addr]
70 * debug = 3, show all TDs in URBs when dumping
73 #define DEBUG_CONFIGURED 1
75 module_param(debug, int, S_IRUGO | S_IWUSR);
76 MODULE_PARM_DESC(debug, "Debug level");
79 #define DEBUG_CONFIGURED 0
84 #define ERRBUF_LEN (32 * 1024)
86 static struct kmem_cache *uhci_up_cachep; /* urb_priv */
88 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state);
89 static void wakeup_rh(struct uhci_hcd *uhci);
90 static void uhci_get_current_frame_number(struct uhci_hcd *uhci);
93 * Calculate the link pointer DMA value for the first Skeleton QH in a frame.
95 static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame)
100 * The interrupt queues will be interleaved as evenly as possible.
101 * There's not much to be done about period-1 interrupts; they have
102 * to occur in every frame. But we can schedule period-2 interrupts
103 * in odd-numbered frames, period-4 interrupts in frames congruent
104 * to 2 (mod 4), and so on. This way each frame only has two
105 * interrupt QHs, which will help spread out bandwidth utilization.
107 * ffs (Find First bit Set) does exactly what we need:
108 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8],
109 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc.
110 * ffs >= 7 => not on any high-period queue, so use
111 * period-1 QH = skelqh[9].
112 * Add in UHCI_NUMFRAMES to insure at least one bit is set.
114 skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES);
117 return LINK_TO_QH(uhci->skelqh[skelnum]);
120 #include "uhci-debug.c"
122 #include "uhci-hub.c"
125 * Finish up a host controller reset and update the recorded state.
127 static void finish_reset(struct uhci_hcd *uhci)
131 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect
132 * bits in the port status and control registers.
133 * We have to clear them by hand.
135 for (port = 0; port < uhci->rh_numports; ++port)
136 uhci_writew(uhci, 0, USBPORTSC1 + (port * 2));
138 uhci->port_c_suspend = uhci->resuming_ports = 0;
139 uhci->rh_state = UHCI_RH_RESET;
140 uhci->is_stopped = UHCI_IS_STOPPED;
141 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
145 * Last rites for a defunct/nonfunctional controller
146 * or one we don't want to use any more.
148 static void uhci_hc_died(struct uhci_hcd *uhci)
150 uhci_get_current_frame_number(uhci);
151 uhci->reset_hc(uhci);
155 /* The current frame may already be partway finished */
156 ++uhci->frame_number;
160 * Initialize a controller that was newly discovered or has lost power
161 * or otherwise been reset while it was suspended. In none of these cases
162 * can we be sure of its previous state.
164 static void check_and_reset_hc(struct uhci_hcd *uhci)
166 if (uhci->check_and_reset_hc(uhci))
170 #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
172 * The two functions below are generic reset functions that are used on systems
173 * that do not have keyboard and mouse legacy support. We assume that we are
174 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined.
178 * Make sure the controller is completely inactive, unable to
179 * generate interrupts or do DMA.
181 static void uhci_generic_reset_hc(struct uhci_hcd *uhci)
183 /* Reset the HC - this will force us to get a
184 * new notification of any already connected
185 * ports due to the virtual disconnect that it
188 uhci_writew(uhci, USBCMD_HCRESET, USBCMD);
191 if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET)
192 dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n");
194 /* Just to be safe, disable interrupt requests and
195 * make sure the controller is stopped.
197 uhci_writew(uhci, 0, USBINTR);
198 uhci_writew(uhci, 0, USBCMD);
202 * Initialize a controller that was newly discovered or has just been
203 * resumed. In either case we can't be sure of its previous state.
205 * Returns: 1 if the controller was reset, 0 otherwise.
207 static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci)
209 unsigned int cmd, intr;
212 * When restarting a suspended controller, we expect all the
213 * settings to be the same as we left them:
215 * Controller is stopped and configured with EGSM set;
216 * No interrupts enabled except possibly Resume Detect.
218 * If any of these conditions are violated we do a complete reset.
221 cmd = uhci_readw(uhci, USBCMD);
222 if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) {
223 dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n",
228 intr = uhci_readw(uhci, USBINTR);
229 if (intr & (~USBINTR_RESUME)) {
230 dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n",
237 dev_dbg(uhci_dev(uhci), "Performing full reset\n");
238 uhci_generic_reset_hc(uhci);
241 #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
244 * Store the basic register settings needed by the controller.
246 static void configure_hc(struct uhci_hcd *uhci)
248 /* Set the frame length to the default: 1 ms exactly */
249 uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF);
251 /* Store the frame list base address */
252 uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD);
254 /* Set the current frame number */
255 uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER,
258 /* perform any arch/bus specific configuration */
259 if (uhci->configure_hc)
260 uhci->configure_hc(uhci);
263 static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
265 /* If we have to ignore overcurrent events then almost by definition
266 * we can't depend on resume-detect interrupts. */
270 return uhci->resume_detect_interrupts_are_broken ?
271 uhci->resume_detect_interrupts_are_broken(uhci) : 0;
274 static int global_suspend_mode_is_broken(struct uhci_hcd *uhci)
276 return uhci->global_suspend_mode_is_broken ?
277 uhci->global_suspend_mode_is_broken(uhci) : 0;
280 static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
281 __releases(uhci->lock)
282 __acquires(uhci->lock)
285 int int_enable, egsm_enable, wakeup_enable;
286 struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub;
288 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED);
289 dev_dbg(&rhdev->dev, "%s%s\n", __func__,
290 (auto_stop ? " (auto-stop)" : ""));
292 /* Start off by assuming Resume-Detect interrupts and EGSM work
293 * and that remote wakeups should be enabled.
295 egsm_enable = USBCMD_EGSM;
297 int_enable = USBINTR_RESUME;
300 /* In auto-stop mode wakeups must always be detected, but
301 * Resume-Detect interrupts may be prohibited. (In the absence
302 * of CONFIG_PM, they are always disallowed.)
305 if (!device_may_wakeup(&rhdev->dev))
308 /* In bus-suspend mode wakeups may be disabled, but if they are
309 * allowed then so are Resume-Detect interrupts.
313 if (!rhdev->do_remote_wakeup)
318 /* EGSM causes the root hub to echo a 'K' signal (resume) out any
319 * port which requests a remote wakeup. According to the USB spec,
320 * every hub is supposed to do this. But if we are ignoring
321 * remote-wakeup requests anyway then there's no point to it.
322 * We also shouldn't enable EGSM if it's broken.
324 if (!wakeup_enable || global_suspend_mode_is_broken(uhci))
327 /* If we're ignoring wakeup events then there's no reason to
328 * enable Resume-Detect interrupts. We also shouldn't enable
329 * them if they are broken or disallowed.
331 * This logic may lead us to enabling RD but not EGSM. The UHCI
332 * spec foolishly says that RD works only when EGSM is on, but
333 * there's no harm in enabling it anyway -- perhaps some chips
336 if (!wakeup_enable || resume_detect_interrupts_are_broken(uhci) ||
338 uhci->RD_enable = int_enable = 0;
340 uhci_writew(uhci, int_enable, USBINTR);
341 uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD);
345 /* If we're auto-stopping then no devices have been attached
346 * for a while, so there shouldn't be any active URBs and the
347 * controller should stop after a few microseconds. Otherwise
348 * we will give the controller one frame to stop.
350 if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) {
351 uhci->rh_state = UHCI_RH_SUSPENDING;
352 spin_unlock_irq(&uhci->lock);
354 spin_lock_irq(&uhci->lock);
358 if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH))
359 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
361 uhci_get_current_frame_number(uhci);
363 uhci->rh_state = new_state;
364 uhci->is_stopped = UHCI_IS_STOPPED;
366 /* If interrupts don't work and remote wakeup is enabled then
367 * the suspended root hub needs to be polled.
369 if (!int_enable && wakeup_enable)
370 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
372 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
374 uhci_scan_schedule(uhci);
378 static void start_rh(struct uhci_hcd *uhci)
380 uhci->is_stopped = 0;
382 /* Mark it configured and running with a 64-byte max packet.
383 * All interrupts are enabled, even though RESUME won't do anything.
385 uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD);
386 uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME |
387 USBINTR_IOC | USBINTR_SP, USBINTR);
389 uhci->rh_state = UHCI_RH_RUNNING;
390 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
393 static void wakeup_rh(struct uhci_hcd *uhci)
394 __releases(uhci->lock)
395 __acquires(uhci->lock)
397 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev,
399 uhci->rh_state == UHCI_RH_AUTO_STOPPED ?
400 " (auto-start)" : "");
402 /* If we are auto-stopped then no devices are attached so there's
403 * no need for wakeup signals. Otherwise we send Global Resume
406 if (uhci->rh_state == UHCI_RH_SUSPENDED) {
409 /* Keep EGSM on if it was set before */
410 egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM;
411 uhci->rh_state = UHCI_RH_RESUMING;
412 uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD);
413 spin_unlock_irq(&uhci->lock);
415 spin_lock_irq(&uhci->lock);
419 /* End Global Resume and wait for EOP to be sent */
420 uhci_writew(uhci, USBCMD_CF, USBCMD);
423 if (uhci_readw(uhci, USBCMD) & USBCMD_FGR)
424 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
429 /* Restart root hub polling */
430 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
433 static irqreturn_t uhci_irq(struct usb_hcd *hcd)
435 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
436 unsigned short status;
439 * Read the interrupt status, and write it back to clear the
440 * interrupt cause. Contrary to the UHCI specification, the
441 * "HC Halted" status bit is persistent: it is RO, not R/WC.
443 status = uhci_readw(uhci, USBSTS);
444 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
446 uhci_writew(uhci, status, USBSTS); /* Clear it */
448 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
449 if (status & USBSTS_HSE)
450 dev_err(uhci_dev(uhci), "host system error, "
452 if (status & USBSTS_HCPE)
453 dev_err(uhci_dev(uhci), "host controller process "
454 "error, something bad happened!\n");
455 if (status & USBSTS_HCH) {
456 spin_lock(&uhci->lock);
457 if (uhci->rh_state >= UHCI_RH_RUNNING) {
458 dev_err(uhci_dev(uhci),
459 "host controller halted, "
461 if (debug > 1 && errbuf) {
462 /* Print the schedule for debugging */
463 uhci_sprint_schedule(uhci,
470 /* Force a callback in case there are
472 mod_timer(&hcd->rh_timer, jiffies);
474 spin_unlock(&uhci->lock);
478 if (status & USBSTS_RD)
479 usb_hcd_poll_rh_status(hcd);
481 spin_lock(&uhci->lock);
482 uhci_scan_schedule(uhci);
483 spin_unlock(&uhci->lock);
490 * Store the current frame number in uhci->frame_number if the controller
491 * is running. Expand from 11 bits (of which we use only 10) to a
492 * full-sized integer.
494 * Like many other parts of the driver, this code relies on being polled
495 * more than once per second as long as the controller is running.
497 static void uhci_get_current_frame_number(struct uhci_hcd *uhci)
499 if (!uhci->is_stopped) {
502 delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) &
503 (UHCI_NUMFRAMES - 1);
504 uhci->frame_number += delta;
509 * De-allocate all resources
511 static void release_uhci(struct uhci_hcd *uhci)
515 if (DEBUG_CONFIGURED) {
516 spin_lock_irq(&uhci->lock);
517 uhci->is_initialized = 0;
518 spin_unlock_irq(&uhci->lock);
520 debugfs_remove(uhci->dentry);
523 for (i = 0; i < UHCI_NUM_SKELQH; i++)
524 uhci_free_qh(uhci, uhci->skelqh[i]);
526 uhci_free_td(uhci, uhci->term_td);
528 dma_pool_destroy(uhci->qh_pool);
530 dma_pool_destroy(uhci->td_pool);
532 kfree(uhci->frame_cpu);
534 dma_free_coherent(uhci_dev(uhci),
535 UHCI_NUMFRAMES * sizeof(*uhci->frame),
536 uhci->frame, uhci->frame_dma_handle);
540 * Allocate a frame list, and then setup the skeleton
542 * The hardware doesn't really know any difference
543 * in the queues, but the order does matter for the
544 * protocols higher up. The order in which the queues
545 * are encountered by the hardware is:
547 * - All isochronous events are handled before any
548 * of the queues. We don't do that here, because
549 * we'll create the actual TD entries on demand.
550 * - The first queue is the high-period interrupt queue.
551 * - The second queue is the period-1 interrupt and async
552 * (low-speed control, full-speed control, then bulk) queue.
553 * - The third queue is the terminating bandwidth reclamation queue,
554 * which contains no members, loops back to itself, and is present
555 * only when FSBR is on and there are no full-speed control or bulk QHs.
557 static int uhci_start(struct usb_hcd *hcd)
559 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
562 struct dentry __maybe_unused *dentry;
564 hcd->uses_new_polling = 1;
566 spin_lock_init(&uhci->lock);
567 setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout,
568 (unsigned long) uhci);
569 INIT_LIST_HEAD(&uhci->idle_qh_list);
570 init_waitqueue_head(&uhci->waitqh);
572 #ifdef UHCI_DEBUG_OPS
573 dentry = debugfs_create_file(hcd->self.bus_name,
574 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root,
575 uhci, &uhci_debug_operations);
577 dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n");
580 uhci->dentry = dentry;
583 uhci->frame = dma_alloc_coherent(uhci_dev(uhci),
584 UHCI_NUMFRAMES * sizeof(*uhci->frame),
585 &uhci->frame_dma_handle, 0);
587 dev_err(uhci_dev(uhci), "unable to allocate "
588 "consistent memory for frame list\n");
589 goto err_alloc_frame;
591 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame));
593 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu),
595 if (!uhci->frame_cpu) {
596 dev_err(uhci_dev(uhci), "unable to allocate "
597 "memory for frame pointers\n");
598 goto err_alloc_frame_cpu;
601 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci),
602 sizeof(struct uhci_td), 16, 0);
603 if (!uhci->td_pool) {
604 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n");
605 goto err_create_td_pool;
608 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci),
609 sizeof(struct uhci_qh), 16, 0);
610 if (!uhci->qh_pool) {
611 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n");
612 goto err_create_qh_pool;
615 uhci->term_td = uhci_alloc_td(uhci);
616 if (!uhci->term_td) {
617 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n");
618 goto err_alloc_term_td;
621 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
622 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL);
623 if (!uhci->skelqh[i]) {
624 dev_err(uhci_dev(uhci), "unable to allocate QH\n");
625 goto err_alloc_skelqh;
630 * 8 Interrupt queues; link all higher int queues to int1 = async
632 for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)
633 uhci->skelqh[i]->link = LINK_TO_QH(uhci->skel_async_qh);
634 uhci->skel_async_qh->link = UHCI_PTR_TERM;
635 uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_term_qh);
637 /* This dummy TD is to work around a bug in Intel PIIX controllers */
638 uhci_fill_td(uhci->term_td, 0, uhci_explen(0) |
639 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
640 uhci->term_td->link = UHCI_PTR_TERM;
641 uhci->skel_async_qh->element = uhci->skel_term_qh->element =
642 LINK_TO_TD(uhci->term_td);
645 * Fill the frame list: make all entries point to the proper
648 for (i = 0; i < UHCI_NUMFRAMES; i++) {
650 /* Only place we don't use the frame list routines */
651 uhci->frame[i] = uhci_frame_skel_link(uhci, i);
655 * Some architectures require a full mb() to enforce completion of
656 * the memory writes above before the I/O transfers in configure_hc().
661 uhci->is_initialized = 1;
662 spin_lock_irq(&uhci->lock);
664 spin_unlock_irq(&uhci->lock);
671 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
673 uhci_free_qh(uhci, uhci->skelqh[i]);
676 uhci_free_td(uhci, uhci->term_td);
679 dma_pool_destroy(uhci->qh_pool);
682 dma_pool_destroy(uhci->td_pool);
685 kfree(uhci->frame_cpu);
688 dma_free_coherent(uhci_dev(uhci),
689 UHCI_NUMFRAMES * sizeof(*uhci->frame),
690 uhci->frame, uhci->frame_dma_handle);
693 debugfs_remove(uhci->dentry);
698 static void uhci_stop(struct usb_hcd *hcd)
700 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
702 spin_lock_irq(&uhci->lock);
703 if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead)
705 uhci_scan_schedule(uhci);
706 spin_unlock_irq(&uhci->lock);
707 synchronize_irq(hcd->irq);
709 del_timer_sync(&uhci->fsbr_timer);
714 static int uhci_rh_suspend(struct usb_hcd *hcd)
716 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
719 spin_lock_irq(&uhci->lock);
720 if (!HCD_HW_ACCESSIBLE(hcd))
723 ; /* Dead controllers tell no tales */
725 /* Once the controller is stopped, port resumes that are already
726 * in progress won't complete. Hence if remote wakeup is enabled
727 * for the root hub and any ports are in the middle of a resume or
728 * remote wakeup, we must fail the suspend.
730 else if (hcd->self.root_hub->do_remote_wakeup &&
731 uhci->resuming_ports) {
732 dev_dbg(uhci_dev(uhci), "suspend failed because a port "
736 suspend_rh(uhci, UHCI_RH_SUSPENDED);
737 spin_unlock_irq(&uhci->lock);
741 static int uhci_rh_resume(struct usb_hcd *hcd)
743 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
746 spin_lock_irq(&uhci->lock);
747 if (!HCD_HW_ACCESSIBLE(hcd))
749 else if (!uhci->dead)
751 spin_unlock_irq(&uhci->lock);
757 /* Wait until a particular device/endpoint's QH is idle, and free it */
758 static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd,
759 struct usb_host_endpoint *hep)
761 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
764 spin_lock_irq(&uhci->lock);
765 qh = (struct uhci_qh *) hep->hcpriv;
769 while (qh->state != QH_STATE_IDLE) {
771 spin_unlock_irq(&uhci->lock);
772 wait_event_interruptible(uhci->waitqh,
773 qh->state == QH_STATE_IDLE);
774 spin_lock_irq(&uhci->lock);
778 uhci_free_qh(uhci, qh);
780 spin_unlock_irq(&uhci->lock);
783 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
785 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
786 unsigned frame_number;
789 /* Minimize latency by avoiding the spinlock */
790 frame_number = uhci->frame_number;
792 delta = (uhci_readw(uhci, USBFRNUM) - frame_number) &
793 (UHCI_NUMFRAMES - 1);
794 return frame_number + delta;
797 /* Determines number of ports on controller */
798 static int uhci_count_ports(struct usb_hcd *hcd)
800 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
801 unsigned io_size = (unsigned) hcd->rsrc_len;
804 /* The UHCI spec says devices must have 2 ports, and goes on to say
805 * they may have more but gives no way to determine how many there
806 * are. However according to the UHCI spec, Bit 7 of the port
807 * status and control register is always set to 1. So we try to
808 * use this to our advantage. Another common failure mode when
809 * a nonexistent register is addressed is to return all ones, so
810 * we test for that also.
812 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
813 unsigned int portstatus;
815 portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2));
816 if (!(portstatus & 0x0080) || portstatus == 0xffff)
820 dev_info(uhci_dev(uhci), "detected %d ports\n", port);
822 /* Anything greater than 7 is weird so we'll ignore it. */
823 if (port > UHCI_RH_MAXCHILD) {
824 dev_info(uhci_dev(uhci), "port count misdetected? "
825 "forcing to 2 ports\n");
832 static const char hcd_name[] = "uhci_hcd";
835 #include "uhci-pci.c"
836 #define PCI_DRIVER uhci_pci_driver
839 #ifdef CONFIG_SPARC_LEON
840 #include "uhci-grlib.c"
841 #define PLATFORM_DRIVER uhci_grlib_driver
844 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
845 #error "missing bus glue for uhci-hcd"
848 static int __init uhci_hcd_init(void)
850 int retval = -ENOMEM;
855 printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n",
856 ignore_oc ? ", overcurrent ignored" : "");
857 set_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
859 if (DEBUG_CONFIGURED) {
860 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
863 uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root);
864 if (!uhci_debugfs_root)
868 uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
869 sizeof(struct urb_priv), 0, 0, NULL);
873 #ifdef PLATFORM_DRIVER
874 retval = platform_driver_register(&PLATFORM_DRIVER);
880 retval = pci_register_driver(&PCI_DRIVER);
890 #ifdef PLATFORM_DRIVER
891 platform_driver_unregister(&PLATFORM_DRIVER);
894 kmem_cache_destroy(uhci_up_cachep);
897 debugfs_remove(uhci_debugfs_root);
904 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
908 static void __exit uhci_hcd_cleanup(void)
910 #ifdef PLATFORM_DRIVER
911 platform_driver_unregister(&PLATFORM_DRIVER);
914 pci_unregister_driver(&PCI_DRIVER);
916 kmem_cache_destroy(uhci_up_cachep);
917 debugfs_remove(uhci_debugfs_root);
919 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded);
922 module_init(uhci_hcd_init);
923 module_exit(uhci_hcd_cleanup);
925 MODULE_AUTHOR(DRIVER_AUTHOR);
926 MODULE_DESCRIPTION(DRIVER_DESC);
927 MODULE_LICENSE("GPL");