2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #error "This file is PCI bus glue. CONFIG_PCI must be defined."
25 /*-------------------------------------------------------------------------*/
27 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
28 * off the controller (maybe it can boot from highspeed USB disks).
30 static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
32 struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
34 /* always say Linux will own the hardware */
35 pci_write_config_byte(pdev, where + 3, 1);
37 /* maybe wait a while for BIOS to respond */
38 if (cap & (1 << 16)) {
44 pci_read_config_dword(pdev, where, &cap);
45 } while ((cap & (1 << 16)) && msec);
46 if (cap & (1 << 16)) {
47 ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
49 // some BIOS versions seem buggy...
51 ehci_warn(ehci, "continuing after BIOS bug...\n");
52 /* disable all SMIs, and clear "BIOS owns" flag */
53 pci_write_config_dword(pdev, where + 4, 0);
54 pci_write_config_byte(pdev, where + 2, 0);
56 ehci_dbg(ehci, "BIOS handoff succeeded\n");
61 /* called by khubd or root hub init threads */
62 static int ehci_pci_reset(struct usb_hcd *hcd)
64 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
65 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
67 unsigned count = 256/4;
69 spin_lock_init (&ehci->lock);
71 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
73 dbg_hcs_params(ehci, "reset");
74 dbg_hcc_params(ehci, "reset");
76 /* cache this readonly data; minimize chip reads */
77 ehci->hcs_params = readl(&ehci->caps->hcs_params);
79 /* NOTE: only the parts below this line are PCI-specific */
81 switch (pdev->vendor) {
82 case PCI_VENDOR_ID_TDI:
83 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
84 ehci->is_tdi_rh_tt = 1;
88 case PCI_VENDOR_ID_AMD:
89 /* AMD8111 EHCI doesn't work, according to AMD errata */
90 if (pdev->device == 0x7463) {
91 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
95 case PCI_VENDOR_ID_NVIDIA:
96 /* NVidia reports that certain chips don't handle
97 * QH, ITD, or SITD addresses above 2GB. (But TD,
98 * data buffer, and periodic schedule are normal.)
100 switch (pdev->device) {
101 case 0x003c: /* MCP04 */
102 case 0x005b: /* CK804 */
103 case 0x00d8: /* CK8 */
104 case 0x00e8: /* CK8S */
105 if (pci_set_consistent_dma_mask(pdev,
107 ehci_warn(ehci, "can't enable NVidia "
108 "workaround for >2GB RAM\n");
114 /* optional debug port, normally in the first BAR */
115 temp = pci_find_capability(pdev, 0x0a);
117 pci_read_config_dword(pdev, temp, &temp);
119 if ((temp & (3 << 13)) == (1 << 13)) {
121 ehci->debug = hcd->regs + temp;
122 temp = readl(&ehci->debug->control);
123 ehci_info(ehci, "debug port %d%s\n",
124 HCS_DEBUG_PORT(ehci->hcs_params),
125 (temp & DBGP_ENABLED)
128 if (!(temp & DBGP_ENABLED))
133 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
135 /* EHCI 0.96 and later may have "extended capabilities" */
136 while (temp && count--) {
139 pci_read_config_dword(to_pci_dev(hcd->self.controller),
141 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
142 switch (cap & 0xff) {
143 case 1: /* BIOS/SMM/... handoff */
144 if (bios_handoff(ehci, temp, cap) != 0)
147 case 0: /* illegal reserved capability */
148 ehci_warn(ehci, "illegal capability!\n");
151 default: /* unknown */
154 temp = (cap >> 8) & 0xff;
157 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
160 if (ehci_is_TDI(ehci))
163 ehci_port_power(ehci, 0);
165 /* at least the Genesys GL880S needs fixup here */
166 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
168 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
169 ehci_dbg(ehci, "bogus port configuration: "
170 "cc=%d x pcc=%d < ports=%d\n",
171 HCS_N_CC(ehci->hcs_params),
172 HCS_N_PCC(ehci->hcs_params),
173 HCS_N_PORTS(ehci->hcs_params));
175 switch (pdev->vendor) {
176 case 0x17a0: /* GENESYS */
177 /* GL880S: should be PORTS=2 */
178 temp |= (ehci->hcs_params & ~0xf);
179 ehci->hcs_params = temp;
181 case PCI_VENDOR_ID_NVIDIA:
182 /* NF4: should be PCC=10 */
187 /* force HC to halt state */
188 return ehci_halt(ehci);
191 static int ehci_pci_start(struct usb_hcd *hcd)
193 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
195 struct pci_dev *pdev;
198 pdev = to_pci_dev(hcd->self.controller);
200 /* Serial Bus Release Number is at PCI 0x60 offset */
201 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
203 /* port wake capability, reported by boot firmware */
204 pci_read_config_word(pdev, 0x62, &port_wake);
205 hcd->can_wakeup = (port_wake & 1) != 0;
207 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
208 result = pci_set_mwi(pdev);
210 ehci_dbg(ehci, "MWI active\n");
212 return ehci_run(hcd);
215 /* always called by thread; normally rmmod */
217 static void ehci_pci_stop(struct usb_hcd *hcd)
222 /*-------------------------------------------------------------------------*/
226 /* suspend/resume, section 4.3 */
228 /* These routines rely on the PCI bus glue
229 * to handle powerdown and wakeup, and currently also on
230 * transceivers that don't need any software attention to set up
231 * the right sort of wakeup.
232 * Also they depend on separate root hub suspend/resume.
235 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
237 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
239 if (time_before(jiffies, ehci->next_statechange))
242 // could save FLADJ in case of Vaux power loss
243 // ... we'd only use it to handle clock skew
248 static int ehci_pci_resume(struct usb_hcd *hcd)
250 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
252 struct usb_device *root = hcd->self.root_hub;
253 int retval = -EINVAL;
255 // maybe restore FLADJ
257 if (time_before(jiffies, ehci->next_statechange))
260 /* If CF is clear, we lost PCI Vaux power and need to restart. */
261 if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF))
264 /* If any port is suspended (or owned by the companion),
265 * we know we can/must resume the HC (and mustn't reset it).
266 * We just defer that to the root hub code.
268 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
271 status = readl(&ehci->regs->port_status [port]);
272 if (!(status & PORT_POWER))
274 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
275 usb_hcd_resume_root_hub(hcd);
281 ehci_dbg(ehci, "lost power, restarting\n");
282 for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
284 if (!root->children [port])
286 usb_set_device_state(root->children[port],
287 USB_STATE_NOTATTACHED);
290 /* Else reset, to cope with power loss or flush-to-storage
291 * style "resume" having let BIOS kick in during reboot.
293 (void) ehci_halt(ehci);
294 (void) ehci_reset(ehci);
295 (void) ehci_pci_reset(hcd);
297 /* emptying the schedule aborts any urbs */
298 spin_lock_irq(&ehci->lock);
300 ehci->reclaim_ready = 1;
301 ehci_work(ehci, NULL);
302 spin_unlock_irq(&ehci->lock);
304 /* restart; khubd will disconnect devices */
305 retval = ehci_run(hcd);
307 /* here we "know" root ports should always stay powered;
308 * but some controllers may lose all power.
310 ehci_port_power(ehci, 1);
316 static const struct hc_driver ehci_pci_hc_driver = {
317 .description = hcd_name,
318 .product_desc = "EHCI Host Controller",
319 .hcd_priv_size = sizeof(struct ehci_hcd),
322 * generic hardware linkage
325 .flags = HCD_MEMORY | HCD_USB2,
328 * basic lifecycle operations
330 .reset = ehci_pci_reset,
331 .start = ehci_pci_start,
333 .suspend = ehci_pci_suspend,
334 .resume = ehci_pci_resume,
336 .stop = ehci_pci_stop,
339 * managing i/o requests and associated device resources
341 .urb_enqueue = ehci_urb_enqueue,
342 .urb_dequeue = ehci_urb_dequeue,
343 .endpoint_disable = ehci_endpoint_disable,
348 .get_frame_number = ehci_get_frame,
353 .hub_status_data = ehci_hub_status_data,
354 .hub_control = ehci_hub_control,
355 .bus_suspend = ehci_bus_suspend,
356 .bus_resume = ehci_bus_resume,
359 /*-------------------------------------------------------------------------*/
361 /* PCI driver selection metadata; PCI hotplugging uses this */
362 static const struct pci_device_id pci_ids [] = { {
363 /* handle any USB 2.0 EHCI controller */
364 PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
365 .driver_data = (unsigned long) &ehci_pci_hc_driver,
367 { /* end: all zeroes */ }
369 MODULE_DEVICE_TABLE(pci, pci_ids);
371 /* pci driver glue; this is a "new style" PCI driver module */
372 static struct pci_driver ehci_pci_driver = {
373 .name = (char *) hcd_name,
376 .probe = usb_hcd_pci_probe,
377 .remove = usb_hcd_pci_remove,
380 .suspend = usb_hcd_pci_suspend,
381 .resume = usb_hcd_pci_resume,
385 static int __init ehci_hcd_pci_init(void)
390 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
392 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
393 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
395 return pci_register_driver(&ehci_pci_driver);
397 module_init(ehci_hcd_pci_init);
399 static void __exit ehci_hcd_pci_cleanup(void)
401 pci_unregister_driver(&ehci_pci_driver);
403 module_exit(ehci_hcd_pci_cleanup);