Pileus Git - ~andy/linux/blob - drivers/usb/gadget/s3c-hsudc.c

   1 /* linux/drivers/usb/gadget/s3c-hsudc.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S3C24XX USB 2.0 High-speed USB controller gadget driver
   7  *
   8  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
   9  * Each endpoint can be configured as either in or out endpoint. Endpoints
  10  * can be configured for Bulk or Interrupt transfer mode.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15 */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/clk.h>
  27 #include <linux/usb/ch9.h>
  28 #include <linux/usb/gadget.h>
  29 #include <linux/usb/otg.h>
  30 #include <linux/prefetch.h>
  31 #include <linux/platform_data/s3c-hsudc.h>
  32 #include <linux/regulator/consumer.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <mach/regs-s3c2443-clock.h>
  36
  37 #define S3C_HSUDC_REG(x)        (x)
  38
  39 /* Non-Indexed Registers */
  40 #define S3C_IR                          S3C_HSUDC_REG(0x00) /* Index Register */
  41 #define S3C_EIR                         S3C_HSUDC_REG(0x04) /* EP Intr Status */
  42 #define S3C_EIR_EP0                     (1<<0)
  43 #define S3C_EIER                        S3C_HSUDC_REG(0x08) /* EP Intr Enable */
  44 #define S3C_FAR                         S3C_HSUDC_REG(0x0c) /* Gadget Address */
  45 #define S3C_FNR                         S3C_HSUDC_REG(0x10) /* Frame Number */
  46 #define S3C_EDR                         S3C_HSUDC_REG(0x14) /* EP Direction */
  47 #define S3C_TR                          S3C_HSUDC_REG(0x18) /* Test Register */
  48 #define S3C_SSR                         S3C_HSUDC_REG(0x1c) /* System Status */
  49 #define S3C_SSR_DTZIEN_EN               (0xff8f)
  50 #define S3C_SSR_ERR                     (0xff80)
  51 #define S3C_SSR_VBUSON                  (1 << 8)
  52 #define S3C_SSR_HSP                     (1 << 4)
  53 #define S3C_SSR_SDE                     (1 << 3)
  54 #define S3C_SSR_RESUME                  (1 << 2)
  55 #define S3C_SSR_SUSPEND                 (1 << 1)
  56 #define S3C_SSR_RESET                   (1 << 0)
  57 #define S3C_SCR                         S3C_HSUDC_REG(0x20) /* System Control */
  58 #define S3C_SCR_DTZIEN_EN               (1 << 14)
  59 #define S3C_SCR_RRD_EN                  (1 << 5)
  60 #define S3C_SCR_SUS_EN                  (1 << 1)
  61 #define S3C_SCR_RST_EN                  (1 << 0)
  62 #define S3C_EP0SR                       S3C_HSUDC_REG(0x24) /* EP0 Status */
  63 #define S3C_EP0SR_EP0_LWO               (1 << 6)
  64 #define S3C_EP0SR_STALL                 (1 << 4)
  65 #define S3C_EP0SR_TX_SUCCESS            (1 << 1)
  66 #define S3C_EP0SR_RX_SUCCESS            (1 << 0)
  67 #define S3C_EP0CR                       S3C_HSUDC_REG(0x28) /* EP0 Control */
  68 #define S3C_BR(_x)                      S3C_HSUDC_REG(0x60 + (_x * 4))
  69
  70 /* Indexed Registers */
  71 #define S3C_ESR                         S3C_HSUDC_REG(0x2c) /* EPn Status */
  72 #define S3C_ESR_FLUSH                   (1 << 6)
  73 #define S3C_ESR_STALL                   (1 << 5)
  74 #define S3C_ESR_LWO                     (1 << 4)
  75 #define S3C_ESR_PSIF_ONE                (1 << 2)
  76 #define S3C_ESR_PSIF_TWO                (2 << 2)
  77 #define S3C_ESR_TX_SUCCESS              (1 << 1)
  78 #define S3C_ESR_RX_SUCCESS              (1 << 0)
  79 #define S3C_ECR                         S3C_HSUDC_REG(0x30) /* EPn Control */
  80 #define S3C_ECR_DUEN                    (1 << 7)
  81 #define S3C_ECR_FLUSH                   (1 << 6)
  82 #define S3C_ECR_STALL                   (1 << 1)
  83 #define S3C_ECR_IEMS                    (1 << 0)
  84 #define S3C_BRCR                        S3C_HSUDC_REG(0x34) /* Read Count */
  85 #define S3C_BWCR                        S3C_HSUDC_REG(0x38) /* Write Count */
  86 #define S3C_MPR                         S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
  87
  88 #define WAIT_FOR_SETUP                  (0)
  89 #define DATA_STATE_XMIT                 (1)
  90 #define DATA_STATE_RECV                 (2)
  91
  92 static const char * const s3c_hsudc_supply_names[] = {
  93         "vdda",         /* analog phy supply, 3.3V */
  94         "vddi",         /* digital phy supply, 1.2V */
  95         "vddosc",       /* oscillator supply, 1.8V - 3.3V */
  96 };
  97
  98 /**
  99  * struct s3c_hsudc_ep - Endpoint representation used by driver.
 100  * @ep: USB gadget layer representation of device endpoint.
 101  * @name: Endpoint name (as required by ep autoconfiguration).
 102  * @dev: Reference to the device controller to which this EP belongs.
 103  * @desc: Endpoint descriptor obtained from the gadget driver.
 104  * @queue: Transfer request queue for the endpoint.
 105  * @stopped: Maintains state of endpoint, set if EP is halted.
 106  * @bEndpointAddress: EP address (including direction bit).
 107  * @fifo: Base address of EP FIFO.
 108  */
 109 struct s3c_hsudc_ep {
 110         struct usb_ep ep;
 111         char name[20];
 112         struct s3c_hsudc *dev;
 113         const struct usb_endpoint_descriptor *desc;
 114         struct list_head queue;
 115         u8 stopped;
 116         u8 wedge;
 117         u8 bEndpointAddress;
 118         void __iomem *fifo;
 119 };
 120
 121 /**
 122  * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
 123  * @req: Reference to USB gadget transfer request.
 124  * @queue: Used for inserting this request to the endpoint request queue.
 125  */
 126 struct s3c_hsudc_req {
 127         struct usb_request req;
 128         struct list_head queue;
 129 };
 130
 131 /**
 132  * struct s3c_hsudc - Driver's abstraction of the device controller.
 133  * @gadget: Instance of usb_gadget which is referenced by gadget driver.
 134  * @driver: Reference to currenty active gadget driver.
 135  * @dev: The device reference used by probe function.
 136  * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
 137  * @regs: Remapped base address of controller's register space.
 138  * @mem_rsrc: Device memory resource used for remapping device register space.
 139  * irq: IRQ number used by the controller.
 140  * uclk: Reference to the controller clock.
 141  * ep0state: Current state of EP0.
 142  * ep: List of endpoints supported by the controller.
 143  */
 144 struct s3c_hsudc {
 145         struct usb_gadget gadget;
 146         struct usb_gadget_driver *driver;
 147         struct device *dev;
 148         struct s3c24xx_hsudc_platdata *pd;
 149         struct usb_phy *transceiver;
 150         struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
 151         spinlock_t lock;
 152         void __iomem *regs;
 153         struct resource *mem_rsrc;
 154         int irq;
 155         struct clk *uclk;
 156         int ep0state;
 157         struct s3c_hsudc_ep ep[];
 158 };
 159
 160 #define ep_maxpacket(_ep)       ((_ep)->ep.maxpacket)
 161 #define ep_is_in(_ep)           ((_ep)->bEndpointAddress & USB_DIR_IN)
 162 #define ep_index(_ep)           ((_ep)->bEndpointAddress & \
 163                                         USB_ENDPOINT_NUMBER_MASK)
 164
 165 static const char driver_name[] = "s3c-udc";
 166 static const char ep0name[] = "ep0-control";
 167
 168 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
 169 {
 170         return container_of(req, struct s3c_hsudc_req, req);
 171 }
 172
 173 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
 174 {
 175         return container_of(ep, struct s3c_hsudc_ep, ep);
 176 }
 177
 178 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
 179 {
 180         return container_of(gadget, struct s3c_hsudc, gadget);
 181 }
 182
 183 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
 184 {
 185         ep_addr &= USB_ENDPOINT_NUMBER_MASK;
 186         writel(ep_addr, hsudc->regs + S3C_IR);
 187 }
 188
 189 static inline void __orr32(void __iomem *ptr, u32 val)
 190 {
 191         writel(readl(ptr) | val, ptr);
 192 }
 193
 194 static void s3c_hsudc_init_phy(void)
 195 {
 196         u32 cfg;
 197
 198         cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
 199         writel(cfg, S3C2443_PWRCFG);
 200
 201         cfg = readl(S3C2443_URSTCON);
 202         cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 203         writel(cfg, S3C2443_URSTCON);
 204         mdelay(1);
 205
 206         cfg = readl(S3C2443_URSTCON);
 207         cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 208         writel(cfg, S3C2443_URSTCON);
 209
 210         cfg = readl(S3C2443_PHYCTRL);
 211         cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
 212         cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
 213         writel(cfg, S3C2443_PHYCTRL);
 214
 215         cfg = readl(S3C2443_PHYPWR);
 216         cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
 217                 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
 218                 S3C2443_PHYPWR_ANALOG_PD);
 219         cfg |= S3C2443_PHYPWR_COMMON_ON;
 220         writel(cfg, S3C2443_PHYPWR);
 221
 222         cfg = readl(S3C2443_UCLKCON);
 223         cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
 224                 S3C2443_UCLKCON_TCLKEN);
 225         writel(cfg, S3C2443_UCLKCON);
 226 }
 227
 228 static void s3c_hsudc_uninit_phy(void)
 229 {
 230         u32 cfg;
 231
 232         cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
 233         writel(cfg, S3C2443_PWRCFG);
 234
 235         writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
 236
 237         cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
 238         writel(cfg, S3C2443_UCLKCON);
 239 }
 240
 241 /**
 242  * s3c_hsudc_complete_request - Complete a transfer request.
 243  * @hsep: Endpoint to which the request belongs.
 244  * @hsreq: Transfer request to be completed.
 245  * @status: Transfer completion status for the transfer request.
 246  */
 247 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
 248                                 struct s3c_hsudc_req *hsreq, int status)
 249 {
 250         unsigned int stopped = hsep->stopped;
 251         struct s3c_hsudc *hsudc = hsep->dev;
 252
 253         list_del_init(&hsreq->queue);
 254         hsreq->req.status = status;
 255
 256         if (!ep_index(hsep)) {
 257                 hsudc->ep0state = WAIT_FOR_SETUP;
 258                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 259         }
 260
 261         hsep->stopped = 1;
 262         spin_unlock(&hsudc->lock);
 263         if (hsreq->req.complete != NULL)
 264                 hsreq->req.complete(&hsep->ep, &hsreq->req);
 265         spin_lock(&hsudc->lock);
 266         hsep->stopped = stopped;
 267 }
 268
 269 /**
 270  * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
 271  * @hsep: Endpoint for which queued requests have to be terminated.
 272  * @status: Transfer completion status for the transfer request.
 273  */
 274 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
 275 {
 276         struct s3c_hsudc_req *hsreq;
 277
 278         while (!list_empty(&hsep->queue)) {
 279                 hsreq = list_entry(hsep->queue.next,
 280                                 struct s3c_hsudc_req, queue);
 281                 s3c_hsudc_complete_request(hsep, hsreq, status);
 282         }
 283 }
 284
 285 /**
 286  * s3c_hsudc_stop_activity - Stop activity on all endpoints.
 287  * @hsudc: Device controller for which EP activity is to be stopped.
 288  * @driver: Reference to the gadget driver which is currently active.
 289  *
 290  * All the endpoints are stopped and any pending transfer requests if any on
 291  * the endpoint are terminated.
 292  */
 293 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
 294 {
 295         struct s3c_hsudc_ep *hsep;
 296         int epnum;
 297
 298         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
 299
 300         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
 301                 hsep = &hsudc->ep[epnum];
 302                 hsep->stopped = 1;
 303                 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 304         }
 305 }
 306
 307 /**
 308  * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
 309  * @hsudc: Device controller from which setup packet is to be read.
 310  * @buf: The buffer into which the setup packet is read.
 311  *
 312  * The setup packet received in the EP0 fifo is read and stored into a
 313  * given buffer address.
 314  */
 315
 316 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
 317 {
 318         int count;
 319
 320         count = readl(hsudc->regs + S3C_BRCR);
 321         while (count--)
 322                 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
 323
 324         writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
 325 }
 326
 327 /**
 328  * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
 329  * @hsep: Endpoint to which the data is to be written.
 330  * @hsreq: Transfer request from which the next chunk of data is written.
 331  *
 332  * Write the next chunk of data from a transfer request to the endpoint FIFO.
 333  * If the transfer request completes, 1 is returned, otherwise 0 is returned.
 334  */
 335 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
 336                                 struct s3c_hsudc_req *hsreq)
 337 {
 338         u16 *buf;
 339         u32 max = ep_maxpacket(hsep);
 340         u32 count, length;
 341         bool is_last;
 342         void __iomem *fifo = hsep->fifo;
 343
 344         buf = hsreq->req.buf + hsreq->req.actual;
 345         prefetch(buf);
 346
 347         length = hsreq->req.length - hsreq->req.actual;
 348         length = min(length, max);
 349         hsreq->req.actual += length;
 350
 351         writel(length, hsep->dev->regs + S3C_BWCR);
 352         for (count = 0; count < length; count += 2)
 353                 writel(*buf++, fifo);
 354
 355         if (count != max) {
 356                 is_last = true;
 357         } else {
 358                 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
 359                         is_last = false;
 360                 else
 361                         is_last = true;
 362         }
 363
 364         if (is_last) {
 365                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 366                 return 1;
 367         }
 368
 369         return 0;
 370 }
 371
 372 /**
 373  * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
 374  * @hsep: Endpoint from which the data is to be read.
 375  * @hsreq: Transfer request to which the next chunk of data read is written.
 376  *
 377  * Read the next chunk of data from the endpoint FIFO and a write it to the
 378  * transfer request buffer. If the transfer request completes, 1 is returned,
 379  * otherwise 0 is returned.
 380  */
 381 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
 382                                 struct s3c_hsudc_req *hsreq)
 383 {
 384         struct s3c_hsudc *hsudc = hsep->dev;
 385         u32 csr, offset;
 386         u16 *buf, word;
 387         u32 buflen, rcnt, rlen;
 388         void __iomem *fifo = hsep->fifo;
 389         u32 is_short = 0;
 390
 391         offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 392         csr = readl(hsudc->regs + offset);
 393         if (!(csr & S3C_ESR_RX_SUCCESS))
 394                 return -EINVAL;
 395
 396         buf = hsreq->req.buf + hsreq->req.actual;
 397         prefetchw(buf);
 398         buflen = hsreq->req.length - hsreq->req.actual;
 399
 400         rcnt = readl(hsudc->regs + S3C_BRCR);
 401         rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
 402
 403         hsreq->req.actual += min(rlen, buflen);
 404         is_short = (rlen < hsep->ep.maxpacket);
 405
 406         while (rcnt-- != 0) {
 407                 word = (u16)readl(fifo);
 408                 if (buflen) {
 409                         *buf++ = word;
 410                         buflen--;
 411                 } else {
 412                         hsreq->req.status = -EOVERFLOW;
 413                 }
 414         }
 415
 416         writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
 417
 418         if (is_short || hsreq->req.actual == hsreq->req.length) {
 419                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 420                 return 1;
 421         }
 422
 423         return 0;
 424 }
 425
 426 /**
 427  * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
 428  * @hsudc - Device controller for which the interrupt is to be handled.
 429  * @ep_idx - Endpoint number on which an interrupt is pending.
 430  *
 431  * Handles interrupt for a in-endpoint. The interrupts that are handled are
 432  * stall and data transmit complete interrupt.
 433  */
 434 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 435 {
 436         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 437         struct s3c_hsudc_req *hsreq;
 438         u32 csr;
 439
 440         csr = readl((u32)hsudc->regs + S3C_ESR);
 441         if (csr & S3C_ESR_STALL) {
 442                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 443                 return;
 444         }
 445
 446         if (csr & S3C_ESR_TX_SUCCESS) {
 447                 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
 448                 if (list_empty(&hsep->queue))
 449                         return;
 450
 451                 hsreq = list_entry(hsep->queue.next,
 452                                 struct s3c_hsudc_req, queue);
 453                 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
 454                                 (csr & S3C_ESR_PSIF_TWO))
 455                         s3c_hsudc_write_fifo(hsep, hsreq);
 456         }
 457 }
 458
 459 /**
 460  * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
 461  * @hsudc - Device controller for which the interrupt is to be handled.
 462  * @ep_idx - Endpoint number on which an interrupt is pending.
 463  *
 464  * Handles interrupt for a out-endpoint. The interrupts that are handled are
 465  * stall, flush and data ready interrupt.
 466  */
 467 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 468 {
 469         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 470         struct s3c_hsudc_req *hsreq;
 471         u32 csr;
 472
 473         csr = readl((u32)hsudc->regs + S3C_ESR);
 474         if (csr & S3C_ESR_STALL) {
 475                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 476                 return;
 477         }
 478
 479         if (csr & S3C_ESR_FLUSH) {
 480                 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
 481                 return;
 482         }
 483
 484         if (csr & S3C_ESR_RX_SUCCESS) {
 485                 if (list_empty(&hsep->queue))
 486                         return;
 487
 488                 hsreq = list_entry(hsep->queue.next,
 489                                 struct s3c_hsudc_req, queue);
 490                 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
 491                                 (csr & S3C_ESR_PSIF_TWO))
 492                         s3c_hsudc_read_fifo(hsep, hsreq);
 493         }
 494 }
 495
 496 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
 497  * @_ep: Endpoint on which halt has to be set or cleared.
 498  * @value: 1 for setting halt on endpoint, 0 to clear halt.
 499  *
 500  * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
 501  * If halt is cleared, for in-endpoints, if there are any pending
 502  * transfer requests, transfers are started.
 503  */
 504 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
 505 {
 506         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 507         struct s3c_hsudc *hsudc = hsep->dev;
 508         struct s3c_hsudc_req *hsreq;
 509         unsigned long irqflags;
 510         u32 ecr;
 511         u32 offset;
 512
 513         if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
 514                 return -EAGAIN;
 515
 516         spin_lock_irqsave(&hsudc->lock, irqflags);
 517         set_index(hsudc, ep_index(hsep));
 518         offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
 519         ecr = readl(hsudc->regs + offset);
 520
 521         if (value) {
 522                 ecr |= S3C_ECR_STALL;
 523                 if (ep_index(hsep))
 524                         ecr |= S3C_ECR_FLUSH;
 525                 hsep->stopped = 1;
 526         } else {
 527                 ecr &= ~S3C_ECR_STALL;
 528                 hsep->stopped = hsep->wedge = 0;
 529         }
 530         writel(ecr, hsudc->regs + offset);
 531
 532         if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
 533                 hsreq = list_entry(hsep->queue.next,
 534                         struct s3c_hsudc_req, queue);
 535                 if (hsreq)
 536                         s3c_hsudc_write_fifo(hsep, hsreq);
 537         }
 538
 539         spin_unlock_irqrestore(&hsudc->lock, irqflags);
 540         return 0;
 541 }
 542
 543 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
 544  * @_ep: Endpoint on which wedge has to be set.
 545  *
 546  * Sets the halt feature with the clear requests ignored.
 547  */
 548 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
 549 {
 550         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 551
 552         if (!hsep)
 553                 return -EINVAL;
 554
 555         hsep->wedge = 1;
 556         return usb_ep_set_halt(_ep);
 557 }
 558
 559 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
 560  * @_ep: Device controller on which the set/clear feature needs to be handled.
 561  * @ctrl: Control request as received on the endpoint 0.
 562  *
 563  * Handle set feature or clear feature control requests on the control endpoint.
 564  */
 565 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
 566                                         struct usb_ctrlrequest *ctrl)
 567 {
 568         struct s3c_hsudc_ep *hsep;
 569         bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
 570         u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
 571
 572         if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
 573                 hsep = &hsudc->ep[ep_num];
 574                 switch (le16_to_cpu(ctrl->wValue)) {
 575                 case USB_ENDPOINT_HALT:
 576                         if (set || (!set && !hsep->wedge))
 577                                 s3c_hsudc_set_halt(&hsep->ep, set);
 578                         return 0;
 579                 }
 580         }
 581
 582         return -ENOENT;
 583 }
 584
 585 /**
 586  * s3c_hsudc_process_req_status - Handle get status control request.
 587  * @hsudc: Device controller on which get status request has be handled.
 588  * @ctrl: Control request as received on the endpoint 0.
 589  *
 590  * Handle get status control request received on control endpoint.
 591  */
 592 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
 593                                         struct usb_ctrlrequest *ctrl)
 594 {
 595         struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
 596         struct s3c_hsudc_req hsreq;
 597         struct s3c_hsudc_ep *hsep;
 598         __le16 reply;
 599         u8 epnum;
 600
 601         switch (ctrl->bRequestType & USB_RECIP_MASK) {
 602         case USB_RECIP_DEVICE:
 603                 reply = cpu_to_le16(0);
 604                 break;
 605
 606         case USB_RECIP_INTERFACE:
 607                 reply = cpu_to_le16(0);
 608                 break;
 609
 610         case USB_RECIP_ENDPOINT:
 611                 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
 612                 hsep = &hsudc->ep[epnum];
 613                 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
 614                 break;
 615         }
 616
 617         INIT_LIST_HEAD(&hsreq.queue);
 618         hsreq.req.length = 2;
 619         hsreq.req.buf = &reply;
 620         hsreq.req.actual = 0;
 621         hsreq.req.complete = NULL;
 622         s3c_hsudc_write_fifo(hsep0, &hsreq);
 623 }
 624
 625 /**
 626  * s3c_hsudc_process_setup - Process control request received on endpoint 0.
 627  * @hsudc: Device controller on which control request has been received.
 628  *
 629  * Read the control request received on endpoint 0, decode it and handle
 630  * the request.
 631  */
 632 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
 633 {
 634         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 635         struct usb_ctrlrequest ctrl = {0};
 636         int ret;
 637
 638         s3c_hsudc_nuke_ep(hsep, -EPROTO);
 639         s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
 640
 641         if (ctrl.bRequestType & USB_DIR_IN) {
 642                 hsep->bEndpointAddress |= USB_DIR_IN;
 643                 hsudc->ep0state = DATA_STATE_XMIT;
 644         } else {
 645                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 646                 hsudc->ep0state = DATA_STATE_RECV;
 647         }
 648
 649         switch (ctrl.bRequest) {
 650         case USB_REQ_SET_ADDRESS:
 651                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
 652                         break;
 653                 hsudc->ep0state = WAIT_FOR_SETUP;
 654                 return;
 655
 656         case USB_REQ_GET_STATUS:
 657                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 658                         break;
 659                 s3c_hsudc_process_req_status(hsudc, &ctrl);
 660                 return;
 661
 662         case USB_REQ_SET_FEATURE:
 663         case USB_REQ_CLEAR_FEATURE:
 664                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 665                         break;
 666                 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
 667                 hsudc->ep0state = WAIT_FOR_SETUP;
 668                 return;
 669         }
 670
 671         if (hsudc->driver) {
 672                 spin_unlock(&hsudc->lock);
 673                 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
 674                 spin_lock(&hsudc->lock);
 675
 676                 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
 677                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 678                         hsudc->ep0state = WAIT_FOR_SETUP;
 679                 }
 680
 681                 if (ret < 0) {
 682                         dev_err(hsudc->dev, "setup failed, returned %d\n",
 683                                                 ret);
 684                         s3c_hsudc_set_halt(&hsep->ep, 1);
 685                         hsudc->ep0state = WAIT_FOR_SETUP;
 686                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 687                 }
 688         }
 689 }
 690
 691 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
 692  * @hsudc: Device controller on which endpoint 0 interrupt has occured.
 693  *
 694  * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
 695  * when a stall handshake is sent to host or data is sent/received on
 696  * endpoint 0.
 697  */
 698 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
 699 {
 700         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 701         struct s3c_hsudc_req *hsreq;
 702         u32 csr = readl(hsudc->regs + S3C_EP0SR);
 703         u32 ecr;
 704
 705         if (csr & S3C_EP0SR_STALL) {
 706                 ecr = readl(hsudc->regs + S3C_EP0CR);
 707                 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
 708                 writel(ecr, hsudc->regs + S3C_EP0CR);
 709
 710                 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
 711                 hsep->stopped = 0;
 712
 713                 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
 714                 hsudc->ep0state = WAIT_FOR_SETUP;
 715                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 716                 return;
 717         }
 718
 719         if (csr & S3C_EP0SR_TX_SUCCESS) {
 720                 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
 721                 if (ep_is_in(hsep)) {
 722                         if (list_empty(&hsep->queue))
 723                                 return;
 724
 725                         hsreq = list_entry(hsep->queue.next,
 726                                         struct s3c_hsudc_req, queue);
 727                         s3c_hsudc_write_fifo(hsep, hsreq);
 728                 }
 729         }
 730
 731         if (csr & S3C_EP0SR_RX_SUCCESS) {
 732                 if (hsudc->ep0state == WAIT_FOR_SETUP)
 733                         s3c_hsudc_process_setup(hsudc);
 734                 else {
 735                         if (!ep_is_in(hsep)) {
 736                                 if (list_empty(&hsep->queue))
 737                                         return;
 738                                 hsreq = list_entry(hsep->queue.next,
 739                                         struct s3c_hsudc_req, queue);
 740                                 s3c_hsudc_read_fifo(hsep, hsreq);
 741                         }
 742                 }
 743         }
 744 }
 745
 746 /**
 747  * s3c_hsudc_ep_enable - Enable a endpoint.
 748  * @_ep: The endpoint to be enabled.
 749  * @desc: Endpoint descriptor.
 750  *
 751  * Enables a endpoint when called from the gadget driver. Endpoint stall if
 752  * any is cleared, transfer type is configured and endpoint interrupt is
 753  * enabled.
 754  */
 755 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
 756                                 const struct usb_endpoint_descriptor *desc)
 757 {
 758         struct s3c_hsudc_ep *hsep;
 759         struct s3c_hsudc *hsudc;
 760         unsigned long flags;
 761         u32 ecr = 0;
 762
 763         hsep = our_ep(_ep);
 764         if (!_ep || !desc || hsep->desc || _ep->name == ep0name
 765                 || desc->bDescriptorType != USB_DT_ENDPOINT
 766                 || hsep->bEndpointAddress != desc->bEndpointAddress
 767                 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
 768                 return -EINVAL;
 769
 770         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 771                 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
 772                 || !desc->wMaxPacketSize)
 773                 return -ERANGE;
 774
 775         hsudc = hsep->dev;
 776         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 777                 return -ESHUTDOWN;
 778
 779         spin_lock_irqsave(&hsudc->lock, flags);
 780
 781         set_index(hsudc, hsep->bEndpointAddress);
 782         ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
 783         writel(ecr, hsudc->regs + S3C_ECR);
 784
 785         hsep->stopped = hsep->wedge = 0;
 786         hsep->desc = desc;
 787         hsep->ep.maxpacket = usb_endpoint_maxp(desc);
 788
 789         s3c_hsudc_set_halt(_ep, 0);
 790         __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 791
 792         spin_unlock_irqrestore(&hsudc->lock, flags);
 793         return 0;
 794 }
 795
 796 /**
 797  * s3c_hsudc_ep_disable - Disable a endpoint.
 798  * @_ep: The endpoint to be disabled.
 799  * @desc: Endpoint descriptor.
 800  *
 801  * Disables a endpoint when called from the gadget driver.
 802  */
 803 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
 804 {
 805         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 806         struct s3c_hsudc *hsudc = hsep->dev;
 807         unsigned long flags;
 808
 809         if (!_ep || !hsep->desc)
 810                 return -EINVAL;
 811
 812         spin_lock_irqsave(&hsudc->lock, flags);
 813
 814         set_index(hsudc, hsep->bEndpointAddress);
 815         __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 816
 817         s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 818
 819         hsep->desc = 0;
 820         hsep->ep.desc = NULL;
 821         hsep->stopped = 1;
 822
 823         spin_unlock_irqrestore(&hsudc->lock, flags);
 824         return 0;
 825 }
 826
 827 /**
 828  * s3c_hsudc_alloc_request - Allocate a new request.
 829  * @_ep: Endpoint for which request is allocated (not used).
 830  * @gfp_flags: Flags used for the allocation.
 831  *
 832  * Allocates a single transfer request structure when called from gadget driver.
 833  */
 834 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
 835                                                 gfp_t gfp_flags)
 836 {
 837         struct s3c_hsudc_req *hsreq;
 838
 839         hsreq = kzalloc(sizeof *hsreq, gfp_flags);
 840         if (!hsreq)
 841                 return 0;
 842
 843         INIT_LIST_HEAD(&hsreq->queue);
 844         return &hsreq->req;
 845 }
 846
 847 /**
 848  * s3c_hsudc_free_request - Deallocate a request.
 849  * @ep: Endpoint for which request is deallocated (not used).
 850  * @_req: Request to be deallocated.
 851  *
 852  * Allocates a single transfer request structure when called from gadget driver.
 853  */
 854 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
 855 {
 856         struct s3c_hsudc_req *hsreq;
 857
 858         hsreq = our_req(_req);
 859         WARN_ON(!list_empty(&hsreq->queue));
 860         kfree(hsreq);
 861 }
 862
 863 /**
 864  * s3c_hsudc_queue - Queue a transfer request for the endpoint.
 865  * @_ep: Endpoint for which the request is queued.
 866  * @_req: Request to be queued.
 867  * @gfp_flags: Not used.
 868  *
 869  * Start or enqueue a request for a endpoint when called from gadget driver.
 870  */
 871 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
 872                         gfp_t gfp_flags)
 873 {
 874         struct s3c_hsudc_req *hsreq;
 875         struct s3c_hsudc_ep *hsep;
 876         struct s3c_hsudc *hsudc;
 877         unsigned long flags;
 878         u32 offset;
 879         u32 csr;
 880
 881         hsreq = our_req(_req);
 882         if ((!_req || !_req->complete || !_req->buf ||
 883                 !list_empty(&hsreq->queue)))
 884                 return -EINVAL;
 885
 886         hsep = our_ep(_ep);
 887         hsudc = hsep->dev;
 888         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 889                 return -ESHUTDOWN;
 890
 891         spin_lock_irqsave(&hsudc->lock, flags);
 892         set_index(hsudc, hsep->bEndpointAddress);
 893
 894         _req->status = -EINPROGRESS;
 895         _req->actual = 0;
 896
 897         if (!ep_index(hsep) && _req->length == 0) {
 898                 hsudc->ep0state = WAIT_FOR_SETUP;
 899                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 900                 spin_unlock_irqrestore(&hsudc->lock, flags);
 901                 return 0;
 902         }
 903
 904         if (list_empty(&hsep->queue) && !hsep->stopped) {
 905                 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 906                 if (ep_is_in(hsep)) {
 907                         csr = readl((u32)hsudc->regs + offset);
 908                         if (!(csr & S3C_ESR_TX_SUCCESS) &&
 909                                 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
 910                                 hsreq = 0;
 911                 } else {
 912                         csr = readl((u32)hsudc->regs + offset);
 913                         if ((csr & S3C_ESR_RX_SUCCESS)
 914                                    && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
 915                                 hsreq = 0;
 916                 }
 917         }
 918
 919         if (hsreq != 0)
 920                 list_add_tail(&hsreq->queue, &hsep->queue);
 921
 922         spin_unlock_irqrestore(&hsudc->lock, flags);
 923         return 0;
 924 }
 925
 926 /**
 927  * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
 928  * @_ep: Endpoint from which the request is dequeued.
 929  * @_req: Request to be dequeued.
 930  *
 931  * Dequeue a request from a endpoint when called from gadget driver.
 932  */
 933 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 934 {
 935         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 936         struct s3c_hsudc *hsudc = hsep->dev;
 937         struct s3c_hsudc_req *hsreq;
 938         unsigned long flags;
 939
 940         hsep = our_ep(_ep);
 941         if (!_ep || hsep->ep.name == ep0name)
 942                 return -EINVAL;
 943
 944         spin_lock_irqsave(&hsudc->lock, flags);
 945
 946         list_for_each_entry(hsreq, &hsep->queue, queue) {
 947                 if (&hsreq->req == _req)
 948                         break;
 949         }
 950         if (&hsreq->req != _req) {
 951                 spin_unlock_irqrestore(&hsudc->lock, flags);
 952                 return -EINVAL;
 953         }
 954
 955         set_index(hsudc, hsep->bEndpointAddress);
 956         s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
 957
 958         spin_unlock_irqrestore(&hsudc->lock, flags);
 959         return 0;
 960 }
 961
 962 static struct usb_ep_ops s3c_hsudc_ep_ops = {
 963         .enable = s3c_hsudc_ep_enable,
 964         .disable = s3c_hsudc_ep_disable,
 965         .alloc_request = s3c_hsudc_alloc_request,
 966         .free_request = s3c_hsudc_free_request,
 967         .queue = s3c_hsudc_queue,
 968         .dequeue = s3c_hsudc_dequeue,
 969         .set_halt = s3c_hsudc_set_halt,
 970         .set_wedge = s3c_hsudc_set_wedge,
 971 };
 972
 973 /**
 974  * s3c_hsudc_initep - Initialize a endpoint to default state.
 975  * @hsudc - Reference to the device controller.
 976  * @hsep - Endpoint to be initialized.
 977  * @epnum - Address to be assigned to the endpoint.
 978  *
 979  * Initialize a endpoint with default configuration.
 980  */
 981 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
 982                                 struct s3c_hsudc_ep *hsep, int epnum)
 983 {
 984         char *dir;
 985
 986         if ((epnum % 2) == 0) {
 987                 dir = "out";
 988         } else {
 989                 dir = "in";
 990                 hsep->bEndpointAddress = USB_DIR_IN;
 991         }
 992
 993         hsep->bEndpointAddress |= epnum;
 994         if (epnum)
 995                 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
 996         else
 997                 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
 998
 999         INIT_LIST_HEAD(&hsep->queue);
1000         INIT_LIST_HEAD(&hsep->ep.ep_list);
1001         if (epnum)
1002                 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1003
1004         hsep->dev = hsudc;
1005         hsep->ep.name = hsep->name;
1006         hsep->ep.maxpacket = epnum ? 512 : 64;
1007         hsep->ep.ops = &s3c_hsudc_ep_ops;
1008         hsep->fifo = hsudc->regs + S3C_BR(epnum);
1009         hsep->desc = 0;
1010         hsep->ep.desc = NULL;
1011         hsep->stopped = 0;
1012         hsep->wedge = 0;
1013
1014         set_index(hsudc, epnum);
1015         writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1016 }
1017
1018 /**
1019  * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1020  * @hsudc: Reference to device controller.
1021  *
1022  * Configures all endpoints to default state.
1023  */
1024 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1025 {
1026         int epnum;
1027
1028         hsudc->ep0state = WAIT_FOR_SETUP;
1029         INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1030         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1031                 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1032 }
1033
1034 /**
1035  * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1036  * @hsudc: Reference to device controller.
1037  *
1038  * Reconfigures the device controller registers to a default state.
1039  */
1040 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1041 {
1042         writel(0xAA, hsudc->regs + S3C_EDR);
1043         writel(1, hsudc->regs + S3C_EIER);
1044         writel(0, hsudc->regs + S3C_TR);
1045         writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1046                         S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1047         writel(0, hsudc->regs + S3C_EP0CR);
1048
1049         s3c_hsudc_setup_ep(hsudc);
1050 }
1051
1052 /**
1053  * s3c_hsudc_irq - Interrupt handler for device controller.
1054  * @irq: Not used.
1055  * @_dev: Reference to the device controller.
1056  *
1057  * Interrupt handler for the device controller. This handler handles controller
1058  * interrupts and endpoint interrupts.
1059  */
1060 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1061 {
1062         struct s3c_hsudc *hsudc = _dev;
1063         struct s3c_hsudc_ep *hsep;
1064         u32 ep_intr;
1065         u32 sys_status;
1066         u32 ep_idx;
1067
1068         spin_lock(&hsudc->lock);
1069
1070         sys_status = readl(hsudc->regs + S3C_SSR);
1071         ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1072
1073         if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1074                 spin_unlock(&hsudc->lock);
1075                 return IRQ_HANDLED;
1076         }
1077
1078         if (sys_status) {
1079                 if (sys_status & S3C_SSR_VBUSON)
1080                         writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1081
1082                 if (sys_status & S3C_SSR_ERR)
1083                         writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1084
1085                 if (sys_status & S3C_SSR_SDE) {
1086                         writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1087                         hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1088                                 USB_SPEED_HIGH : USB_SPEED_FULL;
1089                 }
1090
1091                 if (sys_status & S3C_SSR_SUSPEND) {
1092                         writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1093                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1094                                 && hsudc->driver && hsudc->driver->suspend)
1095                                 hsudc->driver->suspend(&hsudc->gadget);
1096                 }
1097
1098                 if (sys_status & S3C_SSR_RESUME) {
1099                         writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1100                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1101                                 && hsudc->driver && hsudc->driver->resume)
1102                                 hsudc->driver->resume(&hsudc->gadget);
1103                 }
1104
1105                 if (sys_status & S3C_SSR_RESET) {
1106                         writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1107                         for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1108                                 hsep = &hsudc->ep[ep_idx];
1109                                 hsep->stopped = 1;
1110                                 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1111                         }
1112                         s3c_hsudc_reconfig(hsudc);
1113                         hsudc->ep0state = WAIT_FOR_SETUP;
1114                 }
1115         }
1116
1117         if (ep_intr & S3C_EIR_EP0) {
1118                 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1119                 set_index(hsudc, 0);
1120                 s3c_hsudc_handle_ep0_intr(hsudc);
1121         }
1122
1123         ep_intr >>= 1;
1124         ep_idx = 1;
1125         while (ep_intr) {
1126                 if (ep_intr & 1)  {
1127                         hsep = &hsudc->ep[ep_idx];
1128                         set_index(hsudc, ep_idx);
1129                         writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1130                         if (ep_is_in(hsep))
1131                                 s3c_hsudc_epin_intr(hsudc, ep_idx);
1132                         else
1133                                 s3c_hsudc_epout_intr(hsudc, ep_idx);
1134                 }
1135                 ep_intr >>= 1;
1136                 ep_idx++;
1137         }
1138
1139         spin_unlock(&hsudc->lock);
1140         return IRQ_HANDLED;
1141 }
1142
1143 static int s3c_hsudc_start(struct usb_gadget *gadget,
1144                 struct usb_gadget_driver *driver)
1145 {
1146         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1147         int ret;
1148
1149         if (!driver
1150                 || driver->max_speed < USB_SPEED_FULL
1151                 || !driver->setup)
1152                 return -EINVAL;
1153
1154         if (!hsudc)
1155                 return -ENODEV;
1156
1157         if (hsudc->driver)
1158                 return -EBUSY;
1159
1160         hsudc->driver = driver;
1161         hsudc->gadget.dev.driver = &driver->driver;
1162
1163         ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1164                                     hsudc->supplies);
1165         if (ret != 0) {
1166                 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1167                 goto err_supplies;
1168         }
1169
1170         /* connect to bus through transceiver */
1171         if (hsudc->transceiver) {
1172                 ret = otg_set_peripheral(hsudc->transceiver->otg,
1173                                         &hsudc->gadget);
1174                 if (ret) {
1175                         dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1176                                         hsudc->gadget.name);
1177                         goto err_otg;
1178                 }
1179         }
1180
1181         enable_irq(hsudc->irq);
1182         dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1183
1184         s3c_hsudc_reconfig(hsudc);
1185
1186         pm_runtime_get_sync(hsudc->dev);
1187
1188         s3c_hsudc_init_phy();
1189         if (hsudc->pd->gpio_init)
1190                 hsudc->pd->gpio_init();
1191
1192         return 0;
1193 err_otg:
1194         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1195 err_supplies:
1196         hsudc->driver = NULL;
1197         hsudc->gadget.dev.driver = NULL;
1198         return ret;
1199 }
1200
1201 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1202                 struct usb_gadget_driver *driver)
1203 {
1204         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1205         unsigned long flags;
1206
1207         if (!hsudc)
1208                 return -ENODEV;
1209
1210         if (!driver || driver != hsudc->driver)
1211                 return -EINVAL;
1212
1213         spin_lock_irqsave(&hsudc->lock, flags);
1214         hsudc->driver = NULL;
1215         hsudc->gadget.dev.driver = NULL;
1216         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1217         s3c_hsudc_uninit_phy();
1218
1219         pm_runtime_put(hsudc->dev);
1220
1221         if (hsudc->pd->gpio_uninit)
1222                 hsudc->pd->gpio_uninit();
1223         s3c_hsudc_stop_activity(hsudc);
1224         spin_unlock_irqrestore(&hsudc->lock, flags);
1225
1226         if (hsudc->transceiver)
1227                 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1228
1229         disable_irq(hsudc->irq);
1230
1231         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1232
1233         dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1234                         driver->driver.name);
1235         return 0;
1236 }
1237
1238 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1239 {
1240         return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1241 }
1242
1243 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1244 {
1245         return s3c_hsudc_read_frameno(to_hsudc(gadget));
1246 }
1247
1248 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1249 {
1250         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1251
1252         if (!hsudc)
1253                 return -ENODEV;
1254
1255         if (hsudc->transceiver)
1256                 return usb_phy_set_power(hsudc->transceiver, mA);
1257
1258         return -EOPNOTSUPP;
1259 }
1260
1261 static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1262         .get_frame      = s3c_hsudc_gadget_getframe,
1263         .udc_start      = s3c_hsudc_start,
1264         .udc_stop       = s3c_hsudc_stop,
1265         .vbus_draw      = s3c_hsudc_vbus_draw,
1266 };
1267
1268 static int __devinit s3c_hsudc_probe(struct platform_device *pdev)
1269 {
1270         struct device *dev = &pdev->dev;
1271         struct resource *res;
1272         struct s3c_hsudc *hsudc;
1273         struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1274         int ret, i;
1275
1276         hsudc = kzalloc(sizeof(struct s3c_hsudc) +
1277                         sizeof(struct s3c_hsudc_ep) * pd->epnum,
1278                         GFP_KERNEL);
1279         if (!hsudc) {
1280                 dev_err(dev, "cannot allocate memory\n");
1281                 return -ENOMEM;
1282         }
1283
1284         platform_set_drvdata(pdev, dev);
1285         hsudc->dev = dev;
1286         hsudc->pd = pdev->dev.platform_data;
1287
1288         hsudc->transceiver = usb_get_transceiver();
1289
1290         for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1291                 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1292
1293         ret = regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1294                                  hsudc->supplies);
1295         if (ret != 0) {
1296                 dev_err(dev, "failed to request supplies: %d\n", ret);
1297                 goto err_supplies;
1298         }
1299
1300         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1301         if (!res) {
1302                 dev_err(dev, "unable to obtain driver resource data\n");
1303                 ret = -ENODEV;
1304                 goto err_res;
1305         }
1306
1307         hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
1308                                 dev_name(&pdev->dev));
1309         if (!hsudc->mem_rsrc) {
1310                 dev_err(dev, "failed to reserve register area\n");
1311                 ret = -ENODEV;
1312                 goto err_res;
1313         }
1314
1315         hsudc->regs = ioremap(res->start, resource_size(res));
1316         if (!hsudc->regs) {
1317                 dev_err(dev, "error mapping device register area\n");
1318                 ret = -EBUSY;
1319                 goto err_remap;
1320         }
1321
1322         spin_lock_init(&hsudc->lock);
1323
1324         dev_set_name(&hsudc->gadget.dev, "gadget");
1325
1326         hsudc->gadget.max_speed = USB_SPEED_HIGH;
1327         hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1328         hsudc->gadget.name = dev_name(dev);
1329         hsudc->gadget.dev.parent = dev;
1330         hsudc->gadget.dev.dma_mask = dev->dma_mask;
1331         hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1332
1333         hsudc->gadget.is_otg = 0;
1334         hsudc->gadget.is_a_peripheral = 0;
1335         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1336
1337         s3c_hsudc_setup_ep(hsudc);
1338
1339         ret = platform_get_irq(pdev, 0);
1340         if (ret < 0) {
1341                 dev_err(dev, "unable to obtain IRQ number\n");
1342                 goto err_irq;
1343         }
1344         hsudc->irq = ret;
1345
1346         ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
1347         if (ret < 0) {
1348                 dev_err(dev, "irq request failed\n");
1349                 goto err_irq;
1350         }
1351
1352         hsudc->uclk = clk_get(&pdev->dev, "usb-device");
1353         if (IS_ERR(hsudc->uclk)) {
1354                 dev_err(dev, "failed to find usb-device clock source\n");
1355                 ret = PTR_ERR(hsudc->uclk);
1356                 goto err_clk;
1357         }
1358         clk_enable(hsudc->uclk);
1359
1360         local_irq_disable();
1361
1362         disable_irq(hsudc->irq);
1363         local_irq_enable();
1364
1365         ret = device_register(&hsudc->gadget.dev);
1366         if (ret) {
1367                 put_device(&hsudc->gadget.dev);
1368                 goto err_add_device;
1369         }
1370
1371         ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1372         if (ret)
1373                 goto err_add_udc;
1374
1375         pm_runtime_enable(dev);
1376
1377         return 0;
1378 err_add_udc:
1379         device_unregister(&hsudc->gadget.dev);
1380 err_add_device:
1381         clk_disable(hsudc->uclk);
1382         clk_put(hsudc->uclk);
1383 err_clk:
1384         free_irq(hsudc->irq, hsudc);
1385 err_irq:
1386         iounmap(hsudc->regs);
1387
1388 err_remap:
1389         release_mem_region(res->start, resource_size(res));
1390 err_res:
1391         if (hsudc->transceiver)
1392                 usb_put_transceiver(hsudc->transceiver);
1393
1394         regulator_bulk_free(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1395 err_supplies:
1396         kfree(hsudc);
1397         return ret;
1398 }
1399
1400 static struct platform_driver s3c_hsudc_driver = {
1401         .driver         = {
1402                 .owner  = THIS_MODULE,
1403                 .name   = "s3c-hsudc",
1404         },
1405         .probe          = s3c_hsudc_probe,
1406 };
1407
1408 module_platform_driver(s3c_hsudc_driver);
1409
1410 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1411 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1412 MODULE_LICENSE("GPL");
1413 MODULE_ALIAS("platform:s3c-hsudc");