Pileus Git - ~andy/linux/blob - drivers/usb/gadget/s3c-hsudc.c

   1 /* linux/drivers/usb/gadget/s3c-hsudc.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S3C24XX USB 2.0 High-speed USB controller gadget driver
   7  *
   8  * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
   9  * Each endpoint can be configured as either in or out endpoint. Endpoints
  10  * can be configured for Bulk or Interrupt transfer mode.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15 */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/delay.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30 #include <linux/usb/otg.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/platform_data/s3c-hsudc.h>
  33 #include <linux/regulator/consumer.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <mach/regs-s3c2443-clock.h>
  37
  38 #define S3C_HSUDC_REG(x)        (x)
  39
  40 /* Non-Indexed Registers */
  41 #define S3C_IR                          S3C_HSUDC_REG(0x00) /* Index Register */
  42 #define S3C_EIR                         S3C_HSUDC_REG(0x04) /* EP Intr Status */
  43 #define S3C_EIR_EP0                     (1<<0)
  44 #define S3C_EIER                        S3C_HSUDC_REG(0x08) /* EP Intr Enable */
  45 #define S3C_FAR                         S3C_HSUDC_REG(0x0c) /* Gadget Address */
  46 #define S3C_FNR                         S3C_HSUDC_REG(0x10) /* Frame Number */
  47 #define S3C_EDR                         S3C_HSUDC_REG(0x14) /* EP Direction */
  48 #define S3C_TR                          S3C_HSUDC_REG(0x18) /* Test Register */
  49 #define S3C_SSR                         S3C_HSUDC_REG(0x1c) /* System Status */
  50 #define S3C_SSR_DTZIEN_EN               (0xff8f)
  51 #define S3C_SSR_ERR                     (0xff80)
  52 #define S3C_SSR_VBUSON                  (1 << 8)
  53 #define S3C_SSR_HSP                     (1 << 4)
  54 #define S3C_SSR_SDE                     (1 << 3)
  55 #define S3C_SSR_RESUME                  (1 << 2)
  56 #define S3C_SSR_SUSPEND                 (1 << 1)
  57 #define S3C_SSR_RESET                   (1 << 0)
  58 #define S3C_SCR                         S3C_HSUDC_REG(0x20) /* System Control */
  59 #define S3C_SCR_DTZIEN_EN               (1 << 14)
  60 #define S3C_SCR_RRD_EN                  (1 << 5)
  61 #define S3C_SCR_SUS_EN                  (1 << 1)
  62 #define S3C_SCR_RST_EN                  (1 << 0)
  63 #define S3C_EP0SR                       S3C_HSUDC_REG(0x24) /* EP0 Status */
  64 #define S3C_EP0SR_EP0_LWO               (1 << 6)
  65 #define S3C_EP0SR_STALL                 (1 << 4)
  66 #define S3C_EP0SR_TX_SUCCESS            (1 << 1)
  67 #define S3C_EP0SR_RX_SUCCESS            (1 << 0)
  68 #define S3C_EP0CR                       S3C_HSUDC_REG(0x28) /* EP0 Control */
  69 #define S3C_BR(_x)                      S3C_HSUDC_REG(0x60 + (_x * 4))
  70
  71 /* Indexed Registers */
  72 #define S3C_ESR                         S3C_HSUDC_REG(0x2c) /* EPn Status */
  73 #define S3C_ESR_FLUSH                   (1 << 6)
  74 #define S3C_ESR_STALL                   (1 << 5)
  75 #define S3C_ESR_LWO                     (1 << 4)
  76 #define S3C_ESR_PSIF_ONE                (1 << 2)
  77 #define S3C_ESR_PSIF_TWO                (2 << 2)
  78 #define S3C_ESR_TX_SUCCESS              (1 << 1)
  79 #define S3C_ESR_RX_SUCCESS              (1 << 0)
  80 #define S3C_ECR                         S3C_HSUDC_REG(0x30) /* EPn Control */
  81 #define S3C_ECR_DUEN                    (1 << 7)
  82 #define S3C_ECR_FLUSH                   (1 << 6)
  83 #define S3C_ECR_STALL                   (1 << 1)
  84 #define S3C_ECR_IEMS                    (1 << 0)
  85 #define S3C_BRCR                        S3C_HSUDC_REG(0x34) /* Read Count */
  86 #define S3C_BWCR                        S3C_HSUDC_REG(0x38) /* Write Count */
  87 #define S3C_MPR                         S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
  88
  89 #define WAIT_FOR_SETUP                  (0)
  90 #define DATA_STATE_XMIT                 (1)
  91 #define DATA_STATE_RECV                 (2)
  92
  93 static const char * const s3c_hsudc_supply_names[] = {
  94         "vdda",         /* analog phy supply, 3.3V */
  95         "vddi",         /* digital phy supply, 1.2V */
  96         "vddosc",       /* oscillator supply, 1.8V - 3.3V */
  97 };
  98
  99 /**
 100  * struct s3c_hsudc_ep - Endpoint representation used by driver.
 101  * @ep: USB gadget layer representation of device endpoint.
 102  * @name: Endpoint name (as required by ep autoconfiguration).
 103  * @dev: Reference to the device controller to which this EP belongs.
 104  * @desc: Endpoint descriptor obtained from the gadget driver.
 105  * @queue: Transfer request queue for the endpoint.
 106  * @stopped: Maintains state of endpoint, set if EP is halted.
 107  * @bEndpointAddress: EP address (including direction bit).
 108  * @fifo: Base address of EP FIFO.
 109  */
 110 struct s3c_hsudc_ep {
 111         struct usb_ep ep;
 112         char name[20];
 113         struct s3c_hsudc *dev;
 114         struct list_head queue;
 115         u8 stopped;
 116         u8 wedge;
 117         u8 bEndpointAddress;
 118         void __iomem *fifo;
 119 };
 120
 121 /**
 122  * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
 123  * @req: Reference to USB gadget transfer request.
 124  * @queue: Used for inserting this request to the endpoint request queue.
 125  */
 126 struct s3c_hsudc_req {
 127         struct usb_request req;
 128         struct list_head queue;
 129 };
 130
 131 /**
 132  * struct s3c_hsudc - Driver's abstraction of the device controller.
 133  * @gadget: Instance of usb_gadget which is referenced by gadget driver.
 134  * @driver: Reference to currenty active gadget driver.
 135  * @dev: The device reference used by probe function.
 136  * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
 137  * @regs: Remapped base address of controller's register space.
 138  * irq: IRQ number used by the controller.
 139  * uclk: Reference to the controller clock.
 140  * ep0state: Current state of EP0.
 141  * ep: List of endpoints supported by the controller.
 142  */
 143 struct s3c_hsudc {
 144         struct usb_gadget gadget;
 145         struct usb_gadget_driver *driver;
 146         struct device *dev;
 147         struct s3c24xx_hsudc_platdata *pd;
 148         struct usb_phy *transceiver;
 149         struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsudc_supply_names)];
 150         spinlock_t lock;
 151         void __iomem *regs;
 152         int irq;
 153         struct clk *uclk;
 154         int ep0state;
 155         struct s3c_hsudc_ep ep[];
 156 };
 157
 158 #define ep_maxpacket(_ep)       ((_ep)->ep.maxpacket)
 159 #define ep_is_in(_ep)           ((_ep)->bEndpointAddress & USB_DIR_IN)
 160 #define ep_index(_ep)           ((_ep)->bEndpointAddress & \
 161                                         USB_ENDPOINT_NUMBER_MASK)
 162
 163 static const char driver_name[] = "s3c-udc";
 164 static const char ep0name[] = "ep0-control";
 165
 166 static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
 167 {
 168         return container_of(req, struct s3c_hsudc_req, req);
 169 }
 170
 171 static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
 172 {
 173         return container_of(ep, struct s3c_hsudc_ep, ep);
 174 }
 175
 176 static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
 177 {
 178         return container_of(gadget, struct s3c_hsudc, gadget);
 179 }
 180
 181 static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
 182 {
 183         ep_addr &= USB_ENDPOINT_NUMBER_MASK;
 184         writel(ep_addr, hsudc->regs + S3C_IR);
 185 }
 186
 187 static inline void __orr32(void __iomem *ptr, u32 val)
 188 {
 189         writel(readl(ptr) | val, ptr);
 190 }
 191
 192 static void s3c_hsudc_init_phy(void)
 193 {
 194         u32 cfg;
 195
 196         cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
 197         writel(cfg, S3C2443_PWRCFG);
 198
 199         cfg = readl(S3C2443_URSTCON);
 200         cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 201         writel(cfg, S3C2443_URSTCON);
 202         mdelay(1);
 203
 204         cfg = readl(S3C2443_URSTCON);
 205         cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
 206         writel(cfg, S3C2443_URSTCON);
 207
 208         cfg = readl(S3C2443_PHYCTRL);
 209         cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
 210         cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
 211         writel(cfg, S3C2443_PHYCTRL);
 212
 213         cfg = readl(S3C2443_PHYPWR);
 214         cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
 215                 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
 216                 S3C2443_PHYPWR_ANALOG_PD);
 217         cfg |= S3C2443_PHYPWR_COMMON_ON;
 218         writel(cfg, S3C2443_PHYPWR);
 219
 220         cfg = readl(S3C2443_UCLKCON);
 221         cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
 222                 S3C2443_UCLKCON_TCLKEN);
 223         writel(cfg, S3C2443_UCLKCON);
 224 }
 225
 226 static void s3c_hsudc_uninit_phy(void)
 227 {
 228         u32 cfg;
 229
 230         cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
 231         writel(cfg, S3C2443_PWRCFG);
 232
 233         writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
 234
 235         cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
 236         writel(cfg, S3C2443_UCLKCON);
 237 }
 238
 239 /**
 240  * s3c_hsudc_complete_request - Complete a transfer request.
 241  * @hsep: Endpoint to which the request belongs.
 242  * @hsreq: Transfer request to be completed.
 243  * @status: Transfer completion status for the transfer request.
 244  */
 245 static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
 246                                 struct s3c_hsudc_req *hsreq, int status)
 247 {
 248         unsigned int stopped = hsep->stopped;
 249         struct s3c_hsudc *hsudc = hsep->dev;
 250
 251         list_del_init(&hsreq->queue);
 252         hsreq->req.status = status;
 253
 254         if (!ep_index(hsep)) {
 255                 hsudc->ep0state = WAIT_FOR_SETUP;
 256                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 257         }
 258
 259         hsep->stopped = 1;
 260         spin_unlock(&hsudc->lock);
 261         if (hsreq->req.complete != NULL)
 262                 hsreq->req.complete(&hsep->ep, &hsreq->req);
 263         spin_lock(&hsudc->lock);
 264         hsep->stopped = stopped;
 265 }
 266
 267 /**
 268  * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
 269  * @hsep: Endpoint for which queued requests have to be terminated.
 270  * @status: Transfer completion status for the transfer request.
 271  */
 272 static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
 273 {
 274         struct s3c_hsudc_req *hsreq;
 275
 276         while (!list_empty(&hsep->queue)) {
 277                 hsreq = list_entry(hsep->queue.next,
 278                                 struct s3c_hsudc_req, queue);
 279                 s3c_hsudc_complete_request(hsep, hsreq, status);
 280         }
 281 }
 282
 283 /**
 284  * s3c_hsudc_stop_activity - Stop activity on all endpoints.
 285  * @hsudc: Device controller for which EP activity is to be stopped.
 286  * @driver: Reference to the gadget driver which is currently active.
 287  *
 288  * All the endpoints are stopped and any pending transfer requests if any on
 289  * the endpoint are terminated.
 290  */
 291 static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc)
 292 {
 293         struct s3c_hsudc_ep *hsep;
 294         int epnum;
 295
 296         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
 297
 298         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
 299                 hsep = &hsudc->ep[epnum];
 300                 hsep->stopped = 1;
 301                 s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 302         }
 303 }
 304
 305 /**
 306  * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
 307  * @hsudc: Device controller from which setup packet is to be read.
 308  * @buf: The buffer into which the setup packet is read.
 309  *
 310  * The setup packet received in the EP0 fifo is read and stored into a
 311  * given buffer address.
 312  */
 313
 314 static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
 315 {
 316         int count;
 317
 318         count = readl(hsudc->regs + S3C_BRCR);
 319         while (count--)
 320                 *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
 321
 322         writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
 323 }
 324
 325 /**
 326  * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
 327  * @hsep: Endpoint to which the data is to be written.
 328  * @hsreq: Transfer request from which the next chunk of data is written.
 329  *
 330  * Write the next chunk of data from a transfer request to the endpoint FIFO.
 331  * If the transfer request completes, 1 is returned, otherwise 0 is returned.
 332  */
 333 static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
 334                                 struct s3c_hsudc_req *hsreq)
 335 {
 336         u16 *buf;
 337         u32 max = ep_maxpacket(hsep);
 338         u32 count, length;
 339         bool is_last;
 340         void __iomem *fifo = hsep->fifo;
 341
 342         buf = hsreq->req.buf + hsreq->req.actual;
 343         prefetch(buf);
 344
 345         length = hsreq->req.length - hsreq->req.actual;
 346         length = min(length, max);
 347         hsreq->req.actual += length;
 348
 349         writel(length, hsep->dev->regs + S3C_BWCR);
 350         for (count = 0; count < length; count += 2)
 351                 writel(*buf++, fifo);
 352
 353         if (count != max) {
 354                 is_last = true;
 355         } else {
 356                 if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
 357                         is_last = false;
 358                 else
 359                         is_last = true;
 360         }
 361
 362         if (is_last) {
 363                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 364                 return 1;
 365         }
 366
 367         return 0;
 368 }
 369
 370 /**
 371  * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
 372  * @hsep: Endpoint from which the data is to be read.
 373  * @hsreq: Transfer request to which the next chunk of data read is written.
 374  *
 375  * Read the next chunk of data from the endpoint FIFO and a write it to the
 376  * transfer request buffer. If the transfer request completes, 1 is returned,
 377  * otherwise 0 is returned.
 378  */
 379 static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
 380                                 struct s3c_hsudc_req *hsreq)
 381 {
 382         struct s3c_hsudc *hsudc = hsep->dev;
 383         u32 csr, offset;
 384         u16 *buf, word;
 385         u32 buflen, rcnt, rlen;
 386         void __iomem *fifo = hsep->fifo;
 387         u32 is_short = 0;
 388
 389         offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 390         csr = readl(hsudc->regs + offset);
 391         if (!(csr & S3C_ESR_RX_SUCCESS))
 392                 return -EINVAL;
 393
 394         buf = hsreq->req.buf + hsreq->req.actual;
 395         prefetchw(buf);
 396         buflen = hsreq->req.length - hsreq->req.actual;
 397
 398         rcnt = readl(hsudc->regs + S3C_BRCR);
 399         rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
 400
 401         hsreq->req.actual += min(rlen, buflen);
 402         is_short = (rlen < hsep->ep.maxpacket);
 403
 404         while (rcnt-- != 0) {
 405                 word = (u16)readl(fifo);
 406                 if (buflen) {
 407                         *buf++ = word;
 408                         buflen--;
 409                 } else {
 410                         hsreq->req.status = -EOVERFLOW;
 411                 }
 412         }
 413
 414         writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
 415
 416         if (is_short || hsreq->req.actual == hsreq->req.length) {
 417                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 418                 return 1;
 419         }
 420
 421         return 0;
 422 }
 423
 424 /**
 425  * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
 426  * @hsudc - Device controller for which the interrupt is to be handled.
 427  * @ep_idx - Endpoint number on which an interrupt is pending.
 428  *
 429  * Handles interrupt for a in-endpoint. The interrupts that are handled are
 430  * stall and data transmit complete interrupt.
 431  */
 432 static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 433 {
 434         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 435         struct s3c_hsudc_req *hsreq;
 436         u32 csr;
 437
 438         csr = readl(hsudc->regs + S3C_ESR);
 439         if (csr & S3C_ESR_STALL) {
 440                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 441                 return;
 442         }
 443
 444         if (csr & S3C_ESR_TX_SUCCESS) {
 445                 writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
 446                 if (list_empty(&hsep->queue))
 447                         return;
 448
 449                 hsreq = list_entry(hsep->queue.next,
 450                                 struct s3c_hsudc_req, queue);
 451                 if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
 452                                 (csr & S3C_ESR_PSIF_TWO))
 453                         s3c_hsudc_write_fifo(hsep, hsreq);
 454         }
 455 }
 456
 457 /**
 458  * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
 459  * @hsudc - Device controller for which the interrupt is to be handled.
 460  * @ep_idx - Endpoint number on which an interrupt is pending.
 461  *
 462  * Handles interrupt for a out-endpoint. The interrupts that are handled are
 463  * stall, flush and data ready interrupt.
 464  */
 465 static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
 466 {
 467         struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
 468         struct s3c_hsudc_req *hsreq;
 469         u32 csr;
 470
 471         csr = readl(hsudc->regs + S3C_ESR);
 472         if (csr & S3C_ESR_STALL) {
 473                 writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
 474                 return;
 475         }
 476
 477         if (csr & S3C_ESR_FLUSH) {
 478                 __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
 479                 return;
 480         }
 481
 482         if (csr & S3C_ESR_RX_SUCCESS) {
 483                 if (list_empty(&hsep->queue))
 484                         return;
 485
 486                 hsreq = list_entry(hsep->queue.next,
 487                                 struct s3c_hsudc_req, queue);
 488                 if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
 489                                 (csr & S3C_ESR_PSIF_TWO))
 490                         s3c_hsudc_read_fifo(hsep, hsreq);
 491         }
 492 }
 493
 494 /** s3c_hsudc_set_halt - Set or clear a endpoint halt.
 495  * @_ep: Endpoint on which halt has to be set or cleared.
 496  * @value: 1 for setting halt on endpoint, 0 to clear halt.
 497  *
 498  * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
 499  * If halt is cleared, for in-endpoints, if there are any pending
 500  * transfer requests, transfers are started.
 501  */
 502 static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
 503 {
 504         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 505         struct s3c_hsudc *hsudc = hsep->dev;
 506         struct s3c_hsudc_req *hsreq;
 507         unsigned long irqflags;
 508         u32 ecr;
 509         u32 offset;
 510
 511         if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
 512                 return -EAGAIN;
 513
 514         spin_lock_irqsave(&hsudc->lock, irqflags);
 515         set_index(hsudc, ep_index(hsep));
 516         offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
 517         ecr = readl(hsudc->regs + offset);
 518
 519         if (value) {
 520                 ecr |= S3C_ECR_STALL;
 521                 if (ep_index(hsep))
 522                         ecr |= S3C_ECR_FLUSH;
 523                 hsep->stopped = 1;
 524         } else {
 525                 ecr &= ~S3C_ECR_STALL;
 526                 hsep->stopped = hsep->wedge = 0;
 527         }
 528         writel(ecr, hsudc->regs + offset);
 529
 530         if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
 531                 hsreq = list_entry(hsep->queue.next,
 532                         struct s3c_hsudc_req, queue);
 533                 if (hsreq)
 534                         s3c_hsudc_write_fifo(hsep, hsreq);
 535         }
 536
 537         spin_unlock_irqrestore(&hsudc->lock, irqflags);
 538         return 0;
 539 }
 540
 541 /** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
 542  * @_ep: Endpoint on which wedge has to be set.
 543  *
 544  * Sets the halt feature with the clear requests ignored.
 545  */
 546 static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
 547 {
 548         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 549
 550         if (!hsep)
 551                 return -EINVAL;
 552
 553         hsep->wedge = 1;
 554         return usb_ep_set_halt(_ep);
 555 }
 556
 557 /** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
 558  * @_ep: Device controller on which the set/clear feature needs to be handled.
 559  * @ctrl: Control request as received on the endpoint 0.
 560  *
 561  * Handle set feature or clear feature control requests on the control endpoint.
 562  */
 563 static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
 564                                         struct usb_ctrlrequest *ctrl)
 565 {
 566         struct s3c_hsudc_ep *hsep;
 567         bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
 568         u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
 569
 570         if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
 571                 hsep = &hsudc->ep[ep_num];
 572                 switch (le16_to_cpu(ctrl->wValue)) {
 573                 case USB_ENDPOINT_HALT:
 574                         if (set || (!set && !hsep->wedge))
 575                                 s3c_hsudc_set_halt(&hsep->ep, set);
 576                         return 0;
 577                 }
 578         }
 579
 580         return -ENOENT;
 581 }
 582
 583 /**
 584  * s3c_hsudc_process_req_status - Handle get status control request.
 585  * @hsudc: Device controller on which get status request has be handled.
 586  * @ctrl: Control request as received on the endpoint 0.
 587  *
 588  * Handle get status control request received on control endpoint.
 589  */
 590 static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
 591                                         struct usb_ctrlrequest *ctrl)
 592 {
 593         struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
 594         struct s3c_hsudc_req hsreq;
 595         struct s3c_hsudc_ep *hsep;
 596         __le16 reply;
 597         u8 epnum;
 598
 599         switch (ctrl->bRequestType & USB_RECIP_MASK) {
 600         case USB_RECIP_DEVICE:
 601                 reply = cpu_to_le16(0);
 602                 break;
 603
 604         case USB_RECIP_INTERFACE:
 605                 reply = cpu_to_le16(0);
 606                 break;
 607
 608         case USB_RECIP_ENDPOINT:
 609                 epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
 610                 hsep = &hsudc->ep[epnum];
 611                 reply = cpu_to_le16(hsep->stopped ? 1 : 0);
 612                 break;
 613         }
 614
 615         INIT_LIST_HEAD(&hsreq.queue);
 616         hsreq.req.length = 2;
 617         hsreq.req.buf = &reply;
 618         hsreq.req.actual = 0;
 619         hsreq.req.complete = NULL;
 620         s3c_hsudc_write_fifo(hsep0, &hsreq);
 621 }
 622
 623 /**
 624  * s3c_hsudc_process_setup - Process control request received on endpoint 0.
 625  * @hsudc: Device controller on which control request has been received.
 626  *
 627  * Read the control request received on endpoint 0, decode it and handle
 628  * the request.
 629  */
 630 static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
 631 {
 632         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 633         struct usb_ctrlrequest ctrl = {0};
 634         int ret;
 635
 636         s3c_hsudc_nuke_ep(hsep, -EPROTO);
 637         s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
 638
 639         if (ctrl.bRequestType & USB_DIR_IN) {
 640                 hsep->bEndpointAddress |= USB_DIR_IN;
 641                 hsudc->ep0state = DATA_STATE_XMIT;
 642         } else {
 643                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 644                 hsudc->ep0state = DATA_STATE_RECV;
 645         }
 646
 647         switch (ctrl.bRequest) {
 648         case USB_REQ_SET_ADDRESS:
 649                 if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
 650                         break;
 651                 hsudc->ep0state = WAIT_FOR_SETUP;
 652                 return;
 653
 654         case USB_REQ_GET_STATUS:
 655                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 656                         break;
 657                 s3c_hsudc_process_req_status(hsudc, &ctrl);
 658                 return;
 659
 660         case USB_REQ_SET_FEATURE:
 661         case USB_REQ_CLEAR_FEATURE:
 662                 if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
 663                         break;
 664                 s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
 665                 hsudc->ep0state = WAIT_FOR_SETUP;
 666                 return;
 667         }
 668
 669         if (hsudc->driver) {
 670                 spin_unlock(&hsudc->lock);
 671                 ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
 672                 spin_lock(&hsudc->lock);
 673
 674                 if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
 675                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 676                         hsudc->ep0state = WAIT_FOR_SETUP;
 677                 }
 678
 679                 if (ret < 0) {
 680                         dev_err(hsudc->dev, "setup failed, returned %d\n",
 681                                                 ret);
 682                         s3c_hsudc_set_halt(&hsep->ep, 1);
 683                         hsudc->ep0state = WAIT_FOR_SETUP;
 684                         hsep->bEndpointAddress &= ~USB_DIR_IN;
 685                 }
 686         }
 687 }
 688
 689 /** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
 690  * @hsudc: Device controller on which endpoint 0 interrupt has occured.
 691  *
 692  * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
 693  * when a stall handshake is sent to host or data is sent/received on
 694  * endpoint 0.
 695  */
 696 static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
 697 {
 698         struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
 699         struct s3c_hsudc_req *hsreq;
 700         u32 csr = readl(hsudc->regs + S3C_EP0SR);
 701         u32 ecr;
 702
 703         if (csr & S3C_EP0SR_STALL) {
 704                 ecr = readl(hsudc->regs + S3C_EP0CR);
 705                 ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
 706                 writel(ecr, hsudc->regs + S3C_EP0CR);
 707
 708                 writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
 709                 hsep->stopped = 0;
 710
 711                 s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
 712                 hsudc->ep0state = WAIT_FOR_SETUP;
 713                 hsep->bEndpointAddress &= ~USB_DIR_IN;
 714                 return;
 715         }
 716
 717         if (csr & S3C_EP0SR_TX_SUCCESS) {
 718                 writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
 719                 if (ep_is_in(hsep)) {
 720                         if (list_empty(&hsep->queue))
 721                                 return;
 722
 723                         hsreq = list_entry(hsep->queue.next,
 724                                         struct s3c_hsudc_req, queue);
 725                         s3c_hsudc_write_fifo(hsep, hsreq);
 726                 }
 727         }
 728
 729         if (csr & S3C_EP0SR_RX_SUCCESS) {
 730                 if (hsudc->ep0state == WAIT_FOR_SETUP)
 731                         s3c_hsudc_process_setup(hsudc);
 732                 else {
 733                         if (!ep_is_in(hsep)) {
 734                                 if (list_empty(&hsep->queue))
 735                                         return;
 736                                 hsreq = list_entry(hsep->queue.next,
 737                                         struct s3c_hsudc_req, queue);
 738                                 s3c_hsudc_read_fifo(hsep, hsreq);
 739                         }
 740                 }
 741         }
 742 }
 743
 744 /**
 745  * s3c_hsudc_ep_enable - Enable a endpoint.
 746  * @_ep: The endpoint to be enabled.
 747  * @desc: Endpoint descriptor.
 748  *
 749  * Enables a endpoint when called from the gadget driver. Endpoint stall if
 750  * any is cleared, transfer type is configured and endpoint interrupt is
 751  * enabled.
 752  */
 753 static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
 754                                 const struct usb_endpoint_descriptor *desc)
 755 {
 756         struct s3c_hsudc_ep *hsep;
 757         struct s3c_hsudc *hsudc;
 758         unsigned long flags;
 759         u32 ecr = 0;
 760
 761         hsep = our_ep(_ep);
 762         if (!_ep || !desc || _ep->name == ep0name
 763                 || desc->bDescriptorType != USB_DT_ENDPOINT
 764                 || hsep->bEndpointAddress != desc->bEndpointAddress
 765                 || ep_maxpacket(hsep) < usb_endpoint_maxp(desc))
 766                 return -EINVAL;
 767
 768         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 769                 && usb_endpoint_maxp(desc) != ep_maxpacket(hsep))
 770                 || !desc->wMaxPacketSize)
 771                 return -ERANGE;
 772
 773         hsudc = hsep->dev;
 774         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 775                 return -ESHUTDOWN;
 776
 777         spin_lock_irqsave(&hsudc->lock, flags);
 778
 779         set_index(hsudc, hsep->bEndpointAddress);
 780         ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
 781         writel(ecr, hsudc->regs + S3C_ECR);
 782
 783         hsep->stopped = hsep->wedge = 0;
 784         hsep->ep.desc = desc;
 785         hsep->ep.maxpacket = usb_endpoint_maxp(desc);
 786
 787         s3c_hsudc_set_halt(_ep, 0);
 788         __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 789
 790         spin_unlock_irqrestore(&hsudc->lock, flags);
 791         return 0;
 792 }
 793
 794 /**
 795  * s3c_hsudc_ep_disable - Disable a endpoint.
 796  * @_ep: The endpoint to be disabled.
 797  * @desc: Endpoint descriptor.
 798  *
 799  * Disables a endpoint when called from the gadget driver.
 800  */
 801 static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
 802 {
 803         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 804         struct s3c_hsudc *hsudc = hsep->dev;
 805         unsigned long flags;
 806
 807         if (!_ep || !hsep->ep.desc)
 808                 return -EINVAL;
 809
 810         spin_lock_irqsave(&hsudc->lock, flags);
 811
 812         set_index(hsudc, hsep->bEndpointAddress);
 813         __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
 814
 815         s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
 816
 817         hsep->ep.desc = NULL;
 818         hsep->stopped = 1;
 819
 820         spin_unlock_irqrestore(&hsudc->lock, flags);
 821         return 0;
 822 }
 823
 824 /**
 825  * s3c_hsudc_alloc_request - Allocate a new request.
 826  * @_ep: Endpoint for which request is allocated (not used).
 827  * @gfp_flags: Flags used for the allocation.
 828  *
 829  * Allocates a single transfer request structure when called from gadget driver.
 830  */
 831 static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
 832                                                 gfp_t gfp_flags)
 833 {
 834         struct s3c_hsudc_req *hsreq;
 835
 836         hsreq = kzalloc(sizeof(*hsreq), gfp_flags);
 837         if (!hsreq)
 838                 return NULL;
 839
 840         INIT_LIST_HEAD(&hsreq->queue);
 841         return &hsreq->req;
 842 }
 843
 844 /**
 845  * s3c_hsudc_free_request - Deallocate a request.
 846  * @ep: Endpoint for which request is deallocated (not used).
 847  * @_req: Request to be deallocated.
 848  *
 849  * Allocates a single transfer request structure when called from gadget driver.
 850  */
 851 static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
 852 {
 853         struct s3c_hsudc_req *hsreq;
 854
 855         hsreq = our_req(_req);
 856         WARN_ON(!list_empty(&hsreq->queue));
 857         kfree(hsreq);
 858 }
 859
 860 /**
 861  * s3c_hsudc_queue - Queue a transfer request for the endpoint.
 862  * @_ep: Endpoint for which the request is queued.
 863  * @_req: Request to be queued.
 864  * @gfp_flags: Not used.
 865  *
 866  * Start or enqueue a request for a endpoint when called from gadget driver.
 867  */
 868 static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
 869                         gfp_t gfp_flags)
 870 {
 871         struct s3c_hsudc_req *hsreq;
 872         struct s3c_hsudc_ep *hsep;
 873         struct s3c_hsudc *hsudc;
 874         unsigned long flags;
 875         u32 offset;
 876         u32 csr;
 877
 878         hsreq = our_req(_req);
 879         if ((!_req || !_req->complete || !_req->buf ||
 880                 !list_empty(&hsreq->queue)))
 881                 return -EINVAL;
 882
 883         hsep = our_ep(_ep);
 884         hsudc = hsep->dev;
 885         if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
 886                 return -ESHUTDOWN;
 887
 888         spin_lock_irqsave(&hsudc->lock, flags);
 889         set_index(hsudc, hsep->bEndpointAddress);
 890
 891         _req->status = -EINPROGRESS;
 892         _req->actual = 0;
 893
 894         if (!ep_index(hsep) && _req->length == 0) {
 895                 hsudc->ep0state = WAIT_FOR_SETUP;
 896                 s3c_hsudc_complete_request(hsep, hsreq, 0);
 897                 spin_unlock_irqrestore(&hsudc->lock, flags);
 898                 return 0;
 899         }
 900
 901         if (list_empty(&hsep->queue) && !hsep->stopped) {
 902                 offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
 903                 if (ep_is_in(hsep)) {
 904                         csr = readl(hsudc->regs + offset);
 905                         if (!(csr & S3C_ESR_TX_SUCCESS) &&
 906                                 (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
 907                                 hsreq = NULL;
 908                 } else {
 909                         csr = readl(hsudc->regs + offset);
 910                         if ((csr & S3C_ESR_RX_SUCCESS)
 911                                    && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
 912                                 hsreq = NULL;
 913                 }
 914         }
 915
 916         if (hsreq)
 917                 list_add_tail(&hsreq->queue, &hsep->queue);
 918
 919         spin_unlock_irqrestore(&hsudc->lock, flags);
 920         return 0;
 921 }
 922
 923 /**
 924  * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
 925  * @_ep: Endpoint from which the request is dequeued.
 926  * @_req: Request to be dequeued.
 927  *
 928  * Dequeue a request from a endpoint when called from gadget driver.
 929  */
 930 static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 931 {
 932         struct s3c_hsudc_ep *hsep = our_ep(_ep);
 933         struct s3c_hsudc *hsudc = hsep->dev;
 934         struct s3c_hsudc_req *hsreq;
 935         unsigned long flags;
 936
 937         hsep = our_ep(_ep);
 938         if (!_ep || hsep->ep.name == ep0name)
 939                 return -EINVAL;
 940
 941         spin_lock_irqsave(&hsudc->lock, flags);
 942
 943         list_for_each_entry(hsreq, &hsep->queue, queue) {
 944                 if (&hsreq->req == _req)
 945                         break;
 946         }
 947         if (&hsreq->req != _req) {
 948                 spin_unlock_irqrestore(&hsudc->lock, flags);
 949                 return -EINVAL;
 950         }
 951
 952         set_index(hsudc, hsep->bEndpointAddress);
 953         s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
 954
 955         spin_unlock_irqrestore(&hsudc->lock, flags);
 956         return 0;
 957 }
 958
 959 static struct usb_ep_ops s3c_hsudc_ep_ops = {
 960         .enable = s3c_hsudc_ep_enable,
 961         .disable = s3c_hsudc_ep_disable,
 962         .alloc_request = s3c_hsudc_alloc_request,
 963         .free_request = s3c_hsudc_free_request,
 964         .queue = s3c_hsudc_queue,
 965         .dequeue = s3c_hsudc_dequeue,
 966         .set_halt = s3c_hsudc_set_halt,
 967         .set_wedge = s3c_hsudc_set_wedge,
 968 };
 969
 970 /**
 971  * s3c_hsudc_initep - Initialize a endpoint to default state.
 972  * @hsudc - Reference to the device controller.
 973  * @hsep - Endpoint to be initialized.
 974  * @epnum - Address to be assigned to the endpoint.
 975  *
 976  * Initialize a endpoint with default configuration.
 977  */
 978 static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
 979                                 struct s3c_hsudc_ep *hsep, int epnum)
 980 {
 981         char *dir;
 982
 983         if ((epnum % 2) == 0) {
 984                 dir = "out";
 985         } else {
 986                 dir = "in";
 987                 hsep->bEndpointAddress = USB_DIR_IN;
 988         }
 989
 990         hsep->bEndpointAddress |= epnum;
 991         if (epnum)
 992                 snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
 993         else
 994                 snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
 995
 996         INIT_LIST_HEAD(&hsep->queue);
 997         INIT_LIST_HEAD(&hsep->ep.ep_list);
 998         if (epnum)
 999                 list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
1000
1001         hsep->dev = hsudc;
1002         hsep->ep.name = hsep->name;
1003         hsep->ep.maxpacket = epnum ? 512 : 64;
1004         hsep->ep.ops = &s3c_hsudc_ep_ops;
1005         hsep->fifo = hsudc->regs + S3C_BR(epnum);
1006         hsep->ep.desc = NULL;
1007         hsep->stopped = 0;
1008         hsep->wedge = 0;
1009
1010         set_index(hsudc, epnum);
1011         writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
1012 }
1013
1014 /**
1015  * s3c_hsudc_setup_ep - Configure all endpoints to default state.
1016  * @hsudc: Reference to device controller.
1017  *
1018  * Configures all endpoints to default state.
1019  */
1020 static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
1021 {
1022         int epnum;
1023
1024         hsudc->ep0state = WAIT_FOR_SETUP;
1025         INIT_LIST_HEAD(&hsudc->gadget.ep_list);
1026         for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
1027                 s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
1028 }
1029
1030 /**
1031  * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
1032  * @hsudc: Reference to device controller.
1033  *
1034  * Reconfigures the device controller registers to a default state.
1035  */
1036 static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
1037 {
1038         writel(0xAA, hsudc->regs + S3C_EDR);
1039         writel(1, hsudc->regs + S3C_EIER);
1040         writel(0, hsudc->regs + S3C_TR);
1041         writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
1042                         S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
1043         writel(0, hsudc->regs + S3C_EP0CR);
1044
1045         s3c_hsudc_setup_ep(hsudc);
1046 }
1047
1048 /**
1049  * s3c_hsudc_irq - Interrupt handler for device controller.
1050  * @irq: Not used.
1051  * @_dev: Reference to the device controller.
1052  *
1053  * Interrupt handler for the device controller. This handler handles controller
1054  * interrupts and endpoint interrupts.
1055  */
1056 static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
1057 {
1058         struct s3c_hsudc *hsudc = _dev;
1059         struct s3c_hsudc_ep *hsep;
1060         u32 ep_intr;
1061         u32 sys_status;
1062         u32 ep_idx;
1063
1064         spin_lock(&hsudc->lock);
1065
1066         sys_status = readl(hsudc->regs + S3C_SSR);
1067         ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
1068
1069         if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
1070                 spin_unlock(&hsudc->lock);
1071                 return IRQ_HANDLED;
1072         }
1073
1074         if (sys_status) {
1075                 if (sys_status & S3C_SSR_VBUSON)
1076                         writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
1077
1078                 if (sys_status & S3C_SSR_ERR)
1079                         writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
1080
1081                 if (sys_status & S3C_SSR_SDE) {
1082                         writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
1083                         hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
1084                                 USB_SPEED_HIGH : USB_SPEED_FULL;
1085                 }
1086
1087                 if (sys_status & S3C_SSR_SUSPEND) {
1088                         writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
1089                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1090                                 && hsudc->driver && hsudc->driver->suspend)
1091                                 hsudc->driver->suspend(&hsudc->gadget);
1092                 }
1093
1094                 if (sys_status & S3C_SSR_RESUME) {
1095                         writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
1096                         if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
1097                                 && hsudc->driver && hsudc->driver->resume)
1098                                 hsudc->driver->resume(&hsudc->gadget);
1099                 }
1100
1101                 if (sys_status & S3C_SSR_RESET) {
1102                         writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
1103                         for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
1104                                 hsep = &hsudc->ep[ep_idx];
1105                                 hsep->stopped = 1;
1106                                 s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
1107                         }
1108                         s3c_hsudc_reconfig(hsudc);
1109                         hsudc->ep0state = WAIT_FOR_SETUP;
1110                 }
1111         }
1112
1113         if (ep_intr & S3C_EIR_EP0) {
1114                 writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
1115                 set_index(hsudc, 0);
1116                 s3c_hsudc_handle_ep0_intr(hsudc);
1117         }
1118
1119         ep_intr >>= 1;
1120         ep_idx = 1;
1121         while (ep_intr) {
1122                 if (ep_intr & 1)  {
1123                         hsep = &hsudc->ep[ep_idx];
1124                         set_index(hsudc, ep_idx);
1125                         writel(1 << ep_idx, hsudc->regs + S3C_EIR);
1126                         if (ep_is_in(hsep))
1127                                 s3c_hsudc_epin_intr(hsudc, ep_idx);
1128                         else
1129                                 s3c_hsudc_epout_intr(hsudc, ep_idx);
1130                 }
1131                 ep_intr >>= 1;
1132                 ep_idx++;
1133         }
1134
1135         spin_unlock(&hsudc->lock);
1136         return IRQ_HANDLED;
1137 }
1138
1139 static int s3c_hsudc_start(struct usb_gadget *gadget,
1140                 struct usb_gadget_driver *driver)
1141 {
1142         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1143         int ret;
1144
1145         if (!driver
1146                 || driver->max_speed < USB_SPEED_FULL
1147                 || !driver->setup)
1148                 return -EINVAL;
1149
1150         if (!hsudc)
1151                 return -ENODEV;
1152
1153         if (hsudc->driver)
1154                 return -EBUSY;
1155
1156         hsudc->driver = driver;
1157         hsudc->gadget.dev.driver = &driver->driver;
1158
1159         ret = regulator_bulk_enable(ARRAY_SIZE(hsudc->supplies),
1160                                     hsudc->supplies);
1161         if (ret != 0) {
1162                 dev_err(hsudc->dev, "failed to enable supplies: %d\n", ret);
1163                 goto err_supplies;
1164         }
1165
1166         /* connect to bus through transceiver */
1167         if (!IS_ERR_OR_NULL(hsudc->transceiver)) {
1168                 ret = otg_set_peripheral(hsudc->transceiver->otg,
1169                                         &hsudc->gadget);
1170                 if (ret) {
1171                         dev_err(hsudc->dev, "%s: can't bind to transceiver\n",
1172                                         hsudc->gadget.name);
1173                         goto err_otg;
1174                 }
1175         }
1176
1177         enable_irq(hsudc->irq);
1178         dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
1179
1180         s3c_hsudc_reconfig(hsudc);
1181
1182         pm_runtime_get_sync(hsudc->dev);
1183
1184         s3c_hsudc_init_phy();
1185         if (hsudc->pd->gpio_init)
1186                 hsudc->pd->gpio_init();
1187
1188         return 0;
1189 err_otg:
1190         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1191 err_supplies:
1192         hsudc->driver = NULL;
1193         hsudc->gadget.dev.driver = NULL;
1194         return ret;
1195 }
1196
1197 static int s3c_hsudc_stop(struct usb_gadget *gadget,
1198                 struct usb_gadget_driver *driver)
1199 {
1200         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1201         unsigned long flags;
1202
1203         if (!hsudc)
1204                 return -ENODEV;
1205
1206         if (!driver || driver != hsudc->driver)
1207                 return -EINVAL;
1208
1209         spin_lock_irqsave(&hsudc->lock, flags);
1210         hsudc->driver = NULL;
1211         hsudc->gadget.dev.driver = NULL;
1212         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1213         s3c_hsudc_uninit_phy();
1214
1215         pm_runtime_put(hsudc->dev);
1216
1217         if (hsudc->pd->gpio_uninit)
1218                 hsudc->pd->gpio_uninit();
1219         s3c_hsudc_stop_activity(hsudc);
1220         spin_unlock_irqrestore(&hsudc->lock, flags);
1221
1222         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1223                 (void) otg_set_peripheral(hsudc->transceiver->otg, NULL);
1224
1225         disable_irq(hsudc->irq);
1226
1227         regulator_bulk_disable(ARRAY_SIZE(hsudc->supplies), hsudc->supplies);
1228
1229         dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
1230                         driver->driver.name);
1231         return 0;
1232 }
1233
1234 static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
1235 {
1236         return readl(hsudc->regs + S3C_FNR) & 0x3FF;
1237 }
1238
1239 static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
1240 {
1241         return s3c_hsudc_read_frameno(to_hsudc(gadget));
1242 }
1243
1244 static int s3c_hsudc_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1245 {
1246         struct s3c_hsudc *hsudc = to_hsudc(gadget);
1247
1248         if (!hsudc)
1249                 return -ENODEV;
1250
1251         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1252                 return usb_phy_set_power(hsudc->transceiver, mA);
1253
1254         return -EOPNOTSUPP;
1255 }
1256
1257 static const struct usb_gadget_ops s3c_hsudc_gadget_ops = {
1258         .get_frame      = s3c_hsudc_gadget_getframe,
1259         .udc_start      = s3c_hsudc_start,
1260         .udc_stop       = s3c_hsudc_stop,
1261         .vbus_draw      = s3c_hsudc_vbus_draw,
1262 };
1263
1264 static int s3c_hsudc_probe(struct platform_device *pdev)
1265 {
1266         struct device *dev = &pdev->dev;
1267         struct resource *res;
1268         struct s3c_hsudc *hsudc;
1269         struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
1270         int ret, i;
1271
1272         hsudc = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsudc) +
1273                         sizeof(struct s3c_hsudc_ep) * pd->epnum,
1274                         GFP_KERNEL);
1275         if (!hsudc) {
1276                 dev_err(dev, "cannot allocate memory\n");
1277                 return -ENOMEM;
1278         }
1279
1280         platform_set_drvdata(pdev, dev);
1281         hsudc->dev = dev;
1282         hsudc->pd = pdev->dev.platform_data;
1283
1284         hsudc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
1285
1286         for (i = 0; i < ARRAY_SIZE(hsudc->supplies); i++)
1287                 hsudc->supplies[i].supply = s3c_hsudc_supply_names[i];
1288
1289         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsudc->supplies),
1290                                  hsudc->supplies);
1291         if (ret != 0) {
1292                 dev_err(dev, "failed to request supplies: %d\n", ret);
1293                 goto err_supplies;
1294         }
1295
1296         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297
1298         hsudc->regs = devm_ioremap_resource(&pdev->dev, res);
1299         if (IS_ERR(hsudc->regs)) {
1300                 ret = PTR_ERR(hsudc->regs);
1301                 goto err_res;
1302         }
1303
1304         spin_lock_init(&hsudc->lock);
1305
1306         dev_set_name(&hsudc->gadget.dev, "gadget");
1307
1308         hsudc->gadget.max_speed = USB_SPEED_HIGH;
1309         hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
1310         hsudc->gadget.name = dev_name(dev);
1311         hsudc->gadget.dev.parent = dev;
1312         hsudc->gadget.dev.dma_mask = dev->dma_mask;
1313         hsudc->gadget.ep0 = &hsudc->ep[0].ep;
1314
1315         hsudc->gadget.is_otg = 0;
1316         hsudc->gadget.is_a_peripheral = 0;
1317         hsudc->gadget.speed = USB_SPEED_UNKNOWN;
1318
1319         s3c_hsudc_setup_ep(hsudc);
1320
1321         ret = platform_get_irq(pdev, 0);
1322         if (ret < 0) {
1323                 dev_err(dev, "unable to obtain IRQ number\n");
1324                 goto err_res;
1325         }
1326         hsudc->irq = ret;
1327
1328         ret = devm_request_irq(&pdev->dev, hsudc->irq, s3c_hsudc_irq, 0,
1329                                 driver_name, hsudc);
1330         if (ret < 0) {
1331                 dev_err(dev, "irq request failed\n");
1332                 goto err_res;
1333         }
1334
1335         hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device");
1336         if (IS_ERR(hsudc->uclk)) {
1337                 dev_err(dev, "failed to find usb-device clock source\n");
1338                 ret = PTR_ERR(hsudc->uclk);
1339                 goto err_res;
1340         }
1341         clk_enable(hsudc->uclk);
1342
1343         local_irq_disable();
1344
1345         disable_irq(hsudc->irq);
1346         local_irq_enable();
1347
1348         ret = device_register(&hsudc->gadget.dev);
1349         if (ret) {
1350                 put_device(&hsudc->gadget.dev);
1351                 goto err_add_device;
1352         }
1353
1354         ret = usb_add_gadget_udc(&pdev->dev, &hsudc->gadget);
1355         if (ret)
1356                 goto err_add_udc;
1357
1358         pm_runtime_enable(dev);
1359
1360         return 0;
1361 err_add_udc:
1362         device_unregister(&hsudc->gadget.dev);
1363 err_add_device:
1364         clk_disable(hsudc->uclk);
1365 err_res:
1366         if (!IS_ERR_OR_NULL(hsudc->transceiver))
1367                 usb_put_phy(hsudc->transceiver);
1368
1369 err_supplies:
1370         return ret;
1371 }
1372
1373 static struct platform_driver s3c_hsudc_driver = {
1374         .driver         = {
1375                 .owner  = THIS_MODULE,
1376                 .name   = "s3c-hsudc",
1377         },
1378         .probe          = s3c_hsudc_probe,
1379 };
1380
1381 module_platform_driver(s3c_hsudc_driver);
1382
1383 MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
1384 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1385 MODULE_LICENSE("GPL");
1386 MODULE_ALIAS("platform:s3c-hsudc");