Pileus Git - ~andy/linux/blob - drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #undef  DEBUG
  16 #undef  VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/timer.h>
  26 #include <linux/list.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/mm.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/clk.h>
  37 #include <linux/err.h>
  38 #include <linux/prefetch.h>
  39 #include <linux/io.h>
  40
  41 #include <asm/byteorder.h>
  42 #include <asm/irq.h>
  43 #include <asm/unaligned.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <linux/omap-dma.h>
  47
  48 #include <mach/usb.h>
  49
  50 #include "omap_udc.h"
  51
  52 #undef  USB_TRACE
  53
  54 /* bulk DMA seems to be behaving for both IN and OUT */
  55 #define USE_DMA
  56
  57 /* ISO too */
  58 #define USE_ISO
  59
  60 #define DRIVER_DESC     "OMAP UDC driver"
  61 #define DRIVER_VERSION  "4 October 2004"
  62
  63 #define OMAP_DMA_USB_W2FC_TX0           29
  64 #define OMAP_DMA_USB_W2FC_RX0           26
  65
  66 /*
  67  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  68  * D+ pullup to allow enumeration.  That's too early for the gadget
  69  * framework to use from usb_endpoint_enable(), which happens after
  70  * enumeration as part of activating an interface.  (But if we add an
  71  * optional new "UDC not yet running" state to the gadget driver model,
  72  * even just during driver binding, the endpoint autoconfig logic is the
  73  * natural spot to manufacture new endpoints.)
  74  *
  75  * So instead of using endpoint enable calls to control the hardware setup,
  76  * this driver defines a "fifo mode" parameter.  It's used during driver
  77  * initialization to choose among a set of pre-defined endpoint configs.
  78  * See omap_udc_setup() for available modes, or to add others.  That code
  79  * lives in an init section, so use this driver as a module if you need
  80  * to change the fifo mode after the kernel boots.
  81  *
  82  * Gadget drivers normally ignore endpoints they don't care about, and
  83  * won't include them in configuration descriptors.  That means only
  84  * misbehaving hosts would even notice they exist.
  85  */
  86 #ifdef  USE_ISO
  87 static unsigned fifo_mode = 3;
  88 #else
  89 static unsigned fifo_mode;
  90 #endif
  91
  92 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
  93  * boot parameter "omap_udc:fifo_mode=42"
  94  */
  95 module_param(fifo_mode, uint, 0);
  96 MODULE_PARM_DESC(fifo_mode, "endpoint configuration");
  97
  98 #ifdef  USE_DMA
  99 static bool use_dma = 1;
 100
 101 /* "modprobe omap_udc use_dma=y", or else as a kernel
 102  * boot parameter "omap_udc:use_dma=y"
 103  */
 104 module_param(use_dma, bool, 0);
 105 MODULE_PARM_DESC(use_dma, "enable/disable DMA");
 106 #else   /* !USE_DMA */
 107
 108 /* save a bit of code */
 109 #define use_dma         0
 110 #endif  /* !USE_DMA */
 111
 112
 113 static const char driver_name[] = "omap_udc";
 114 static const char driver_desc[] = DRIVER_DESC;
 115
 116 /*-------------------------------------------------------------------------*/
 117
 118 /* there's a notion of "current endpoint" for modifying endpoint
 119  * state, and PIO access to its FIFO.
 120  */
 121
 122 static void use_ep(struct omap_ep *ep, u16 select)
 123 {
 124         u16     num = ep->bEndpointAddress & 0x0f;
 125
 126         if (ep->bEndpointAddress & USB_DIR_IN)
 127                 num |= UDC_EP_DIR;
 128         omap_writew(num | select, UDC_EP_NUM);
 129         /* when select, MUST deselect later !! */
 130 }
 131
 132 static inline void deselect_ep(void)
 133 {
 134         u16 w;
 135
 136         w = omap_readw(UDC_EP_NUM);
 137         w &= ~UDC_EP_SEL;
 138         omap_writew(w, UDC_EP_NUM);
 139         /* 6 wait states before TX will happen */
 140 }
 141
 142 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 143
 144 /*-------------------------------------------------------------------------*/
 145
 146 static int omap_ep_enable(struct usb_ep *_ep,
 147                 const struct usb_endpoint_descriptor *desc)
 148 {
 149         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 150         struct omap_udc *udc;
 151         unsigned long   flags;
 152         u16             maxp;
 153
 154         /* catch various bogus parameters */
 155         if (!_ep || !desc
 156                         || desc->bDescriptorType != USB_DT_ENDPOINT
 157                         || ep->bEndpointAddress != desc->bEndpointAddress
 158                         || ep->maxpacket < usb_endpoint_maxp(desc)) {
 159                 DBG("%s, bad ep or descriptor\n", __func__);
 160                 return -EINVAL;
 161         }
 162         maxp = usb_endpoint_maxp(desc);
 163         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 164                                 && maxp != ep->maxpacket)
 165                         || usb_endpoint_maxp(desc) > ep->maxpacket
 166                         || !desc->wMaxPacketSize) {
 167                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 168                 return -ERANGE;
 169         }
 170
 171 #ifdef  USE_ISO
 172         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 173                                 && desc->bInterval != 1)) {
 174                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 175                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 176                                 1 << (desc->bInterval - 1));
 177                 return -EDOM;
 178         }
 179 #else
 180         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 181                 DBG("%s, ISO nyet\n", _ep->name);
 182                 return -EDOM;
 183         }
 184 #endif
 185
 186         /* xfer types must match, except that interrupt ~= bulk */
 187         if (ep->bmAttributes != desc->bmAttributes
 188                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 189                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 190                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 191                 return -EINVAL;
 192         }
 193
 194         udc = ep->udc;
 195         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 196                 DBG("%s, bogus device state\n", __func__);
 197                 return -ESHUTDOWN;
 198         }
 199
 200         spin_lock_irqsave(&udc->lock, flags);
 201
 202         ep->ep.desc = desc;
 203         ep->irqs = 0;
 204         ep->stopped = 0;
 205         ep->ep.maxpacket = maxp;
 206
 207         /* set endpoint to initial state */
 208         ep->dma_channel = 0;
 209         ep->has_dma = 0;
 210         ep->lch = -1;
 211         use_ep(ep, UDC_EP_SEL);
 212         omap_writew(udc->clr_halt, UDC_CTRL);
 213         ep->ackwait = 0;
 214         deselect_ep();
 215
 216         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 217                 list_add(&ep->iso, &udc->iso);
 218
 219         /* maybe assign a DMA channel to this endpoint */
 220         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 221                 /* FIXME ISO can dma, but prefers first channel */
 222                 dma_channel_claim(ep, 0);
 223
 224         /* PIO OUT may RX packets */
 225         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 226                         && !ep->has_dma
 227                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 228                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 229                 ep->ackwait = 1 + ep->double_buf;
 230         }
 231
 232         spin_unlock_irqrestore(&udc->lock, flags);
 233         VDBG("%s enabled\n", _ep->name);
 234         return 0;
 235 }
 236
 237 static void nuke(struct omap_ep *, int status);
 238
 239 static int omap_ep_disable(struct usb_ep *_ep)
 240 {
 241         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 242         unsigned long   flags;
 243
 244         if (!_ep || !ep->ep.desc) {
 245                 DBG("%s, %s not enabled\n", __func__,
 246                         _ep ? ep->ep.name : NULL);
 247                 return -EINVAL;
 248         }
 249
 250         spin_lock_irqsave(&ep->udc->lock, flags);
 251         ep->ep.desc = NULL;
 252         nuke(ep, -ESHUTDOWN);
 253         ep->ep.maxpacket = ep->maxpacket;
 254         ep->has_dma = 0;
 255         omap_writew(UDC_SET_HALT, UDC_CTRL);
 256         list_del_init(&ep->iso);
 257         del_timer(&ep->timer);
 258
 259         spin_unlock_irqrestore(&ep->udc->lock, flags);
 260
 261         VDBG("%s disabled\n", _ep->name);
 262         return 0;
 263 }
 264
 265 /*-------------------------------------------------------------------------*/
 266
 267 static struct usb_request *
 268 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 269 {
 270         struct omap_req *req;
 271
 272         req = kzalloc(sizeof(*req), gfp_flags);
 273         if (!req)
 274                 return NULL;
 275
 276         INIT_LIST_HEAD(&req->queue);
 277
 278         return &req->req;
 279 }
 280
 281 static void
 282 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 283 {
 284         struct omap_req *req = container_of(_req, struct omap_req, req);
 285
 286         kfree(req);
 287 }
 288
 289 /*-------------------------------------------------------------------------*/
 290
 291 static void
 292 done(struct omap_ep *ep, struct omap_req *req, int status)
 293 {
 294         struct omap_udc         *udc = ep->udc;
 295         unsigned                stopped = ep->stopped;
 296
 297         list_del_init(&req->queue);
 298
 299         if (req->req.status == -EINPROGRESS)
 300                 req->req.status = status;
 301         else
 302                 status = req->req.status;
 303
 304         if (use_dma && ep->has_dma)
 305                 usb_gadget_unmap_request(&udc->gadget, &req->req,
 306                                 (ep->bEndpointAddress & USB_DIR_IN));
 307
 308 #ifndef USB_TRACE
 309         if (status && status != -ESHUTDOWN)
 310 #endif
 311                 VDBG("complete %s req %p stat %d len %u/%u\n",
 312                         ep->ep.name, &req->req, status,
 313                         req->req.actual, req->req.length);
 314
 315         /* don't modify queue heads during completion callback */
 316         ep->stopped = 1;
 317         spin_unlock(&ep->udc->lock);
 318         req->req.complete(&ep->ep, &req->req);
 319         spin_lock(&ep->udc->lock);
 320         ep->stopped = stopped;
 321 }
 322
 323 /*-------------------------------------------------------------------------*/
 324
 325 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 326 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 327
 328 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 329 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 330
 331 static inline int
 332 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 333 {
 334         unsigned        len;
 335         u16             *wp;
 336
 337         len = min(req->req.length - req->req.actual, max);
 338         req->req.actual += len;
 339
 340         max = len;
 341         if (likely((((int)buf) & 1) == 0)) {
 342                 wp = (u16 *)buf;
 343                 while (max >= 2) {
 344                         omap_writew(*wp++, UDC_DATA);
 345                         max -= 2;
 346                 }
 347                 buf = (u8 *)wp;
 348         }
 349         while (max--)
 350                 omap_writeb(*buf++, UDC_DATA);
 351         return len;
 352 }
 353
 354 /* FIXME change r/w fifo calling convention */
 355
 356
 357 /* return:  0 = still running, 1 = completed, negative = errno */
 358 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 359 {
 360         u8              *buf;
 361         unsigned        count;
 362         int             is_last;
 363         u16             ep_stat;
 364
 365         buf = req->req.buf + req->req.actual;
 366         prefetch(buf);
 367
 368         /* PIO-IN isn't double buffered except for iso */
 369         ep_stat = omap_readw(UDC_STAT_FLG);
 370         if (ep_stat & UDC_FIFO_UNWRITABLE)
 371                 return 0;
 372
 373         count = ep->ep.maxpacket;
 374         count = write_packet(buf, req, count);
 375         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 376         ep->ackwait = 1;
 377
 378         /* last packet is often short (sometimes a zlp) */
 379         if (count != ep->ep.maxpacket)
 380                 is_last = 1;
 381         else if (req->req.length == req->req.actual
 382                         && !req->req.zero)
 383                 is_last = 1;
 384         else
 385                 is_last = 0;
 386
 387         /* NOTE:  requests complete when all IN data is in a
 388          * FIFO (or sometimes later, if a zlp was needed).
 389          * Use usb_ep_fifo_status() where needed.
 390          */
 391         if (is_last)
 392                 done(ep, req, 0);
 393         return is_last;
 394 }
 395
 396 static inline int
 397 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 398 {
 399         unsigned        len;
 400         u16             *wp;
 401
 402         len = min(req->req.length - req->req.actual, avail);
 403         req->req.actual += len;
 404         avail = len;
 405
 406         if (likely((((int)buf) & 1) == 0)) {
 407                 wp = (u16 *)buf;
 408                 while (avail >= 2) {
 409                         *wp++ = omap_readw(UDC_DATA);
 410                         avail -= 2;
 411                 }
 412                 buf = (u8 *)wp;
 413         }
 414         while (avail--)
 415                 *buf++ = omap_readb(UDC_DATA);
 416         return len;
 417 }
 418
 419 /* return:  0 = still running, 1 = queue empty, negative = errno */
 420 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 421 {
 422         u8              *buf;
 423         unsigned        count, avail;
 424         int             is_last;
 425
 426         buf = req->req.buf + req->req.actual;
 427         prefetchw(buf);
 428
 429         for (;;) {
 430                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
 431
 432                 is_last = 0;
 433                 if (ep_stat & FIFO_EMPTY) {
 434                         if (!ep->double_buf)
 435                                 break;
 436                         ep->fnf = 1;
 437                 }
 438                 if (ep_stat & UDC_EP_HALTED)
 439                         break;
 440
 441                 if (ep_stat & UDC_FIFO_FULL)
 442                         avail = ep->ep.maxpacket;
 443                 else  {
 444                         avail = omap_readw(UDC_RXFSTAT);
 445                         ep->fnf = ep->double_buf;
 446                 }
 447                 count = read_packet(buf, req, avail);
 448
 449                 /* partial packet reads may not be errors */
 450                 if (count < ep->ep.maxpacket) {
 451                         is_last = 1;
 452                         /* overflowed this request?  flush extra data */
 453                         if (count != avail) {
 454                                 req->req.status = -EOVERFLOW;
 455                                 avail -= count;
 456                                 while (avail--)
 457                                         omap_readw(UDC_DATA);
 458                         }
 459                 } else if (req->req.length == req->req.actual)
 460                         is_last = 1;
 461                 else
 462                         is_last = 0;
 463
 464                 if (!ep->bEndpointAddress)
 465                         break;
 466                 if (is_last)
 467                         done(ep, req, 0);
 468                 break;
 469         }
 470         return is_last;
 471 }
 472
 473 /*-------------------------------------------------------------------------*/
 474
 475 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 476 {
 477         dma_addr_t      end;
 478
 479         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 480          * the last transfer's bytecount by more than a FIFO's worth.
 481          */
 482         if (cpu_is_omap15xx())
 483                 return 0;
 484
 485         end = omap_get_dma_src_pos(ep->lch);
 486         if (end == ep->dma_counter)
 487                 return 0;
 488
 489         end |= start & (0xffff << 16);
 490         if (end < start)
 491                 end += 0x10000;
 492         return end - start;
 493 }
 494
 495 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 496 {
 497         dma_addr_t      end;
 498
 499         end = omap_get_dma_dst_pos(ep->lch);
 500         if (end == ep->dma_counter)
 501                 return 0;
 502
 503         end |= start & (0xffff << 16);
 504         if (cpu_is_omap15xx())
 505                 end++;
 506         if (end < start)
 507                 end += 0x10000;
 508         return end - start;
 509 }
 510
 511
 512 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 513  * When DMA completion isn't request completion, the UDC continues with
 514  * the next DMA transfer for that USB transfer.
 515  */
 516
 517 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 518 {
 519         u16             txdma_ctrl, w;
 520         unsigned        length = req->req.length - req->req.actual;
 521         const int       sync_mode = cpu_is_omap15xx()
 522                                 ? OMAP_DMA_SYNC_FRAME
 523                                 : OMAP_DMA_SYNC_ELEMENT;
 524         int             dma_trigger = 0;
 525
 526         /* measure length in either bytes or packets */
 527         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 528                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 529                 txdma_ctrl = UDC_TXN_EOT | length;
 530                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 531                                 length, 1, sync_mode, dma_trigger, 0);
 532         } else {
 533                 length = min(length / ep->maxpacket,
 534                                 (unsigned) UDC_TXN_TSC + 1);
 535                 txdma_ctrl = length;
 536                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 537                                 ep->ep.maxpacket >> 1, length, sync_mode,
 538                                 dma_trigger, 0);
 539                 length *= ep->maxpacket;
 540         }
 541         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 542                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 543                 0, 0);
 544
 545         omap_start_dma(ep->lch);
 546         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 547         w = omap_readw(UDC_DMA_IRQ_EN);
 548         w |= UDC_TX_DONE_IE(ep->dma_channel);
 549         omap_writew(w, UDC_DMA_IRQ_EN);
 550         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 551         req->dma_bytes = length;
 552 }
 553
 554 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 555 {
 556         u16 w;
 557
 558         if (status == 0) {
 559                 req->req.actual += req->dma_bytes;
 560
 561                 /* return if this request needs to send data or zlp */
 562                 if (req->req.actual < req->req.length)
 563                         return;
 564                 if (req->req.zero
 565                                 && req->dma_bytes != 0
 566                                 && (req->req.actual % ep->maxpacket) == 0)
 567                         return;
 568         } else
 569                 req->req.actual += dma_src_len(ep, req->req.dma
 570                                                         + req->req.actual);
 571
 572         /* tx completion */
 573         omap_stop_dma(ep->lch);
 574         w = omap_readw(UDC_DMA_IRQ_EN);
 575         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 576         omap_writew(w, UDC_DMA_IRQ_EN);
 577         done(ep, req, status);
 578 }
 579
 580 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 581 {
 582         unsigned packets = req->req.length - req->req.actual;
 583         int dma_trigger = 0;
 584         u16 w;
 585
 586         /* set up this DMA transfer, enable the fifo, start */
 587         packets /= ep->ep.maxpacket;
 588         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 589         req->dma_bytes = packets * ep->ep.maxpacket;
 590         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 591                         ep->ep.maxpacket >> 1, packets,
 592                         OMAP_DMA_SYNC_ELEMENT,
 593                         dma_trigger, 0);
 594         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 595                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 596                 0, 0);
 597         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 598
 599         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 600         w = omap_readw(UDC_DMA_IRQ_EN);
 601         w |= UDC_RX_EOT_IE(ep->dma_channel);
 602         omap_writew(w, UDC_DMA_IRQ_EN);
 603         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 604         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 605
 606         omap_start_dma(ep->lch);
 607 }
 608
 609 static void
 610 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 611 {
 612         u16     count, w;
 613
 614         if (status == 0)
 615                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 616         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 617         count += req->req.actual;
 618         if (one)
 619                 count--;
 620         if (count <= req->req.length)
 621                 req->req.actual = count;
 622
 623         if (count != req->dma_bytes || status)
 624                 omap_stop_dma(ep->lch);
 625
 626         /* if this wasn't short, request may need another transfer */
 627         else if (req->req.actual < req->req.length)
 628                 return;
 629
 630         /* rx completion */
 631         w = omap_readw(UDC_DMA_IRQ_EN);
 632         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 633         omap_writew(w, UDC_DMA_IRQ_EN);
 634         done(ep, req, status);
 635 }
 636
 637 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 638 {
 639         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
 640         struct omap_ep  *ep;
 641         struct omap_req *req;
 642
 643         /* IN dma: tx to host */
 644         if (irq_src & UDC_TXN_DONE) {
 645                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 646                 ep->irqs++;
 647                 /* can see TXN_DONE after dma abort */
 648                 if (!list_empty(&ep->queue)) {
 649                         req = container_of(ep->queue.next,
 650                                                 struct omap_req, queue);
 651                         finish_in_dma(ep, req, 0);
 652                 }
 653                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 654
 655                 if (!list_empty(&ep->queue)) {
 656                         req = container_of(ep->queue.next,
 657                                         struct omap_req, queue);
 658                         next_in_dma(ep, req);
 659                 }
 660         }
 661
 662         /* OUT dma: rx from host */
 663         if (irq_src & UDC_RXN_EOT) {
 664                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 665                 ep->irqs++;
 666                 /* can see RXN_EOT after dma abort */
 667                 if (!list_empty(&ep->queue)) {
 668                         req = container_of(ep->queue.next,
 669                                         struct omap_req, queue);
 670                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 671                 }
 672                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 673
 674                 if (!list_empty(&ep->queue)) {
 675                         req = container_of(ep->queue.next,
 676                                         struct omap_req, queue);
 677                         next_out_dma(ep, req);
 678                 }
 679         }
 680
 681         if (irq_src & UDC_RXN_CNT) {
 682                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 683                 ep->irqs++;
 684                 /* omap15xx does this unasked... */
 685                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 686                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 687         }
 688 }
 689
 690 static void dma_error(int lch, u16 ch_status, void *data)
 691 {
 692         struct omap_ep  *ep = data;
 693
 694         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 695         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 696         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 697
 698         /* complete current transfer ... */
 699 }
 700
 701 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 702 {
 703         u16     reg;
 704         int     status, restart, is_in;
 705         int     dma_channel;
 706
 707         is_in = ep->bEndpointAddress & USB_DIR_IN;
 708         if (is_in)
 709                 reg = omap_readw(UDC_TXDMA_CFG);
 710         else
 711                 reg = omap_readw(UDC_RXDMA_CFG);
 712         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 713
 714         ep->dma_channel = 0;
 715         ep->lch = -1;
 716         if (channel == 0 || channel > 3) {
 717                 if ((reg & 0x0f00) == 0)
 718                         channel = 3;
 719                 else if ((reg & 0x00f0) == 0)
 720                         channel = 2;
 721                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 722                         channel = 1;
 723                 else {
 724                         status = -EMLINK;
 725                         goto just_restart;
 726                 }
 727         }
 728         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 729         ep->dma_channel = channel;
 730
 731         if (is_in) {
 732                 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 733                 status = omap_request_dma(dma_channel,
 734                         ep->ep.name, dma_error, ep, &ep->lch);
 735                 if (status == 0) {
 736                         omap_writew(reg, UDC_TXDMA_CFG);
 737                         /* EMIFF or SDRC */
 738                         omap_set_dma_src_burst_mode(ep->lch,
 739                                                 OMAP_DMA_DATA_BURST_4);
 740                         omap_set_dma_src_data_pack(ep->lch, 1);
 741                         /* TIPB */
 742                         omap_set_dma_dest_params(ep->lch,
 743                                 OMAP_DMA_PORT_TIPB,
 744                                 OMAP_DMA_AMODE_CONSTANT,
 745                                 UDC_DATA_DMA,
 746                                 0, 0);
 747                 }
 748         } else {
 749                 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 750                 status = omap_request_dma(dma_channel,
 751                         ep->ep.name, dma_error, ep, &ep->lch);
 752                 if (status == 0) {
 753                         omap_writew(reg, UDC_RXDMA_CFG);
 754                         /* TIPB */
 755                         omap_set_dma_src_params(ep->lch,
 756                                 OMAP_DMA_PORT_TIPB,
 757                                 OMAP_DMA_AMODE_CONSTANT,
 758                                 UDC_DATA_DMA,
 759                                 0, 0);
 760                         /* EMIFF or SDRC */
 761                         omap_set_dma_dest_burst_mode(ep->lch,
 762                                                 OMAP_DMA_DATA_BURST_4);
 763                         omap_set_dma_dest_data_pack(ep->lch, 1);
 764                 }
 765         }
 766         if (status)
 767                 ep->dma_channel = 0;
 768         else {
 769                 ep->has_dma = 1;
 770                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 771
 772                 /* channel type P: hw synch (fifo) */
 773                 if (!cpu_is_omap15xx())
 774                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 775         }
 776
 777 just_restart:
 778         /* restart any queue, even if the claim failed  */
 779         restart = !ep->stopped && !list_empty(&ep->queue);
 780
 781         if (status)
 782                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 783                         restart ? " (restart)" : "");
 784         else
 785                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 786                         is_in ? 't' : 'r',
 787                         ep->dma_channel - 1, ep->lch,
 788                         restart ? " (restart)" : "");
 789
 790         if (restart) {
 791                 struct omap_req *req;
 792                 req = container_of(ep->queue.next, struct omap_req, queue);
 793                 if (ep->has_dma)
 794                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 795                 else {
 796                         use_ep(ep, UDC_EP_SEL);
 797                         (is_in ? write_fifo : read_fifo)(ep, req);
 798                         deselect_ep();
 799                         if (!is_in) {
 800                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 801                                 ep->ackwait = 1 + ep->double_buf;
 802                         }
 803                         /* IN: 6 wait states before it'll tx */
 804                 }
 805         }
 806 }
 807
 808 static void dma_channel_release(struct omap_ep *ep)
 809 {
 810         int             shift = 4 * (ep->dma_channel - 1);
 811         u16             mask = 0x0f << shift;
 812         struct omap_req *req;
 813         int             active;
 814
 815         /* abort any active usb transfer request */
 816         if (!list_empty(&ep->queue))
 817                 req = container_of(ep->queue.next, struct omap_req, queue);
 818         else
 819                 req = NULL;
 820
 821         active = omap_get_dma_active_status(ep->lch);
 822
 823         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 824                         active ? "active" : "idle",
 825                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 826                         ep->dma_channel - 1, req);
 827
 828         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 829          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 830          */
 831
 832         /* wait till current packet DMA finishes, and fifo empties */
 833         if (ep->bEndpointAddress & USB_DIR_IN) {
 834                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 835                                         UDC_TXDMA_CFG);
 836
 837                 if (req) {
 838                         finish_in_dma(ep, req, -ECONNRESET);
 839
 840                         /* clear FIFO; hosts probably won't empty it */
 841                         use_ep(ep, UDC_EP_SEL);
 842                         omap_writew(UDC_CLR_EP, UDC_CTRL);
 843                         deselect_ep();
 844                 }
 845                 while (omap_readw(UDC_TXDMA_CFG) & mask)
 846                         udelay(10);
 847         } else {
 848                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 849                                         UDC_RXDMA_CFG);
 850
 851                 /* dma empties the fifo */
 852                 while (omap_readw(UDC_RXDMA_CFG) & mask)
 853                         udelay(10);
 854                 if (req)
 855                         finish_out_dma(ep, req, -ECONNRESET, 0);
 856         }
 857         omap_free_dma(ep->lch);
 858         ep->dma_channel = 0;
 859         ep->lch = -1;
 860         /* has_dma still set, till endpoint is fully quiesced */
 861 }
 862
 863
 864 /*-------------------------------------------------------------------------*/
 865
 866 static int
 867 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 868 {
 869         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 870         struct omap_req *req = container_of(_req, struct omap_req, req);
 871         struct omap_udc *udc;
 872         unsigned long   flags;
 873         int             is_iso = 0;
 874
 875         /* catch various bogus parameters */
 876         if (!_req || !req->req.complete || !req->req.buf
 877                         || !list_empty(&req->queue)) {
 878                 DBG("%s, bad params\n", __func__);
 879                 return -EINVAL;
 880         }
 881         if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
 882                 DBG("%s, bad ep\n", __func__);
 883                 return -EINVAL;
 884         }
 885         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 886                 if (req->req.length > ep->ep.maxpacket)
 887                         return -EMSGSIZE;
 888                 is_iso = 1;
 889         }
 890
 891         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 892          * have a hard time with partial packet reads...  reject it.
 893          */
 894         if (use_dma
 895                         && ep->has_dma
 896                         && ep->bEndpointAddress != 0
 897                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 898                         && (req->req.length % ep->ep.maxpacket) != 0) {
 899                 DBG("%s, no partial packet OUT reads\n", __func__);
 900                 return -EMSGSIZE;
 901         }
 902
 903         udc = ep->udc;
 904         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 905                 return -ESHUTDOWN;
 906
 907         if (use_dma && ep->has_dma)
 908                 usb_gadget_map_request(&udc->gadget, &req->req,
 909                                 (ep->bEndpointAddress & USB_DIR_IN));
 910
 911         VDBG("%s queue req %p, len %d buf %p\n",
 912                 ep->ep.name, _req, _req->length, _req->buf);
 913
 914         spin_lock_irqsave(&udc->lock, flags);
 915
 916         req->req.status = -EINPROGRESS;
 917         req->req.actual = 0;
 918
 919         /* maybe kickstart non-iso i/o queues */
 920         if (is_iso) {
 921                 u16 w;
 922
 923                 w = omap_readw(UDC_IRQ_EN);
 924                 w |= UDC_SOF_IE;
 925                 omap_writew(w, UDC_IRQ_EN);
 926         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 927                 int     is_in;
 928
 929                 if (ep->bEndpointAddress == 0) {
 930                         if (!udc->ep0_pending || !list_empty(&ep->queue)) {
 931                                 spin_unlock_irqrestore(&udc->lock, flags);
 932                                 return -EL2HLT;
 933                         }
 934
 935                         /* empty DATA stage? */
 936                         is_in = udc->ep0_in;
 937                         if (!req->req.length) {
 938
 939                                 /* chip became CONFIGURED or ADDRESSED
 940                                  * earlier; drivers may already have queued
 941                                  * requests to non-control endpoints
 942                                  */
 943                                 if (udc->ep0_set_config) {
 944                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
 945
 946                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
 947                                         if (!udc->ep0_reset_config)
 948                                                 irq_en |= UDC_EPN_RX_IE
 949                                                         | UDC_EPN_TX_IE;
 950                                         omap_writew(irq_en, UDC_IRQ_EN);
 951                                 }
 952
 953                                 /* STATUS for zero length DATA stages is
 954                                  * always an IN ... even for IN transfers,
 955                                  * a weird case which seem to stall OMAP.
 956                                  */
 957                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 958                                                 UDC_EP_NUM);
 959                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
 960                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 961                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
 962
 963                                 /* cleanup */
 964                                 udc->ep0_pending = 0;
 965                                 done(ep, req, 0);
 966                                 req = NULL;
 967
 968                         /* non-empty DATA stage */
 969                         } else if (is_in) {
 970                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
 971                                                 UDC_EP_NUM);
 972                         } else {
 973                                 if (udc->ep0_setup)
 974                                         goto irq_wait;
 975                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
 976                         }
 977                 } else {
 978                         is_in = ep->bEndpointAddress & USB_DIR_IN;
 979                         if (!ep->has_dma)
 980                                 use_ep(ep, UDC_EP_SEL);
 981                         /* if ISO: SOF IRQs must be enabled/disabled! */
 982                 }
 983
 984                 if (ep->has_dma)
 985                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 986                 else if (req) {
 987                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
 988                                 req = NULL;
 989                         deselect_ep();
 990                         if (!is_in) {
 991                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 992                                 ep->ackwait = 1 + ep->double_buf;
 993                         }
 994                         /* IN: 6 wait states before it'll tx */
 995                 }
 996         }
 997
 998 irq_wait:
 999         /* irq handler advances the queue */
1000         if (req != NULL)
1001                 list_add_tail(&req->queue, &ep->queue);
1002         spin_unlock_irqrestore(&udc->lock, flags);
1003
1004         return 0;
1005 }
1006
1007 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1008 {
1009         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1010         struct omap_req *req;
1011         unsigned long   flags;
1012
1013         if (!_ep || !_req)
1014                 return -EINVAL;
1015
1016         spin_lock_irqsave(&ep->udc->lock, flags);
1017
1018         /* make sure it's actually queued on this endpoint */
1019         list_for_each_entry(req, &ep->queue, queue) {
1020                 if (&req->req == _req)
1021                         break;
1022         }
1023         if (&req->req != _req) {
1024                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1025                 return -EINVAL;
1026         }
1027
1028         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1029                 int channel = ep->dma_channel;
1030
1031                 /* releasing the channel cancels the request,
1032                  * reclaiming the channel restarts the queue
1033                  */
1034                 dma_channel_release(ep);
1035                 dma_channel_claim(ep, channel);
1036         } else
1037                 done(ep, req, -ECONNRESET);
1038         spin_unlock_irqrestore(&ep->udc->lock, flags);
1039         return 0;
1040 }
1041
1042 /*-------------------------------------------------------------------------*/
1043
1044 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1045 {
1046         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1047         unsigned long   flags;
1048         int             status = -EOPNOTSUPP;
1049
1050         spin_lock_irqsave(&ep->udc->lock, flags);
1051
1052         /* just use protocol stalls for ep0; real halts are annoying */
1053         if (ep->bEndpointAddress == 0) {
1054                 if (!ep->udc->ep0_pending)
1055                         status = -EINVAL;
1056                 else if (value) {
1057                         if (ep->udc->ep0_set_config) {
1058                                 WARNING("error changing config?\n");
1059                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1060                         }
1061                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1062                         ep->udc->ep0_pending = 0;
1063                         status = 0;
1064                 } else /* NOP */
1065                         status = 0;
1066
1067         /* otherwise, all active non-ISO endpoints can halt */
1068         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1069
1070                 /* IN endpoints must already be idle */
1071                 if ((ep->bEndpointAddress & USB_DIR_IN)
1072                                 && !list_empty(&ep->queue)) {
1073                         status = -EAGAIN;
1074                         goto done;
1075                 }
1076
1077                 if (value) {
1078                         int     channel;
1079
1080                         if (use_dma && ep->dma_channel
1081                                         && !list_empty(&ep->queue)) {
1082                                 channel = ep->dma_channel;
1083                                 dma_channel_release(ep);
1084                         } else
1085                                 channel = 0;
1086
1087                         use_ep(ep, UDC_EP_SEL);
1088                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1089                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1090                                 status = 0;
1091                         } else
1092                                 status = -EAGAIN;
1093                         deselect_ep();
1094
1095                         if (channel)
1096                                 dma_channel_claim(ep, channel);
1097                 } else {
1098                         use_ep(ep, 0);
1099                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1100                         ep->ackwait = 0;
1101                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1102                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1103                                 ep->ackwait = 1 + ep->double_buf;
1104                         }
1105                 }
1106         }
1107 done:
1108         VDBG("%s %s halt stat %d\n", ep->ep.name,
1109                 value ? "set" : "clear", status);
1110
1111         spin_unlock_irqrestore(&ep->udc->lock, flags);
1112         return status;
1113 }
1114
1115 static struct usb_ep_ops omap_ep_ops = {
1116         .enable         = omap_ep_enable,
1117         .disable        = omap_ep_disable,
1118
1119         .alloc_request  = omap_alloc_request,
1120         .free_request   = omap_free_request,
1121
1122         .queue          = omap_ep_queue,
1123         .dequeue        = omap_ep_dequeue,
1124
1125         .set_halt       = omap_ep_set_halt,
1126         /* fifo_status ... report bytes in fifo */
1127         /* fifo_flush ... flush fifo */
1128 };
1129
1130 /*-------------------------------------------------------------------------*/
1131
1132 static int omap_get_frame(struct usb_gadget *gadget)
1133 {
1134         u16     sof = omap_readw(UDC_SOF);
1135         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1136 }
1137
1138 static int omap_wakeup(struct usb_gadget *gadget)
1139 {
1140         struct omap_udc *udc;
1141         unsigned long   flags;
1142         int             retval = -EHOSTUNREACH;
1143
1144         udc = container_of(gadget, struct omap_udc, gadget);
1145
1146         spin_lock_irqsave(&udc->lock, flags);
1147         if (udc->devstat & UDC_SUS) {
1148                 /* NOTE:  OTG spec erratum says that OTG devices may
1149                  * issue wakeups without host enable.
1150                  */
1151                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1152                         DBG("remote wakeup...\n");
1153                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1154                         retval = 0;
1155                 }
1156
1157         /* NOTE:  non-OTG systems may use SRP TOO... */
1158         } else if (!(udc->devstat & UDC_ATT)) {
1159                 if (!IS_ERR_OR_NULL(udc->transceiver))
1160                         retval = otg_start_srp(udc->transceiver->otg);
1161         }
1162         spin_unlock_irqrestore(&udc->lock, flags);
1163
1164         return retval;
1165 }
1166
1167 static int
1168 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1169 {
1170         struct omap_udc *udc;
1171         unsigned long   flags;
1172         u16             syscon1;
1173
1174         udc = container_of(gadget, struct omap_udc, gadget);
1175         spin_lock_irqsave(&udc->lock, flags);
1176         syscon1 = omap_readw(UDC_SYSCON1);
1177         if (is_selfpowered)
1178                 syscon1 |= UDC_SELF_PWR;
1179         else
1180                 syscon1 &= ~UDC_SELF_PWR;
1181         omap_writew(syscon1, UDC_SYSCON1);
1182         spin_unlock_irqrestore(&udc->lock, flags);
1183
1184         return 0;
1185 }
1186
1187 static int can_pullup(struct omap_udc *udc)
1188 {
1189         return udc->driver && udc->softconnect && udc->vbus_active;
1190 }
1191
1192 static void pullup_enable(struct omap_udc *udc)
1193 {
1194         u16 w;
1195
1196         w = omap_readw(UDC_SYSCON1);
1197         w |= UDC_PULLUP_EN;
1198         omap_writew(w, UDC_SYSCON1);
1199         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1200                 u32 l;
1201
1202                 l = omap_readl(OTG_CTRL);
1203                 l |= OTG_BSESSVLD;
1204                 omap_writel(l, OTG_CTRL);
1205         }
1206         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1207 }
1208
1209 static void pullup_disable(struct omap_udc *udc)
1210 {
1211         u16 w;
1212
1213         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1214                 u32 l;
1215
1216                 l = omap_readl(OTG_CTRL);
1217                 l &= ~OTG_BSESSVLD;
1218                 omap_writel(l, OTG_CTRL);
1219         }
1220         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1221         w = omap_readw(UDC_SYSCON1);
1222         w &= ~UDC_PULLUP_EN;
1223         omap_writew(w, UDC_SYSCON1);
1224 }
1225
1226 static struct omap_udc *udc;
1227
1228 static void omap_udc_enable_clock(int enable)
1229 {
1230         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1231                 return;
1232
1233         if (enable) {
1234                 clk_enable(udc->dc_clk);
1235                 clk_enable(udc->hhc_clk);
1236                 udelay(100);
1237         } else {
1238                 clk_disable(udc->hhc_clk);
1239                 clk_disable(udc->dc_clk);
1240         }
1241 }
1242
1243 /*
1244  * Called by whatever detects VBUS sessions:  external transceiver
1245  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1246  */
1247 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1248 {
1249         struct omap_udc *udc;
1250         unsigned long   flags;
1251         u32 l;
1252
1253         udc = container_of(gadget, struct omap_udc, gadget);
1254         spin_lock_irqsave(&udc->lock, flags);
1255         VDBG("VBUS %s\n", is_active ? "on" : "off");
1256         udc->vbus_active = (is_active != 0);
1257         if (cpu_is_omap15xx()) {
1258                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1259                 l = omap_readl(FUNC_MUX_CTRL_0);
1260                 if (is_active)
1261                         l |= VBUS_CTRL_1510;
1262                 else
1263                         l &= ~VBUS_CTRL_1510;
1264                 omap_writel(l, FUNC_MUX_CTRL_0);
1265         }
1266         if (udc->dc_clk != NULL && is_active) {
1267                 if (!udc->clk_requested) {
1268                         omap_udc_enable_clock(1);
1269                         udc->clk_requested = 1;
1270                 }
1271         }
1272         if (can_pullup(udc))
1273                 pullup_enable(udc);
1274         else
1275                 pullup_disable(udc);
1276         if (udc->dc_clk != NULL && !is_active) {
1277                 if (udc->clk_requested) {
1278                         omap_udc_enable_clock(0);
1279                         udc->clk_requested = 0;
1280                 }
1281         }
1282         spin_unlock_irqrestore(&udc->lock, flags);
1283         return 0;
1284 }
1285
1286 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1287 {
1288         struct omap_udc *udc;
1289
1290         udc = container_of(gadget, struct omap_udc, gadget);
1291         if (!IS_ERR_OR_NULL(udc->transceiver))
1292                 return usb_phy_set_power(udc->transceiver, mA);
1293         return -EOPNOTSUPP;
1294 }
1295
1296 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1297 {
1298         struct omap_udc *udc;
1299         unsigned long   flags;
1300
1301         udc = container_of(gadget, struct omap_udc, gadget);
1302         spin_lock_irqsave(&udc->lock, flags);
1303         udc->softconnect = (is_on != 0);
1304         if (can_pullup(udc))
1305                 pullup_enable(udc);
1306         else
1307                 pullup_disable(udc);
1308         spin_unlock_irqrestore(&udc->lock, flags);
1309         return 0;
1310 }
1311
1312 static int omap_udc_start(struct usb_gadget *g,
1313                 struct usb_gadget_driver *driver);
1314 static int omap_udc_stop(struct usb_gadget *g,
1315                 struct usb_gadget_driver *driver);
1316
1317 static const struct usb_gadget_ops omap_gadget_ops = {
1318         .get_frame              = omap_get_frame,
1319         .wakeup                 = omap_wakeup,
1320         .set_selfpowered        = omap_set_selfpowered,
1321         .vbus_session           = omap_vbus_session,
1322         .vbus_draw              = omap_vbus_draw,
1323         .pullup                 = omap_pullup,
1324         .udc_start              = omap_udc_start,
1325         .udc_stop               = omap_udc_stop,
1326 };
1327
1328 /*-------------------------------------------------------------------------*/
1329
1330 /* dequeue ALL requests; caller holds udc->lock */
1331 static void nuke(struct omap_ep *ep, int status)
1332 {
1333         struct omap_req *req;
1334
1335         ep->stopped = 1;
1336
1337         if (use_dma && ep->dma_channel)
1338                 dma_channel_release(ep);
1339
1340         use_ep(ep, 0);
1341         omap_writew(UDC_CLR_EP, UDC_CTRL);
1342         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1343                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1344
1345         while (!list_empty(&ep->queue)) {
1346                 req = list_entry(ep->queue.next, struct omap_req, queue);
1347                 done(ep, req, status);
1348         }
1349 }
1350
1351 /* caller holds udc->lock */
1352 static void udc_quiesce(struct omap_udc *udc)
1353 {
1354         struct omap_ep  *ep;
1355
1356         udc->gadget.speed = USB_SPEED_UNKNOWN;
1357         nuke(&udc->ep[0], -ESHUTDOWN);
1358         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
1359                 nuke(ep, -ESHUTDOWN);
1360 }
1361
1362 /*-------------------------------------------------------------------------*/
1363
1364 static void update_otg(struct omap_udc *udc)
1365 {
1366         u16     devstat;
1367
1368         if (!gadget_is_otg(&udc->gadget))
1369                 return;
1370
1371         if (omap_readl(OTG_CTRL) & OTG_ID)
1372                 devstat = omap_readw(UDC_DEVSTAT);
1373         else
1374                 devstat = 0;
1375
1376         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1377         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1378         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1379
1380         /* Enable HNP early, avoiding races on suspend irq path.
1381          * ASSUMES OTG state machine B_BUS_REQ input is true.
1382          */
1383         if (udc->gadget.b_hnp_enable) {
1384                 u32 l;
1385
1386                 l = omap_readl(OTG_CTRL);
1387                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1388                 l &= ~OTG_PULLUP;
1389                 omap_writel(l, OTG_CTRL);
1390         }
1391 }
1392
1393 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1394 {
1395         struct omap_ep  *ep0 = &udc->ep[0];
1396         struct omap_req *req = NULL;
1397
1398         ep0->irqs++;
1399
1400         /* Clear any pending requests and then scrub any rx/tx state
1401          * before starting to handle the SETUP request.
1402          */
1403         if (irq_src & UDC_SETUP) {
1404                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1405
1406                 nuke(ep0, 0);
1407                 if (ack) {
1408                         omap_writew(ack, UDC_IRQ_SRC);
1409                         irq_src = UDC_SETUP;
1410                 }
1411         }
1412
1413         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1414          * This driver uses only uses protocol stalls (ep0 never halts),
1415          * and if we got this far the gadget driver already had a
1416          * chance to stall.  Tries to be forgiving of host oddities.
1417          *
1418          * NOTE:  the last chance gadget drivers have to stall control
1419          * requests is during their request completion callback.
1420          */
1421         if (!list_empty(&ep0->queue))
1422                 req = container_of(ep0->queue.next, struct omap_req, queue);
1423
1424         /* IN == TX to host */
1425         if (irq_src & UDC_EP0_TX) {
1426                 int     stat;
1427
1428                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1429                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1430                 stat = omap_readw(UDC_STAT_FLG);
1431                 if (stat & UDC_ACK) {
1432                         if (udc->ep0_in) {
1433                                 /* write next IN packet from response,
1434                                  * or set up the status stage.
1435                                  */
1436                                 if (req)
1437                                         stat = write_fifo(ep0, req);
1438                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1439                                 if (!req && udc->ep0_pending) {
1440                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1441                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1442                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1443                                         omap_writew(0, UDC_EP_NUM);
1444                                         udc->ep0_pending = 0;
1445                                 } /* else:  6 wait states before it'll tx */
1446                         } else {
1447                                 /* ack status stage of OUT transfer */
1448                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1449                                 if (req)
1450                                         done(ep0, req, 0);
1451                         }
1452                         req = NULL;
1453                 } else if (stat & UDC_STALL) {
1454                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1455                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1456                 } else {
1457                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1458                 }
1459         }
1460
1461         /* OUT == RX from host */
1462         if (irq_src & UDC_EP0_RX) {
1463                 int     stat;
1464
1465                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1466                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1467                 stat = omap_readw(UDC_STAT_FLG);
1468                 if (stat & UDC_ACK) {
1469                         if (!udc->ep0_in) {
1470                                 stat = 0;
1471                                 /* read next OUT packet of request, maybe
1472                                  * reactiviting the fifo; stall on errors.
1473                                  */
1474                                 stat = read_fifo(ep0, req);
1475                                 if (!req || stat < 0) {
1476                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1477                                         udc->ep0_pending = 0;
1478                                         stat = 0;
1479                                 } else if (stat == 0)
1480                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1481                                 omap_writew(0, UDC_EP_NUM);
1482
1483                                 /* activate status stage */
1484                                 if (stat == 1) {
1485                                         done(ep0, req, 0);
1486                                         /* that may have STALLed ep0... */
1487                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1488                                                         UDC_EP_NUM);
1489                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1490                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1491                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1492                                         udc->ep0_pending = 0;
1493                                 }
1494                         } else {
1495                                 /* ack status stage of IN transfer */
1496                                 omap_writew(0, UDC_EP_NUM);
1497                                 if (req)
1498                                         done(ep0, req, 0);
1499                         }
1500                 } else if (stat & UDC_STALL) {
1501                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1502                         omap_writew(0, UDC_EP_NUM);
1503                 } else {
1504                         omap_writew(0, UDC_EP_NUM);
1505                 }
1506         }
1507
1508         /* SETUP starts all control transfers */
1509         if (irq_src & UDC_SETUP) {
1510                 union u {
1511                         u16                     word[4];
1512                         struct usb_ctrlrequest  r;
1513                 } u;
1514                 int                     status = -EINVAL;
1515                 struct omap_ep          *ep;
1516
1517                 /* read the (latest) SETUP message */
1518                 do {
1519                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1520                         /* two bytes at a time */
1521                         u.word[0] = omap_readw(UDC_DATA);
1522                         u.word[1] = omap_readw(UDC_DATA);
1523                         u.word[2] = omap_readw(UDC_DATA);
1524                         u.word[3] = omap_readw(UDC_DATA);
1525                         omap_writew(0, UDC_EP_NUM);
1526                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1527
1528 #define w_value         le16_to_cpu(u.r.wValue)
1529 #define w_index         le16_to_cpu(u.r.wIndex)
1530 #define w_length        le16_to_cpu(u.r.wLength)
1531
1532                 /* Delegate almost all control requests to the gadget driver,
1533                  * except for a handful of ch9 status/feature requests that
1534                  * hardware doesn't autodecode _and_ the gadget API hides.
1535                  */
1536                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1537                 udc->ep0_set_config = 0;
1538                 udc->ep0_pending = 1;
1539                 ep0->stopped = 0;
1540                 ep0->ackwait = 0;
1541                 switch (u.r.bRequest) {
1542                 case USB_REQ_SET_CONFIGURATION:
1543                         /* udc needs to know when ep != 0 is valid */
1544                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1545                                 goto delegate;
1546                         if (w_length != 0)
1547                                 goto do_stall;
1548                         udc->ep0_set_config = 1;
1549                         udc->ep0_reset_config = (w_value == 0);
1550                         VDBG("set config %d\n", w_value);
1551
1552                         /* update udc NOW since gadget driver may start
1553                          * queueing requests immediately; clear config
1554                          * later if it fails the request.
1555                          */
1556                         if (udc->ep0_reset_config)
1557                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1558                         else
1559                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1560                         update_otg(udc);
1561                         goto delegate;
1562                 case USB_REQ_CLEAR_FEATURE:
1563                         /* clear endpoint halt */
1564                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1565                                 goto delegate;
1566                         if (w_value != USB_ENDPOINT_HALT
1567                                         || w_length != 0)
1568                                 goto do_stall;
1569                         ep = &udc->ep[w_index & 0xf];
1570                         if (ep != ep0) {
1571                                 if (w_index & USB_DIR_IN)
1572                                         ep += 16;
1573                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1574                                                 || !ep->ep.desc)
1575                                         goto do_stall;
1576                                 use_ep(ep, 0);
1577                                 omap_writew(udc->clr_halt, UDC_CTRL);
1578                                 ep->ackwait = 0;
1579                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1580                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1581                                         ep->ackwait = 1 + ep->double_buf;
1582                                 }
1583                                 /* NOTE:  assumes the host behaves sanely,
1584                                  * only clearing real halts.  Else we may
1585                                  * need to kill pending transfers and then
1586                                  * restart the queue... very messy for DMA!
1587                                  */
1588                         }
1589                         VDBG("%s halt cleared by host\n", ep->name);
1590                         goto ep0out_status_stage;
1591                 case USB_REQ_SET_FEATURE:
1592                         /* set endpoint halt */
1593                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1594                                 goto delegate;
1595                         if (w_value != USB_ENDPOINT_HALT
1596                                         || w_length != 0)
1597                                 goto do_stall;
1598                         ep = &udc->ep[w_index & 0xf];
1599                         if (w_index & USB_DIR_IN)
1600                                 ep += 16;
1601                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1602                                         || ep == ep0 || !ep->ep.desc)
1603                                 goto do_stall;
1604                         if (use_dma && ep->has_dma) {
1605                                 /* this has rude side-effects (aborts) and
1606                                  * can't really work if DMA-IN is active
1607                                  */
1608                                 DBG("%s host set_halt, NYET\n", ep->name);
1609                                 goto do_stall;
1610                         }
1611                         use_ep(ep, 0);
1612                         /* can't halt if fifo isn't empty... */
1613                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1614                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1615                         VDBG("%s halted by host\n", ep->name);
1616 ep0out_status_stage:
1617                         status = 0;
1618                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1619                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1620                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1621                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1622                         udc->ep0_pending = 0;
1623                         break;
1624                 case USB_REQ_GET_STATUS:
1625                         /* USB_ENDPOINT_HALT status? */
1626                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1627                                 goto intf_status;
1628
1629                         /* ep0 never stalls */
1630                         if (!(w_index & 0xf))
1631                                 goto zero_status;
1632
1633                         /* only active endpoints count */
1634                         ep = &udc->ep[w_index & 0xf];
1635                         if (w_index & USB_DIR_IN)
1636                                 ep += 16;
1637                         if (!ep->ep.desc)
1638                                 goto do_stall;
1639
1640                         /* iso never stalls */
1641                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1642                                 goto zero_status;
1643
1644                         /* FIXME don't assume non-halted endpoints!! */
1645                         ERR("%s status, can't report\n", ep->ep.name);
1646                         goto do_stall;
1647
1648 intf_status:
1649                         /* return interface status.  if we were pedantic,
1650                          * we'd detect non-existent interfaces, and stall.
1651                          */
1652                         if (u.r.bRequestType
1653                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1654                                 goto delegate;
1655
1656 zero_status:
1657                         /* return two zero bytes */
1658                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1659                         omap_writew(0, UDC_DATA);
1660                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1661                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1662                         status = 0;
1663                         VDBG("GET_STATUS, interface %d\n", w_index);
1664                         /* next, status stage */
1665                         break;
1666                 default:
1667 delegate:
1668                         /* activate the ep0out fifo right away */
1669                         if (!udc->ep0_in && w_length) {
1670                                 omap_writew(0, UDC_EP_NUM);
1671                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1672                         }
1673
1674                         /* gadget drivers see class/vendor specific requests,
1675                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1676                          * and more
1677                          */
1678                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1679                                 u.r.bRequestType, u.r.bRequest,
1680                                 w_value, w_index, w_length);
1681
1682 #undef  w_value
1683 #undef  w_index
1684 #undef  w_length
1685
1686                         /* The gadget driver may return an error here,
1687                          * causing an immediate protocol stall.
1688                          *
1689                          * Else it must issue a response, either queueing a
1690                          * response buffer for the DATA stage, or halting ep0
1691                          * (causing a protocol stall, not a real halt).  A
1692                          * zero length buffer means no DATA stage.
1693                          *
1694                          * It's fine to issue that response after the setup()
1695                          * call returns, and this IRQ was handled.
1696                          */
1697                         udc->ep0_setup = 1;
1698                         spin_unlock(&udc->lock);
1699                         status = udc->driver->setup(&udc->gadget, &u.r);
1700                         spin_lock(&udc->lock);
1701                         udc->ep0_setup = 0;
1702                 }
1703
1704                 if (status < 0) {
1705 do_stall:
1706                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1707                                         u.r.bRequestType, u.r.bRequest, status);
1708                         if (udc->ep0_set_config) {
1709                                 if (udc->ep0_reset_config)
1710                                         WARNING("error resetting config?\n");
1711                                 else
1712                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1713                         }
1714                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1715                         udc->ep0_pending = 0;
1716                 }
1717         }
1718 }
1719
1720 /*-------------------------------------------------------------------------*/
1721
1722 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1723
1724 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1725 {
1726         u16     devstat, change;
1727
1728         devstat = omap_readw(UDC_DEVSTAT);
1729         change = devstat ^ udc->devstat;
1730         udc->devstat = devstat;
1731
1732         if (change & (UDC_USB_RESET|UDC_ATT)) {
1733                 udc_quiesce(udc);
1734
1735                 if (change & UDC_ATT) {
1736                         /* driver for any external transceiver will
1737                          * have called omap_vbus_session() already
1738                          */
1739                         if (devstat & UDC_ATT) {
1740                                 udc->gadget.speed = USB_SPEED_FULL;
1741                                 VDBG("connect\n");
1742                                 if (IS_ERR_OR_NULL(udc->transceiver))
1743                                         pullup_enable(udc);
1744                                 /* if (driver->connect) call it */
1745                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1746                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1747                                 if (IS_ERR_OR_NULL(udc->transceiver))
1748                                         pullup_disable(udc);
1749                                 DBG("disconnect, gadget %s\n",
1750                                         udc->driver->driver.name);
1751                                 if (udc->driver->disconnect) {
1752                                         spin_unlock(&udc->lock);
1753                                         udc->driver->disconnect(&udc->gadget);
1754                                         spin_lock(&udc->lock);
1755                                 }
1756                         }
1757                         change &= ~UDC_ATT;
1758                 }
1759
1760                 if (change & UDC_USB_RESET) {
1761                         if (devstat & UDC_USB_RESET) {
1762                                 VDBG("RESET=1\n");
1763                         } else {
1764                                 udc->gadget.speed = USB_SPEED_FULL;
1765                                 INFO("USB reset done, gadget %s\n",
1766                                         udc->driver->driver.name);
1767                                 /* ep0 traffic is legal from now on */
1768                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1769                                                 UDC_IRQ_EN);
1770                         }
1771                         change &= ~UDC_USB_RESET;
1772                 }
1773         }
1774         if (change & UDC_SUS) {
1775                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1776                         /* FIXME tell isp1301 to suspend/resume (?) */
1777                         if (devstat & UDC_SUS) {
1778                                 VDBG("suspend\n");
1779                                 update_otg(udc);
1780                                 /* HNP could be under way already */
1781                                 if (udc->gadget.speed == USB_SPEED_FULL
1782                                                 && udc->driver->suspend) {
1783                                         spin_unlock(&udc->lock);
1784                                         udc->driver->suspend(&udc->gadget);
1785                                         spin_lock(&udc->lock);
1786                                 }
1787                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1788                                         usb_phy_set_suspend(
1789                                                         udc->transceiver, 1);
1790                         } else {
1791                                 VDBG("resume\n");
1792                                 if (!IS_ERR_OR_NULL(udc->transceiver))
1793                                         usb_phy_set_suspend(
1794                                                         udc->transceiver, 0);
1795                                 if (udc->gadget.speed == USB_SPEED_FULL
1796                                                 && udc->driver->resume) {
1797                                         spin_unlock(&udc->lock);
1798                                         udc->driver->resume(&udc->gadget);
1799                                         spin_lock(&udc->lock);
1800                                 }
1801                         }
1802                 }
1803                 change &= ~UDC_SUS;
1804         }
1805         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1806                 update_otg(udc);
1807                 change &= ~OTG_FLAGS;
1808         }
1809
1810         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1811         if (change)
1812                 VDBG("devstat %03x, ignore change %03x\n",
1813                         devstat,  change);
1814
1815         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1816 }
1817
1818 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1819 {
1820         struct omap_udc *udc = _udc;
1821         u16             irq_src;
1822         irqreturn_t     status = IRQ_NONE;
1823         unsigned long   flags;
1824
1825         spin_lock_irqsave(&udc->lock, flags);
1826         irq_src = omap_readw(UDC_IRQ_SRC);
1827
1828         /* Device state change (usb ch9 stuff) */
1829         if (irq_src & UDC_DS_CHG) {
1830                 devstate_irq(_udc, irq_src);
1831                 status = IRQ_HANDLED;
1832                 irq_src &= ~UDC_DS_CHG;
1833         }
1834
1835         /* EP0 control transfers */
1836         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1837                 ep0_irq(_udc, irq_src);
1838                 status = IRQ_HANDLED;
1839                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1840         }
1841
1842         /* DMA transfer completion */
1843         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1844                 dma_irq(_udc, irq_src);
1845                 status = IRQ_HANDLED;
1846                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1847         }
1848
1849         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1850         if (irq_src)
1851                 DBG("udc_irq, unhandled %03x\n", irq_src);
1852         spin_unlock_irqrestore(&udc->lock, flags);
1853
1854         return status;
1855 }
1856
1857 /* workaround for seemingly-lost IRQs for RX ACKs... */
1858 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1859 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1860
1861 static void pio_out_timer(unsigned long _ep)
1862 {
1863         struct omap_ep  *ep = (void *) _ep;
1864         unsigned long   flags;
1865         u16             stat_flg;
1866
1867         spin_lock_irqsave(&ep->udc->lock, flags);
1868         if (!list_empty(&ep->queue) && ep->ackwait) {
1869                 use_ep(ep, UDC_EP_SEL);
1870                 stat_flg = omap_readw(UDC_STAT_FLG);
1871
1872                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1873                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1874                         struct omap_req *req;
1875
1876                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1877                         req = container_of(ep->queue.next,
1878                                         struct omap_req, queue);
1879                         (void) read_fifo(ep, req);
1880                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1881                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1882                         ep->ackwait = 1 + ep->double_buf;
1883                 } else
1884                         deselect_ep();
1885         }
1886         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1887         spin_unlock_irqrestore(&ep->udc->lock, flags);
1888 }
1889
1890 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1891 {
1892         u16             epn_stat, irq_src;
1893         irqreturn_t     status = IRQ_NONE;
1894         struct omap_ep  *ep;
1895         int             epnum;
1896         struct omap_udc *udc = _dev;
1897         struct omap_req *req;
1898         unsigned long   flags;
1899
1900         spin_lock_irqsave(&udc->lock, flags);
1901         epn_stat = omap_readw(UDC_EPN_STAT);
1902         irq_src = omap_readw(UDC_IRQ_SRC);
1903
1904         /* handle OUT first, to avoid some wasteful NAKs */
1905         if (irq_src & UDC_EPN_RX) {
1906                 epnum = (epn_stat >> 8) & 0x0f;
1907                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1908                 status = IRQ_HANDLED;
1909                 ep = &udc->ep[epnum];
1910                 ep->irqs++;
1911
1912                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1913                 ep->fnf = 0;
1914                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1915                         ep->ackwait--;
1916                         if (!list_empty(&ep->queue)) {
1917                                 int stat;
1918                                 req = container_of(ep->queue.next,
1919                                                 struct omap_req, queue);
1920                                 stat = read_fifo(ep, req);
1921                                 if (!ep->double_buf)
1922                                         ep->fnf = 1;
1923                         }
1924                 }
1925                 /* min 6 clock delay before clearing EP_SEL ... */
1926                 epn_stat = omap_readw(UDC_EPN_STAT);
1927                 epn_stat = omap_readw(UDC_EPN_STAT);
1928                 omap_writew(epnum, UDC_EP_NUM);
1929
1930                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1931                  * reduces lossage; timer still needed though (sigh).
1932                  */
1933                 if (ep->fnf) {
1934                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935                         ep->ackwait = 1 + ep->double_buf;
1936                 }
1937                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1938         }
1939
1940         /* then IN transfers */
1941         else if (irq_src & UDC_EPN_TX) {
1942                 epnum = epn_stat & 0x0f;
1943                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1944                 status = IRQ_HANDLED;
1945                 ep = &udc->ep[16 + epnum];
1946                 ep->irqs++;
1947
1948                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
1949                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1950                         ep->ackwait = 0;
1951                         if (!list_empty(&ep->queue)) {
1952                                 req = container_of(ep->queue.next,
1953                                                 struct omap_req, queue);
1954                                 (void) write_fifo(ep, req);
1955                         }
1956                 }
1957                 /* min 6 clock delay before clearing EP_SEL ... */
1958                 epn_stat = omap_readw(UDC_EPN_STAT);
1959                 epn_stat = omap_readw(UDC_EPN_STAT);
1960                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
1961                 /* then 6 clocks before it'd tx */
1962         }
1963
1964         spin_unlock_irqrestore(&udc->lock, flags);
1965         return status;
1966 }
1967
1968 #ifdef  USE_ISO
1969 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
1970 {
1971         struct omap_udc *udc = _dev;
1972         struct omap_ep  *ep;
1973         int             pending = 0;
1974         unsigned long   flags;
1975
1976         spin_lock_irqsave(&udc->lock, flags);
1977
1978         /* handle all non-DMA ISO transfers */
1979         list_for_each_entry(ep, &udc->iso, iso) {
1980                 u16             stat;
1981                 struct omap_req *req;
1982
1983                 if (ep->has_dma || list_empty(&ep->queue))
1984                         continue;
1985                 req = list_entry(ep->queue.next, struct omap_req, queue);
1986
1987                 use_ep(ep, UDC_EP_SEL);
1988                 stat = omap_readw(UDC_STAT_FLG);
1989
1990                 /* NOTE: like the other controller drivers, this isn't
1991                  * currently reporting lost or damaged frames.
1992                  */
1993                 if (ep->bEndpointAddress & USB_DIR_IN) {
1994                         if (stat & UDC_MISS_IN)
1995                                 /* done(ep, req, -EPROTO) */;
1996                         else
1997                                 write_fifo(ep, req);
1998                 } else {
1999                         int     status = 0;
2000
2001                         if (stat & UDC_NO_RXPACKET)
2002                                 status = -EREMOTEIO;
2003                         else if (stat & UDC_ISO_ERR)
2004                                 status = -EILSEQ;
2005                         else if (stat & UDC_DATA_FLUSH)
2006                                 status = -ENOSR;
2007
2008                         if (status)
2009                                 /* done(ep, req, status) */;
2010                         else
2011                                 read_fifo(ep, req);
2012                 }
2013                 deselect_ep();
2014                 /* 6 wait states before next EP */
2015
2016                 ep->irqs++;
2017                 if (!list_empty(&ep->queue))
2018                         pending = 1;
2019         }
2020         if (!pending) {
2021                 u16 w;
2022
2023                 w = omap_readw(UDC_IRQ_EN);
2024                 w &= ~UDC_SOF_IE;
2025                 omap_writew(w, UDC_IRQ_EN);
2026         }
2027         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2028
2029         spin_unlock_irqrestore(&udc->lock, flags);
2030         return IRQ_HANDLED;
2031 }
2032 #endif
2033
2034 /*-------------------------------------------------------------------------*/
2035
2036 static inline int machine_without_vbus_sense(void)
2037 {
2038         return machine_is_omap_innovator()
2039                 || machine_is_omap_osk()
2040                 || machine_is_sx1()
2041                 /* No known omap7xx boards with vbus sense */
2042                 || cpu_is_omap7xx();
2043 }
2044
2045 static int omap_udc_start(struct usb_gadget *g,
2046                 struct usb_gadget_driver *driver)
2047 {
2048         int             status = -ENODEV;
2049         struct omap_ep  *ep;
2050         unsigned long   flags;
2051
2052
2053         spin_lock_irqsave(&udc->lock, flags);
2054         /* reset state */
2055         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2056                 ep->irqs = 0;
2057                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2058                         continue;
2059                 use_ep(ep, 0);
2060                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2061         }
2062         udc->ep0_pending = 0;
2063         udc->ep[0].irqs = 0;
2064         udc->softconnect = 1;
2065
2066         /* hook up the driver */
2067         driver->driver.bus = NULL;
2068         udc->driver = driver;
2069         spin_unlock_irqrestore(&udc->lock, flags);
2070
2071         if (udc->dc_clk != NULL)
2072                 omap_udc_enable_clock(1);
2073
2074         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2075
2076         /* connect to bus through transceiver */
2077         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2078                 status = otg_set_peripheral(udc->transceiver->otg,
2079                                                 &udc->gadget);
2080                 if (status < 0) {
2081                         ERR("can't bind to transceiver\n");
2082                         if (driver->unbind) {
2083                                 driver->unbind(&udc->gadget);
2084                                 udc->driver = NULL;
2085                         }
2086                         goto done;
2087                 }
2088         } else {
2089                 if (can_pullup(udc))
2090                         pullup_enable(udc);
2091                 else
2092                         pullup_disable(udc);
2093         }
2094
2095         /* boards that don't have VBUS sensing can't autogate 48MHz;
2096          * can't enter deep sleep while a gadget driver is active.
2097          */
2098         if (machine_without_vbus_sense())
2099                 omap_vbus_session(&udc->gadget, 1);
2100
2101 done:
2102         if (udc->dc_clk != NULL)
2103                 omap_udc_enable_clock(0);
2104
2105         return status;
2106 }
2107
2108 static int omap_udc_stop(struct usb_gadget *g,
2109                 struct usb_gadget_driver *driver)
2110 {
2111         unsigned long   flags;
2112         int             status = -ENODEV;
2113
2114         if (udc->dc_clk != NULL)
2115                 omap_udc_enable_clock(1);
2116
2117         if (machine_without_vbus_sense())
2118                 omap_vbus_session(&udc->gadget, 0);
2119
2120         if (!IS_ERR_OR_NULL(udc->transceiver))
2121                 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2122         else
2123                 pullup_disable(udc);
2124
2125         spin_lock_irqsave(&udc->lock, flags);
2126         udc_quiesce(udc);
2127         spin_unlock_irqrestore(&udc->lock, flags);
2128
2129         udc->driver = NULL;
2130
2131         if (udc->dc_clk != NULL)
2132                 omap_udc_enable_clock(0);
2133
2134         return status;
2135 }
2136
2137 /*-------------------------------------------------------------------------*/
2138
2139 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2140
2141 #include <linux/seq_file.h>
2142
2143 static const char proc_filename[] = "driver/udc";
2144
2145 #define FOURBITS "%s%s%s%s"
2146 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2147
2148 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2149 {
2150         u16             stat_flg;
2151         struct omap_req *req;
2152         char            buf[20];
2153
2154         use_ep(ep, 0);
2155
2156         if (use_dma && ep->has_dma)
2157                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2158                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2159                         ep->dma_channel - 1, ep->lch);
2160         else
2161                 buf[0] = 0;
2162
2163         stat_flg = omap_readw(UDC_STAT_FLG);
2164         seq_printf(s,
2165                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2166                 ep->name, buf,
2167                 ep->double_buf ? "dbuf " : "",
2168                 ({ char *s;
2169                 switch (ep->ackwait) {
2170                 case 0:
2171                         s = "";
2172                         break;
2173                 case 1:
2174                         s = "(ackw) ";
2175                         break;
2176                 case 2:
2177                         s = "(ackw2) ";
2178                         break;
2179                 default:
2180                         s = "(?) ";
2181                         break;
2182                 } s; }),
2183                 ep->irqs, stat_flg,
2184                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2185                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2186                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2187                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2188                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2189                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2190                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2191                 (stat_flg & UDC_STALL) ? "STALL " : "",
2192                 (stat_flg & UDC_NAK) ? "NAK " : "",
2193                 (stat_flg & UDC_ACK) ? "ACK " : "",
2194                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2195                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2196                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2197
2198         if (list_empty(&ep->queue))
2199                 seq_printf(s, "\t(queue empty)\n");
2200         else
2201                 list_for_each_entry(req, &ep->queue, queue) {
2202                         unsigned        length = req->req.actual;
2203
2204                         if (use_dma && buf[0]) {
2205                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2206                                                 ? dma_src_len : dma_dest_len)
2207                                         (ep, req->req.dma + length);
2208                                 buf[0] = 0;
2209                         }
2210                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2211                                         &req->req, length,
2212                                         req->req.length, req->req.buf);
2213                 }
2214 }
2215
2216 static char *trx_mode(unsigned m, int enabled)
2217 {
2218         switch (m) {
2219         case 0:
2220                 return enabled ? "*6wire" : "unused";
2221         case 1:
2222                 return "4wire";
2223         case 2:
2224                 return "3wire";
2225         case 3:
2226                 return "6wire";
2227         default:
2228                 return "unknown";
2229         }
2230 }
2231
2232 static int proc_otg_show(struct seq_file *s)
2233 {
2234         u32             tmp;
2235         u32             trans = 0;
2236         char            *ctrl_name = "(UNKNOWN)";
2237
2238         tmp = omap_readl(OTG_REV);
2239         ctrl_name = "tranceiver_ctrl";
2240         trans = omap_readw(USB_TRANSCEIVER_CTRL);
2241         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2242                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2243         tmp = omap_readw(OTG_SYSCON_1);
2244         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2245                         FOURBITS "\n", tmp,
2246                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2247                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2248                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2249                         ? "internal"
2250                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2251                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2252                 (tmp & HST_IDLE_EN) ? " !host" : "",
2253                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2254                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2255         tmp = omap_readl(OTG_SYSCON_2);
2256         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2257                         " b_ase_brst=%d hmc=%d\n", tmp,
2258                 (tmp & OTG_EN) ? " otg_en" : "",
2259                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2260                 /* much more SRP stuff */
2261                 (tmp & SRP_DATA) ? " srp_data" : "",
2262                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2263                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2264                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2265                 (tmp & UHOST_EN) ? " uhost_en" : "",
2266                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2267                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2268                 B_ASE_BRST(tmp),
2269                 OTG_HMC(tmp));
2270         tmp = omap_readl(OTG_CTRL);
2271         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2272                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2273                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2274                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2275                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2276                 (tmp & OTG_ID) ? " id" : "",
2277                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2278                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2279                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2280                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2281                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2282                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2283                 (tmp & OTG_PULLDOWN) ? " down" : "",
2284                 (tmp & OTG_PULLUP) ? " up" : "",
2285                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2286                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2287                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2288                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2289                 );
2290         tmp = omap_readw(OTG_IRQ_EN);
2291         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2292         tmp = omap_readw(OTG_IRQ_SRC);
2293         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2294         tmp = omap_readw(OTG_OUTCTRL);
2295         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2296         tmp = omap_readw(OTG_TEST);
2297         seq_printf(s, "otg_test    %04x" "\n", tmp);
2298         return 0;
2299 }
2300
2301 static int proc_udc_show(struct seq_file *s, void *_)
2302 {
2303         u32             tmp;
2304         struct omap_ep  *ep;
2305         unsigned long   flags;
2306
2307         spin_lock_irqsave(&udc->lock, flags);
2308
2309         seq_printf(s, "%s, version: " DRIVER_VERSION
2310 #ifdef  USE_ISO
2311                 " (iso)"
2312 #endif
2313                 "%s\n",
2314                 driver_desc,
2315                 use_dma ?  " (dma)" : "");
2316
2317         tmp = omap_readw(UDC_REV) & 0xff;
2318         seq_printf(s,
2319                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2320                 "hmc %d, transceiver %s\n",
2321                 tmp >> 4, tmp & 0xf,
2322                 fifo_mode,
2323                 udc->driver ? udc->driver->driver.name : "(none)",
2324                 HMC,
2325                 udc->transceiver
2326                         ? udc->transceiver->label
2327                         : (cpu_is_omap1710()
2328                                 ? "external" : "(none)"));
2329         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2330                 omap_readw(ULPD_CLOCK_CTRL),
2331                 omap_readw(ULPD_SOFT_REQ),
2332                 omap_readw(ULPD_STATUS_REQ));
2333
2334         /* OTG controller registers */
2335         if (!cpu_is_omap15xx())
2336                 proc_otg_show(s);
2337
2338         tmp = omap_readw(UDC_SYSCON1);
2339         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2340                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2341                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2342                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2343                 (tmp & UDC_NAK_EN) ? " nak" : "",
2344                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2345                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2346                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2347                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2348         /* syscon2 is write-only */
2349
2350         /* UDC controller registers */
2351         if (!(tmp & UDC_PULLUP_EN)) {
2352                 seq_printf(s, "(suspended)\n");
2353                 spin_unlock_irqrestore(&udc->lock, flags);
2354                 return 0;
2355         }
2356
2357         tmp = omap_readw(UDC_DEVSTAT);
2358         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2359                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2360                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2361                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2362                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2363                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2364                 (tmp & UDC_SUS) ? " SUS" : "",
2365                 (tmp & UDC_CFG) ? " CFG" : "",
2366                 (tmp & UDC_ADD) ? " ADD" : "",
2367                 (tmp & UDC_DEF) ? " DEF" : "",
2368                 (tmp & UDC_ATT) ? " ATT" : "");
2369         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2370         tmp = omap_readw(UDC_IRQ_EN);
2371         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2372                 (tmp & UDC_SOF_IE) ? " sof" : "",
2373                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2374                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2375                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2376                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2377         tmp = omap_readw(UDC_IRQ_SRC);
2378         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2379                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2380                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2381                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2382                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2383                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2384                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2385                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2386                 (tmp & UDC_SETUP) ? " setup" : "",
2387                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2388                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2389         if (use_dma) {
2390                 unsigned i;
2391
2392                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2393                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2394                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2395                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2396                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2397
2398                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2399                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2400                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2401
2402                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2403                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2404                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2405
2406                 tmp = omap_readw(UDC_RXDMA_CFG);
2407                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2408                 if (tmp) {
2409                         for (i = 0; i < 3; i++) {
2410                                 if ((tmp & (0x0f << (i * 4))) == 0)
2411                                         continue;
2412                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2413                                                 omap_readw(UDC_RXDMA(i + 1)));
2414                         }
2415                 }
2416                 tmp = omap_readw(UDC_TXDMA_CFG);
2417                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2418                 if (tmp) {
2419                         for (i = 0; i < 3; i++) {
2420                                 if (!(tmp & (0x0f << (i * 4))))
2421                                         continue;
2422                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2423                                                 omap_readw(UDC_TXDMA(i + 1)));
2424                         }
2425                 }
2426         }
2427
2428         tmp = omap_readw(UDC_DEVSTAT);
2429         if (tmp & UDC_ATT) {
2430                 proc_ep_show(s, &udc->ep[0]);
2431                 if (tmp & UDC_ADD) {
2432                         list_for_each_entry(ep, &udc->gadget.ep_list,
2433                                         ep.ep_list) {
2434                                 if (ep->ep.desc)
2435                                         proc_ep_show(s, ep);
2436                         }
2437                 }
2438         }
2439         spin_unlock_irqrestore(&udc->lock, flags);
2440         return 0;
2441 }
2442
2443 static int proc_udc_open(struct inode *inode, struct file *file)
2444 {
2445         return single_open(file, proc_udc_show, NULL);
2446 }
2447
2448 static const struct file_operations proc_ops = {
2449         .owner          = THIS_MODULE,
2450         .open           = proc_udc_open,
2451         .read           = seq_read,
2452         .llseek         = seq_lseek,
2453         .release        = single_release,
2454 };
2455
2456 static void create_proc_file(void)
2457 {
2458         proc_create(proc_filename, 0, NULL, &proc_ops);
2459 }
2460
2461 static void remove_proc_file(void)
2462 {
2463         remove_proc_entry(proc_filename, NULL);
2464 }
2465
2466 #else
2467
2468 static inline void create_proc_file(void) {}
2469 static inline void remove_proc_file(void) {}
2470
2471 #endif
2472
2473 /*-------------------------------------------------------------------------*/
2474
2475 /* Before this controller can enumerate, we need to pick an endpoint
2476  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2477  * buffer space among the endpoints we'll be operating.
2478  *
2479  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2480  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2481  * capability yet though.
2482  */
2483 static unsigned
2484 omap_ep_setup(char *name, u8 addr, u8 type,
2485                 unsigned buf, unsigned maxp, int dbuf)
2486 {
2487         struct omap_ep  *ep;
2488         u16             epn_rxtx = 0;
2489
2490         /* OUT endpoints first, then IN */
2491         ep = &udc->ep[addr & 0xf];
2492         if (addr & USB_DIR_IN)
2493                 ep += 16;
2494
2495         /* in case of ep init table bugs */
2496         BUG_ON(ep->name[0]);
2497
2498         /* chip setup ... bit values are same for IN, OUT */
2499         if (type == USB_ENDPOINT_XFER_ISOC) {
2500                 switch (maxp) {
2501                 case 8:
2502                         epn_rxtx = 0 << 12;
2503                         break;
2504                 case 16:
2505                         epn_rxtx = 1 << 12;
2506                         break;
2507                 case 32:
2508                         epn_rxtx = 2 << 12;
2509                         break;
2510                 case 64:
2511                         epn_rxtx = 3 << 12;
2512                         break;
2513                 case 128:
2514                         epn_rxtx = 4 << 12;
2515                         break;
2516                 case 256:
2517                         epn_rxtx = 5 << 12;
2518                         break;
2519                 case 512:
2520                         epn_rxtx = 6 << 12;
2521                         break;
2522                 default:
2523                         BUG();
2524                 }
2525                 epn_rxtx |= UDC_EPN_RX_ISO;
2526                 dbuf = 1;
2527         } else {
2528                 /* double-buffering "not supported" on 15xx,
2529                  * and ignored for PIO-IN on newer chips
2530                  * (for more reliable behavior)
2531                  */
2532                 if (!use_dma || cpu_is_omap15xx())
2533                         dbuf = 0;
2534
2535                 switch (maxp) {
2536                 case 8:
2537                         epn_rxtx = 0 << 12;
2538                         break;
2539                 case 16:
2540                         epn_rxtx = 1 << 12;
2541                         break;
2542                 case 32:
2543                         epn_rxtx = 2 << 12;
2544                         break;
2545                 case 64:
2546                         epn_rxtx = 3 << 12;
2547                         break;
2548                 default:
2549                         BUG();
2550                 }
2551                 if (dbuf && addr)
2552                         epn_rxtx |= UDC_EPN_RX_DB;
2553                 init_timer(&ep->timer);
2554                 ep->timer.function = pio_out_timer;
2555                 ep->timer.data = (unsigned long) ep;
2556         }
2557         if (addr)
2558                 epn_rxtx |= UDC_EPN_RX_VALID;
2559         BUG_ON(buf & 0x07);
2560         epn_rxtx |= buf >> 3;
2561
2562         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2563                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2564
2565         if (addr & USB_DIR_IN)
2566                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2567         else
2568                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2569
2570         /* next endpoint's buffer starts after this one's */
2571         buf += maxp;
2572         if (dbuf)
2573                 buf += maxp;
2574         BUG_ON(buf > 2048);
2575
2576         /* set up driver data structures */
2577         BUG_ON(strlen(name) >= sizeof ep->name);
2578         strlcpy(ep->name, name, sizeof ep->name);
2579         INIT_LIST_HEAD(&ep->queue);
2580         INIT_LIST_HEAD(&ep->iso);
2581         ep->bEndpointAddress = addr;
2582         ep->bmAttributes = type;
2583         ep->double_buf = dbuf;
2584         ep->udc = udc;
2585
2586         ep->ep.name = ep->name;
2587         ep->ep.ops = &omap_ep_ops;
2588         ep->maxpacket = maxp;
2589         usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
2590         list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2591
2592         return buf;
2593 }
2594
2595 static void omap_udc_release(struct device *dev)
2596 {
2597         complete(udc->done);
2598         kfree(udc);
2599         udc = NULL;
2600 }
2601
2602 static int
2603 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2604 {
2605         unsigned        tmp, buf;
2606
2607         /* abolish any previous hardware state */
2608         omap_writew(0, UDC_SYSCON1);
2609         omap_writew(0, UDC_IRQ_EN);
2610         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2611         omap_writew(0, UDC_DMA_IRQ_EN);
2612         omap_writew(0, UDC_RXDMA_CFG);
2613         omap_writew(0, UDC_TXDMA_CFG);
2614
2615         /* UDC_PULLUP_EN gates the chip clock */
2616         /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2617
2618         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2619         if (!udc)
2620                 return -ENOMEM;
2621
2622         spin_lock_init(&udc->lock);
2623
2624         udc->gadget.ops = &omap_gadget_ops;
2625         udc->gadget.ep0 = &udc->ep[0].ep;
2626         INIT_LIST_HEAD(&udc->gadget.ep_list);
2627         INIT_LIST_HEAD(&udc->iso);
2628         udc->gadget.speed = USB_SPEED_UNKNOWN;
2629         udc->gadget.max_speed = USB_SPEED_FULL;
2630         udc->gadget.name = driver_name;
2631         udc->transceiver = xceiv;
2632
2633         /* ep0 is special; put it right after the SETUP buffer */
2634         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2635                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2636         list_del_init(&udc->ep[0].ep.ep_list);
2637
2638         /* initially disable all non-ep0 endpoints */
2639         for (tmp = 1; tmp < 15; tmp++) {
2640                 omap_writew(0, UDC_EP_RX(tmp));
2641                 omap_writew(0, UDC_EP_TX(tmp));
2642         }
2643
2644 #define OMAP_BULK_EP(name, addr) \
2645         buf = omap_ep_setup(name "-bulk", addr, \
2646                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2647 #define OMAP_INT_EP(name, addr, maxp) \
2648         buf = omap_ep_setup(name "-int", addr, \
2649                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2650 #define OMAP_ISO_EP(name, addr, maxp) \
2651         buf = omap_ep_setup(name "-iso", addr, \
2652                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2653
2654         switch (fifo_mode) {
2655         case 0:
2656                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2657                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2658                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2659                 break;
2660         case 1:
2661                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2662                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2663                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2664
2665                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2666                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2667                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2668
2669                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2670                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2671                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2672
2673                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2674                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2675                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2676
2677                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2678                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2679                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2680                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2681
2682                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2683                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2684                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2685                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2686
2687                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2688                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2689
2690                 break;
2691
2692 #ifdef  USE_ISO
2693         case 2:                 /* mixed iso/bulk */
2694                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2695                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2696                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2697                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2698
2699                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2700
2701                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2702                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2703                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2704                 break;
2705         case 3:                 /* mixed bulk/iso */
2706                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2707                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2708                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2709
2710                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2711                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2712                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2713
2714                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2715                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2716                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2717                 break;
2718 #endif
2719
2720         /* add more modes as needed */
2721
2722         default:
2723                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2724                 return -ENODEV;
2725         }
2726         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2727         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2728         return 0;
2729 }
2730
2731 static int omap_udc_probe(struct platform_device *pdev)
2732 {
2733         int                     status = -ENODEV;
2734         int                     hmc;
2735         struct usb_phy          *xceiv = NULL;
2736         const char              *type = NULL;
2737         struct omap_usb_config  *config = dev_get_platdata(&pdev->dev);
2738         struct clk              *dc_clk = NULL;
2739         struct clk              *hhc_clk = NULL;
2740
2741         if (cpu_is_omap7xx())
2742                 use_dma = 0;
2743
2744         /* NOTE:  "knows" the order of the resources! */
2745         if (!request_mem_region(pdev->resource[0].start,
2746                         pdev->resource[0].end - pdev->resource[0].start + 1,
2747                         driver_name)) {
2748                 DBG("request_mem_region failed\n");
2749                 return -EBUSY;
2750         }
2751
2752         if (cpu_is_omap16xx()) {
2753                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2754                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2755                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2756                 /* can't use omap_udc_enable_clock yet */
2757                 clk_enable(dc_clk);
2758                 clk_enable(hhc_clk);
2759                 udelay(100);
2760         }
2761
2762         if (cpu_is_omap7xx()) {
2763                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2764                 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2765                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2766                 /* can't use omap_udc_enable_clock yet */
2767                 clk_enable(dc_clk);
2768                 clk_enable(hhc_clk);
2769                 udelay(100);
2770         }
2771
2772         INFO("OMAP UDC rev %d.%d%s\n",
2773                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2774                 config->otg ? ", Mini-AB" : "");
2775
2776         /* use the mode given to us by board init code */
2777         if (cpu_is_omap15xx()) {
2778                 hmc = HMC_1510;
2779                 type = "(unknown)";
2780
2781                 if (machine_without_vbus_sense()) {
2782                         /* just set up software VBUS detect, and then
2783                          * later rig it so we always report VBUS.
2784                          * FIXME without really sensing VBUS, we can't
2785                          * know when to turn PULLUP_EN on/off; and that
2786                          * means we always "need" the 48MHz clock.
2787                          */
2788                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2789                         tmp &= ~VBUS_CTRL_1510;
2790                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2791                         tmp |= VBUS_MODE_1510;
2792                         tmp &= ~VBUS_CTRL_1510;
2793                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2794                 }
2795         } else {
2796                 /* The transceiver may package some GPIO logic or handle
2797                  * loopback and/or transceiverless setup; if we find one,
2798                  * use it.  Except for OTG, we don't _need_ to talk to one;
2799                  * but not having one probably means no VBUS detection.
2800                  */
2801                 xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
2802                 if (!IS_ERR_OR_NULL(xceiv))
2803                         type = xceiv->label;
2804                 else if (config->otg) {
2805                         DBG("OTG requires external transceiver!\n");
2806                         goto cleanup0;
2807                 }
2808
2809                 hmc = HMC_1610;
2810
2811                 switch (hmc) {
2812                 case 0:                 /* POWERUP DEFAULT == 0 */
2813                 case 4:
2814                 case 12:
2815                 case 20:
2816                         if (!cpu_is_omap1710()) {
2817                                 type = "integrated";
2818                                 break;
2819                         }
2820                         /* FALL THROUGH */
2821                 case 3:
2822                 case 11:
2823                 case 16:
2824                 case 19:
2825                 case 25:
2826                         if (IS_ERR_OR_NULL(xceiv)) {
2827                                 DBG("external transceiver not registered!\n");
2828                                 type = "unknown";
2829                         }
2830                         break;
2831                 case 21:                        /* internal loopback */
2832                         type = "loopback";
2833                         break;
2834                 case 14:                        /* transceiverless */
2835                         if (cpu_is_omap1710())
2836                                 goto bad_on_1710;
2837                         /* FALL THROUGH */
2838                 case 13:
2839                 case 15:
2840                         type = "no";
2841                         break;
2842
2843                 default:
2844 bad_on_1710:
2845                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2846                         goto cleanup0;
2847                 }
2848         }
2849
2850         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2851
2852         /* a "gadget" abstracts/virtualizes the controller */
2853         status = omap_udc_setup(pdev, xceiv);
2854         if (status)
2855                 goto cleanup0;
2856
2857         xceiv = NULL;
2858         /* "udc" is now valid */
2859         pullup_disable(udc);
2860 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2861         udc->gadget.is_otg = (config->otg != 0);
2862 #endif
2863
2864         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2865         if (omap_readw(UDC_REV) >= 0x61)
2866                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2867         else
2868                 udc->clr_halt = UDC_RESET_EP;
2869
2870         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2871         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2872                         0, driver_name, udc);
2873         if (status != 0) {
2874                 ERR("can't get irq %d, err %d\n",
2875                         (int) pdev->resource[1].start, status);
2876                 goto cleanup1;
2877         }
2878
2879         /* USB "non-iso" IRQ (PIO for all but ep0) */
2880         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2881                         0, "omap_udc pio", udc);
2882         if (status != 0) {
2883                 ERR("can't get irq %d, err %d\n",
2884                         (int) pdev->resource[2].start, status);
2885                 goto cleanup2;
2886         }
2887 #ifdef  USE_ISO
2888         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2889                         0, "omap_udc iso", udc);
2890         if (status != 0) {
2891                 ERR("can't get irq %d, err %d\n",
2892                         (int) pdev->resource[3].start, status);
2893                 goto cleanup3;
2894         }
2895 #endif
2896         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2897                 udc->dc_clk = dc_clk;
2898                 udc->hhc_clk = hhc_clk;
2899                 clk_disable(hhc_clk);
2900                 clk_disable(dc_clk);
2901         }
2902
2903         create_proc_file();
2904         status = usb_add_gadget_udc_release(&pdev->dev, &udc->gadget,
2905                         omap_udc_release);
2906         if (status)
2907                 goto cleanup4;
2908
2909         return 0;
2910
2911 cleanup4:
2912         remove_proc_file();
2913
2914 #ifdef  USE_ISO
2915 cleanup3:
2916         free_irq(pdev->resource[2].start, udc);
2917 #endif
2918
2919 cleanup2:
2920         free_irq(pdev->resource[1].start, udc);
2921
2922 cleanup1:
2923         kfree(udc);
2924         udc = NULL;
2925
2926 cleanup0:
2927         if (!IS_ERR_OR_NULL(xceiv))
2928                 usb_put_phy(xceiv);
2929
2930         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2931                 clk_disable(hhc_clk);
2932                 clk_disable(dc_clk);
2933                 clk_put(hhc_clk);
2934                 clk_put(dc_clk);
2935         }
2936
2937         release_mem_region(pdev->resource[0].start,
2938                         pdev->resource[0].end - pdev->resource[0].start + 1);
2939
2940         return status;
2941 }
2942
2943 static int omap_udc_remove(struct platform_device *pdev)
2944 {
2945         DECLARE_COMPLETION_ONSTACK(done);
2946
2947         if (!udc)
2948                 return -ENODEV;
2949
2950         usb_del_gadget_udc(&udc->gadget);
2951         if (udc->driver)
2952                 return -EBUSY;
2953
2954         udc->done = &done;
2955
2956         pullup_disable(udc);
2957         if (!IS_ERR_OR_NULL(udc->transceiver)) {
2958                 usb_put_phy(udc->transceiver);
2959                 udc->transceiver = NULL;
2960         }
2961         omap_writew(0, UDC_SYSCON1);
2962
2963         remove_proc_file();
2964
2965 #ifdef  USE_ISO
2966         free_irq(pdev->resource[3].start, udc);
2967 #endif
2968         free_irq(pdev->resource[2].start, udc);
2969         free_irq(pdev->resource[1].start, udc);
2970
2971         if (udc->dc_clk) {
2972                 if (udc->clk_requested)
2973                         omap_udc_enable_clock(0);
2974                 clk_put(udc->hhc_clk);
2975                 clk_put(udc->dc_clk);
2976         }
2977
2978         release_mem_region(pdev->resource[0].start,
2979                         pdev->resource[0].end - pdev->resource[0].start + 1);
2980
2981         wait_for_completion(&done);
2982
2983         return 0;
2984 }
2985
2986 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2987  * system is forced into deep sleep
2988  *
2989  * REVISIT we should probably reject suspend requests when there's a host
2990  * session active, rather than disconnecting, at least on boards that can
2991  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
2992  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2993  * may involve talking to an external transceiver (e.g. isp1301).
2994  */
2995
2996 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
2997 {
2998         u32     devstat;
2999
3000         devstat = omap_readw(UDC_DEVSTAT);
3001
3002         /* we're requesting 48 MHz clock if the pullup is enabled
3003          * (== we're attached to the host) and we're not suspended,
3004          * which would prevent entry to deep sleep...
3005          */
3006         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3007                 WARNING("session active; suspend requires disconnect\n");
3008                 omap_pullup(&udc->gadget, 0);
3009         }
3010
3011         return 0;
3012 }
3013
3014 static int omap_udc_resume(struct platform_device *dev)
3015 {
3016         DBG("resume + wakeup/SRP\n");
3017         omap_pullup(&udc->gadget, 1);
3018
3019         /* maybe the host would enumerate us if we nudged it */
3020         msleep(100);
3021         return omap_wakeup(&udc->gadget);
3022 }
3023
3024 /*-------------------------------------------------------------------------*/
3025
3026 static struct platform_driver udc_driver = {
3027         .probe          = omap_udc_probe,
3028         .remove         = omap_udc_remove,
3029         .suspend        = omap_udc_suspend,
3030         .resume         = omap_udc_resume,
3031         .driver         = {
3032                 .owner  = THIS_MODULE,
3033                 .name   = (char *) driver_name,
3034         },
3035 };
3036
3037 module_platform_driver(udc_driver);
3038
3039 MODULE_DESCRIPTION(DRIVER_DESC);
3040 MODULE_LICENSE("GPL");
3041 MODULE_ALIAS("platform:omap_udc");