Pileus Git - ~andy/linux/blob - drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #undef  DEBUG
  16 #undef  VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/timer.h>
  27 #include <linux/list.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/proc_fs.h>
  30 #include <linux/mm.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/usb/ch9.h>
  34 #include <linux/usb/gadget.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/clk.h>
  38 #include <linux/prefetch.h>
  39
  40 #include <asm/byteorder.h>
  41 #include <asm/io.h>
  42 #include <asm/irq.h>
  43 #include <asm/unaligned.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <plat/dma.h>
  47 #include <plat/usb.h>
  48
  49 #include "omap_udc.h"
  50
  51 #undef  USB_TRACE
  52
  53 /* bulk DMA seems to be behaving for both IN and OUT */
  54 #define USE_DMA
  55
  56 /* ISO too */
  57 #define USE_ISO
  58
  59 #define DRIVER_DESC     "OMAP UDC driver"
  60 #define DRIVER_VERSION  "4 October 2004"
  61
  62 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  63
  64 #define OMAP2_DMA_CH(ch)        (((ch) - 1) << 1)
  65 #define OMAP24XX_DMA(name, ch)  (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
  66
  67 /*
  68  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  69  * D+ pullup to allow enumeration.  That's too early for the gadget
  70  * framework to use from usb_endpoint_enable(), which happens after
  71  * enumeration as part of activating an interface.  (But if we add an
  72  * optional new "UDC not yet running" state to the gadget driver model,
  73  * even just during driver binding, the endpoint autoconfig logic is the
  74  * natural spot to manufacture new endpoints.)
  75  *
  76  * So instead of using endpoint enable calls to control the hardware setup,
  77  * this driver defines a "fifo mode" parameter.  It's used during driver
  78  * initialization to choose among a set of pre-defined endpoint configs.
  79  * See omap_udc_setup() for available modes, or to add others.  That code
  80  * lives in an init section, so use this driver as a module if you need
  81  * to change the fifo mode after the kernel boots.
  82  *
  83  * Gadget drivers normally ignore endpoints they don't care about, and
  84  * won't include them in configuration descriptors.  That means only
  85  * misbehaving hosts would even notice they exist.
  86  */
  87 #ifdef  USE_ISO
  88 static unsigned fifo_mode = 3;
  89 #else
  90 static unsigned fifo_mode = 0;
  91 #endif
  92
  93 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
  94  * boot parameter "omap_udc:fifo_mode=42"
  95  */
  96 module_param (fifo_mode, uint, 0);
  97 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
  98
  99 #ifdef  USE_DMA
 100 static bool use_dma = 1;
 101
 102 /* "modprobe omap_udc use_dma=y", or else as a kernel
 103  * boot parameter "omap_udc:use_dma=y"
 104  */
 105 module_param (use_dma, bool, 0);
 106 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 107 #else   /* !USE_DMA */
 108
 109 /* save a bit of code */
 110 #define use_dma         0
 111 #endif  /* !USE_DMA */
 112
 113
 114 static const char driver_name [] = "omap_udc";
 115 static const char driver_desc [] = DRIVER_DESC;
 116
 117 /*-------------------------------------------------------------------------*/
 118
 119 /* there's a notion of "current endpoint" for modifying endpoint
 120  * state, and PIO access to its FIFO.
 121  */
 122
 123 static void use_ep(struct omap_ep *ep, u16 select)
 124 {
 125         u16     num = ep->bEndpointAddress & 0x0f;
 126
 127         if (ep->bEndpointAddress & USB_DIR_IN)
 128                 num |= UDC_EP_DIR;
 129         omap_writew(num | select, UDC_EP_NUM);
 130         /* when select, MUST deselect later !! */
 131 }
 132
 133 static inline void deselect_ep(void)
 134 {
 135         u16 w;
 136
 137         w = omap_readw(UDC_EP_NUM);
 138         w &= ~UDC_EP_SEL;
 139         omap_writew(w, UDC_EP_NUM);
 140         /* 6 wait states before TX will happen */
 141 }
 142
 143 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 144
 145 /*-------------------------------------------------------------------------*/
 146
 147 static int omap_ep_enable(struct usb_ep *_ep,
 148                 const struct usb_endpoint_descriptor *desc)
 149 {
 150         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 151         struct omap_udc *udc;
 152         unsigned long   flags;
 153         u16             maxp;
 154
 155         /* catch various bogus parameters */
 156         if (!_ep || !desc || ep->ep.desc
 157                         || desc->bDescriptorType != USB_DT_ENDPOINT
 158                         || ep->bEndpointAddress != desc->bEndpointAddress
 159                         || ep->maxpacket < usb_endpoint_maxp(desc)) {
 160                 DBG("%s, bad ep or descriptor\n", __func__);
 161                 return -EINVAL;
 162         }
 163         maxp = usb_endpoint_maxp(desc);
 164         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 165                                 && maxp != ep->maxpacket)
 166                         || usb_endpoint_maxp(desc) > ep->maxpacket
 167                         || !desc->wMaxPacketSize) {
 168                 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
 169                 return -ERANGE;
 170         }
 171
 172 #ifdef  USE_ISO
 173         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 174                                 && desc->bInterval != 1)) {
 175                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 176                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 177                                 1 << (desc->bInterval - 1));
 178                 return -EDOM;
 179         }
 180 #else
 181         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 182                 DBG("%s, ISO nyet\n", _ep->name);
 183                 return -EDOM;
 184         }
 185 #endif
 186
 187         /* xfer types must match, except that interrupt ~= bulk */
 188         if (ep->bmAttributes != desc->bmAttributes
 189                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 190                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 191                 DBG("%s, %s type mismatch\n", __func__, _ep->name);
 192                 return -EINVAL;
 193         }
 194
 195         udc = ep->udc;
 196         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 197                 DBG("%s, bogus device state\n", __func__);
 198                 return -ESHUTDOWN;
 199         }
 200
 201         spin_lock_irqsave(&udc->lock, flags);
 202
 203         ep->ep.desc = desc;
 204         ep->irqs = 0;
 205         ep->stopped = 0;
 206         ep->ep.maxpacket = maxp;
 207
 208         /* set endpoint to initial state */
 209         ep->dma_channel = 0;
 210         ep->has_dma = 0;
 211         ep->lch = -1;
 212         use_ep(ep, UDC_EP_SEL);
 213         omap_writew(udc->clr_halt, UDC_CTRL);
 214         ep->ackwait = 0;
 215         deselect_ep();
 216
 217         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 218                 list_add(&ep->iso, &udc->iso);
 219
 220         /* maybe assign a DMA channel to this endpoint */
 221         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 222                 /* FIXME ISO can dma, but prefers first channel */
 223                 dma_channel_claim(ep, 0);
 224
 225         /* PIO OUT may RX packets */
 226         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 227                         && !ep->has_dma
 228                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 229                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 230                 ep->ackwait = 1 + ep->double_buf;
 231         }
 232
 233         spin_unlock_irqrestore(&udc->lock, flags);
 234         VDBG("%s enabled\n", _ep->name);
 235         return 0;
 236 }
 237
 238 static void nuke(struct omap_ep *, int status);
 239
 240 static int omap_ep_disable(struct usb_ep *_ep)
 241 {
 242         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 243         unsigned long   flags;
 244
 245         if (!_ep || !ep->ep.desc) {
 246                 DBG("%s, %s not enabled\n", __func__,
 247                         _ep ? ep->ep.name : NULL);
 248                 return -EINVAL;
 249         }
 250
 251         spin_lock_irqsave(&ep->udc->lock, flags);
 252         ep->ep.desc = NULL;
 253         nuke (ep, -ESHUTDOWN);
 254         ep->ep.maxpacket = ep->maxpacket;
 255         ep->has_dma = 0;
 256         omap_writew(UDC_SET_HALT, UDC_CTRL);
 257         list_del_init(&ep->iso);
 258         del_timer(&ep->timer);
 259
 260         spin_unlock_irqrestore(&ep->udc->lock, flags);
 261
 262         VDBG("%s disabled\n", _ep->name);
 263         return 0;
 264 }
 265
 266 /*-------------------------------------------------------------------------*/
 267
 268 static struct usb_request *
 269 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 270 {
 271         struct omap_req *req;
 272
 273         req = kzalloc(sizeof(*req), gfp_flags);
 274         if (req) {
 275                 req->req.dma = DMA_ADDR_INVALID;
 276                 INIT_LIST_HEAD (&req->queue);
 277         }
 278         return &req->req;
 279 }
 280
 281 static void
 282 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 283 {
 284         struct omap_req *req = container_of(_req, struct omap_req, req);
 285
 286         if (_req)
 287                 kfree (req);
 288 }
 289
 290 /*-------------------------------------------------------------------------*/
 291
 292 static void
 293 done(struct omap_ep *ep, struct omap_req *req, int status)
 294 {
 295         unsigned                stopped = ep->stopped;
 296
 297         list_del_init(&req->queue);
 298
 299         if (req->req.status == -EINPROGRESS)
 300                 req->req.status = status;
 301         else
 302                 status = req->req.status;
 303
 304         if (use_dma && ep->has_dma) {
 305                 if (req->mapped) {
 306                         dma_unmap_single(ep->udc->gadget.dev.parent,
 307                                 req->req.dma, req->req.length,
 308                                 (ep->bEndpointAddress & USB_DIR_IN)
 309                                         ? DMA_TO_DEVICE
 310                                         : DMA_FROM_DEVICE);
 311                         req->req.dma = DMA_ADDR_INVALID;
 312                         req->mapped = 0;
 313                 } else
 314                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 315                                 req->req.dma, req->req.length,
 316                                 (ep->bEndpointAddress & USB_DIR_IN)
 317                                         ? DMA_TO_DEVICE
 318                                         : DMA_FROM_DEVICE);
 319         }
 320
 321 #ifndef USB_TRACE
 322         if (status && status != -ESHUTDOWN)
 323 #endif
 324                 VDBG("complete %s req %p stat %d len %u/%u\n",
 325                         ep->ep.name, &req->req, status,
 326                         req->req.actual, req->req.length);
 327
 328         /* don't modify queue heads during completion callback */
 329         ep->stopped = 1;
 330         spin_unlock(&ep->udc->lock);
 331         req->req.complete(&ep->ep, &req->req);
 332         spin_lock(&ep->udc->lock);
 333         ep->stopped = stopped;
 334 }
 335
 336 /*-------------------------------------------------------------------------*/
 337
 338 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 339 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 340
 341 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 342 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 343
 344 static inline int
 345 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 346 {
 347         unsigned        len;
 348         u16             *wp;
 349
 350         len = min(req->req.length - req->req.actual, max);
 351         req->req.actual += len;
 352
 353         max = len;
 354         if (likely((((int)buf) & 1) == 0)) {
 355                 wp = (u16 *)buf;
 356                 while (max >= 2) {
 357                         omap_writew(*wp++, UDC_DATA);
 358                         max -= 2;
 359                 }
 360                 buf = (u8 *)wp;
 361         }
 362         while (max--)
 363                 omap_writeb(*buf++, UDC_DATA);
 364         return len;
 365 }
 366
 367 // FIXME change r/w fifo calling convention
 368
 369
 370 // return:  0 = still running, 1 = completed, negative = errno
 371 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 372 {
 373         u8              *buf;
 374         unsigned        count;
 375         int             is_last;
 376         u16             ep_stat;
 377
 378         buf = req->req.buf + req->req.actual;
 379         prefetch(buf);
 380
 381         /* PIO-IN isn't double buffered except for iso */
 382         ep_stat = omap_readw(UDC_STAT_FLG);
 383         if (ep_stat & UDC_FIFO_UNWRITABLE)
 384                 return 0;
 385
 386         count = ep->ep.maxpacket;
 387         count = write_packet(buf, req, count);
 388         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 389         ep->ackwait = 1;
 390
 391         /* last packet is often short (sometimes a zlp) */
 392         if (count != ep->ep.maxpacket)
 393                 is_last = 1;
 394         else if (req->req.length == req->req.actual
 395                         && !req->req.zero)
 396                 is_last = 1;
 397         else
 398                 is_last = 0;
 399
 400         /* NOTE:  requests complete when all IN data is in a
 401          * FIFO (or sometimes later, if a zlp was needed).
 402          * Use usb_ep_fifo_status() where needed.
 403          */
 404         if (is_last)
 405                 done(ep, req, 0);
 406         return is_last;
 407 }
 408
 409 static inline int
 410 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 411 {
 412         unsigned        len;
 413         u16             *wp;
 414
 415         len = min(req->req.length - req->req.actual, avail);
 416         req->req.actual += len;
 417         avail = len;
 418
 419         if (likely((((int)buf) & 1) == 0)) {
 420                 wp = (u16 *)buf;
 421                 while (avail >= 2) {
 422                         *wp++ = omap_readw(UDC_DATA);
 423                         avail -= 2;
 424                 }
 425                 buf = (u8 *)wp;
 426         }
 427         while (avail--)
 428                 *buf++ = omap_readb(UDC_DATA);
 429         return len;
 430 }
 431
 432 // return:  0 = still running, 1 = queue empty, negative = errno
 433 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 434 {
 435         u8              *buf;
 436         unsigned        count, avail;
 437         int             is_last;
 438
 439         buf = req->req.buf + req->req.actual;
 440         prefetchw(buf);
 441
 442         for (;;) {
 443                 u16     ep_stat = omap_readw(UDC_STAT_FLG);
 444
 445                 is_last = 0;
 446                 if (ep_stat & FIFO_EMPTY) {
 447                         if (!ep->double_buf)
 448                                 break;
 449                         ep->fnf = 1;
 450                 }
 451                 if (ep_stat & UDC_EP_HALTED)
 452                         break;
 453
 454                 if (ep_stat & UDC_FIFO_FULL)
 455                         avail = ep->ep.maxpacket;
 456                 else  {
 457                         avail = omap_readw(UDC_RXFSTAT);
 458                         ep->fnf = ep->double_buf;
 459                 }
 460                 count = read_packet(buf, req, avail);
 461
 462                 /* partial packet reads may not be errors */
 463                 if (count < ep->ep.maxpacket) {
 464                         is_last = 1;
 465                         /* overflowed this request?  flush extra data */
 466                         if (count != avail) {
 467                                 req->req.status = -EOVERFLOW;
 468                                 avail -= count;
 469                                 while (avail--)
 470                                         omap_readw(UDC_DATA);
 471                         }
 472                 } else if (req->req.length == req->req.actual)
 473                         is_last = 1;
 474                 else
 475                         is_last = 0;
 476
 477                 if (!ep->bEndpointAddress)
 478                         break;
 479                 if (is_last)
 480                         done(ep, req, 0);
 481                 break;
 482         }
 483         return is_last;
 484 }
 485
 486 /*-------------------------------------------------------------------------*/
 487
 488 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 489 {
 490         dma_addr_t      end;
 491
 492         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 493          * the last transfer's bytecount by more than a FIFO's worth.
 494          */
 495         if (cpu_is_omap15xx())
 496                 return 0;
 497
 498         end = omap_get_dma_src_pos(ep->lch);
 499         if (end == ep->dma_counter)
 500                 return 0;
 501
 502         end |= start & (0xffff << 16);
 503         if (end < start)
 504                 end += 0x10000;
 505         return end - start;
 506 }
 507
 508 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 509 {
 510         dma_addr_t      end;
 511
 512         end = omap_get_dma_dst_pos(ep->lch);
 513         if (end == ep->dma_counter)
 514                 return 0;
 515
 516         end |= start & (0xffff << 16);
 517         if (cpu_is_omap15xx())
 518                 end++;
 519         if (end < start)
 520                 end += 0x10000;
 521         return end - start;
 522 }
 523
 524
 525 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 526  * When DMA completion isn't request completion, the UDC continues with
 527  * the next DMA transfer for that USB transfer.
 528  */
 529
 530 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 531 {
 532         u16             txdma_ctrl, w;
 533         unsigned        length = req->req.length - req->req.actual;
 534         const int       sync_mode = cpu_is_omap15xx()
 535                                 ? OMAP_DMA_SYNC_FRAME
 536                                 : OMAP_DMA_SYNC_ELEMENT;
 537         int             dma_trigger = 0;
 538
 539         if (cpu_is_omap24xx())
 540                 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
 541
 542         /* measure length in either bytes or packets */
 543         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 544                         || (cpu_is_omap24xx() && length < ep->maxpacket)
 545                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 546                 txdma_ctrl = UDC_TXN_EOT | length;
 547                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 548                                 length, 1, sync_mode, dma_trigger, 0);
 549         } else {
 550                 length = min(length / ep->maxpacket,
 551                                 (unsigned) UDC_TXN_TSC + 1);
 552                 txdma_ctrl = length;
 553                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 554                                 ep->ep.maxpacket >> 1, length, sync_mode,
 555                                 dma_trigger, 0);
 556                 length *= ep->maxpacket;
 557         }
 558         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 559                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 560                 0, 0);
 561
 562         omap_start_dma(ep->lch);
 563         ep->dma_counter = omap_get_dma_src_pos(ep->lch);
 564         w = omap_readw(UDC_DMA_IRQ_EN);
 565         w |= UDC_TX_DONE_IE(ep->dma_channel);
 566         omap_writew(w, UDC_DMA_IRQ_EN);
 567         omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
 568         req->dma_bytes = length;
 569 }
 570
 571 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 572 {
 573         u16 w;
 574
 575         if (status == 0) {
 576                 req->req.actual += req->dma_bytes;
 577
 578                 /* return if this request needs to send data or zlp */
 579                 if (req->req.actual < req->req.length)
 580                         return;
 581                 if (req->req.zero
 582                                 && req->dma_bytes != 0
 583                                 && (req->req.actual % ep->maxpacket) == 0)
 584                         return;
 585         } else
 586                 req->req.actual += dma_src_len(ep, req->req.dma
 587                                                         + req->req.actual);
 588
 589         /* tx completion */
 590         omap_stop_dma(ep->lch);
 591         w = omap_readw(UDC_DMA_IRQ_EN);
 592         w &= ~UDC_TX_DONE_IE(ep->dma_channel);
 593         omap_writew(w, UDC_DMA_IRQ_EN);
 594         done(ep, req, status);
 595 }
 596
 597 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 598 {
 599         unsigned packets = req->req.length - req->req.actual;
 600         int dma_trigger = 0;
 601         u16 w;
 602
 603         if (cpu_is_omap24xx())
 604                 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
 605
 606         /* NOTE:  we filtered out "short reads" before, so we know
 607          * the buffer has only whole numbers of packets.
 608          * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
 609          */
 610         if (cpu_is_omap24xx() && packets < ep->maxpacket) {
 611                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 612                                 packets, 1, OMAP_DMA_SYNC_ELEMENT,
 613                                 dma_trigger, 0);
 614                 req->dma_bytes = packets;
 615         } else {
 616                 /* set up this DMA transfer, enable the fifo, start */
 617                 packets /= ep->ep.maxpacket;
 618                 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 619                 req->dma_bytes = packets * ep->ep.maxpacket;
 620                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 621                                 ep->ep.maxpacket >> 1, packets,
 622                                 OMAP_DMA_SYNC_ELEMENT,
 623                                 dma_trigger, 0);
 624         }
 625         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 626                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 627                 0, 0);
 628         ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
 629
 630         omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
 631         w = omap_readw(UDC_DMA_IRQ_EN);
 632         w |= UDC_RX_EOT_IE(ep->dma_channel);
 633         omap_writew(w, UDC_DMA_IRQ_EN);
 634         omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
 635         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 636
 637         omap_start_dma(ep->lch);
 638 }
 639
 640 static void
 641 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 642 {
 643         u16     count, w;
 644
 645         if (status == 0)
 646                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 647         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 648         count += req->req.actual;
 649         if (one)
 650                 count--;
 651         if (count <= req->req.length)
 652                 req->req.actual = count;
 653
 654         if (count != req->dma_bytes || status)
 655                 omap_stop_dma(ep->lch);
 656
 657         /* if this wasn't short, request may need another transfer */
 658         else if (req->req.actual < req->req.length)
 659                 return;
 660
 661         /* rx completion */
 662         w = omap_readw(UDC_DMA_IRQ_EN);
 663         w &= ~UDC_RX_EOT_IE(ep->dma_channel);
 664         omap_writew(w, UDC_DMA_IRQ_EN);
 665         done(ep, req, status);
 666 }
 667
 668 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 669 {
 670         u16             dman_stat = omap_readw(UDC_DMAN_STAT);
 671         struct omap_ep  *ep;
 672         struct omap_req *req;
 673
 674         /* IN dma: tx to host */
 675         if (irq_src & UDC_TXN_DONE) {
 676                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 677                 ep->irqs++;
 678                 /* can see TXN_DONE after dma abort */
 679                 if (!list_empty(&ep->queue)) {
 680                         req = container_of(ep->queue.next,
 681                                                 struct omap_req, queue);
 682                         finish_in_dma(ep, req, 0);
 683                 }
 684                 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
 685
 686                 if (!list_empty (&ep->queue)) {
 687                         req = container_of(ep->queue.next,
 688                                         struct omap_req, queue);
 689                         next_in_dma(ep, req);
 690                 }
 691         }
 692
 693         /* OUT dma: rx from host */
 694         if (irq_src & UDC_RXN_EOT) {
 695                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 696                 ep->irqs++;
 697                 /* can see RXN_EOT after dma abort */
 698                 if (!list_empty(&ep->queue)) {
 699                         req = container_of(ep->queue.next,
 700                                         struct omap_req, queue);
 701                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 702                 }
 703                 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
 704
 705                 if (!list_empty (&ep->queue)) {
 706                         req = container_of(ep->queue.next,
 707                                         struct omap_req, queue);
 708                         next_out_dma(ep, req);
 709                 }
 710         }
 711
 712         if (irq_src & UDC_RXN_CNT) {
 713                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 714                 ep->irqs++;
 715                 /* omap15xx does this unasked... */
 716                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 717                 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
 718         }
 719 }
 720
 721 static void dma_error(int lch, u16 ch_status, void *data)
 722 {
 723         struct omap_ep  *ep = data;
 724
 725         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 726         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 727         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 728
 729         /* complete current transfer ... */
 730 }
 731
 732 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 733 {
 734         u16     reg;
 735         int     status, restart, is_in;
 736         int     dma_channel;
 737
 738         is_in = ep->bEndpointAddress & USB_DIR_IN;
 739         if (is_in)
 740                 reg = omap_readw(UDC_TXDMA_CFG);
 741         else
 742                 reg = omap_readw(UDC_RXDMA_CFG);
 743         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 744
 745         ep->dma_channel = 0;
 746         ep->lch = -1;
 747         if (channel == 0 || channel > 3) {
 748                 if ((reg & 0x0f00) == 0)
 749                         channel = 3;
 750                 else if ((reg & 0x00f0) == 0)
 751                         channel = 2;
 752                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 753                         channel = 1;
 754                 else {
 755                         status = -EMLINK;
 756                         goto just_restart;
 757                 }
 758         }
 759         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 760         ep->dma_channel = channel;
 761
 762         if (is_in) {
 763                 if (cpu_is_omap24xx())
 764                         dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
 765                 else
 766                         dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
 767                 status = omap_request_dma(dma_channel,
 768                         ep->ep.name, dma_error, ep, &ep->lch);
 769                 if (status == 0) {
 770                         omap_writew(reg, UDC_TXDMA_CFG);
 771                         /* EMIFF or SDRC */
 772                         omap_set_dma_src_burst_mode(ep->lch,
 773                                                 OMAP_DMA_DATA_BURST_4);
 774                         omap_set_dma_src_data_pack(ep->lch, 1);
 775                         /* TIPB */
 776                         omap_set_dma_dest_params(ep->lch,
 777                                 OMAP_DMA_PORT_TIPB,
 778                                 OMAP_DMA_AMODE_CONSTANT,
 779                                 UDC_DATA_DMA,
 780                                 0, 0);
 781                 }
 782         } else {
 783                 if (cpu_is_omap24xx())
 784                         dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
 785                 else
 786                         dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
 787
 788                 status = omap_request_dma(dma_channel,
 789                         ep->ep.name, dma_error, ep, &ep->lch);
 790                 if (status == 0) {
 791                         omap_writew(reg, UDC_RXDMA_CFG);
 792                         /* TIPB */
 793                         omap_set_dma_src_params(ep->lch,
 794                                 OMAP_DMA_PORT_TIPB,
 795                                 OMAP_DMA_AMODE_CONSTANT,
 796                                 UDC_DATA_DMA,
 797                                 0, 0);
 798                         /* EMIFF or SDRC */
 799                         omap_set_dma_dest_burst_mode(ep->lch,
 800                                                 OMAP_DMA_DATA_BURST_4);
 801                         omap_set_dma_dest_data_pack(ep->lch, 1);
 802                 }
 803         }
 804         if (status)
 805                 ep->dma_channel = 0;
 806         else {
 807                 ep->has_dma = 1;
 808                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 809
 810                 /* channel type P: hw synch (fifo) */
 811                 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
 812                         omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
 813         }
 814
 815 just_restart:
 816         /* restart any queue, even if the claim failed  */
 817         restart = !ep->stopped && !list_empty(&ep->queue);
 818
 819         if (status)
 820                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 821                         restart ? " (restart)" : "");
 822         else
 823                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 824                         is_in ? 't' : 'r',
 825                         ep->dma_channel - 1, ep->lch,
 826                         restart ? " (restart)" : "");
 827
 828         if (restart) {
 829                 struct omap_req *req;
 830                 req = container_of(ep->queue.next, struct omap_req, queue);
 831                 if (ep->has_dma)
 832                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 833                 else {
 834                         use_ep(ep, UDC_EP_SEL);
 835                         (is_in ? write_fifo : read_fifo)(ep, req);
 836                         deselect_ep();
 837                         if (!is_in) {
 838                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
 839                                 ep->ackwait = 1 + ep->double_buf;
 840                         }
 841                         /* IN: 6 wait states before it'll tx */
 842                 }
 843         }
 844 }
 845
 846 static void dma_channel_release(struct omap_ep *ep)
 847 {
 848         int             shift = 4 * (ep->dma_channel - 1);
 849         u16             mask = 0x0f << shift;
 850         struct omap_req *req;
 851         int             active;
 852
 853         /* abort any active usb transfer request */
 854         if (!list_empty(&ep->queue))
 855                 req = container_of(ep->queue.next, struct omap_req, queue);
 856         else
 857                 req = NULL;
 858
 859         active = omap_get_dma_active_status(ep->lch);
 860
 861         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 862                         active ? "active" : "idle",
 863                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 864                         ep->dma_channel - 1, req);
 865
 866         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 867          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 868          */
 869
 870         /* wait till current packet DMA finishes, and fifo empties */
 871         if (ep->bEndpointAddress & USB_DIR_IN) {
 872                 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 873                                         UDC_TXDMA_CFG);
 874
 875                 if (req) {
 876                         finish_in_dma(ep, req, -ECONNRESET);
 877
 878                         /* clear FIFO; hosts probably won't empty it */
 879                         use_ep(ep, UDC_EP_SEL);
 880                         omap_writew(UDC_CLR_EP, UDC_CTRL);
 881                         deselect_ep();
 882                 }
 883                 while (omap_readw(UDC_TXDMA_CFG) & mask)
 884                         udelay(10);
 885         } else {
 886                 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
 887                                         UDC_RXDMA_CFG);
 888
 889                 /* dma empties the fifo */
 890                 while (omap_readw(UDC_RXDMA_CFG) & mask)
 891                         udelay(10);
 892                 if (req)
 893                         finish_out_dma(ep, req, -ECONNRESET, 0);
 894         }
 895         omap_free_dma(ep->lch);
 896         ep->dma_channel = 0;
 897         ep->lch = -1;
 898         /* has_dma still set, till endpoint is fully quiesced */
 899 }
 900
 901
 902 /*-------------------------------------------------------------------------*/
 903
 904 static int
 905 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 906 {
 907         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 908         struct omap_req *req = container_of(_req, struct omap_req, req);
 909         struct omap_udc *udc;
 910         unsigned long   flags;
 911         int             is_iso = 0;
 912
 913         /* catch various bogus parameters */
 914         if (!_req || !req->req.complete || !req->req.buf
 915                         || !list_empty(&req->queue)) {
 916                 DBG("%s, bad params\n", __func__);
 917                 return -EINVAL;
 918         }
 919         if (!_ep || (!ep->ep.desc && ep->bEndpointAddress)) {
 920                 DBG("%s, bad ep\n", __func__);
 921                 return -EINVAL;
 922         }
 923         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 924                 if (req->req.length > ep->ep.maxpacket)
 925                         return -EMSGSIZE;
 926                 is_iso = 1;
 927         }
 928
 929         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 930          * have a hard time with partial packet reads...  reject it.
 931          * Except OMAP2 can handle the small packets.
 932          */
 933         if (use_dma
 934                         && ep->has_dma
 935                         && ep->bEndpointAddress != 0
 936                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 937                         && !cpu_class_is_omap2()
 938                         && (req->req.length % ep->ep.maxpacket) != 0) {
 939                 DBG("%s, no partial packet OUT reads\n", __func__);
 940                 return -EMSGSIZE;
 941         }
 942
 943         udc = ep->udc;
 944         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 945                 return -ESHUTDOWN;
 946
 947         if (use_dma && ep->has_dma) {
 948                 if (req->req.dma == DMA_ADDR_INVALID) {
 949                         req->req.dma = dma_map_single(
 950                                 ep->udc->gadget.dev.parent,
 951                                 req->req.buf,
 952                                 req->req.length,
 953                                 (ep->bEndpointAddress & USB_DIR_IN)
 954                                         ? DMA_TO_DEVICE
 955                                         : DMA_FROM_DEVICE);
 956                         req->mapped = 1;
 957                 } else {
 958                         dma_sync_single_for_device(
 959                                 ep->udc->gadget.dev.parent,
 960                                 req->req.dma, req->req.length,
 961                                 (ep->bEndpointAddress & USB_DIR_IN)
 962                                         ? DMA_TO_DEVICE
 963                                         : DMA_FROM_DEVICE);
 964                         req->mapped = 0;
 965                 }
 966         }
 967
 968         VDBG("%s queue req %p, len %d buf %p\n",
 969                 ep->ep.name, _req, _req->length, _req->buf);
 970
 971         spin_lock_irqsave(&udc->lock, flags);
 972
 973         req->req.status = -EINPROGRESS;
 974         req->req.actual = 0;
 975
 976         /* maybe kickstart non-iso i/o queues */
 977         if (is_iso) {
 978                 u16 w;
 979
 980                 w = omap_readw(UDC_IRQ_EN);
 981                 w |= UDC_SOF_IE;
 982                 omap_writew(w, UDC_IRQ_EN);
 983         } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
 984                 int     is_in;
 985
 986                 if (ep->bEndpointAddress == 0) {
 987                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
 988                                 spin_unlock_irqrestore(&udc->lock, flags);
 989                                 return -EL2HLT;
 990                         }
 991
 992                         /* empty DATA stage? */
 993                         is_in = udc->ep0_in;
 994                         if (!req->req.length) {
 995
 996                                 /* chip became CONFIGURED or ADDRESSED
 997                                  * earlier; drivers may already have queued
 998                                  * requests to non-control endpoints
 999                                  */
1000                                 if (udc->ep0_set_config) {
1001                                         u16     irq_en = omap_readw(UDC_IRQ_EN);
1002
1003                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1004                                         if (!udc->ep0_reset_config)
1005                                                 irq_en |= UDC_EPN_RX_IE
1006                                                         | UDC_EPN_TX_IE;
1007                                         omap_writew(irq_en, UDC_IRQ_EN);
1008                                 }
1009
1010                                 /* STATUS for zero length DATA stages is
1011                                  * always an IN ... even for IN transfers,
1012                                  * a weird case which seem to stall OMAP.
1013                                  */
1014                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1015                                 omap_writew(UDC_CLR_EP, UDC_CTRL);
1016                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1017                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1018
1019                                 /* cleanup */
1020                                 udc->ep0_pending = 0;
1021                                 done(ep, req, 0);
1022                                 req = NULL;
1023
1024                         /* non-empty DATA stage */
1025                         } else if (is_in) {
1026                                 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1027                         } else {
1028                                 if (udc->ep0_setup)
1029                                         goto irq_wait;
1030                                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1031                         }
1032                 } else {
1033                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1034                         if (!ep->has_dma)
1035                                 use_ep(ep, UDC_EP_SEL);
1036                         /* if ISO: SOF IRQs must be enabled/disabled! */
1037                 }
1038
1039                 if (ep->has_dma)
1040                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1041                 else if (req) {
1042                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1043                                 req = NULL;
1044                         deselect_ep();
1045                         if (!is_in) {
1046                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1047                                 ep->ackwait = 1 + ep->double_buf;
1048                         }
1049                         /* IN: 6 wait states before it'll tx */
1050                 }
1051         }
1052
1053 irq_wait:
1054         /* irq handler advances the queue */
1055         if (req != NULL)
1056                 list_add_tail(&req->queue, &ep->queue);
1057         spin_unlock_irqrestore(&udc->lock, flags);
1058
1059         return 0;
1060 }
1061
1062 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1063 {
1064         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1065         struct omap_req *req;
1066         unsigned long   flags;
1067
1068         if (!_ep || !_req)
1069                 return -EINVAL;
1070
1071         spin_lock_irqsave(&ep->udc->lock, flags);
1072
1073         /* make sure it's actually queued on this endpoint */
1074         list_for_each_entry (req, &ep->queue, queue) {
1075                 if (&req->req == _req)
1076                         break;
1077         }
1078         if (&req->req != _req) {
1079                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1080                 return -EINVAL;
1081         }
1082
1083         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1084                 int channel = ep->dma_channel;
1085
1086                 /* releasing the channel cancels the request,
1087                  * reclaiming the channel restarts the queue
1088                  */
1089                 dma_channel_release(ep);
1090                 dma_channel_claim(ep, channel);
1091         } else
1092                 done(ep, req, -ECONNRESET);
1093         spin_unlock_irqrestore(&ep->udc->lock, flags);
1094         return 0;
1095 }
1096
1097 /*-------------------------------------------------------------------------*/
1098
1099 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1100 {
1101         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1102         unsigned long   flags;
1103         int             status = -EOPNOTSUPP;
1104
1105         spin_lock_irqsave(&ep->udc->lock, flags);
1106
1107         /* just use protocol stalls for ep0; real halts are annoying */
1108         if (ep->bEndpointAddress == 0) {
1109                 if (!ep->udc->ep0_pending)
1110                         status = -EINVAL;
1111                 else if (value) {
1112                         if (ep->udc->ep0_set_config) {
1113                                 WARNING("error changing config?\n");
1114                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1115                         }
1116                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1117                         ep->udc->ep0_pending = 0;
1118                         status = 0;
1119                 } else /* NOP */
1120                         status = 0;
1121
1122         /* otherwise, all active non-ISO endpoints can halt */
1123         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->ep.desc) {
1124
1125                 /* IN endpoints must already be idle */
1126                 if ((ep->bEndpointAddress & USB_DIR_IN)
1127                                 && !list_empty(&ep->queue)) {
1128                         status = -EAGAIN;
1129                         goto done;
1130                 }
1131
1132                 if (value) {
1133                         int     channel;
1134
1135                         if (use_dma && ep->dma_channel
1136                                         && !list_empty(&ep->queue)) {
1137                                 channel = ep->dma_channel;
1138                                 dma_channel_release(ep);
1139                         } else
1140                                 channel = 0;
1141
1142                         use_ep(ep, UDC_EP_SEL);
1143                         if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1144                                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1145                                 status = 0;
1146                         } else
1147                                 status = -EAGAIN;
1148                         deselect_ep();
1149
1150                         if (channel)
1151                                 dma_channel_claim(ep, channel);
1152                 } else {
1153                         use_ep(ep, 0);
1154                         omap_writew(ep->udc->clr_halt, UDC_CTRL);
1155                         ep->ackwait = 0;
1156                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1157                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1158                                 ep->ackwait = 1 + ep->double_buf;
1159                         }
1160                 }
1161         }
1162 done:
1163         VDBG("%s %s halt stat %d\n", ep->ep.name,
1164                 value ? "set" : "clear", status);
1165
1166         spin_unlock_irqrestore(&ep->udc->lock, flags);
1167         return status;
1168 }
1169
1170 static struct usb_ep_ops omap_ep_ops = {
1171         .enable         = omap_ep_enable,
1172         .disable        = omap_ep_disable,
1173
1174         .alloc_request  = omap_alloc_request,
1175         .free_request   = omap_free_request,
1176
1177         .queue          = omap_ep_queue,
1178         .dequeue        = omap_ep_dequeue,
1179
1180         .set_halt       = omap_ep_set_halt,
1181         // fifo_status ... report bytes in fifo
1182         // fifo_flush ... flush fifo
1183 };
1184
1185 /*-------------------------------------------------------------------------*/
1186
1187 static int omap_get_frame(struct usb_gadget *gadget)
1188 {
1189         u16     sof = omap_readw(UDC_SOF);
1190         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1191 }
1192
1193 static int omap_wakeup(struct usb_gadget *gadget)
1194 {
1195         struct omap_udc *udc;
1196         unsigned long   flags;
1197         int             retval = -EHOSTUNREACH;
1198
1199         udc = container_of(gadget, struct omap_udc, gadget);
1200
1201         spin_lock_irqsave(&udc->lock, flags);
1202         if (udc->devstat & UDC_SUS) {
1203                 /* NOTE:  OTG spec erratum says that OTG devices may
1204                  * issue wakeups without host enable.
1205                  */
1206                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1207                         DBG("remote wakeup...\n");
1208                         omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1209                         retval = 0;
1210                 }
1211
1212         /* NOTE:  non-OTG systems may use SRP TOO... */
1213         } else if (!(udc->devstat & UDC_ATT)) {
1214                 if (udc->transceiver)
1215                         retval = otg_start_srp(udc->transceiver->otg);
1216         }
1217         spin_unlock_irqrestore(&udc->lock, flags);
1218
1219         return retval;
1220 }
1221
1222 static int
1223 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1224 {
1225         struct omap_udc *udc;
1226         unsigned long   flags;
1227         u16             syscon1;
1228
1229         udc = container_of(gadget, struct omap_udc, gadget);
1230         spin_lock_irqsave(&udc->lock, flags);
1231         syscon1 = omap_readw(UDC_SYSCON1);
1232         if (is_selfpowered)
1233                 syscon1 |= UDC_SELF_PWR;
1234         else
1235                 syscon1 &= ~UDC_SELF_PWR;
1236         omap_writew(syscon1, UDC_SYSCON1);
1237         spin_unlock_irqrestore(&udc->lock, flags);
1238
1239         return 0;
1240 }
1241
1242 static int can_pullup(struct omap_udc *udc)
1243 {
1244         return udc->driver && udc->softconnect && udc->vbus_active;
1245 }
1246
1247 static void pullup_enable(struct omap_udc *udc)
1248 {
1249         u16 w;
1250
1251         w = omap_readw(UDC_SYSCON1);
1252         w |= UDC_PULLUP_EN;
1253         omap_writew(w, UDC_SYSCON1);
1254         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1255                 u32 l;
1256
1257                 l = omap_readl(OTG_CTRL);
1258                 l |= OTG_BSESSVLD;
1259                 omap_writel(l, OTG_CTRL);
1260         }
1261         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1262 }
1263
1264 static void pullup_disable(struct omap_udc *udc)
1265 {
1266         u16 w;
1267
1268         if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1269                 u32 l;
1270
1271                 l = omap_readl(OTG_CTRL);
1272                 l &= ~OTG_BSESSVLD;
1273                 omap_writel(l, OTG_CTRL);
1274         }
1275         omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1276         w = omap_readw(UDC_SYSCON1);
1277         w &= ~UDC_PULLUP_EN;
1278         omap_writew(w, UDC_SYSCON1);
1279 }
1280
1281 static struct omap_udc *udc;
1282
1283 static void omap_udc_enable_clock(int enable)
1284 {
1285         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1286                 return;
1287
1288         if (enable) {
1289                 clk_enable(udc->dc_clk);
1290                 clk_enable(udc->hhc_clk);
1291                 udelay(100);
1292         } else {
1293                 clk_disable(udc->hhc_clk);
1294                 clk_disable(udc->dc_clk);
1295         }
1296 }
1297
1298 /*
1299  * Called by whatever detects VBUS sessions:  external transceiver
1300  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1301  */
1302 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1303 {
1304         struct omap_udc *udc;
1305         unsigned long   flags;
1306         u32 l;
1307
1308         udc = container_of(gadget, struct omap_udc, gadget);
1309         spin_lock_irqsave(&udc->lock, flags);
1310         VDBG("VBUS %s\n", is_active ? "on" : "off");
1311         udc->vbus_active = (is_active != 0);
1312         if (cpu_is_omap15xx()) {
1313                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1314                 l = omap_readl(FUNC_MUX_CTRL_0);
1315                 if (is_active)
1316                         l |= VBUS_CTRL_1510;
1317                 else
1318                         l &= ~VBUS_CTRL_1510;
1319                 omap_writel(l, FUNC_MUX_CTRL_0);
1320         }
1321         if (udc->dc_clk != NULL && is_active) {
1322                 if (!udc->clk_requested) {
1323                         omap_udc_enable_clock(1);
1324                         udc->clk_requested = 1;
1325                 }
1326         }
1327         if (can_pullup(udc))
1328                 pullup_enable(udc);
1329         else
1330                 pullup_disable(udc);
1331         if (udc->dc_clk != NULL && !is_active) {
1332                 if (udc->clk_requested) {
1333                         omap_udc_enable_clock(0);
1334                         udc->clk_requested = 0;
1335                 }
1336         }
1337         spin_unlock_irqrestore(&udc->lock, flags);
1338         return 0;
1339 }
1340
1341 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1342 {
1343         struct omap_udc *udc;
1344
1345         udc = container_of(gadget, struct omap_udc, gadget);
1346         if (udc->transceiver)
1347                 return usb_phy_set_power(udc->transceiver, mA);
1348         return -EOPNOTSUPP;
1349 }
1350
1351 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1352 {
1353         struct omap_udc *udc;
1354         unsigned long   flags;
1355
1356         udc = container_of(gadget, struct omap_udc, gadget);
1357         spin_lock_irqsave(&udc->lock, flags);
1358         udc->softconnect = (is_on != 0);
1359         if (can_pullup(udc))
1360                 pullup_enable(udc);
1361         else
1362                 pullup_disable(udc);
1363         spin_unlock_irqrestore(&udc->lock, flags);
1364         return 0;
1365 }
1366
1367 static int omap_udc_start(struct usb_gadget_driver *driver,
1368                 int (*bind)(struct usb_gadget *));
1369 static int omap_udc_stop(struct usb_gadget_driver *driver);
1370
1371 static struct usb_gadget_ops omap_gadget_ops = {
1372         .get_frame              = omap_get_frame,
1373         .wakeup                 = omap_wakeup,
1374         .set_selfpowered        = omap_set_selfpowered,
1375         .vbus_session           = omap_vbus_session,
1376         .vbus_draw              = omap_vbus_draw,
1377         .pullup                 = omap_pullup,
1378         .start                  = omap_udc_start,
1379         .stop                   = omap_udc_stop,
1380 };
1381
1382 /*-------------------------------------------------------------------------*/
1383
1384 /* dequeue ALL requests; caller holds udc->lock */
1385 static void nuke(struct omap_ep *ep, int status)
1386 {
1387         struct omap_req *req;
1388
1389         ep->stopped = 1;
1390
1391         if (use_dma && ep->dma_channel)
1392                 dma_channel_release(ep);
1393
1394         use_ep(ep, 0);
1395         omap_writew(UDC_CLR_EP, UDC_CTRL);
1396         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1397                 omap_writew(UDC_SET_HALT, UDC_CTRL);
1398
1399         while (!list_empty(&ep->queue)) {
1400                 req = list_entry(ep->queue.next, struct omap_req, queue);
1401                 done(ep, req, status);
1402         }
1403 }
1404
1405 /* caller holds udc->lock */
1406 static void udc_quiesce(struct omap_udc *udc)
1407 {
1408         struct omap_ep  *ep;
1409
1410         udc->gadget.speed = USB_SPEED_UNKNOWN;
1411         nuke(&udc->ep[0], -ESHUTDOWN);
1412         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1413                 nuke(ep, -ESHUTDOWN);
1414 }
1415
1416 /*-------------------------------------------------------------------------*/
1417
1418 static void update_otg(struct omap_udc *udc)
1419 {
1420         u16     devstat;
1421
1422         if (!gadget_is_otg(&udc->gadget))
1423                 return;
1424
1425         if (omap_readl(OTG_CTRL) & OTG_ID)
1426                 devstat = omap_readw(UDC_DEVSTAT);
1427         else
1428                 devstat = 0;
1429
1430         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1431         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1432         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1433
1434         /* Enable HNP early, avoiding races on suspend irq path.
1435          * ASSUMES OTG state machine B_BUS_REQ input is true.
1436          */
1437         if (udc->gadget.b_hnp_enable) {
1438                 u32 l;
1439
1440                 l = omap_readl(OTG_CTRL);
1441                 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1442                 l &= ~OTG_PULLUP;
1443                 omap_writel(l, OTG_CTRL);
1444         }
1445 }
1446
1447 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1448 {
1449         struct omap_ep  *ep0 = &udc->ep[0];
1450         struct omap_req *req = NULL;
1451
1452         ep0->irqs++;
1453
1454         /* Clear any pending requests and then scrub any rx/tx state
1455          * before starting to handle the SETUP request.
1456          */
1457         if (irq_src & UDC_SETUP) {
1458                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1459
1460                 nuke(ep0, 0);
1461                 if (ack) {
1462                         omap_writew(ack, UDC_IRQ_SRC);
1463                         irq_src = UDC_SETUP;
1464                 }
1465         }
1466
1467         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1468          * This driver uses only uses protocol stalls (ep0 never halts),
1469          * and if we got this far the gadget driver already had a
1470          * chance to stall.  Tries to be forgiving of host oddities.
1471          *
1472          * NOTE:  the last chance gadget drivers have to stall control
1473          * requests is during their request completion callback.
1474          */
1475         if (!list_empty(&ep0->queue))
1476                 req = container_of(ep0->queue.next, struct omap_req, queue);
1477
1478         /* IN == TX to host */
1479         if (irq_src & UDC_EP0_TX) {
1480                 int     stat;
1481
1482                 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1483                 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1484                 stat = omap_readw(UDC_STAT_FLG);
1485                 if (stat & UDC_ACK) {
1486                         if (udc->ep0_in) {
1487                                 /* write next IN packet from response,
1488                                  * or set up the status stage.
1489                                  */
1490                                 if (req)
1491                                         stat = write_fifo(ep0, req);
1492                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1493                                 if (!req && udc->ep0_pending) {
1494                                         omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1495                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1496                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1497                                         omap_writew(0, UDC_EP_NUM);
1498                                         udc->ep0_pending = 0;
1499                                 } /* else:  6 wait states before it'll tx */
1500                         } else {
1501                                 /* ack status stage of OUT transfer */
1502                                 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1503                                 if (req)
1504                                         done(ep0, req, 0);
1505                         }
1506                         req = NULL;
1507                 } else if (stat & UDC_STALL) {
1508                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1509                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1510                 } else {
1511                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1512                 }
1513         }
1514
1515         /* OUT == RX from host */
1516         if (irq_src & UDC_EP0_RX) {
1517                 int     stat;
1518
1519                 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1520                 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1521                 stat = omap_readw(UDC_STAT_FLG);
1522                 if (stat & UDC_ACK) {
1523                         if (!udc->ep0_in) {
1524                                 stat = 0;
1525                                 /* read next OUT packet of request, maybe
1526                                  * reactiviting the fifo; stall on errors.
1527                                  */
1528                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1529                                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1530                                         udc->ep0_pending = 0;
1531                                         stat = 0;
1532                                 } else if (stat == 0)
1533                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1534                                 omap_writew(0, UDC_EP_NUM);
1535
1536                                 /* activate status stage */
1537                                 if (stat == 1) {
1538                                         done(ep0, req, 0);
1539                                         /* that may have STALLed ep0... */
1540                                         omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1541                                                         UDC_EP_NUM);
1542                                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1543                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1544                                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1545                                         udc->ep0_pending = 0;
1546                                 }
1547                         } else {
1548                                 /* ack status stage of IN transfer */
1549                                 omap_writew(0, UDC_EP_NUM);
1550                                 if (req)
1551                                         done(ep0, req, 0);
1552                         }
1553                 } else if (stat & UDC_STALL) {
1554                         omap_writew(UDC_CLR_HALT, UDC_CTRL);
1555                         omap_writew(0, UDC_EP_NUM);
1556                 } else {
1557                         omap_writew(0, UDC_EP_NUM);
1558                 }
1559         }
1560
1561         /* SETUP starts all control transfers */
1562         if (irq_src & UDC_SETUP) {
1563                 union u {
1564                         u16                     word[4];
1565                         struct usb_ctrlrequest  r;
1566                 } u;
1567                 int                     status = -EINVAL;
1568                 struct omap_ep          *ep;
1569
1570                 /* read the (latest) SETUP message */
1571                 do {
1572                         omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1573                         /* two bytes at a time */
1574                         u.word[0] = omap_readw(UDC_DATA);
1575                         u.word[1] = omap_readw(UDC_DATA);
1576                         u.word[2] = omap_readw(UDC_DATA);
1577                         u.word[3] = omap_readw(UDC_DATA);
1578                         omap_writew(0, UDC_EP_NUM);
1579                 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1580
1581 #define w_value         le16_to_cpu(u.r.wValue)
1582 #define w_index         le16_to_cpu(u.r.wIndex)
1583 #define w_length        le16_to_cpu(u.r.wLength)
1584
1585                 /* Delegate almost all control requests to the gadget driver,
1586                  * except for a handful of ch9 status/feature requests that
1587                  * hardware doesn't autodecode _and_ the gadget API hides.
1588                  */
1589                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1590                 udc->ep0_set_config = 0;
1591                 udc->ep0_pending = 1;
1592                 ep0->stopped = 0;
1593                 ep0->ackwait = 0;
1594                 switch (u.r.bRequest) {
1595                 case USB_REQ_SET_CONFIGURATION:
1596                         /* udc needs to know when ep != 0 is valid */
1597                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1598                                 goto delegate;
1599                         if (w_length != 0)
1600                                 goto do_stall;
1601                         udc->ep0_set_config = 1;
1602                         udc->ep0_reset_config = (w_value == 0);
1603                         VDBG("set config %d\n", w_value);
1604
1605                         /* update udc NOW since gadget driver may start
1606                          * queueing requests immediately; clear config
1607                          * later if it fails the request.
1608                          */
1609                         if (udc->ep0_reset_config)
1610                                 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1611                         else
1612                                 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1613                         update_otg(udc);
1614                         goto delegate;
1615                 case USB_REQ_CLEAR_FEATURE:
1616                         /* clear endpoint halt */
1617                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1618                                 goto delegate;
1619                         if (w_value != USB_ENDPOINT_HALT
1620                                         || w_length != 0)
1621                                 goto do_stall;
1622                         ep = &udc->ep[w_index & 0xf];
1623                         if (ep != ep0) {
1624                                 if (w_index & USB_DIR_IN)
1625                                         ep += 16;
1626                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1627                                                 || !ep->ep.desc)
1628                                         goto do_stall;
1629                                 use_ep(ep, 0);
1630                                 omap_writew(udc->clr_halt, UDC_CTRL);
1631                                 ep->ackwait = 0;
1632                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1633                                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1634                                         ep->ackwait = 1 + ep->double_buf;
1635                                 }
1636                                 /* NOTE:  assumes the host behaves sanely,
1637                                  * only clearing real halts.  Else we may
1638                                  * need to kill pending transfers and then
1639                                  * restart the queue... very messy for DMA!
1640                                  */
1641                         }
1642                         VDBG("%s halt cleared by host\n", ep->name);
1643                         goto ep0out_status_stage;
1644                 case USB_REQ_SET_FEATURE:
1645                         /* set endpoint halt */
1646                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1647                                 goto delegate;
1648                         if (w_value != USB_ENDPOINT_HALT
1649                                         || w_length != 0)
1650                                 goto do_stall;
1651                         ep = &udc->ep[w_index & 0xf];
1652                         if (w_index & USB_DIR_IN)
1653                                 ep += 16;
1654                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1655                                         || ep == ep0 || !ep->ep.desc)
1656                                 goto do_stall;
1657                         if (use_dma && ep->has_dma) {
1658                                 /* this has rude side-effects (aborts) and
1659                                  * can't really work if DMA-IN is active
1660                                  */
1661                                 DBG("%s host set_halt, NYET \n", ep->name);
1662                                 goto do_stall;
1663                         }
1664                         use_ep(ep, 0);
1665                         /* can't halt if fifo isn't empty... */
1666                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1667                         omap_writew(UDC_SET_HALT, UDC_CTRL);
1668                         VDBG("%s halted by host\n", ep->name);
1669 ep0out_status_stage:
1670                         status = 0;
1671                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1672                         omap_writew(UDC_CLR_EP, UDC_CTRL);
1673                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1674                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1675                         udc->ep0_pending = 0;
1676                         break;
1677                 case USB_REQ_GET_STATUS:
1678                         /* USB_ENDPOINT_HALT status? */
1679                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1680                                 goto intf_status;
1681
1682                         /* ep0 never stalls */
1683                         if (!(w_index & 0xf))
1684                                 goto zero_status;
1685
1686                         /* only active endpoints count */
1687                         ep = &udc->ep[w_index & 0xf];
1688                         if (w_index & USB_DIR_IN)
1689                                 ep += 16;
1690                         if (!ep->ep.desc)
1691                                 goto do_stall;
1692
1693                         /* iso never stalls */
1694                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1695                                 goto zero_status;
1696
1697                         /* FIXME don't assume non-halted endpoints!! */
1698                         ERR("%s status, can't report\n", ep->ep.name);
1699                         goto do_stall;
1700
1701 intf_status:
1702                         /* return interface status.  if we were pedantic,
1703                          * we'd detect non-existent interfaces, and stall.
1704                          */
1705                         if (u.r.bRequestType
1706                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1707                                 goto delegate;
1708
1709 zero_status:
1710                         /* return two zero bytes */
1711                         omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1712                         omap_writew(0, UDC_DATA);
1713                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1714                         omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1715                         status = 0;
1716                         VDBG("GET_STATUS, interface %d\n", w_index);
1717                         /* next, status stage */
1718                         break;
1719                 default:
1720 delegate:
1721                         /* activate the ep0out fifo right away */
1722                         if (!udc->ep0_in && w_length) {
1723                                 omap_writew(0, UDC_EP_NUM);
1724                                 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1725                         }
1726
1727                         /* gadget drivers see class/vendor specific requests,
1728                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1729                          * and more
1730                          */
1731                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1732                                 u.r.bRequestType, u.r.bRequest,
1733                                 w_value, w_index, w_length);
1734
1735 #undef  w_value
1736 #undef  w_index
1737 #undef  w_length
1738
1739                         /* The gadget driver may return an error here,
1740                          * causing an immediate protocol stall.
1741                          *
1742                          * Else it must issue a response, either queueing a
1743                          * response buffer for the DATA stage, or halting ep0
1744                          * (causing a protocol stall, not a real halt).  A
1745                          * zero length buffer means no DATA stage.
1746                          *
1747                          * It's fine to issue that response after the setup()
1748                          * call returns, and this IRQ was handled.
1749                          */
1750                         udc->ep0_setup = 1;
1751                         spin_unlock(&udc->lock);
1752                         status = udc->driver->setup (&udc->gadget, &u.r);
1753                         spin_lock(&udc->lock);
1754                         udc->ep0_setup = 0;
1755                 }
1756
1757                 if (status < 0) {
1758 do_stall:
1759                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1760                                         u.r.bRequestType, u.r.bRequest, status);
1761                         if (udc->ep0_set_config) {
1762                                 if (udc->ep0_reset_config)
1763                                         WARNING("error resetting config?\n");
1764                                 else
1765                                         omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1766                         }
1767                         omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1768                         udc->ep0_pending = 0;
1769                 }
1770         }
1771 }
1772
1773 /*-------------------------------------------------------------------------*/
1774
1775 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1776
1777 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1778 {
1779         u16     devstat, change;
1780
1781         devstat = omap_readw(UDC_DEVSTAT);
1782         change = devstat ^ udc->devstat;
1783         udc->devstat = devstat;
1784
1785         if (change & (UDC_USB_RESET|UDC_ATT)) {
1786                 udc_quiesce(udc);
1787
1788                 if (change & UDC_ATT) {
1789                         /* driver for any external transceiver will
1790                          * have called omap_vbus_session() already
1791                          */
1792                         if (devstat & UDC_ATT) {
1793                                 udc->gadget.speed = USB_SPEED_FULL;
1794                                 VDBG("connect\n");
1795                                 if (!udc->transceiver)
1796                                         pullup_enable(udc);
1797                                 // if (driver->connect) call it
1798                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1799                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1800                                 if (!udc->transceiver)
1801                                         pullup_disable(udc);
1802                                 DBG("disconnect, gadget %s\n",
1803                                         udc->driver->driver.name);
1804                                 if (udc->driver->disconnect) {
1805                                         spin_unlock(&udc->lock);
1806                                         udc->driver->disconnect(&udc->gadget);
1807                                         spin_lock(&udc->lock);
1808                                 }
1809                         }
1810                         change &= ~UDC_ATT;
1811                 }
1812
1813                 if (change & UDC_USB_RESET) {
1814                         if (devstat & UDC_USB_RESET) {
1815                                 VDBG("RESET=1\n");
1816                         } else {
1817                                 udc->gadget.speed = USB_SPEED_FULL;
1818                                 INFO("USB reset done, gadget %s\n",
1819                                         udc->driver->driver.name);
1820                                 /* ep0 traffic is legal from now on */
1821                                 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1822                                                 UDC_IRQ_EN);
1823                         }
1824                         change &= ~UDC_USB_RESET;
1825                 }
1826         }
1827         if (change & UDC_SUS) {
1828                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1829                         // FIXME tell isp1301 to suspend/resume (?)
1830                         if (devstat & UDC_SUS) {
1831                                 VDBG("suspend\n");
1832                                 update_otg(udc);
1833                                 /* HNP could be under way already */
1834                                 if (udc->gadget.speed == USB_SPEED_FULL
1835                                                 && udc->driver->suspend) {
1836                                         spin_unlock(&udc->lock);
1837                                         udc->driver->suspend(&udc->gadget);
1838                                         spin_lock(&udc->lock);
1839                                 }
1840                                 if (udc->transceiver)
1841                                         usb_phy_set_suspend(
1842                                                         udc->transceiver, 1);
1843                         } else {
1844                                 VDBG("resume\n");
1845                                 if (udc->transceiver)
1846                                         usb_phy_set_suspend(
1847                                                         udc->transceiver, 0);
1848                                 if (udc->gadget.speed == USB_SPEED_FULL
1849                                                 && udc->driver->resume) {
1850                                         spin_unlock(&udc->lock);
1851                                         udc->driver->resume(&udc->gadget);
1852                                         spin_lock(&udc->lock);
1853                                 }
1854                         }
1855                 }
1856                 change &= ~UDC_SUS;
1857         }
1858         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1859                 update_otg(udc);
1860                 change &= ~OTG_FLAGS;
1861         }
1862
1863         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1864         if (change)
1865                 VDBG("devstat %03x, ignore change %03x\n",
1866                         devstat,  change);
1867
1868         omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1869 }
1870
1871 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1872 {
1873         struct omap_udc *udc = _udc;
1874         u16             irq_src;
1875         irqreturn_t     status = IRQ_NONE;
1876         unsigned long   flags;
1877
1878         spin_lock_irqsave(&udc->lock, flags);
1879         irq_src = omap_readw(UDC_IRQ_SRC);
1880
1881         /* Device state change (usb ch9 stuff) */
1882         if (irq_src & UDC_DS_CHG) {
1883                 devstate_irq(_udc, irq_src);
1884                 status = IRQ_HANDLED;
1885                 irq_src &= ~UDC_DS_CHG;
1886         }
1887
1888         /* EP0 control transfers */
1889         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1890                 ep0_irq(_udc, irq_src);
1891                 status = IRQ_HANDLED;
1892                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1893         }
1894
1895         /* DMA transfer completion */
1896         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1897                 dma_irq(_udc, irq_src);
1898                 status = IRQ_HANDLED;
1899                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1900         }
1901
1902         irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1903         if (irq_src)
1904                 DBG("udc_irq, unhandled %03x\n", irq_src);
1905         spin_unlock_irqrestore(&udc->lock, flags);
1906
1907         return status;
1908 }
1909
1910 /* workaround for seemingly-lost IRQs for RX ACKs... */
1911 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1912 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1913
1914 static void pio_out_timer(unsigned long _ep)
1915 {
1916         struct omap_ep  *ep = (void *) _ep;
1917         unsigned long   flags;
1918         u16             stat_flg;
1919
1920         spin_lock_irqsave(&ep->udc->lock, flags);
1921         if (!list_empty(&ep->queue) && ep->ackwait) {
1922                 use_ep(ep, UDC_EP_SEL);
1923                 stat_flg = omap_readw(UDC_STAT_FLG);
1924
1925                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1926                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1927                         struct omap_req *req;
1928
1929                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1930                         req = container_of(ep->queue.next,
1931                                         struct omap_req, queue);
1932                         (void) read_fifo(ep, req);
1933                         omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1934                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1935                         ep->ackwait = 1 + ep->double_buf;
1936                 } else
1937                         deselect_ep();
1938         }
1939         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1940         spin_unlock_irqrestore(&ep->udc->lock, flags);
1941 }
1942
1943 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1944 {
1945         u16             epn_stat, irq_src;
1946         irqreturn_t     status = IRQ_NONE;
1947         struct omap_ep  *ep;
1948         int             epnum;
1949         struct omap_udc *udc = _dev;
1950         struct omap_req *req;
1951         unsigned long   flags;
1952
1953         spin_lock_irqsave(&udc->lock, flags);
1954         epn_stat = omap_readw(UDC_EPN_STAT);
1955         irq_src = omap_readw(UDC_IRQ_SRC);
1956
1957         /* handle OUT first, to avoid some wasteful NAKs */
1958         if (irq_src & UDC_EPN_RX) {
1959                 epnum = (epn_stat >> 8) & 0x0f;
1960                 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1961                 status = IRQ_HANDLED;
1962                 ep = &udc->ep[epnum];
1963                 ep->irqs++;
1964
1965                 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1966                 ep->fnf = 0;
1967                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1968                         ep->ackwait--;
1969                         if (!list_empty(&ep->queue)) {
1970                                 int stat;
1971                                 req = container_of(ep->queue.next,
1972                                                 struct omap_req, queue);
1973                                 stat = read_fifo(ep, req);
1974                                 if (!ep->double_buf)
1975                                         ep->fnf = 1;
1976                         }
1977                 }
1978                 /* min 6 clock delay before clearing EP_SEL ... */
1979                 epn_stat = omap_readw(UDC_EPN_STAT);
1980                 epn_stat = omap_readw(UDC_EPN_STAT);
1981                 omap_writew(epnum, UDC_EP_NUM);
1982
1983                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1984                  * reduces lossage; timer still needed though (sigh).
1985                  */
1986                 if (ep->fnf) {
1987                         omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1988                         ep->ackwait = 1 + ep->double_buf;
1989                 }
1990                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1991         }
1992
1993         /* then IN transfers */
1994         else if (irq_src & UDC_EPN_TX) {
1995                 epnum = epn_stat & 0x0f;
1996                 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1997                 status = IRQ_HANDLED;
1998                 ep = &udc->ep[16 + epnum];
1999                 ep->irqs++;
2000
2001                 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2002                 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2003                         ep->ackwait = 0;
2004                         if (!list_empty(&ep->queue)) {
2005                                 req = container_of(ep->queue.next,
2006                                                 struct omap_req, queue);
2007                                 (void) write_fifo(ep, req);
2008                         }
2009                 }
2010                 /* min 6 clock delay before clearing EP_SEL ... */
2011                 epn_stat = omap_readw(UDC_EPN_STAT);
2012                 epn_stat = omap_readw(UDC_EPN_STAT);
2013                 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2014                 /* then 6 clocks before it'd tx */
2015         }
2016
2017         spin_unlock_irqrestore(&udc->lock, flags);
2018         return status;
2019 }
2020
2021 #ifdef  USE_ISO
2022 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2023 {
2024         struct omap_udc *udc = _dev;
2025         struct omap_ep  *ep;
2026         int             pending = 0;
2027         unsigned long   flags;
2028
2029         spin_lock_irqsave(&udc->lock, flags);
2030
2031         /* handle all non-DMA ISO transfers */
2032         list_for_each_entry (ep, &udc->iso, iso) {
2033                 u16             stat;
2034                 struct omap_req *req;
2035
2036                 if (ep->has_dma || list_empty(&ep->queue))
2037                         continue;
2038                 req = list_entry(ep->queue.next, struct omap_req, queue);
2039
2040                 use_ep(ep, UDC_EP_SEL);
2041                 stat = omap_readw(UDC_STAT_FLG);
2042
2043                 /* NOTE: like the other controller drivers, this isn't
2044                  * currently reporting lost or damaged frames.
2045                  */
2046                 if (ep->bEndpointAddress & USB_DIR_IN) {
2047                         if (stat & UDC_MISS_IN)
2048                                 /* done(ep, req, -EPROTO) */;
2049                         else
2050                                 write_fifo(ep, req);
2051                 } else {
2052                         int     status = 0;
2053
2054                         if (stat & UDC_NO_RXPACKET)
2055                                 status = -EREMOTEIO;
2056                         else if (stat & UDC_ISO_ERR)
2057                                 status = -EILSEQ;
2058                         else if (stat & UDC_DATA_FLUSH)
2059                                 status = -ENOSR;
2060
2061                         if (status)
2062                                 /* done(ep, req, status) */;
2063                         else
2064                                 read_fifo(ep, req);
2065                 }
2066                 deselect_ep();
2067                 /* 6 wait states before next EP */
2068
2069                 ep->irqs++;
2070                 if (!list_empty(&ep->queue))
2071                         pending = 1;
2072         }
2073         if (!pending) {
2074                 u16 w;
2075
2076                 w = omap_readw(UDC_IRQ_EN);
2077                 w &= ~UDC_SOF_IE;
2078                 omap_writew(w, UDC_IRQ_EN);
2079         }
2080         omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2081
2082         spin_unlock_irqrestore(&udc->lock, flags);
2083         return IRQ_HANDLED;
2084 }
2085 #endif
2086
2087 /*-------------------------------------------------------------------------*/
2088
2089 static inline int machine_without_vbus_sense(void)
2090 {
2091         return (machine_is_omap_innovator()
2092                 || machine_is_omap_osk()
2093                 || machine_is_omap_apollon()
2094 #ifndef CONFIG_MACH_OMAP_H4_OTG
2095                 || machine_is_omap_h4()
2096 #endif
2097                 || machine_is_sx1()
2098                 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
2099                 );
2100 }
2101
2102 static int omap_udc_start(struct usb_gadget_driver *driver,
2103                 int (*bind)(struct usb_gadget *))
2104 {
2105         int             status = -ENODEV;
2106         struct omap_ep  *ep;
2107         unsigned long   flags;
2108
2109         /* basic sanity tests */
2110         if (!udc)
2111                 return -ENODEV;
2112         if (!driver
2113                         // FIXME if otg, check:  driver->is_otg
2114                         || driver->max_speed < USB_SPEED_FULL
2115                         || !bind || !driver->setup)
2116                 return -EINVAL;
2117
2118         spin_lock_irqsave(&udc->lock, flags);
2119         if (udc->driver) {
2120                 spin_unlock_irqrestore(&udc->lock, flags);
2121                 return -EBUSY;
2122         }
2123
2124         /* reset state */
2125         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2126                 ep->irqs = 0;
2127                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2128                         continue;
2129                 use_ep(ep, 0);
2130                 omap_writew(UDC_SET_HALT, UDC_CTRL);
2131         }
2132         udc->ep0_pending = 0;
2133         udc->ep[0].irqs = 0;
2134         udc->softconnect = 1;
2135
2136         /* hook up the driver */
2137         driver->driver.bus = NULL;
2138         udc->driver = driver;
2139         udc->gadget.dev.driver = &driver->driver;
2140         spin_unlock_irqrestore(&udc->lock, flags);
2141
2142         if (udc->dc_clk != NULL)
2143                 omap_udc_enable_clock(1);
2144
2145         status = bind(&udc->gadget);
2146         if (status) {
2147                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2148                 udc->gadget.dev.driver = NULL;
2149                 udc->driver = NULL;
2150                 goto done;
2151         }
2152         DBG("bound to driver %s\n", driver->driver.name);
2153
2154         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2155
2156         /* connect to bus through transceiver */
2157         if (udc->transceiver) {
2158                 status = otg_set_peripheral(udc->transceiver->otg,
2159                                                 &udc->gadget);
2160                 if (status < 0) {
2161                         ERR("can't bind to transceiver\n");
2162                         if (driver->unbind) {
2163                                 driver->unbind (&udc->gadget);
2164                                 udc->gadget.dev.driver = NULL;
2165                                 udc->driver = NULL;
2166                         }
2167                         goto done;
2168                 }
2169         } else {
2170                 if (can_pullup(udc))
2171                         pullup_enable (udc);
2172                 else
2173                         pullup_disable (udc);
2174         }
2175
2176         /* boards that don't have VBUS sensing can't autogate 48MHz;
2177          * can't enter deep sleep while a gadget driver is active.
2178          */
2179         if (machine_without_vbus_sense())
2180                 omap_vbus_session(&udc->gadget, 1);
2181
2182 done:
2183         if (udc->dc_clk != NULL)
2184                 omap_udc_enable_clock(0);
2185         return status;
2186 }
2187
2188 static int omap_udc_stop(struct usb_gadget_driver *driver)
2189 {
2190         unsigned long   flags;
2191         int             status = -ENODEV;
2192
2193         if (!udc)
2194                 return -ENODEV;
2195         if (!driver || driver != udc->driver || !driver->unbind)
2196                 return -EINVAL;
2197
2198         if (udc->dc_clk != NULL)
2199                 omap_udc_enable_clock(1);
2200
2201         if (machine_without_vbus_sense())
2202                 omap_vbus_session(&udc->gadget, 0);
2203
2204         if (udc->transceiver)
2205                 (void) otg_set_peripheral(udc->transceiver->otg, NULL);
2206         else
2207                 pullup_disable(udc);
2208
2209         spin_lock_irqsave(&udc->lock, flags);
2210         udc_quiesce(udc);
2211         spin_unlock_irqrestore(&udc->lock, flags);
2212
2213         driver->unbind(&udc->gadget);
2214         udc->gadget.dev.driver = NULL;
2215         udc->driver = NULL;
2216
2217         if (udc->dc_clk != NULL)
2218                 omap_udc_enable_clock(0);
2219         DBG("unregistered driver '%s'\n", driver->driver.name);
2220         return status;
2221 }
2222
2223 /*-------------------------------------------------------------------------*/
2224
2225 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2226
2227 #include <linux/seq_file.h>
2228
2229 static const char proc_filename[] = "driver/udc";
2230
2231 #define FOURBITS "%s%s%s%s"
2232 #define EIGHTBITS FOURBITS FOURBITS
2233
2234 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2235 {
2236         u16             stat_flg;
2237         struct omap_req *req;
2238         char            buf[20];
2239
2240         use_ep(ep, 0);
2241
2242         if (use_dma && ep->has_dma)
2243                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2244                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2245                         ep->dma_channel - 1, ep->lch);
2246         else
2247                 buf[0] = 0;
2248
2249         stat_flg = omap_readw(UDC_STAT_FLG);
2250         seq_printf(s,
2251                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2252                 ep->name, buf,
2253                 ep->double_buf ? "dbuf " : "",
2254                 ({char *s; switch(ep->ackwait){
2255                 case 0: s = ""; break;
2256                 case 1: s = "(ackw) "; break;
2257                 case 2: s = "(ackw2) "; break;
2258                 default: s = "(?) "; break;
2259                 } s;}),
2260                 ep->irqs, stat_flg,
2261                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2262                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2263                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2264                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2265                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2266                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2267                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2268                 (stat_flg & UDC_STALL) ? "STALL " : "",
2269                 (stat_flg & UDC_NAK) ? "NAK " : "",
2270                 (stat_flg & UDC_ACK) ? "ACK " : "",
2271                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2272                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2273                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2274
2275         if (list_empty (&ep->queue))
2276                 seq_printf(s, "\t(queue empty)\n");
2277         else
2278                 list_for_each_entry (req, &ep->queue, queue) {
2279                         unsigned        length = req->req.actual;
2280
2281                         if (use_dma && buf[0]) {
2282                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2283                                                 ? dma_src_len : dma_dest_len)
2284                                         (ep, req->req.dma + length);
2285                                 buf[0] = 0;
2286                         }
2287                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2288                                         &req->req, length,
2289                                         req->req.length, req->req.buf);
2290                 }
2291 }
2292
2293 static char *trx_mode(unsigned m, int enabled)
2294 {
2295         switch (m) {
2296         case 0:         return enabled ? "*6wire" : "unused";
2297         case 1:         return "4wire";
2298         case 2:         return "3wire";
2299         case 3:         return "6wire";
2300         default:        return "unknown";
2301         }
2302 }
2303
2304 static int proc_otg_show(struct seq_file *s)
2305 {
2306         u32             tmp;
2307         u32             trans = 0;
2308         char            *ctrl_name = "(UNKNOWN)";
2309
2310         /* XXX This needs major revision for OMAP2+ */
2311         tmp = omap_readl(OTG_REV);
2312         if (cpu_class_is_omap1()) {
2313                 ctrl_name = "tranceiver_ctrl";
2314                 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2315         }
2316         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2317                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2318         tmp = omap_readw(OTG_SYSCON_1);
2319         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2320                         FOURBITS "\n", tmp,
2321                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2322                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2323                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2324                         ? "internal"
2325                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2326                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2327                 (tmp & HST_IDLE_EN) ? " !host" : "",
2328                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2329                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2330         tmp = omap_readl(OTG_SYSCON_2);
2331         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2332                         " b_ase_brst=%d hmc=%d\n", tmp,
2333                 (tmp & OTG_EN) ? " otg_en" : "",
2334                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2335                 // much more SRP stuff
2336                 (tmp & SRP_DATA) ? " srp_data" : "",
2337                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2338                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2339                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2340                 (tmp & UHOST_EN) ? " uhost_en" : "",
2341                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2342                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2343                 B_ASE_BRST(tmp),
2344                 OTG_HMC(tmp));
2345         tmp = omap_readl(OTG_CTRL);
2346         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2347                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2348                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2349                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2350                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2351                 (tmp & OTG_ID) ? " id" : "",
2352                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2353                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2354                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2355                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2356                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2357                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2358                 (tmp & OTG_PULLDOWN) ? " down" : "",
2359                 (tmp & OTG_PULLUP) ? " up" : "",
2360                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2361                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2362                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2363                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2364                 );
2365         tmp = omap_readw(OTG_IRQ_EN);
2366         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2367         tmp = omap_readw(OTG_IRQ_SRC);
2368         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2369         tmp = omap_readw(OTG_OUTCTRL);
2370         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2371         tmp = omap_readw(OTG_TEST);
2372         seq_printf(s, "otg_test    %04x" "\n", tmp);
2373         return 0;
2374 }
2375
2376 static int proc_udc_show(struct seq_file *s, void *_)
2377 {
2378         u32             tmp;
2379         struct omap_ep  *ep;
2380         unsigned long   flags;
2381
2382         spin_lock_irqsave(&udc->lock, flags);
2383
2384         seq_printf(s, "%s, version: " DRIVER_VERSION
2385 #ifdef  USE_ISO
2386                 " (iso)"
2387 #endif
2388                 "%s\n",
2389                 driver_desc,
2390                 use_dma ?  " (dma)" : "");
2391
2392         tmp = omap_readw(UDC_REV) & 0xff;
2393         seq_printf(s,
2394                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2395                 "hmc %d, transceiver %s\n",
2396                 tmp >> 4, tmp & 0xf,
2397                 fifo_mode,
2398                 udc->driver ? udc->driver->driver.name : "(none)",
2399                 HMC,
2400                 udc->transceiver
2401                         ? udc->transceiver->label
2402                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2403                                 ? "external" : "(none)"));
2404         if (cpu_class_is_omap1()) {
2405                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2406                         omap_readw(ULPD_CLOCK_CTRL),
2407                         omap_readw(ULPD_SOFT_REQ),
2408                         omap_readw(ULPD_STATUS_REQ));
2409         }
2410
2411         /* OTG controller registers */
2412         if (!cpu_is_omap15xx())
2413                 proc_otg_show(s);
2414
2415         tmp = omap_readw(UDC_SYSCON1);
2416         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2417                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2418                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2419                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2420                 (tmp & UDC_NAK_EN) ? " nak" : "",
2421                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2422                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2423                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2424                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2425         // syscon2 is write-only
2426
2427         /* UDC controller registers */
2428         if (!(tmp & UDC_PULLUP_EN)) {
2429                 seq_printf(s, "(suspended)\n");
2430                 spin_unlock_irqrestore(&udc->lock, flags);
2431                 return 0;
2432         }
2433
2434         tmp = omap_readw(UDC_DEVSTAT);
2435         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2436                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2437                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2438                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2439                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2440                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2441                 (tmp & UDC_SUS) ? " SUS" : "",
2442                 (tmp & UDC_CFG) ? " CFG" : "",
2443                 (tmp & UDC_ADD) ? " ADD" : "",
2444                 (tmp & UDC_DEF) ? " DEF" : "",
2445                 (tmp & UDC_ATT) ? " ATT" : "");
2446         seq_printf(s, "sof         %04x\n", omap_readw(UDC_SOF));
2447         tmp = omap_readw(UDC_IRQ_EN);
2448         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2449                 (tmp & UDC_SOF_IE) ? " sof" : "",
2450                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2451                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2452                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2453                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2454         tmp = omap_readw(UDC_IRQ_SRC);
2455         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2456                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2457                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2458                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2459                 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2460                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2461                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2462                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2463                 (tmp & UDC_SETUP) ? " setup" : "",
2464                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2465                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2466         if (use_dma) {
2467                 unsigned i;
2468
2469                 tmp = omap_readw(UDC_DMA_IRQ_EN);
2470                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2471                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2472                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2473                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2474
2475                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2476                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2477                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2478
2479                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2480                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2481                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2482
2483                 tmp = omap_readw(UDC_RXDMA_CFG);
2484                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2485                 if (tmp) {
2486                         for (i = 0; i < 3; i++) {
2487                                 if ((tmp & (0x0f << (i * 4))) == 0)
2488                                         continue;
2489                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2490                                                 omap_readw(UDC_RXDMA(i + 1)));
2491                         }
2492                 }
2493                 tmp = omap_readw(UDC_TXDMA_CFG);
2494                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2495                 if (tmp) {
2496                         for (i = 0; i < 3; i++) {
2497                                 if (!(tmp & (0x0f << (i * 4))))
2498                                         continue;
2499                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2500                                                 omap_readw(UDC_TXDMA(i + 1)));
2501                         }
2502                 }
2503         }
2504
2505         tmp = omap_readw(UDC_DEVSTAT);
2506         if (tmp & UDC_ATT) {
2507                 proc_ep_show(s, &udc->ep[0]);
2508                 if (tmp & UDC_ADD) {
2509                         list_for_each_entry (ep, &udc->gadget.ep_list,
2510                                         ep.ep_list) {
2511                                 if (ep->ep.desc)
2512                                         proc_ep_show(s, ep);
2513                         }
2514                 }
2515         }
2516         spin_unlock_irqrestore(&udc->lock, flags);
2517         return 0;
2518 }
2519
2520 static int proc_udc_open(struct inode *inode, struct file *file)
2521 {
2522         return single_open(file, proc_udc_show, NULL);
2523 }
2524
2525 static const struct file_operations proc_ops = {
2526         .owner          = THIS_MODULE,
2527         .open           = proc_udc_open,
2528         .read           = seq_read,
2529         .llseek         = seq_lseek,
2530         .release        = single_release,
2531 };
2532
2533 static void create_proc_file(void)
2534 {
2535         proc_create(proc_filename, 0, NULL, &proc_ops);
2536 }
2537
2538 static void remove_proc_file(void)
2539 {
2540         remove_proc_entry(proc_filename, NULL);
2541 }
2542
2543 #else
2544
2545 static inline void create_proc_file(void) {}
2546 static inline void remove_proc_file(void) {}
2547
2548 #endif
2549
2550 /*-------------------------------------------------------------------------*/
2551
2552 /* Before this controller can enumerate, we need to pick an endpoint
2553  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2554  * buffer space among the endpoints we'll be operating.
2555  *
2556  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2557  * UDC_SYSCON_1.CFG_LOCK is set can now work.  We won't use that
2558  * capability yet though.
2559  */
2560 static unsigned __init
2561 omap_ep_setup(char *name, u8 addr, u8 type,
2562                 unsigned buf, unsigned maxp, int dbuf)
2563 {
2564         struct omap_ep  *ep;
2565         u16             epn_rxtx = 0;
2566
2567         /* OUT endpoints first, then IN */
2568         ep = &udc->ep[addr & 0xf];
2569         if (addr & USB_DIR_IN)
2570                 ep += 16;
2571
2572         /* in case of ep init table bugs */
2573         BUG_ON(ep->name[0]);
2574
2575         /* chip setup ... bit values are same for IN, OUT */
2576         if (type == USB_ENDPOINT_XFER_ISOC) {
2577                 switch (maxp) {
2578                 case 8:         epn_rxtx = 0 << 12; break;
2579                 case 16:        epn_rxtx = 1 << 12; break;
2580                 case 32:        epn_rxtx = 2 << 12; break;
2581                 case 64:        epn_rxtx = 3 << 12; break;
2582                 case 128:       epn_rxtx = 4 << 12; break;
2583                 case 256:       epn_rxtx = 5 << 12; break;
2584                 case 512:       epn_rxtx = 6 << 12; break;
2585                 default:        BUG();
2586                 }
2587                 epn_rxtx |= UDC_EPN_RX_ISO;
2588                 dbuf = 1;
2589         } else {
2590                 /* double-buffering "not supported" on 15xx,
2591                  * and ignored for PIO-IN on newer chips
2592                  * (for more reliable behavior)
2593                  */
2594                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2595                         dbuf = 0;
2596
2597                 switch (maxp) {
2598                 case 8:         epn_rxtx = 0 << 12; break;
2599                 case 16:        epn_rxtx = 1 << 12; break;
2600                 case 32:        epn_rxtx = 2 << 12; break;
2601                 case 64:        epn_rxtx = 3 << 12; break;
2602                 default:        BUG();
2603                 }
2604                 if (dbuf && addr)
2605                         epn_rxtx |= UDC_EPN_RX_DB;
2606                 init_timer(&ep->timer);
2607                 ep->timer.function = pio_out_timer;
2608                 ep->timer.data = (unsigned long) ep;
2609         }
2610         if (addr)
2611                 epn_rxtx |= UDC_EPN_RX_VALID;
2612         BUG_ON(buf & 0x07);
2613         epn_rxtx |= buf >> 3;
2614
2615         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2616                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2617
2618         if (addr & USB_DIR_IN)
2619                 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2620         else
2621                 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2622
2623         /* next endpoint's buffer starts after this one's */
2624         buf += maxp;
2625         if (dbuf)
2626                 buf += maxp;
2627         BUG_ON(buf > 2048);
2628
2629         /* set up driver data structures */
2630         BUG_ON(strlen(name) >= sizeof ep->name);
2631         strlcpy(ep->name, name, sizeof ep->name);
2632         INIT_LIST_HEAD(&ep->queue);
2633         INIT_LIST_HEAD(&ep->iso);
2634         ep->bEndpointAddress = addr;
2635         ep->bmAttributes = type;
2636         ep->double_buf = dbuf;
2637         ep->udc = udc;
2638
2639         ep->ep.name = ep->name;
2640         ep->ep.ops = &omap_ep_ops;
2641         ep->ep.maxpacket = ep->maxpacket = maxp;
2642         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2643
2644         return buf;
2645 }
2646
2647 static void omap_udc_release(struct device *dev)
2648 {
2649         complete(udc->done);
2650         kfree (udc);
2651         udc = NULL;
2652 }
2653
2654 static int __init
2655 omap_udc_setup(struct platform_device *odev, struct usb_phy *xceiv)
2656 {
2657         unsigned        tmp, buf;
2658
2659         /* abolish any previous hardware state */
2660         omap_writew(0, UDC_SYSCON1);
2661         omap_writew(0, UDC_IRQ_EN);
2662         omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2663         omap_writew(0, UDC_DMA_IRQ_EN);
2664         omap_writew(0, UDC_RXDMA_CFG);
2665         omap_writew(0, UDC_TXDMA_CFG);
2666
2667         /* UDC_PULLUP_EN gates the chip clock */
2668         // OTG_SYSCON_1 |= DEV_IDLE_EN;
2669
2670         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2671         if (!udc)
2672                 return -ENOMEM;
2673
2674         spin_lock_init (&udc->lock);
2675
2676         udc->gadget.ops = &omap_gadget_ops;
2677         udc->gadget.ep0 = &udc->ep[0].ep;
2678         INIT_LIST_HEAD(&udc->gadget.ep_list);
2679         INIT_LIST_HEAD(&udc->iso);
2680         udc->gadget.speed = USB_SPEED_UNKNOWN;
2681         udc->gadget.max_speed = USB_SPEED_FULL;
2682         udc->gadget.name = driver_name;
2683
2684         device_initialize(&udc->gadget.dev);
2685         dev_set_name(&udc->gadget.dev, "gadget");
2686         udc->gadget.dev.release = omap_udc_release;
2687         udc->gadget.dev.parent = &odev->dev;
2688         if (use_dma)
2689                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2690
2691         udc->transceiver = xceiv;
2692
2693         /* ep0 is special; put it right after the SETUP buffer */
2694         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2695                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2696         list_del_init(&udc->ep[0].ep.ep_list);
2697
2698         /* initially disable all non-ep0 endpoints */
2699         for (tmp = 1; tmp < 15; tmp++) {
2700                 omap_writew(0, UDC_EP_RX(tmp));
2701                 omap_writew(0, UDC_EP_TX(tmp));
2702         }
2703
2704 #define OMAP_BULK_EP(name,addr) \
2705         buf = omap_ep_setup(name "-bulk", addr, \
2706                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2707 #define OMAP_INT_EP(name,addr, maxp) \
2708         buf = omap_ep_setup(name "-int", addr, \
2709                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2710 #define OMAP_ISO_EP(name,addr, maxp) \
2711         buf = omap_ep_setup(name "-iso", addr, \
2712                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2713
2714         switch (fifo_mode) {
2715         case 0:
2716                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2717                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2718                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2719                 break;
2720         case 1:
2721                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2722                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2723                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2724
2725                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2726                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2727                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2728
2729                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2730                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2731                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2732
2733                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2734                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2735                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2736
2737                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2738                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2739                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2740                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2741
2742                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2743                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2744                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2745                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2746
2747                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2748                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2749
2750                 break;
2751
2752 #ifdef  USE_ISO
2753         case 2:                 /* mixed iso/bulk */
2754                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2755                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2756                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2757                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2758
2759                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2760
2761                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2762                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2763                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2764                 break;
2765         case 3:                 /* mixed bulk/iso */
2766                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2767                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2768                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2769
2770                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2771                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2772                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2773
2774                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2775                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2776                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2777                 break;
2778 #endif
2779
2780         /* add more modes as needed */
2781
2782         default:
2783                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2784                 return -ENODEV;
2785         }
2786         omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2787         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2788         return 0;
2789 }
2790
2791 static int __init omap_udc_probe(struct platform_device *pdev)
2792 {
2793         int                     status = -ENODEV;
2794         int                     hmc;
2795         struct usb_phy          *xceiv = NULL;
2796         const char              *type = NULL;
2797         struct omap_usb_config  *config = pdev->dev.platform_data;
2798         struct clk              *dc_clk;
2799         struct clk              *hhc_clk;
2800
2801         /* NOTE:  "knows" the order of the resources! */
2802         if (!request_mem_region(pdev->resource[0].start,
2803                         pdev->resource[0].end - pdev->resource[0].start + 1,
2804                         driver_name)) {
2805                 DBG("request_mem_region failed\n");
2806                 return -EBUSY;
2807         }
2808
2809         if (cpu_is_omap16xx()) {
2810                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2811                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2812                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2813                 /* can't use omap_udc_enable_clock yet */
2814                 clk_enable(dc_clk);
2815                 clk_enable(hhc_clk);
2816                 udelay(100);
2817         }
2818
2819         if (cpu_is_omap24xx()) {
2820                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2821                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2822                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2823                 /* can't use omap_udc_enable_clock yet */
2824                 clk_enable(dc_clk);
2825                 clk_enable(hhc_clk);
2826                 udelay(100);
2827         }
2828
2829         if (cpu_is_omap7xx()) {
2830                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2831                 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2832                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2833                 /* can't use omap_udc_enable_clock yet */
2834                 clk_enable(dc_clk);
2835                 clk_enable(hhc_clk);
2836                 udelay(100);
2837         }
2838
2839         INFO("OMAP UDC rev %d.%d%s\n",
2840                 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2841                 config->otg ? ", Mini-AB" : "");
2842
2843         /* use the mode given to us by board init code */
2844         if (cpu_is_omap15xx()) {
2845                 hmc = HMC_1510;
2846                 type = "(unknown)";
2847
2848                 if (machine_without_vbus_sense()) {
2849                         /* just set up software VBUS detect, and then
2850                          * later rig it so we always report VBUS.
2851                          * FIXME without really sensing VBUS, we can't
2852                          * know when to turn PULLUP_EN on/off; and that
2853                          * means we always "need" the 48MHz clock.
2854                          */
2855                         u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2856                         tmp &= ~VBUS_CTRL_1510;
2857                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2858                         tmp |= VBUS_MODE_1510;
2859                         tmp &= ~VBUS_CTRL_1510;
2860                         omap_writel(tmp, FUNC_MUX_CTRL_0);
2861                 }
2862         } else {
2863                 /* The transceiver may package some GPIO logic or handle
2864                  * loopback and/or transceiverless setup; if we find one,
2865                  * use it.  Except for OTG, we don't _need_ to talk to one;
2866                  * but not having one probably means no VBUS detection.
2867                  */
2868                 xceiv = usb_get_transceiver();
2869                 if (xceiv)
2870                         type = xceiv->label;
2871                 else if (config->otg) {
2872                         DBG("OTG requires external transceiver!\n");
2873                         goto cleanup0;
2874                 }
2875
2876                 hmc = HMC_1610;
2877
2878                 if (cpu_is_omap24xx()) {
2879                         /* this could be transceiverless in one of the
2880                          * "we don't need to know" modes.
2881                          */
2882                         type = "external";
2883                         goto known;
2884                 }
2885
2886                 switch (hmc) {
2887                 case 0:                 /* POWERUP DEFAULT == 0 */
2888                 case 4:
2889                 case 12:
2890                 case 20:
2891                         if (!cpu_is_omap1710()) {
2892                                 type = "integrated";
2893                                 break;
2894                         }
2895                         /* FALL THROUGH */
2896                 case 3:
2897                 case 11:
2898                 case 16:
2899                 case 19:
2900                 case 25:
2901                         if (!xceiv) {
2902                                 DBG("external transceiver not registered!\n");
2903                                 type = "unknown";
2904                         }
2905                         break;
2906                 case 21:                        /* internal loopback */
2907                         type = "loopback";
2908                         break;
2909                 case 14:                        /* transceiverless */
2910                         if (cpu_is_omap1710())
2911                                 goto bad_on_1710;
2912                         /* FALL THROUGH */
2913                 case 13:
2914                 case 15:
2915                         type = "no";
2916                         break;
2917
2918                 default:
2919 bad_on_1710:
2920                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2921                         goto cleanup0;
2922                 }
2923         }
2924 known:
2925         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2926
2927         /* a "gadget" abstracts/virtualizes the controller */
2928         status = omap_udc_setup(pdev, xceiv);
2929         if (status) {
2930                 goto cleanup0;
2931         }
2932         xceiv = NULL;
2933         // "udc" is now valid
2934         pullup_disable(udc);
2935 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2936         udc->gadget.is_otg = (config->otg != 0);
2937 #endif
2938
2939         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2940         if (omap_readw(UDC_REV) >= 0x61)
2941                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2942         else
2943                 udc->clr_halt = UDC_RESET_EP;
2944
2945         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2946         status = request_irq(pdev->resource[1].start, omap_udc_irq,
2947                         IRQF_SAMPLE_RANDOM, driver_name, udc);
2948         if (status != 0) {
2949                 ERR("can't get irq %d, err %d\n",
2950                         (int) pdev->resource[1].start, status);
2951                 goto cleanup1;
2952         }
2953
2954         /* USB "non-iso" IRQ (PIO for all but ep0) */
2955         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2956                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2957         if (status != 0) {
2958                 ERR("can't get irq %d, err %d\n",
2959                         (int) pdev->resource[2].start, status);
2960                 goto cleanup2;
2961         }
2962 #ifdef  USE_ISO
2963         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2964                         0, "omap_udc iso", udc);
2965         if (status != 0) {
2966                 ERR("can't get irq %d, err %d\n",
2967                         (int) pdev->resource[3].start, status);
2968                 goto cleanup3;
2969         }
2970 #endif
2971         if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2972                 udc->dc_clk = dc_clk;
2973                 udc->hhc_clk = hhc_clk;
2974                 clk_disable(hhc_clk);
2975                 clk_disable(dc_clk);
2976         }
2977
2978         if (cpu_is_omap24xx()) {
2979                 udc->dc_clk = dc_clk;
2980                 udc->hhc_clk = hhc_clk;
2981                 /* FIXME OMAP2 don't release hhc & dc clock */
2982 #if 0
2983                 clk_disable(hhc_clk);
2984                 clk_disable(dc_clk);
2985 #endif
2986         }
2987
2988         create_proc_file();
2989         status = device_add(&udc->gadget.dev);
2990         if (status)
2991                 goto cleanup4;
2992
2993         status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2994         if (!status)
2995                 return status;
2996         /* If fail, fall through */
2997 cleanup4:
2998         remove_proc_file();
2999
3000 #ifdef  USE_ISO
3001 cleanup3:
3002         free_irq(pdev->resource[2].start, udc);
3003 #endif
3004
3005 cleanup2:
3006         free_irq(pdev->resource[1].start, udc);
3007
3008 cleanup1:
3009         kfree (udc);
3010         udc = NULL;
3011
3012 cleanup0:
3013         if (xceiv)
3014                 usb_put_transceiver(xceiv);
3015
3016         if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
3017                 clk_disable(hhc_clk);
3018                 clk_disable(dc_clk);
3019                 clk_put(hhc_clk);
3020                 clk_put(dc_clk);
3021         }
3022
3023         release_mem_region(pdev->resource[0].start,
3024                         pdev->resource[0].end - pdev->resource[0].start + 1);
3025
3026         return status;
3027 }
3028
3029 static int __exit omap_udc_remove(struct platform_device *pdev)
3030 {
3031         DECLARE_COMPLETION_ONSTACK(done);
3032
3033         if (!udc)
3034                 return -ENODEV;
3035
3036         usb_del_gadget_udc(&udc->gadget);
3037         if (udc->driver)
3038                 return -EBUSY;
3039
3040         udc->done = &done;
3041
3042         pullup_disable(udc);
3043         if (udc->transceiver) {
3044                 usb_put_transceiver(udc->transceiver);
3045                 udc->transceiver = NULL;
3046         }
3047         omap_writew(0, UDC_SYSCON1);
3048
3049         remove_proc_file();
3050
3051 #ifdef  USE_ISO
3052         free_irq(pdev->resource[3].start, udc);
3053 #endif
3054         free_irq(pdev->resource[2].start, udc);
3055         free_irq(pdev->resource[1].start, udc);
3056
3057         if (udc->dc_clk) {
3058                 if (udc->clk_requested)
3059                         omap_udc_enable_clock(0);
3060                 clk_put(udc->hhc_clk);
3061                 clk_put(udc->dc_clk);
3062         }
3063
3064         release_mem_region(pdev->resource[0].start,
3065                         pdev->resource[0].end - pdev->resource[0].start + 1);
3066
3067         device_unregister(&udc->gadget.dev);
3068         wait_for_completion(&done);
3069
3070         return 0;
3071 }
3072
3073 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3074  * system is forced into deep sleep
3075  *
3076  * REVISIT we should probably reject suspend requests when there's a host
3077  * session active, rather than disconnecting, at least on boards that can
3078  * report VBUS irqs (UDC_DEVSTAT.UDC_ATT).  And in any case, we need to
3079  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3080  * may involve talking to an external transceiver (e.g. isp1301).
3081  */
3082
3083 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3084 {
3085         u32     devstat;
3086
3087         devstat = omap_readw(UDC_DEVSTAT);
3088
3089         /* we're requesting 48 MHz clock if the pullup is enabled
3090          * (== we're attached to the host) and we're not suspended,
3091          * which would prevent entry to deep sleep...
3092          */
3093         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3094                 WARNING("session active; suspend requires disconnect\n");
3095                 omap_pullup(&udc->gadget, 0);
3096         }
3097
3098         return 0;
3099 }
3100
3101 static int omap_udc_resume(struct platform_device *dev)
3102 {
3103         DBG("resume + wakeup/SRP\n");
3104         omap_pullup(&udc->gadget, 1);
3105
3106         /* maybe the host would enumerate us if we nudged it */
3107         msleep(100);
3108         return omap_wakeup(&udc->gadget);
3109 }
3110
3111 /*-------------------------------------------------------------------------*/
3112
3113 static struct platform_driver udc_driver = {
3114         .remove         = __exit_p(omap_udc_remove),
3115         .suspend        = omap_udc_suspend,
3116         .resume         = omap_udc_resume,
3117         .driver         = {
3118                 .owner  = THIS_MODULE,
3119                 .name   = (char *) driver_name,
3120         },
3121 };
3122
3123 static int __init udc_init(void)
3124 {
3125         /* Disable DMA for omap7xx -- it doesn't work right. */
3126         if (cpu_is_omap7xx())
3127                 use_dma = 0;
3128
3129         INFO("%s, version: " DRIVER_VERSION
3130 #ifdef  USE_ISO
3131                 " (iso)"
3132 #endif
3133                 "%s\n", driver_desc,
3134                 use_dma ?  " (dma)" : "");
3135         return platform_driver_probe(&udc_driver, omap_udc_probe);
3136 }
3137 module_init(udc_init);
3138
3139 static void __exit udc_exit(void)
3140 {
3141         platform_driver_unregister(&udc_driver);
3142 }
3143 module_exit(udc_exit);
3144
3145 MODULE_DESCRIPTION(DRIVER_DESC);
3146 MODULE_LICENSE("GPL");
3147 MODULE_ALIAS("platform:omap_udc");