Pileus Git - ~andy/linux/blob - drivers/usb/gadget/fsl_udc_core.c

   1 /*
   2  * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Author: Li Yang <leoli@freescale.com>
   6  *         Jiang Bo <tanya.jiang@freescale.com>
   7  *
   8  * Description:
   9  * Freescale high-speed USB SOC DR module device controller driver.
  10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11  * The driver is previously named as mpc_udc.  Based on bare board
  12  * code from Dave Liu and Shlomi Gridish.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  */
  19
  20 #undef VERBOSE
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/ioport.h>
  25 #include <linux/types.h>
  26 #include <linux/errno.h>
  27 #include <linux/slab.h>
  28 #include <linux/init.h>
  29 #include <linux/list.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/mm.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/fsl_devices.h>
  41 #include <linux/dmapool.h>
  42 #include <linux/delay.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/unaligned.h>
  47 #include <asm/dma.h>
  48
  49 #include "fsl_usb2_udc.h"
  50
  51 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  52 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  53 #define DRIVER_VERSION  "Apr 20, 2007"
  54
  55 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  56
  57 static const char driver_name[] = "fsl-usb2-udc";
  58 static const char driver_desc[] = DRIVER_DESC;
  59
  60 static struct usb_dr_device *dr_regs;
  61 #ifndef CONFIG_ARCH_MXC
  62 static struct usb_sys_interface *usb_sys_regs;
  63 #endif
  64
  65 /* it is initialized in probe()  */
  66 static struct fsl_udc *udc_controller = NULL;
  67
  68 static const struct usb_endpoint_descriptor
  69 fsl_ep0_desc = {
  70         .bLength =              USB_DT_ENDPOINT_SIZE,
  71         .bDescriptorType =      USB_DT_ENDPOINT,
  72         .bEndpointAddress =     0,
  73         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  74         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  75 };
  76
  77 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  78
  79 #ifdef CONFIG_PPC32
  80 /*
  81  * On some SoCs, the USB controller registers can be big or little endian,
  82  * depending on the version of the chip. In order to be able to run the
  83  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  84  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  85  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  86  * call through those pointers. Platform code for SoCs that have BE USB
  87  * registers should set pdata->big_endian_mmio flag.
  88  *
  89  * This also applies to controller-to-cpu accessors for the USB descriptors,
  90  * since their endianness is also SoC dependant. Platform code for SoCs that
  91  * have BE USB descriptors should set pdata->big_endian_desc flag.
  92  */
  93 static u32 _fsl_readl_be(const unsigned __iomem *p)
  94 {
  95         return in_be32(p);
  96 }
  97
  98 static u32 _fsl_readl_le(const unsigned __iomem *p)
  99 {
 100         return in_le32(p);
 101 }
 102
 103 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 104 {
 105         out_be32(p, v);
 106 }
 107
 108 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 109 {
 110         out_le32(p, v);
 111 }
 112
 113 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 114 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 115
 116 #define fsl_readl(p)            (*_fsl_readl)((p))
 117 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 118
 119 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 120 {
 121         if (pdata->big_endian_mmio) {
 122                 _fsl_readl = _fsl_readl_be;
 123                 _fsl_writel = _fsl_writel_be;
 124         } else {
 125                 _fsl_readl = _fsl_readl_le;
 126                 _fsl_writel = _fsl_writel_le;
 127         }
 128 }
 129
 130 static inline u32 cpu_to_hc32(const u32 x)
 131 {
 132         return udc_controller->pdata->big_endian_desc
 133                 ? (__force u32)cpu_to_be32(x)
 134                 : (__force u32)cpu_to_le32(x);
 135 }
 136
 137 static inline u32 hc32_to_cpu(const u32 x)
 138 {
 139         return udc_controller->pdata->big_endian_desc
 140                 ? be32_to_cpu((__force __be32)x)
 141                 : le32_to_cpu((__force __le32)x);
 142 }
 143 #else /* !CONFIG_PPC32 */
 144 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 145
 146 #define fsl_readl(addr)         readl(addr)
 147 #define fsl_writel(val32, addr) writel(val32, addr)
 148 #define cpu_to_hc32(x)          cpu_to_le32(x)
 149 #define hc32_to_cpu(x)          le32_to_cpu(x)
 150 #endif /* CONFIG_PPC32 */
 151
 152 /********************************************************************
 153  *      Internal Used Function
 154 ********************************************************************/
 155 /*-----------------------------------------------------------------
 156  * done() - retire a request; caller blocked irqs
 157  * @status : request status to be set, only works when
 158  *      request is still in progress.
 159  *--------------------------------------------------------------*/
 160 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 161 {
 162         struct fsl_udc *udc = NULL;
 163         unsigned char stopped = ep->stopped;
 164         struct ep_td_struct *curr_td, *next_td;
 165         int j;
 166
 167         udc = (struct fsl_udc *)ep->udc;
 168         /* Removed the req from fsl_ep->queue */
 169         list_del_init(&req->queue);
 170
 171         /* req.status should be set as -EINPROGRESS in ep_queue() */
 172         if (req->req.status == -EINPROGRESS)
 173                 req->req.status = status;
 174         else
 175                 status = req->req.status;
 176
 177         /* Free dtd for the request */
 178         next_td = req->head;
 179         for (j = 0; j < req->dtd_count; j++) {
 180                 curr_td = next_td;
 181                 if (j != req->dtd_count - 1) {
 182                         next_td = curr_td->next_td_virt;
 183                 }
 184                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 185         }
 186
 187         if (req->mapped) {
 188                 dma_unmap_single(ep->udc->gadget.dev.parent,
 189                         req->req.dma, req->req.length,
 190                         ep_is_in(ep)
 191                                 ? DMA_TO_DEVICE
 192                                 : DMA_FROM_DEVICE);
 193                 req->req.dma = DMA_ADDR_INVALID;
 194                 req->mapped = 0;
 195         } else
 196                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 197                         req->req.dma, req->req.length,
 198                         ep_is_in(ep)
 199                                 ? DMA_TO_DEVICE
 200                                 : DMA_FROM_DEVICE);
 201
 202         if (status && (status != -ESHUTDOWN))
 203                 VDBG("complete %s req %p stat %d len %u/%u",
 204                         ep->ep.name, &req->req, status,
 205                         req->req.actual, req->req.length);
 206
 207         ep->stopped = 1;
 208
 209         spin_unlock(&ep->udc->lock);
 210         /* complete() is from gadget layer,
 211          * eg fsg->bulk_in_complete() */
 212         if (req->req.complete)
 213                 req->req.complete(&ep->ep, &req->req);
 214
 215         spin_lock(&ep->udc->lock);
 216         ep->stopped = stopped;
 217 }
 218
 219 /*-----------------------------------------------------------------
 220  * nuke(): delete all requests related to this ep
 221  * called with spinlock held
 222  *--------------------------------------------------------------*/
 223 static void nuke(struct fsl_ep *ep, int status)
 224 {
 225         ep->stopped = 1;
 226
 227         /* Flush fifo */
 228         fsl_ep_fifo_flush(&ep->ep);
 229
 230         /* Whether this eq has request linked */
 231         while (!list_empty(&ep->queue)) {
 232                 struct fsl_req *req = NULL;
 233
 234                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 235                 done(ep, req, status);
 236         }
 237 }
 238
 239 /*------------------------------------------------------------------
 240         Internal Hardware related function
 241  ------------------------------------------------------------------*/
 242
 243 static int dr_controller_setup(struct fsl_udc *udc)
 244 {
 245         unsigned int tmp, portctrl, ep_num;
 246         unsigned int max_no_of_ep;
 247 #ifndef CONFIG_ARCH_MXC
 248         unsigned int ctrl;
 249 #endif
 250         unsigned long timeout;
 251 #define FSL_UDC_RESET_TIMEOUT 1000
 252
 253         /* Config PHY interface */
 254         portctrl = fsl_readl(&dr_regs->portsc1);
 255         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 256         switch (udc->phy_mode) {
 257         case FSL_USB2_PHY_ULPI:
 258                 portctrl |= PORTSCX_PTS_ULPI;
 259                 break;
 260         case FSL_USB2_PHY_UTMI_WIDE:
 261                 portctrl |= PORTSCX_PTW_16BIT;
 262                 /* fall through */
 263         case FSL_USB2_PHY_UTMI:
 264                 portctrl |= PORTSCX_PTS_UTMI;
 265                 break;
 266         case FSL_USB2_PHY_SERIAL:
 267                 portctrl |= PORTSCX_PTS_FSLS;
 268                 break;
 269         default:
 270                 return -EINVAL;
 271         }
 272         fsl_writel(portctrl, &dr_regs->portsc1);
 273
 274         /* Stop and reset the usb controller */
 275         tmp = fsl_readl(&dr_regs->usbcmd);
 276         tmp &= ~USB_CMD_RUN_STOP;
 277         fsl_writel(tmp, &dr_regs->usbcmd);
 278
 279         tmp = fsl_readl(&dr_regs->usbcmd);
 280         tmp |= USB_CMD_CTRL_RESET;
 281         fsl_writel(tmp, &dr_regs->usbcmd);
 282
 283         /* Wait for reset to complete */
 284         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 285         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 286                 if (time_after(jiffies, timeout)) {
 287                         ERR("udc reset timeout!\n");
 288                         return -ETIMEDOUT;
 289                 }
 290                 cpu_relax();
 291         }
 292
 293         /* Set the controller as device mode */
 294         tmp = fsl_readl(&dr_regs->usbmode);
 295         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 296         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 297         /* Disable Setup Lockout */
 298         tmp |= USB_MODE_SETUP_LOCK_OFF;
 299         if (udc->pdata->es)
 300                 tmp |= USB_MODE_ES;
 301         fsl_writel(tmp, &dr_regs->usbmode);
 302
 303         /* Clear the setup status */
 304         fsl_writel(0, &dr_regs->usbsts);
 305
 306         tmp = udc->ep_qh_dma;
 307         tmp &= USB_EP_LIST_ADDRESS_MASK;
 308         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 309
 310         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 311                 udc->ep_qh, (int)tmp,
 312                 fsl_readl(&dr_regs->endpointlistaddr));
 313
 314         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 315         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 316                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 317                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 318                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 319                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 320                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 321         }
 322         /* Config control enable i/o output, cpu endian register */
 323 #ifndef CONFIG_ARCH_MXC
 324         if (udc->pdata->have_sysif_regs) {
 325                 ctrl = __raw_readl(&usb_sys_regs->control);
 326                 ctrl |= USB_CTRL_IOENB;
 327                 __raw_writel(ctrl, &usb_sys_regs->control);
 328         }
 329 #endif
 330
 331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 332         /* Turn on cache snooping hardware, since some PowerPC platforms
 333          * wholly rely on hardware to deal with cache coherent. */
 334
 335         if (udc->pdata->have_sysif_regs) {
 336                 /* Setup Snooping for all the 4GB space */
 337                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 338                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 339                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 340                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 341         }
 342 #endif
 343
 344         return 0;
 345 }
 346
 347 /* Enable DR irq and set controller to run state */
 348 static void dr_controller_run(struct fsl_udc *udc)
 349 {
 350         u32 temp;
 351
 352         /* Enable DR irq reg */
 353         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 354                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 355                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 356
 357         fsl_writel(temp, &dr_regs->usbintr);
 358
 359         /* Clear stopped bit */
 360         udc->stopped = 0;
 361
 362         /* Set the controller as device mode */
 363         temp = fsl_readl(&dr_regs->usbmode);
 364         temp |= USB_MODE_CTRL_MODE_DEVICE;
 365         fsl_writel(temp, &dr_regs->usbmode);
 366
 367         /* Set controller to Run */
 368         temp = fsl_readl(&dr_regs->usbcmd);
 369         temp |= USB_CMD_RUN_STOP;
 370         fsl_writel(temp, &dr_regs->usbcmd);
 371 }
 372
 373 static void dr_controller_stop(struct fsl_udc *udc)
 374 {
 375         unsigned int tmp;
 376
 377         pr_debug("%s\n", __func__);
 378
 379         /* if we're in OTG mode, and the Host is currently using the port,
 380          * stop now and don't rip the controller out from under the
 381          * ehci driver
 382          */
 383         if (udc->gadget.is_otg) {
 384                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 385                         pr_debug("udc: Leaving early\n");
 386                         return;
 387                 }
 388         }
 389
 390         /* disable all INTR */
 391         fsl_writel(0, &dr_regs->usbintr);
 392
 393         /* Set stopped bit for isr */
 394         udc->stopped = 1;
 395
 396         /* disable IO output */
 397 /*      usb_sys_regs->control = 0; */
 398
 399         /* set controller to Stop */
 400         tmp = fsl_readl(&dr_regs->usbcmd);
 401         tmp &= ~USB_CMD_RUN_STOP;
 402         fsl_writel(tmp, &dr_regs->usbcmd);
 403 }
 404
 405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 406                         unsigned char ep_type)
 407 {
 408         unsigned int tmp_epctrl = 0;
 409
 410         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 411         if (dir) {
 412                 if (ep_num)
 413                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 414                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 415                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 416                 tmp_epctrl |= ((unsigned int)(ep_type)
 417                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 418         } else {
 419                 if (ep_num)
 420                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 421                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 422                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 423                 tmp_epctrl |= ((unsigned int)(ep_type)
 424                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 425         }
 426
 427         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 428 }
 429
 430 static void
 431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 432 {
 433         u32 tmp_epctrl = 0;
 434
 435         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 436
 437         if (value) {
 438                 /* set the stall bit */
 439                 if (dir)
 440                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 441                 else
 442                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 443         } else {
 444                 /* clear the stall bit and reset data toggle */
 445                 if (dir) {
 446                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 447                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 448                 } else {
 449                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 450                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 451                 }
 452         }
 453         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 454 }
 455
 456 /* Get stall status of a specific ep
 457    Return: 0: not stalled; 1:stalled */
 458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 459 {
 460         u32 epctrl;
 461
 462         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 463         if (dir)
 464                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 465         else
 466                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 467 }
 468
 469 /********************************************************************
 470         Internal Structure Build up functions
 471 ********************************************************************/
 472
 473 /*------------------------------------------------------------------
 474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 475  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 476  * @mult: Mult field
 477  ------------------------------------------------------------------*/
 478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 479                 unsigned char dir, unsigned char ep_type,
 480                 unsigned int max_pkt_len,
 481                 unsigned int zlt, unsigned char mult)
 482 {
 483         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 484         unsigned int tmp = 0;
 485
 486         /* set the Endpoint Capabilites in QH */
 487         switch (ep_type) {
 488         case USB_ENDPOINT_XFER_CONTROL:
 489                 /* Interrupt On Setup (IOS). for control ep  */
 490                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 491                         | EP_QUEUE_HEAD_IOS;
 492                 break;
 493         case USB_ENDPOINT_XFER_ISOC:
 494                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 495                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 496                 break;
 497         case USB_ENDPOINT_XFER_BULK:
 498         case USB_ENDPOINT_XFER_INT:
 499                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 500                 break;
 501         default:
 502                 VDBG("error ep type is %d", ep_type);
 503                 return;
 504         }
 505         if (zlt)
 506                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 507
 508         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 509         p_QH->next_dtd_ptr = 1;
 510         p_QH->size_ioc_int_sts = 0;
 511 }
 512
 513 /* Setup qh structure and ep register for ep0. */
 514 static void ep0_setup(struct fsl_udc *udc)
 515 {
 516         /* the intialization of an ep includes: fields in QH, Regs,
 517          * fsl_ep struct */
 518         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 519                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 520         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 521                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 522         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 523         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 524
 525         return;
 526
 527 }
 528
 529 /***********************************************************************
 530                 Endpoint Management Functions
 531 ***********************************************************************/
 532
 533 /*-------------------------------------------------------------------------
 534  * when configurations are set, or when interface settings change
 535  * for example the do_set_interface() in gadget layer,
 536  * the driver will enable or disable the relevant endpoints
 537  * ep0 doesn't use this routine. It is always enabled.
 538 -------------------------------------------------------------------------*/
 539 static int fsl_ep_enable(struct usb_ep *_ep,
 540                 const struct usb_endpoint_descriptor *desc)
 541 {
 542         struct fsl_udc *udc = NULL;
 543         struct fsl_ep *ep = NULL;
 544         unsigned short max = 0;
 545         unsigned char mult = 0, zlt;
 546         int retval = -EINVAL;
 547         unsigned long flags = 0;
 548
 549         ep = container_of(_ep, struct fsl_ep, ep);
 550
 551         /* catch various bogus parameters */
 552         if (!_ep || !desc || ep->desc
 553                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 554                 return -EINVAL;
 555
 556         udc = ep->udc;
 557
 558         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 559                 return -ESHUTDOWN;
 560
 561         max = usb_endpoint_maxp(desc);
 562
 563         /* Disable automatic zlp generation.  Driver is responsible to indicate
 564          * explicitly through req->req.zero.  This is needed to enable multi-td
 565          * request. */
 566         zlt = 1;
 567
 568         /* Assume the max packet size from gadget is always correct */
 569         switch (desc->bmAttributes & 0x03) {
 570         case USB_ENDPOINT_XFER_CONTROL:
 571         case USB_ENDPOINT_XFER_BULK:
 572         case USB_ENDPOINT_XFER_INT:
 573                 /* mult = 0.  Execute N Transactions as demonstrated by
 574                  * the USB variable length packet protocol where N is
 575                  * computed using the Maximum Packet Length (dQH) and
 576                  * the Total Bytes field (dTD) */
 577                 mult = 0;
 578                 break;
 579         case USB_ENDPOINT_XFER_ISOC:
 580                 /* Calculate transactions needed for high bandwidth iso */
 581                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 582                 max = max & 0x7ff;      /* bit 0~10 */
 583                 /* 3 transactions at most */
 584                 if (mult > 3)
 585                         goto en_done;
 586                 break;
 587         default:
 588                 goto en_done;
 589         }
 590
 591         spin_lock_irqsave(&udc->lock, flags);
 592         ep->ep.maxpacket = max;
 593         ep->desc = desc;
 594         ep->stopped = 0;
 595
 596         /* Controller related setup */
 597         /* Init EPx Queue Head (Ep Capabilites field in QH
 598          * according to max, zlt, mult) */
 599         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 600                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 601                                         ?  USB_SEND : USB_RECV),
 602                         (unsigned char) (desc->bmAttributes
 603                                         & USB_ENDPOINT_XFERTYPE_MASK),
 604                         max, zlt, mult);
 605
 606         /* Init endpoint ctrl register */
 607         dr_ep_setup((unsigned char) ep_index(ep),
 608                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 609                                         ? USB_SEND : USB_RECV),
 610                         (unsigned char) (desc->bmAttributes
 611                                         & USB_ENDPOINT_XFERTYPE_MASK));
 612
 613         spin_unlock_irqrestore(&udc->lock, flags);
 614         retval = 0;
 615
 616         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 617                         ep->desc->bEndpointAddress & 0x0f,
 618                         (desc->bEndpointAddress & USB_DIR_IN)
 619                                 ? "in" : "out", max);
 620 en_done:
 621         return retval;
 622 }
 623
 624 /*---------------------------------------------------------------------
 625  * @ep : the ep being unconfigured. May not be ep0
 626  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 627 *---------------------------------------------------------------------*/
 628 static int fsl_ep_disable(struct usb_ep *_ep)
 629 {
 630         struct fsl_udc *udc = NULL;
 631         struct fsl_ep *ep = NULL;
 632         unsigned long flags = 0;
 633         u32 epctrl;
 634         int ep_num;
 635
 636         ep = container_of(_ep, struct fsl_ep, ep);
 637         if (!_ep || !ep->desc) {
 638                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 639                 return -EINVAL;
 640         }
 641
 642         /* disable ep on controller */
 643         ep_num = ep_index(ep);
 644         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 645         if (ep_is_in(ep)) {
 646                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 647                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 648         } else {
 649                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 650                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 651         }
 652         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 653
 654         udc = (struct fsl_udc *)ep->udc;
 655         spin_lock_irqsave(&udc->lock, flags);
 656
 657         /* nuke all pending requests (does flush) */
 658         nuke(ep, -ESHUTDOWN);
 659
 660         ep->desc = NULL;
 661         ep->ep.desc = NULL;
 662         ep->stopped = 1;
 663         spin_unlock_irqrestore(&udc->lock, flags);
 664
 665         VDBG("disabled %s OK", _ep->name);
 666         return 0;
 667 }
 668
 669 /*---------------------------------------------------------------------
 670  * allocate a request object used by this endpoint
 671  * the main operation is to insert the req->queue to the eq->queue
 672  * Returns the request, or null if one could not be allocated
 673 *---------------------------------------------------------------------*/
 674 static struct usb_request *
 675 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 676 {
 677         struct fsl_req *req = NULL;
 678
 679         req = kzalloc(sizeof *req, gfp_flags);
 680         if (!req)
 681                 return NULL;
 682
 683         req->req.dma = DMA_ADDR_INVALID;
 684         INIT_LIST_HEAD(&req->queue);
 685
 686         return &req->req;
 687 }
 688
 689 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 690 {
 691         struct fsl_req *req = NULL;
 692
 693         req = container_of(_req, struct fsl_req, req);
 694
 695         if (_req)
 696                 kfree(req);
 697 }
 698
 699 /* Actually add a dTD chain to an empty dQH and let go */
 700 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 701 {
 702         struct ep_queue_head *qh = get_qh_by_ep(ep);
 703
 704         /* Write dQH next pointer and terminate bit to 0 */
 705         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 706                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 707
 708         /* Clear active and halt bit */
 709         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 710                                         | EP_QUEUE_HEAD_STATUS_HALT));
 711
 712         /* Ensure that updates to the QH will occur before priming. */
 713         wmb();
 714
 715         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 716         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 717                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 718 }
 719
 720 /* Add dTD chain to the dQH of an EP */
 721 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 722 {
 723         u32 temp, bitmask, tmp_stat;
 724
 725         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 726         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 727
 728         bitmask = ep_is_in(ep)
 729                 ? (1 << (ep_index(ep) + 16))
 730                 : (1 << (ep_index(ep)));
 731
 732         /* check if the pipe is empty */
 733         if (!(list_empty(&ep->queue))) {
 734                 /* Add td to the end */
 735                 struct fsl_req *lastreq;
 736                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 737                 lastreq->tail->next_td_ptr =
 738                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 739                 /* Read prime bit, if 1 goto done */
 740                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 741                         return;
 742
 743                 do {
 744                         /* Set ATDTW bit in USBCMD */
 745                         temp = fsl_readl(&dr_regs->usbcmd);
 746                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 747
 748                         /* Read correct status bit */
 749                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 750
 751                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 752
 753                 /* Write ATDTW bit to 0 */
 754                 temp = fsl_readl(&dr_regs->usbcmd);
 755                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 756
 757                 if (tmp_stat)
 758                         return;
 759         }
 760
 761         fsl_prime_ep(ep, req->head);
 762 }
 763
 764 /* Fill in the dTD structure
 765  * @req: request that the transfer belongs to
 766  * @length: return actually data length of the dTD
 767  * @dma: return dma address of the dTD
 768  * @is_last: return flag if it is the last dTD of the request
 769  * return: pointer to the built dTD */
 770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 771                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 772 {
 773         u32 swap_temp;
 774         struct ep_td_struct *dtd;
 775
 776         /* how big will this transfer be? */
 777         *length = min(req->req.length - req->req.actual,
 778                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 779
 780         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 781         if (dtd == NULL)
 782                 return dtd;
 783
 784         dtd->td_dma = *dma;
 785         /* Clear reserved field */
 786         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 787         swap_temp &= ~DTD_RESERVED_FIELDS;
 788         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 789
 790         /* Init all of buffer page pointers */
 791         swap_temp = (u32) (req->req.dma + req->req.actual);
 792         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 793         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 794         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 795         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 796         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 797
 798         req->req.actual += *length;
 799
 800         /* zlp is needed if req->req.zero is set */
 801         if (req->req.zero) {
 802                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 803                         *is_last = 1;
 804                 else
 805                         *is_last = 0;
 806         } else if (req->req.length == req->req.actual)
 807                 *is_last = 1;
 808         else
 809                 *is_last = 0;
 810
 811         if ((*is_last) == 0)
 812                 VDBG("multi-dtd request!");
 813         /* Fill in the transfer size; set active bit */
 814         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 815
 816         /* Enable interrupt for the last dtd of a request */
 817         if (*is_last && !req->req.no_interrupt)
 818                 swap_temp |= DTD_IOC;
 819
 820         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 821
 822         mb();
 823
 824         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 825
 826         return dtd;
 827 }
 828
 829 /* Generate dtd chain for a request */
 830 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 831 {
 832         unsigned        count;
 833         int             is_last;
 834         int             is_first =1;
 835         struct ep_td_struct     *last_dtd = NULL, *dtd;
 836         dma_addr_t dma;
 837
 838         do {
 839                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 840                 if (dtd == NULL)
 841                         return -ENOMEM;
 842
 843                 if (is_first) {
 844                         is_first = 0;
 845                         req->head = dtd;
 846                 } else {
 847                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 848                         last_dtd->next_td_virt = dtd;
 849                 }
 850                 last_dtd = dtd;
 851
 852                 req->dtd_count++;
 853         } while (!is_last);
 854
 855         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 856
 857         req->tail = dtd;
 858
 859         return 0;
 860 }
 861
 862 /* queues (submits) an I/O request to an endpoint */
 863 static int
 864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 865 {
 866         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 867         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 868         struct fsl_udc *udc;
 869         unsigned long flags;
 870
 871         /* catch various bogus parameters */
 872         if (!_req || !req->req.complete || !req->req.buf
 873                         || !list_empty(&req->queue)) {
 874                 VDBG("%s, bad params", __func__);
 875                 return -EINVAL;
 876         }
 877         if (unlikely(!_ep || !ep->desc)) {
 878                 VDBG("%s, bad ep", __func__);
 879                 return -EINVAL;
 880         }
 881         if (usb_endpoint_xfer_isoc(ep->desc)) {
 882                 if (req->req.length > ep->ep.maxpacket)
 883                         return -EMSGSIZE;
 884         }
 885
 886         udc = ep->udc;
 887         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 888                 return -ESHUTDOWN;
 889
 890         req->ep = ep;
 891
 892         /* map virtual address to hardware */
 893         if (req->req.dma == DMA_ADDR_INVALID) {
 894                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 895                                         req->req.buf,
 896                                         req->req.length, ep_is_in(ep)
 897                                                 ? DMA_TO_DEVICE
 898                                                 : DMA_FROM_DEVICE);
 899                 req->mapped = 1;
 900         } else {
 901                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 902                                         req->req.dma, req->req.length,
 903                                         ep_is_in(ep)
 904                                                 ? DMA_TO_DEVICE
 905                                                 : DMA_FROM_DEVICE);
 906                 req->mapped = 0;
 907         }
 908
 909         req->req.status = -EINPROGRESS;
 910         req->req.actual = 0;
 911         req->dtd_count = 0;
 912
 913         /* build dtds and push them to device queue */
 914         if (!fsl_req_to_dtd(req, gfp_flags)) {
 915                 spin_lock_irqsave(&udc->lock, flags);
 916                 fsl_queue_td(ep, req);
 917         } else {
 918                 return -ENOMEM;
 919         }
 920
 921         /* Update ep0 state */
 922         if ((ep_index(ep) == 0))
 923                 udc->ep0_state = DATA_STATE_XMIT;
 924
 925         /* irq handler advances the queue */
 926         if (req != NULL)
 927                 list_add_tail(&req->queue, &ep->queue);
 928         spin_unlock_irqrestore(&udc->lock, flags);
 929
 930         return 0;
 931 }
 932
 933 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 934 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 935 {
 936         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 937         struct fsl_req *req;
 938         unsigned long flags;
 939         int ep_num, stopped, ret = 0;
 940         u32 epctrl;
 941
 942         if (!_ep || !_req)
 943                 return -EINVAL;
 944
 945         spin_lock_irqsave(&ep->udc->lock, flags);
 946         stopped = ep->stopped;
 947
 948         /* Stop the ep before we deal with the queue */
 949         ep->stopped = 1;
 950         ep_num = ep_index(ep);
 951         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 952         if (ep_is_in(ep))
 953                 epctrl &= ~EPCTRL_TX_ENABLE;
 954         else
 955                 epctrl &= ~EPCTRL_RX_ENABLE;
 956         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 957
 958         /* make sure it's actually queued on this endpoint */
 959         list_for_each_entry(req, &ep->queue, queue) {
 960                 if (&req->req == _req)
 961                         break;
 962         }
 963         if (&req->req != _req) {
 964                 ret = -EINVAL;
 965                 goto out;
 966         }
 967
 968         /* The request is in progress, or completed but not dequeued */
 969         if (ep->queue.next == &req->queue) {
 970                 _req->status = -ECONNRESET;
 971                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 972
 973                 /* The request isn't the last request in this ep queue */
 974                 if (req->queue.next != &ep->queue) {
 975                         struct fsl_req *next_req;
 976
 977                         next_req = list_entry(req->queue.next, struct fsl_req,
 978                                         queue);
 979
 980                         /* prime with dTD of next request */
 981                         fsl_prime_ep(ep, next_req->head);
 982                 }
 983         /* The request hasn't been processed, patch up the TD chain */
 984         } else {
 985                 struct fsl_req *prev_req;
 986
 987                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 988                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 989         }
 990
 991         done(ep, req, -ECONNRESET);
 992
 993         /* Enable EP */
 994 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 995         if (ep_is_in(ep))
 996                 epctrl |= EPCTRL_TX_ENABLE;
 997         else
 998                 epctrl |= EPCTRL_RX_ENABLE;
 999         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1000         ep->stopped = stopped;
1001
1002         spin_unlock_irqrestore(&ep->udc->lock, flags);
1003         return ret;
1004 }
1005
1006 /*-------------------------------------------------------------------------*/
1007
1008 /*-----------------------------------------------------------------
1009  * modify the endpoint halt feature
1010  * @ep: the non-isochronous endpoint being stalled
1011  * @value: 1--set halt  0--clear halt
1012  * Returns zero, or a negative error code.
1013 *----------------------------------------------------------------*/
1014 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1015 {
1016         struct fsl_ep *ep = NULL;
1017         unsigned long flags = 0;
1018         int status = -EOPNOTSUPP;       /* operation not supported */
1019         unsigned char ep_dir = 0, ep_num = 0;
1020         struct fsl_udc *udc = NULL;
1021
1022         ep = container_of(_ep, struct fsl_ep, ep);
1023         udc = ep->udc;
1024         if (!_ep || !ep->desc) {
1025                 status = -EINVAL;
1026                 goto out;
1027         }
1028
1029         if (usb_endpoint_xfer_isoc(ep->desc)) {
1030                 status = -EOPNOTSUPP;
1031                 goto out;
1032         }
1033
1034         /* Attempt to halt IN ep will fail if any transfer requests
1035          * are still queue */
1036         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1037                 status = -EAGAIN;
1038                 goto out;
1039         }
1040
1041         status = 0;
1042         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1043         ep_num = (unsigned char)(ep_index(ep));
1044         spin_lock_irqsave(&ep->udc->lock, flags);
1045         dr_ep_change_stall(ep_num, ep_dir, value);
1046         spin_unlock_irqrestore(&ep->udc->lock, flags);
1047
1048         if (ep_index(ep) == 0) {
1049                 udc->ep0_state = WAIT_FOR_SETUP;
1050                 udc->ep0_dir = 0;
1051         }
1052 out:
1053         VDBG(" %s %s halt stat %d", ep->ep.name,
1054                         value ?  "set" : "clear", status);
1055
1056         return status;
1057 }
1058
1059 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1060 {
1061         struct fsl_ep *ep;
1062         struct fsl_udc *udc;
1063         int size = 0;
1064         u32 bitmask;
1065         struct ep_queue_head *qh;
1066
1067         ep = container_of(_ep, struct fsl_ep, ep);
1068         if (!_ep || (!ep->desc && ep_index(ep) != 0))
1069                 return -ENODEV;
1070
1071         udc = (struct fsl_udc *)ep->udc;
1072
1073         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1074                 return -ESHUTDOWN;
1075
1076         qh = get_qh_by_ep(ep);
1077
1078         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1079             (1 << (ep_index(ep)));
1080
1081         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1082                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1083                     >> DTD_LENGTH_BIT_POS;
1084
1085         pr_debug("%s %u\n", __func__, size);
1086         return size;
1087 }
1088
1089 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1090 {
1091         struct fsl_ep *ep;
1092         int ep_num, ep_dir;
1093         u32 bits;
1094         unsigned long timeout;
1095 #define FSL_UDC_FLUSH_TIMEOUT 1000
1096
1097         if (!_ep) {
1098                 return;
1099         } else {
1100                 ep = container_of(_ep, struct fsl_ep, ep);
1101                 if (!ep->desc)
1102                         return;
1103         }
1104         ep_num = ep_index(ep);
1105         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1106
1107         if (ep_num == 0)
1108                 bits = (1 << 16) | 1;
1109         else if (ep_dir == USB_SEND)
1110                 bits = 1 << (16 + ep_num);
1111         else
1112                 bits = 1 << ep_num;
1113
1114         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1115         do {
1116                 fsl_writel(bits, &dr_regs->endptflush);
1117
1118                 /* Wait until flush complete */
1119                 while (fsl_readl(&dr_regs->endptflush)) {
1120                         if (time_after(jiffies, timeout)) {
1121                                 ERR("ep flush timeout\n");
1122                                 return;
1123                         }
1124                         cpu_relax();
1125                 }
1126                 /* See if we need to flush again */
1127         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1128 }
1129
1130 static struct usb_ep_ops fsl_ep_ops = {
1131         .enable = fsl_ep_enable,
1132         .disable = fsl_ep_disable,
1133
1134         .alloc_request = fsl_alloc_request,
1135         .free_request = fsl_free_request,
1136
1137         .queue = fsl_ep_queue,
1138         .dequeue = fsl_ep_dequeue,
1139
1140         .set_halt = fsl_ep_set_halt,
1141         .fifo_status = fsl_ep_fifo_status,
1142         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1143 };
1144
1145 /*-------------------------------------------------------------------------
1146                 Gadget Driver Layer Operations
1147 -------------------------------------------------------------------------*/
1148
1149 /*----------------------------------------------------------------------
1150  * Get the current frame number (from DR frame_index Reg )
1151  *----------------------------------------------------------------------*/
1152 static int fsl_get_frame(struct usb_gadget *gadget)
1153 {
1154         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1155 }
1156
1157 /*-----------------------------------------------------------------------
1158  * Tries to wake up the host connected to this gadget
1159  -----------------------------------------------------------------------*/
1160 static int fsl_wakeup(struct usb_gadget *gadget)
1161 {
1162         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1163         u32 portsc;
1164
1165         /* Remote wakeup feature not enabled by host */
1166         if (!udc->remote_wakeup)
1167                 return -ENOTSUPP;
1168
1169         portsc = fsl_readl(&dr_regs->portsc1);
1170         /* not suspended? */
1171         if (!(portsc & PORTSCX_PORT_SUSPEND))
1172                 return 0;
1173         /* trigger force resume */
1174         portsc |= PORTSCX_PORT_FORCE_RESUME;
1175         fsl_writel(portsc, &dr_regs->portsc1);
1176         return 0;
1177 }
1178
1179 static int can_pullup(struct fsl_udc *udc)
1180 {
1181         return udc->driver && udc->softconnect && udc->vbus_active;
1182 }
1183
1184 /* Notify controller that VBUS is powered, Called by whatever
1185    detects VBUS sessions */
1186 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1187 {
1188         struct fsl_udc  *udc;
1189         unsigned long   flags;
1190
1191         udc = container_of(gadget, struct fsl_udc, gadget);
1192         spin_lock_irqsave(&udc->lock, flags);
1193         VDBG("VBUS %s", is_active ? "on" : "off");
1194         udc->vbus_active = (is_active != 0);
1195         if (can_pullup(udc))
1196                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1197                                 &dr_regs->usbcmd);
1198         else
1199                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1200                                 &dr_regs->usbcmd);
1201         spin_unlock_irqrestore(&udc->lock, flags);
1202         return 0;
1203 }
1204
1205 /* constrain controller's VBUS power usage
1206  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1207  * reporting how much power the device may consume.  For example, this
1208  * could affect how quickly batteries are recharged.
1209  *
1210  * Returns zero on success, else negative errno.
1211  */
1212 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1213 {
1214         struct fsl_udc *udc;
1215
1216         udc = container_of(gadget, struct fsl_udc, gadget);
1217         if (udc->transceiver)
1218                 return usb_phy_set_power(udc->transceiver, mA);
1219         return -ENOTSUPP;
1220 }
1221
1222 /* Change Data+ pullup status
1223  * this func is used by usb_gadget_connect/disconnet
1224  */
1225 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1226 {
1227         struct fsl_udc *udc;
1228
1229         udc = container_of(gadget, struct fsl_udc, gadget);
1230         udc->softconnect = (is_on != 0);
1231         if (can_pullup(udc))
1232                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1233                                 &dr_regs->usbcmd);
1234         else
1235                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1236                                 &dr_regs->usbcmd);
1237
1238         return 0;
1239 }
1240
1241 static int fsl_start(struct usb_gadget_driver *driver,
1242                 int (*bind)(struct usb_gadget *));
1243 static int fsl_stop(struct usb_gadget_driver *driver);
1244 /* defined in gadget.h */
1245 static struct usb_gadget_ops fsl_gadget_ops = {
1246         .get_frame = fsl_get_frame,
1247         .wakeup = fsl_wakeup,
1248 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1249         .vbus_session = fsl_vbus_session,
1250         .vbus_draw = fsl_vbus_draw,
1251         .pullup = fsl_pullup,
1252         .start = fsl_start,
1253         .stop = fsl_stop,
1254 };
1255
1256 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1257    on new transaction */
1258 static void ep0stall(struct fsl_udc *udc)
1259 {
1260         u32 tmp;
1261
1262         /* must set tx and rx to stall at the same time */
1263         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1264         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1265         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1266         udc->ep0_state = WAIT_FOR_SETUP;
1267         udc->ep0_dir = 0;
1268 }
1269
1270 /* Prime a status phase for ep0 */
1271 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1272 {
1273         struct fsl_req *req = udc->status_req;
1274         struct fsl_ep *ep;
1275
1276         if (direction == EP_DIR_IN)
1277                 udc->ep0_dir = USB_DIR_IN;
1278         else
1279                 udc->ep0_dir = USB_DIR_OUT;
1280
1281         ep = &udc->eps[0];
1282         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1283
1284         req->ep = ep;
1285         req->req.length = 0;
1286         req->req.status = -EINPROGRESS;
1287         req->req.actual = 0;
1288         req->req.complete = NULL;
1289         req->dtd_count = 0;
1290
1291         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1292                         req->req.buf, req->req.length,
1293                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1294         req->mapped = 1;
1295
1296         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1297                 fsl_queue_td(ep, req);
1298         else
1299                 return -ENOMEM;
1300
1301         list_add_tail(&req->queue, &ep->queue);
1302
1303         return 0;
1304 }
1305
1306 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1307 {
1308         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1309
1310         if (ep->name)
1311                 nuke(ep, -ESHUTDOWN);
1312 }
1313
1314 /*
1315  * ch9 Set address
1316  */
1317 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1318 {
1319         /* Save the new address to device struct */
1320         udc->device_address = (u8) value;
1321         /* Update usb state */
1322         udc->usb_state = USB_STATE_ADDRESS;
1323         /* Status phase */
1324         if (ep0_prime_status(udc, EP_DIR_IN))
1325                 ep0stall(udc);
1326 }
1327
1328 /*
1329  * ch9 Get status
1330  */
1331 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1332                 u16 index, u16 length)
1333 {
1334         u16 tmp = 0;            /* Status, cpu endian */
1335         struct fsl_req *req;
1336         struct fsl_ep *ep;
1337
1338         ep = &udc->eps[0];
1339
1340         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1341                 /* Get device status */
1342                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1343                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1344         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1345                 /* Get interface status */
1346                 /* We don't have interface information in udc driver */
1347                 tmp = 0;
1348         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1349                 /* Get endpoint status */
1350                 struct fsl_ep *target_ep;
1351
1352                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1353
1354                 /* stall if endpoint doesn't exist */
1355                 if (!target_ep->desc)
1356                         goto stall;
1357                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1358                                 << USB_ENDPOINT_HALT;
1359         }
1360
1361         udc->ep0_dir = USB_DIR_IN;
1362         /* Borrow the per device status_req */
1363         req = udc->status_req;
1364         /* Fill in the reqest structure */
1365         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1366
1367         req->ep = ep;
1368         req->req.length = 2;
1369         req->req.status = -EINPROGRESS;
1370         req->req.actual = 0;
1371         req->req.complete = NULL;
1372         req->dtd_count = 0;
1373
1374         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1375                                 req->req.buf, req->req.length,
1376                                 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1377         req->mapped = 1;
1378
1379         /* prime the data phase */
1380         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1381                 fsl_queue_td(ep, req);
1382         else                    /* no mem */
1383                 goto stall;
1384
1385         list_add_tail(&req->queue, &ep->queue);
1386         udc->ep0_state = DATA_STATE_XMIT;
1387         return;
1388 stall:
1389         ep0stall(udc);
1390 }
1391
1392 static void setup_received_irq(struct fsl_udc *udc,
1393                 struct usb_ctrlrequest *setup)
1394 {
1395         u16 wValue = le16_to_cpu(setup->wValue);
1396         u16 wIndex = le16_to_cpu(setup->wIndex);
1397         u16 wLength = le16_to_cpu(setup->wLength);
1398
1399         udc_reset_ep_queue(udc, 0);
1400
1401         /* We process some stardard setup requests here */
1402         switch (setup->bRequest) {
1403         case USB_REQ_GET_STATUS:
1404                 /* Data+Status phase from udc */
1405                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1406                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1407                         break;
1408                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1409                 return;
1410
1411         case USB_REQ_SET_ADDRESS:
1412                 /* Status phase from udc */
1413                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1414                                                 | USB_RECIP_DEVICE))
1415                         break;
1416                 ch9setaddress(udc, wValue, wIndex, wLength);
1417                 return;
1418
1419         case USB_REQ_CLEAR_FEATURE:
1420         case USB_REQ_SET_FEATURE:
1421                 /* Status phase from udc */
1422         {
1423                 int rc = -EOPNOTSUPP;
1424                 u16 ptc = 0;
1425
1426                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1427                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1428                         int pipe = get_pipe_by_windex(wIndex);
1429                         struct fsl_ep *ep;
1430
1431                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1432                                 break;
1433                         ep = get_ep_by_pipe(udc, pipe);
1434
1435                         spin_unlock(&udc->lock);
1436                         rc = fsl_ep_set_halt(&ep->ep,
1437                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1438                                                 ? 1 : 0);
1439                         spin_lock(&udc->lock);
1440
1441                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1442                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1443                                 | USB_TYPE_STANDARD)) {
1444                         /* Note: The driver has not include OTG support yet.
1445                          * This will be set when OTG support is added */
1446                         if (wValue == USB_DEVICE_TEST_MODE)
1447                                 ptc = wIndex >> 8;
1448                         else if (gadget_is_otg(&udc->gadget)) {
1449                                 if (setup->bRequest ==
1450                                     USB_DEVICE_B_HNP_ENABLE)
1451                                         udc->gadget.b_hnp_enable = 1;
1452                                 else if (setup->bRequest ==
1453                                          USB_DEVICE_A_HNP_SUPPORT)
1454                                         udc->gadget.a_hnp_support = 1;
1455                                 else if (setup->bRequest ==
1456                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1457                                         udc->gadget.a_alt_hnp_support = 1;
1458                         }
1459                         rc = 0;
1460                 } else
1461                         break;
1462
1463                 if (rc == 0) {
1464                         if (ep0_prime_status(udc, EP_DIR_IN))
1465                                 ep0stall(udc);
1466                 }
1467                 if (ptc) {
1468                         u32 tmp;
1469
1470                         mdelay(10);
1471                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1472                         fsl_writel(tmp, &dr_regs->portsc1);
1473                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1474                 }
1475
1476                 return;
1477         }
1478
1479         default:
1480                 break;
1481         }
1482
1483         /* Requests handled by gadget */
1484         if (wLength) {
1485                 /* Data phase from gadget, status phase from udc */
1486                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1487                                 ?  USB_DIR_IN : USB_DIR_OUT;
1488                 spin_unlock(&udc->lock);
1489                 if (udc->driver->setup(&udc->gadget,
1490                                 &udc->local_setup_buff) < 0)
1491                         ep0stall(udc);
1492                 spin_lock(&udc->lock);
1493                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1494                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1495         } else {
1496                 /* No data phase, IN status from gadget */
1497                 udc->ep0_dir = USB_DIR_IN;
1498                 spin_unlock(&udc->lock);
1499                 if (udc->driver->setup(&udc->gadget,
1500                                 &udc->local_setup_buff) < 0)
1501                         ep0stall(udc);
1502                 spin_lock(&udc->lock);
1503                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1504         }
1505 }
1506
1507 /* Process request for Data or Status phase of ep0
1508  * prime status phase if needed */
1509 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1510                 struct fsl_req *req)
1511 {
1512         if (udc->usb_state == USB_STATE_ADDRESS) {
1513                 /* Set the new address */
1514                 u32 new_address = (u32) udc->device_address;
1515                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1516                                 &dr_regs->deviceaddr);
1517         }
1518
1519         done(ep0, req, 0);
1520
1521         switch (udc->ep0_state) {
1522         case DATA_STATE_XMIT:
1523                 /* receive status phase */
1524                 if (ep0_prime_status(udc, EP_DIR_OUT))
1525                         ep0stall(udc);
1526                 break;
1527         case DATA_STATE_RECV:
1528                 /* send status phase */
1529                 if (ep0_prime_status(udc, EP_DIR_IN))
1530                         ep0stall(udc);
1531                 break;
1532         case WAIT_FOR_OUT_STATUS:
1533                 udc->ep0_state = WAIT_FOR_SETUP;
1534                 break;
1535         case WAIT_FOR_SETUP:
1536                 ERR("Unexpect ep0 packets\n");
1537                 break;
1538         default:
1539                 ep0stall(udc);
1540                 break;
1541         }
1542 }
1543
1544 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1545  * being corrupted by another incoming setup packet */
1546 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1547 {
1548         u32 temp;
1549         struct ep_queue_head *qh;
1550         struct fsl_usb2_platform_data *pdata = udc->pdata;
1551
1552         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1553
1554         /* Clear bit in ENDPTSETUPSTAT */
1555         temp = fsl_readl(&dr_regs->endptsetupstat);
1556         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1557
1558         /* while a hazard exists when setup package arrives */
1559         do {
1560                 /* Set Setup Tripwire */
1561                 temp = fsl_readl(&dr_regs->usbcmd);
1562                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1563
1564                 /* Copy the setup packet to local buffer */
1565                 if (pdata->le_setup_buf) {
1566                         u32 *p = (u32 *)buffer_ptr;
1567                         u32 *s = (u32 *)qh->setup_buffer;
1568
1569                         /* Convert little endian setup buffer to CPU endian */
1570                         *p++ = le32_to_cpu(*s++);
1571                         *p = le32_to_cpu(*s);
1572                 } else {
1573                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1574                 }
1575         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1576
1577         /* Clear Setup Tripwire */
1578         temp = fsl_readl(&dr_regs->usbcmd);
1579         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1580 }
1581
1582 /* process-ep_req(): free the completed Tds for this req */
1583 static int process_ep_req(struct fsl_udc *udc, int pipe,
1584                 struct fsl_req *curr_req)
1585 {
1586         struct ep_td_struct *curr_td;
1587         int     td_complete, actual, remaining_length, j, tmp;
1588         int     status = 0;
1589         int     errors = 0;
1590         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1591         int direction = pipe % 2;
1592
1593         curr_td = curr_req->head;
1594         td_complete = 0;
1595         actual = curr_req->req.length;
1596
1597         for (j = 0; j < curr_req->dtd_count; j++) {
1598                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1599                                         & DTD_PACKET_SIZE)
1600                                 >> DTD_LENGTH_BIT_POS;
1601                 actual -= remaining_length;
1602
1603                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1604                 if (errors & DTD_ERROR_MASK) {
1605                         if (errors & DTD_STATUS_HALTED) {
1606                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1607                                 /* Clear the errors and Halt condition */
1608                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1609                                 tmp &= ~errors;
1610                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1611                                 status = -EPIPE;
1612                                 /* FIXME: continue with next queued TD? */
1613
1614                                 break;
1615                         }
1616                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1617                                 VDBG("Transfer overflow");
1618                                 status = -EPROTO;
1619                                 break;
1620                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1621                                 VDBG("ISO error");
1622                                 status = -EILSEQ;
1623                                 break;
1624                         } else
1625                                 ERR("Unknown error has occurred (0x%x)!\n",
1626                                         errors);
1627
1628                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1629                                 & DTD_STATUS_ACTIVE) {
1630                         VDBG("Request not complete");
1631                         status = REQ_UNCOMPLETE;
1632                         return status;
1633                 } else if (remaining_length) {
1634                         if (direction) {
1635                                 VDBG("Transmit dTD remaining length not zero");
1636                                 status = -EPROTO;
1637                                 break;
1638                         } else {
1639                                 td_complete++;
1640                                 break;
1641                         }
1642                 } else {
1643                         td_complete++;
1644                         VDBG("dTD transmitted successful");
1645                 }
1646
1647                 if (j != curr_req->dtd_count - 1)
1648                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1649         }
1650
1651         if (status)
1652                 return status;
1653
1654         curr_req->req.actual = actual;
1655
1656         return 0;
1657 }
1658
1659 /* Process a DTD completion interrupt */
1660 static void dtd_complete_irq(struct fsl_udc *udc)
1661 {
1662         u32 bit_pos;
1663         int i, ep_num, direction, bit_mask, status;
1664         struct fsl_ep *curr_ep;
1665         struct fsl_req *curr_req, *temp_req;
1666
1667         /* Clear the bits in the register */
1668         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1669         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1670
1671         if (!bit_pos)
1672                 return;
1673
1674         for (i = 0; i < udc->max_ep; i++) {
1675                 ep_num = i >> 1;
1676                 direction = i % 2;
1677
1678                 bit_mask = 1 << (ep_num + 16 * direction);
1679
1680                 if (!(bit_pos & bit_mask))
1681                         continue;
1682
1683                 curr_ep = get_ep_by_pipe(udc, i);
1684
1685                 /* If the ep is configured */
1686                 if (curr_ep->name == NULL) {
1687                         WARNING("Invalid EP?");
1688                         continue;
1689                 }
1690
1691                 /* process the req queue until an uncomplete request */
1692                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1693                                 queue) {
1694                         status = process_ep_req(udc, i, curr_req);
1695
1696                         VDBG("status of process_ep_req= %d, ep = %d",
1697                                         status, ep_num);
1698                         if (status == REQ_UNCOMPLETE)
1699                                 break;
1700                         /* write back status to req */
1701                         curr_req->req.status = status;
1702
1703                         if (ep_num == 0) {
1704                                 ep0_req_complete(udc, curr_ep, curr_req);
1705                                 break;
1706                         } else
1707                                 done(curr_ep, curr_req, status);
1708                 }
1709         }
1710 }
1711
1712 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1713 {
1714         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1715         case PORTSCX_PORT_SPEED_HIGH:
1716                 return USB_SPEED_HIGH;
1717         case PORTSCX_PORT_SPEED_FULL:
1718                 return USB_SPEED_FULL;
1719         case PORTSCX_PORT_SPEED_LOW:
1720                 return USB_SPEED_LOW;
1721         default:
1722                 return USB_SPEED_UNKNOWN;
1723         }
1724 }
1725
1726 /* Process a port change interrupt */
1727 static void port_change_irq(struct fsl_udc *udc)
1728 {
1729         if (udc->bus_reset)
1730                 udc->bus_reset = 0;
1731
1732         /* Bus resetting is finished */
1733         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1734                 /* Get the speed */
1735                 udc->gadget.speed =
1736                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1737
1738         /* Update USB state */
1739         if (!udc->resume_state)
1740                 udc->usb_state = USB_STATE_DEFAULT;
1741 }
1742
1743 /* Process suspend interrupt */
1744 static void suspend_irq(struct fsl_udc *udc)
1745 {
1746         udc->resume_state = udc->usb_state;
1747         udc->usb_state = USB_STATE_SUSPENDED;
1748
1749         /* report suspend to the driver, serial.c does not support this */
1750         if (udc->driver->suspend)
1751                 udc->driver->suspend(&udc->gadget);
1752 }
1753
1754 static void bus_resume(struct fsl_udc *udc)
1755 {
1756         udc->usb_state = udc->resume_state;
1757         udc->resume_state = 0;
1758
1759         /* report resume to the driver, serial.c does not support this */
1760         if (udc->driver->resume)
1761                 udc->driver->resume(&udc->gadget);
1762 }
1763
1764 /* Clear up all ep queues */
1765 static int reset_queues(struct fsl_udc *udc)
1766 {
1767         u8 pipe;
1768
1769         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1770                 udc_reset_ep_queue(udc, pipe);
1771
1772         /* report disconnect; the driver is already quiesced */
1773         spin_unlock(&udc->lock);
1774         udc->driver->disconnect(&udc->gadget);
1775         spin_lock(&udc->lock);
1776
1777         return 0;
1778 }
1779
1780 /* Process reset interrupt */
1781 static void reset_irq(struct fsl_udc *udc)
1782 {
1783         u32 temp;
1784         unsigned long timeout;
1785
1786         /* Clear the device address */
1787         temp = fsl_readl(&dr_regs->deviceaddr);
1788         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1789
1790         udc->device_address = 0;
1791
1792         /* Clear usb state */
1793         udc->resume_state = 0;
1794         udc->ep0_dir = 0;
1795         udc->ep0_state = WAIT_FOR_SETUP;
1796         udc->remote_wakeup = 0; /* default to 0 on reset */
1797         udc->gadget.b_hnp_enable = 0;
1798         udc->gadget.a_hnp_support = 0;
1799         udc->gadget.a_alt_hnp_support = 0;
1800
1801         /* Clear all the setup token semaphores */
1802         temp = fsl_readl(&dr_regs->endptsetupstat);
1803         fsl_writel(temp, &dr_regs->endptsetupstat);
1804
1805         /* Clear all the endpoint complete status bits */
1806         temp = fsl_readl(&dr_regs->endptcomplete);
1807         fsl_writel(temp, &dr_regs->endptcomplete);
1808
1809         timeout = jiffies + 100;
1810         while (fsl_readl(&dr_regs->endpointprime)) {
1811                 /* Wait until all endptprime bits cleared */
1812                 if (time_after(jiffies, timeout)) {
1813                         ERR("Timeout for reset\n");
1814                         break;
1815                 }
1816                 cpu_relax();
1817         }
1818
1819         /* Write 1s to the flush register */
1820         fsl_writel(0xffffffff, &dr_regs->endptflush);
1821
1822         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1823                 VDBG("Bus reset");
1824                 /* Bus is reseting */
1825                 udc->bus_reset = 1;
1826                 /* Reset all the queues, include XD, dTD, EP queue
1827                  * head and TR Queue */
1828                 reset_queues(udc);
1829                 udc->usb_state = USB_STATE_DEFAULT;
1830         } else {
1831                 VDBG("Controller reset");
1832                 /* initialize usb hw reg except for regs for EP, not
1833                  * touch usbintr reg */
1834                 dr_controller_setup(udc);
1835
1836                 /* Reset all internal used Queues */
1837                 reset_queues(udc);
1838
1839                 ep0_setup(udc);
1840
1841                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1842                 dr_controller_run(udc);
1843                 udc->usb_state = USB_STATE_ATTACHED;
1844         }
1845 }
1846
1847 /*
1848  * USB device controller interrupt handler
1849  */
1850 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1851 {
1852         struct fsl_udc *udc = _udc;
1853         u32 irq_src;
1854         irqreturn_t status = IRQ_NONE;
1855         unsigned long flags;
1856
1857         /* Disable ISR for OTG host mode */
1858         if (udc->stopped)
1859                 return IRQ_NONE;
1860         spin_lock_irqsave(&udc->lock, flags);
1861         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1862         /* Clear notification bits */
1863         fsl_writel(irq_src, &dr_regs->usbsts);
1864
1865         /* VDBG("irq_src [0x%8x]", irq_src); */
1866
1867         /* Need to resume? */
1868         if (udc->usb_state == USB_STATE_SUSPENDED)
1869                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1870                         bus_resume(udc);
1871
1872         /* USB Interrupt */
1873         if (irq_src & USB_STS_INT) {
1874                 VDBG("Packet int");
1875                 /* Setup package, we only support ep0 as control ep */
1876                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1877                         tripwire_handler(udc, 0,
1878                                         (u8 *) (&udc->local_setup_buff));
1879                         setup_received_irq(udc, &udc->local_setup_buff);
1880                         status = IRQ_HANDLED;
1881                 }
1882
1883                 /* completion of dtd */
1884                 if (fsl_readl(&dr_regs->endptcomplete)) {
1885                         dtd_complete_irq(udc);
1886                         status = IRQ_HANDLED;
1887                 }
1888         }
1889
1890         /* SOF (for ISO transfer) */
1891         if (irq_src & USB_STS_SOF) {
1892                 status = IRQ_HANDLED;
1893         }
1894
1895         /* Port Change */
1896         if (irq_src & USB_STS_PORT_CHANGE) {
1897                 port_change_irq(udc);
1898                 status = IRQ_HANDLED;
1899         }
1900
1901         /* Reset Received */
1902         if (irq_src & USB_STS_RESET) {
1903                 VDBG("reset int");
1904                 reset_irq(udc);
1905                 status = IRQ_HANDLED;
1906         }
1907
1908         /* Sleep Enable (Suspend) */
1909         if (irq_src & USB_STS_SUSPEND) {
1910                 suspend_irq(udc);
1911                 status = IRQ_HANDLED;
1912         }
1913
1914         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1915                 VDBG("Error IRQ %x", irq_src);
1916         }
1917
1918         spin_unlock_irqrestore(&udc->lock, flags);
1919         return status;
1920 }
1921
1922 /*----------------------------------------------------------------*
1923  * Hook to gadget drivers
1924  * Called by initialization code of gadget drivers
1925 *----------------------------------------------------------------*/
1926 static int fsl_start(struct usb_gadget_driver *driver,
1927                 int (*bind)(struct usb_gadget *))
1928 {
1929         int retval = -ENODEV;
1930         unsigned long flags = 0;
1931
1932         if (!udc_controller)
1933                 return -ENODEV;
1934
1935         if (!driver || driver->max_speed < USB_SPEED_FULL
1936                         || !bind || !driver->disconnect || !driver->setup)
1937                 return -EINVAL;
1938
1939         if (udc_controller->driver)
1940                 return -EBUSY;
1941
1942         /* lock is needed but whether should use this lock or another */
1943         spin_lock_irqsave(&udc_controller->lock, flags);
1944
1945         driver->driver.bus = NULL;
1946         /* hook up the driver */
1947         udc_controller->driver = driver;
1948         udc_controller->gadget.dev.driver = &driver->driver;
1949         spin_unlock_irqrestore(&udc_controller->lock, flags);
1950
1951         /* bind udc driver to gadget driver */
1952         retval = bind(&udc_controller->gadget);
1953         if (retval) {
1954                 VDBG("bind to %s --> %d", driver->driver.name, retval);
1955                 udc_controller->gadget.dev.driver = NULL;
1956                 udc_controller->driver = NULL;
1957                 goto out;
1958         }
1959
1960         if (udc_controller->transceiver) {
1961                 /* Suspend the controller until OTG enable it */
1962                 udc_controller->stopped = 1;
1963                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1964
1965                 /* connect to bus through transceiver */
1966                 if (udc_controller->transceiver) {
1967                         retval = otg_set_peripheral(
1968                                         udc_controller->transceiver->otg,
1969                                                     &udc_controller->gadget);
1970                         if (retval < 0) {
1971                                 ERR("can't bind to transceiver\n");
1972                                 driver->unbind(&udc_controller->gadget);
1973                                 udc_controller->gadget.dev.driver = 0;
1974                                 udc_controller->driver = 0;
1975                                 return retval;
1976                         }
1977                 }
1978         } else {
1979                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1980                 dr_controller_run(udc_controller);
1981                 udc_controller->usb_state = USB_STATE_ATTACHED;
1982                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1983                 udc_controller->ep0_dir = 0;
1984         }
1985         printk(KERN_INFO "%s: bind to driver %s\n",
1986                         udc_controller->gadget.name, driver->driver.name);
1987
1988 out:
1989         if (retval)
1990                 printk(KERN_WARNING "gadget driver register failed %d\n",
1991                        retval);
1992         return retval;
1993 }
1994
1995 /* Disconnect from gadget driver */
1996 static int fsl_stop(struct usb_gadget_driver *driver)
1997 {
1998         struct fsl_ep *loop_ep;
1999         unsigned long flags;
2000
2001         if (!udc_controller)
2002                 return -ENODEV;
2003
2004         if (!driver || driver != udc_controller->driver || !driver->unbind)
2005                 return -EINVAL;
2006
2007         if (udc_controller->transceiver)
2008                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
2009
2010         /* stop DR, disable intr */
2011         dr_controller_stop(udc_controller);
2012
2013         /* in fact, no needed */
2014         udc_controller->usb_state = USB_STATE_ATTACHED;
2015         udc_controller->ep0_state = WAIT_FOR_SETUP;
2016         udc_controller->ep0_dir = 0;
2017
2018         /* stand operation */
2019         spin_lock_irqsave(&udc_controller->lock, flags);
2020         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2021         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2022         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2023                         ep.ep_list)
2024                 nuke(loop_ep, -ESHUTDOWN);
2025         spin_unlock_irqrestore(&udc_controller->lock, flags);
2026
2027         /* report disconnect; the controller is already quiesced */
2028         driver->disconnect(&udc_controller->gadget);
2029
2030         /* unbind gadget and unhook driver. */
2031         driver->unbind(&udc_controller->gadget);
2032         udc_controller->gadget.dev.driver = NULL;
2033         udc_controller->driver = NULL;
2034
2035         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2036                driver->driver.name);
2037         return 0;
2038 }
2039
2040 /*-------------------------------------------------------------------------
2041                 PROC File System Support
2042 -------------------------------------------------------------------------*/
2043 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2044
2045 #include <linux/seq_file.h>
2046
2047 static const char proc_filename[] = "driver/fsl_usb2_udc";
2048
2049 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2050                 int *eof, void *_dev)
2051 {
2052         char *buf = page;
2053         char *next = buf;
2054         unsigned size = count;
2055         unsigned long flags;
2056         int t, i;
2057         u32 tmp_reg;
2058         struct fsl_ep *ep = NULL;
2059         struct fsl_req *req;
2060
2061         struct fsl_udc *udc = udc_controller;
2062         if (off != 0)
2063                 return 0;
2064
2065         spin_lock_irqsave(&udc->lock, flags);
2066
2067         /* ------basic driver information ---- */
2068         t = scnprintf(next, size,
2069                         DRIVER_DESC "\n"
2070                         "%s version: %s\n"
2071                         "Gadget driver: %s\n\n",
2072                         driver_name, DRIVER_VERSION,
2073                         udc->driver ? udc->driver->driver.name : "(none)");
2074         size -= t;
2075         next += t;
2076
2077         /* ------ DR Registers ----- */
2078         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2079         t = scnprintf(next, size,
2080                         "USBCMD reg:\n"
2081                         "SetupTW: %d\n"
2082                         "Run/Stop: %s\n\n",
2083                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2084                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2085         size -= t;
2086         next += t;
2087
2088         tmp_reg = fsl_readl(&dr_regs->usbsts);
2089         t = scnprintf(next, size,
2090                         "USB Status Reg:\n"
2091                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2092                         "USB Error Interrupt: %s\n\n",
2093                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2094                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2095                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2096                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2097         size -= t;
2098         next += t;
2099
2100         tmp_reg = fsl_readl(&dr_regs->usbintr);
2101         t = scnprintf(next, size,
2102                         "USB Intrrupt Enable Reg:\n"
2103                         "Sleep Enable: %d SOF Received Enable: %d "
2104                         "Reset Enable: %d\n"
2105                         "System Error Enable: %d "
2106                         "Port Change Dectected Enable: %d\n"
2107                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2108                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2109                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2110                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2111                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2112                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2113                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2114                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2115         size -= t;
2116         next += t;
2117
2118         tmp_reg = fsl_readl(&dr_regs->frindex);
2119         t = scnprintf(next, size,
2120                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2121                         (tmp_reg & USB_FRINDEX_MASKS));
2122         size -= t;
2123         next += t;
2124
2125         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2126         t = scnprintf(next, size,
2127                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2128                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2129         size -= t;
2130         next += t;
2131
2132         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2133         t = scnprintf(next, size,
2134                         "USB Endpoint List Address Reg: "
2135                         "Device Addr is 0x%x\n\n",
2136                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2137         size -= t;
2138         next += t;
2139
2140         tmp_reg = fsl_readl(&dr_regs->portsc1);
2141         t = scnprintf(next, size,
2142                 "USB Port Status&Control Reg:\n"
2143                 "Port Transceiver Type : %s Port Speed: %s\n"
2144                 "PHY Low Power Suspend: %s Port Reset: %s "
2145                 "Port Suspend Mode: %s\n"
2146                 "Over-current Change: %s "
2147                 "Port Enable/Disable Change: %s\n"
2148                 "Port Enabled/Disabled: %s "
2149                 "Current Connect Status: %s\n\n", ( {
2150                         char *s;
2151                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2152                         case PORTSCX_PTS_UTMI:
2153                                 s = "UTMI"; break;
2154                         case PORTSCX_PTS_ULPI:
2155                                 s = "ULPI "; break;
2156                         case PORTSCX_PTS_FSLS:
2157                                 s = "FS/LS Serial"; break;
2158                         default:
2159                                 s = "None"; break;
2160                         }
2161                         s;} ),
2162                 usb_speed_string(portscx_device_speed(tmp_reg)),
2163                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2164                 "Normal PHY mode" : "Low power mode",
2165                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2166                 "Not in Reset",
2167                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2168                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2169                 "No",
2170                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2171                 "Not change",
2172                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2173                 "Not correct",
2174                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2175                 "Attached" : "Not-Att");
2176         size -= t;
2177         next += t;
2178
2179         tmp_reg = fsl_readl(&dr_regs->usbmode);
2180         t = scnprintf(next, size,
2181                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2182                                 char *s;
2183                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2184                                 case USB_MODE_CTRL_MODE_IDLE:
2185                                         s = "Idle"; break;
2186                                 case USB_MODE_CTRL_MODE_DEVICE:
2187                                         s = "Device Controller"; break;
2188                                 case USB_MODE_CTRL_MODE_HOST:
2189                                         s = "Host Controller"; break;
2190                                 default:
2191                                         s = "None"; break;
2192                                 }
2193                                 s;
2194                         } ));
2195         size -= t;
2196         next += t;
2197
2198         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2199         t = scnprintf(next, size,
2200                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2201                         (tmp_reg & EP_SETUP_STATUS_MASK));
2202         size -= t;
2203         next += t;
2204
2205         for (i = 0; i < udc->max_ep / 2; i++) {
2206                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2207                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2208                                 i, tmp_reg);
2209                 size -= t;
2210                 next += t;
2211         }
2212         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2213         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2214         size -= t;
2215         next += t;
2216
2217 #ifndef CONFIG_ARCH_MXC
2218         if (udc->pdata->have_sysif_regs) {
2219                 tmp_reg = usb_sys_regs->snoop1;
2220                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2221                 size -= t;
2222                 next += t;
2223
2224                 tmp_reg = usb_sys_regs->control;
2225                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2226                                 tmp_reg);
2227                 size -= t;
2228                 next += t;
2229         }
2230 #endif
2231
2232         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2233         ep = &udc->eps[0];
2234         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2235                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2236         size -= t;
2237         next += t;
2238
2239         if (list_empty(&ep->queue)) {
2240                 t = scnprintf(next, size, "its req queue is empty\n\n");
2241                 size -= t;
2242                 next += t;
2243         } else {
2244                 list_for_each_entry(req, &ep->queue, queue) {
2245                         t = scnprintf(next, size,
2246                                 "req %p actual 0x%x length 0x%x buf %p\n",
2247                                 &req->req, req->req.actual,
2248                                 req->req.length, req->req.buf);
2249                         size -= t;
2250                         next += t;
2251                 }
2252         }
2253         /* other gadget->eplist ep */
2254         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2255                 if (ep->desc) {
2256                         t = scnprintf(next, size,
2257                                         "\nFor %s Maxpkt is 0x%x "
2258                                         "index is 0x%x\n",
2259                                         ep->ep.name, ep_maxpacket(ep),
2260                                         ep_index(ep));
2261                         size -= t;
2262                         next += t;
2263
2264                         if (list_empty(&ep->queue)) {
2265                                 t = scnprintf(next, size,
2266                                                 "its req queue is empty\n\n");
2267                                 size -= t;
2268                                 next += t;
2269                         } else {
2270                                 list_for_each_entry(req, &ep->queue, queue) {
2271                                         t = scnprintf(next, size,
2272                                                 "req %p actual 0x%x length "
2273                                                 "0x%x  buf %p\n",
2274                                                 &req->req, req->req.actual,
2275                                                 req->req.length, req->req.buf);
2276                                         size -= t;
2277                                         next += t;
2278                                         }       /* end for each_entry of ep req */
2279                                 }       /* end for else */
2280                         }       /* end for if(ep->queue) */
2281                 }               /* end (ep->desc) */
2282
2283         spin_unlock_irqrestore(&udc->lock, flags);
2284
2285         *eof = 1;
2286         return count - size;
2287 }
2288
2289 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2290                                 0, NULL, fsl_proc_read, NULL)
2291
2292 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2293
2294 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2295
2296 #define create_proc_file()      do {} while (0)
2297 #define remove_proc_file()      do {} while (0)
2298
2299 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2300
2301 /*-------------------------------------------------------------------------*/
2302
2303 /* Release udc structures */
2304 static void fsl_udc_release(struct device *dev)
2305 {
2306         complete(udc_controller->done);
2307         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2308                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2309         kfree(udc_controller);
2310 }
2311
2312 /******************************************************************
2313         Internal structure setup functions
2314 *******************************************************************/
2315 /*------------------------------------------------------------------
2316  * init resource for globle controller
2317  * Return the udc handle on success or NULL on failure
2318  ------------------------------------------------------------------*/
2319 static int __init struct_udc_setup(struct fsl_udc *udc,
2320                 struct platform_device *pdev)
2321 {
2322         struct fsl_usb2_platform_data *pdata;
2323         size_t size;
2324
2325         pdata = pdev->dev.platform_data;
2326         udc->phy_mode = pdata->phy_mode;
2327
2328         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2329         if (!udc->eps) {
2330                 ERR("malloc fsl_ep failed\n");
2331                 return -1;
2332         }
2333
2334         /* initialized QHs, take care of alignment */
2335         size = udc->max_ep * sizeof(struct ep_queue_head);
2336         if (size < QH_ALIGNMENT)
2337                 size = QH_ALIGNMENT;
2338         else if ((size % QH_ALIGNMENT) != 0) {
2339                 size += QH_ALIGNMENT + 1;
2340                 size &= ~(QH_ALIGNMENT - 1);
2341         }
2342         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2343                                         &udc->ep_qh_dma, GFP_KERNEL);
2344         if (!udc->ep_qh) {
2345                 ERR("malloc QHs for udc failed\n");
2346                 kfree(udc->eps);
2347                 return -1;
2348         }
2349
2350         udc->ep_qh_size = size;
2351
2352         /* Initialize ep0 status request structure */
2353         /* FIXME: fsl_alloc_request() ignores ep argument */
2354         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2355                         struct fsl_req, req);
2356         /* allocate a small amount of memory to get valid address */
2357         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2358
2359         udc->resume_state = USB_STATE_NOTATTACHED;
2360         udc->usb_state = USB_STATE_POWERED;
2361         udc->ep0_dir = 0;
2362         udc->remote_wakeup = 0; /* default to 0 on reset */
2363
2364         return 0;
2365 }
2366
2367 /*----------------------------------------------------------------
2368  * Setup the fsl_ep struct for eps
2369  * Link fsl_ep->ep to gadget->ep_list
2370  * ep0out is not used so do nothing here
2371  * ep0in should be taken care
2372  *--------------------------------------------------------------*/
2373 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2374                 char *name, int link)
2375 {
2376         struct fsl_ep *ep = &udc->eps[index];
2377
2378         ep->udc = udc;
2379         strcpy(ep->name, name);
2380         ep->ep.name = ep->name;
2381
2382         ep->ep.ops = &fsl_ep_ops;
2383         ep->stopped = 0;
2384
2385         /* for ep0: maxP defined in desc
2386          * for other eps, maxP is set by epautoconfig() called by gadget layer
2387          */
2388         ep->ep.maxpacket = (unsigned short) ~0;
2389
2390         /* the queue lists any req for this ep */
2391         INIT_LIST_HEAD(&ep->queue);
2392
2393         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2394         if (link)
2395                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2396         ep->gadget = &udc->gadget;
2397         ep->qh = &udc->ep_qh[index];
2398
2399         return 0;
2400 }
2401
2402 /* Driver probe function
2403  * all intialization operations implemented here except enabling usb_intr reg
2404  * board setup should have been done in the platform code
2405  */
2406 static int __init fsl_udc_probe(struct platform_device *pdev)
2407 {
2408         struct fsl_usb2_platform_data *pdata;
2409         struct resource *res;
2410         int ret = -ENODEV;
2411         unsigned int i;
2412         u32 dccparams;
2413
2414         if (strcmp(pdev->name, driver_name)) {
2415                 VDBG("Wrong device");
2416                 return -ENODEV;
2417         }
2418
2419         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2420         if (udc_controller == NULL) {
2421                 ERR("malloc udc failed\n");
2422                 return -ENOMEM;
2423         }
2424
2425         pdata = pdev->dev.platform_data;
2426         udc_controller->pdata = pdata;
2427         spin_lock_init(&udc_controller->lock);
2428         udc_controller->stopped = 1;
2429
2430 #ifdef CONFIG_USB_OTG
2431         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2432                 udc_controller->transceiver = usb_get_transceiver();
2433                 if (!udc_controller->transceiver) {
2434                         ERR("Can't find OTG driver!\n");
2435                         ret = -ENODEV;
2436                         goto err_kfree;
2437                 }
2438         }
2439 #endif
2440
2441         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2442         if (!res) {
2443                 ret = -ENXIO;
2444                 goto err_kfree;
2445         }
2446
2447         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2448                 if (!request_mem_region(res->start, resource_size(res),
2449                                         driver_name)) {
2450                         ERR("request mem region for %s failed\n", pdev->name);
2451                         ret = -EBUSY;
2452                         goto err_kfree;
2453                 }
2454         }
2455
2456         dr_regs = ioremap(res->start, resource_size(res));
2457         if (!dr_regs) {
2458                 ret = -ENOMEM;
2459                 goto err_release_mem_region;
2460         }
2461
2462         pdata->regs = (void *)dr_regs;
2463
2464         /*
2465          * do platform specific init: check the clock, grab/config pins, etc.
2466          */
2467         if (pdata->init && pdata->init(pdev)) {
2468                 ret = -ENODEV;
2469                 goto err_iounmap_noclk;
2470         }
2471
2472         /* Set accessors only after pdata->init() ! */
2473         fsl_set_accessors(pdata);
2474
2475 #ifndef CONFIG_ARCH_MXC
2476         if (pdata->have_sysif_regs)
2477                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2478 #endif
2479
2480         /* Initialize USB clocks */
2481         ret = fsl_udc_clk_init(pdev);
2482         if (ret < 0)
2483                 goto err_iounmap_noclk;
2484
2485         /* Read Device Controller Capability Parameters register */
2486         dccparams = fsl_readl(&dr_regs->dccparams);
2487         if (!(dccparams & DCCPARAMS_DC)) {
2488                 ERR("This SOC doesn't support device role\n");
2489                 ret = -ENODEV;
2490                 goto err_iounmap;
2491         }
2492         /* Get max device endpoints */
2493         /* DEN is bidirectional ep number, max_ep doubles the number */
2494         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2495
2496         udc_controller->irq = platform_get_irq(pdev, 0);
2497         if (!udc_controller->irq) {
2498                 ret = -ENODEV;
2499                 goto err_iounmap;
2500         }
2501
2502         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2503                         driver_name, udc_controller);
2504         if (ret != 0) {
2505                 ERR("cannot request irq %d err %d\n",
2506                                 udc_controller->irq, ret);
2507                 goto err_iounmap;
2508         }
2509
2510         /* Initialize the udc structure including QH member and other member */
2511         if (struct_udc_setup(udc_controller, pdev)) {
2512                 ERR("Can't initialize udc data structure\n");
2513                 ret = -ENOMEM;
2514                 goto err_free_irq;
2515         }
2516
2517         if (!udc_controller->transceiver) {
2518                 /* initialize usb hw reg except for regs for EP,
2519                  * leave usbintr reg untouched */
2520                 dr_controller_setup(udc_controller);
2521         }
2522
2523         fsl_udc_clk_finalize(pdev);
2524
2525         /* Setup gadget structure */
2526         udc_controller->gadget.ops = &fsl_gadget_ops;
2527         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2528         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2529         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2530         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2531         udc_controller->gadget.name = driver_name;
2532
2533         /* Setup gadget.dev and register with kernel */
2534         dev_set_name(&udc_controller->gadget.dev, "gadget");
2535         udc_controller->gadget.dev.release = fsl_udc_release;
2536         udc_controller->gadget.dev.parent = &pdev->dev;
2537         ret = device_register(&udc_controller->gadget.dev);
2538         if (ret < 0)
2539                 goto err_free_irq;
2540
2541         if (udc_controller->transceiver)
2542                 udc_controller->gadget.is_otg = 1;
2543
2544         /* setup QH and epctrl for ep0 */
2545         ep0_setup(udc_controller);
2546
2547         /* setup udc->eps[] for ep0 */
2548         struct_ep_setup(udc_controller, 0, "ep0", 0);
2549         /* for ep0: the desc defined here;
2550          * for other eps, gadget layer called ep_enable with defined desc
2551          */
2552         udc_controller->eps[0].desc = &fsl_ep0_desc;
2553         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2554
2555         /* setup the udc->eps[] for non-control endpoints and link
2556          * to gadget.ep_list */
2557         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2558                 char name[14];
2559
2560                 sprintf(name, "ep%dout", i);
2561                 struct_ep_setup(udc_controller, i * 2, name, 1);
2562                 sprintf(name, "ep%din", i);
2563                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2564         }
2565
2566         /* use dma_pool for TD management */
2567         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2568                         sizeof(struct ep_td_struct),
2569                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2570         if (udc_controller->td_pool == NULL) {
2571                 ret = -ENOMEM;
2572                 goto err_unregister;
2573         }
2574
2575         ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2576         if (ret)
2577                 goto err_del_udc;
2578
2579         create_proc_file();
2580         return 0;
2581
2582 err_del_udc:
2583         dma_pool_destroy(udc_controller->td_pool);
2584 err_unregister:
2585         device_unregister(&udc_controller->gadget.dev);
2586 err_free_irq:
2587         free_irq(udc_controller->irq, udc_controller);
2588 err_iounmap:
2589         if (pdata->exit)
2590                 pdata->exit(pdev);
2591         fsl_udc_clk_release();
2592 err_iounmap_noclk:
2593         iounmap(dr_regs);
2594 err_release_mem_region:
2595         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2596                 release_mem_region(res->start, resource_size(res));
2597 err_kfree:
2598         kfree(udc_controller);
2599         udc_controller = NULL;
2600         return ret;
2601 }
2602
2603 /* Driver removal function
2604  * Free resources and finish pending transactions
2605  */
2606 static int __exit fsl_udc_remove(struct platform_device *pdev)
2607 {
2608         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2609         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2610
2611         DECLARE_COMPLETION(done);
2612
2613         if (!udc_controller)
2614                 return -ENODEV;
2615
2616         usb_del_gadget_udc(&udc_controller->gadget);
2617         udc_controller->done = &done;
2618
2619         fsl_udc_clk_release();
2620
2621         /* DR has been stopped in usb_gadget_unregister_driver() */
2622         remove_proc_file();
2623
2624         /* Free allocated memory */
2625         kfree(udc_controller->status_req->req.buf);
2626         kfree(udc_controller->status_req);
2627         kfree(udc_controller->eps);
2628
2629         dma_pool_destroy(udc_controller->td_pool);
2630         free_irq(udc_controller->irq, udc_controller);
2631         iounmap(dr_regs);
2632         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2633                 release_mem_region(res->start, resource_size(res));
2634
2635         device_unregister(&udc_controller->gadget.dev);
2636         /* free udc --wait for the release() finished */
2637         wait_for_completion(&done);
2638
2639         /*
2640          * do platform specific un-initialization:
2641          * release iomux pins, etc.
2642          */
2643         if (pdata->exit)
2644                 pdata->exit(pdev);
2645
2646         return 0;
2647 }
2648
2649 /*-----------------------------------------------------------------
2650  * Modify Power management attributes
2651  * Used by OTG statemachine to disable gadget temporarily
2652  -----------------------------------------------------------------*/
2653 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2654 {
2655         dr_controller_stop(udc_controller);
2656         return 0;
2657 }
2658
2659 /*-----------------------------------------------------------------
2660  * Invoked on USB resume. May be called in_interrupt.
2661  * Here we start the DR controller and enable the irq
2662  *-----------------------------------------------------------------*/
2663 static int fsl_udc_resume(struct platform_device *pdev)
2664 {
2665         /* Enable DR irq reg and set controller Run */
2666         if (udc_controller->stopped) {
2667                 dr_controller_setup(udc_controller);
2668                 dr_controller_run(udc_controller);
2669         }
2670         udc_controller->usb_state = USB_STATE_ATTACHED;
2671         udc_controller->ep0_state = WAIT_FOR_SETUP;
2672         udc_controller->ep0_dir = 0;
2673         return 0;
2674 }
2675
2676 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2677 {
2678         struct fsl_udc *udc = udc_controller;
2679         u32 mode, usbcmd;
2680
2681         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2682
2683         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2684
2685         /*
2686          * If the controller is already stopped, then this must be a
2687          * PM suspend.  Remember this fact, so that we will leave the
2688          * controller stopped at PM resume time.
2689          */
2690         if (udc->stopped) {
2691                 pr_debug("gadget already stopped, leaving early\n");
2692                 udc->already_stopped = 1;
2693                 return 0;
2694         }
2695
2696         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2697                 pr_debug("gadget not in device mode, leaving early\n");
2698                 return 0;
2699         }
2700
2701         /* stop the controller */
2702         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2703         fsl_writel(usbcmd, &dr_regs->usbcmd);
2704
2705         udc->stopped = 1;
2706
2707         pr_info("USB Gadget suspended\n");
2708
2709         return 0;
2710 }
2711
2712 static int fsl_udc_otg_resume(struct device *dev)
2713 {
2714         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2715                  udc_controller->stopped, udc_controller->already_stopped);
2716
2717         /*
2718          * If the controller was stopped at suspend time, then
2719          * don't resume it now.
2720          */
2721         if (udc_controller->already_stopped) {
2722                 udc_controller->already_stopped = 0;
2723                 pr_debug("gadget was already stopped, leaving early\n");
2724                 return 0;
2725         }
2726
2727         pr_info("USB Gadget resume\n");
2728
2729         return fsl_udc_resume(NULL);
2730 }
2731
2732 /*-------------------------------------------------------------------------
2733         Register entry point for the peripheral controller driver
2734 --------------------------------------------------------------------------*/
2735
2736 static struct platform_driver udc_driver = {
2737         .remove  = __exit_p(fsl_udc_remove),
2738         /* these suspend and resume are not usb suspend and resume */
2739         .suspend = fsl_udc_suspend,
2740         .resume  = fsl_udc_resume,
2741         .driver  = {
2742                 .name = (char *)driver_name,
2743                 .owner = THIS_MODULE,
2744                 /* udc suspend/resume called from OTG driver */
2745                 .suspend = fsl_udc_otg_suspend,
2746                 .resume  = fsl_udc_otg_resume,
2747         },
2748 };
2749
2750 static int __init udc_init(void)
2751 {
2752         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2753         return platform_driver_probe(&udc_driver, fsl_udc_probe);
2754 }
2755
2756 module_init(udc_init);
2757
2758 static void __exit udc_exit(void)
2759 {
2760         platform_driver_unregister(&udc_driver);
2761         printk(KERN_WARNING "%s unregistered\n", driver_desc);
2762 }
2763
2764 module_exit(udc_exit);
2765
2766 MODULE_DESCRIPTION(DRIVER_DESC);
2767 MODULE_AUTHOR(DRIVER_AUTHOR);
2768 MODULE_LICENSE("GPL");
2769 MODULE_ALIAS("platform:fsl-usb2-udc");