2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/interrupt.h>
46 #include <linux/list.h>
47 #include <linux/dma-mapping.h>
49 #include <linux/usb/ch9.h>
50 #include <linux/usb/gadget.h>
51 #include <linux/usb/composite.h>
57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
68 case EP0_STATUS_PHASE:
69 return "Status Phase";
75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
78 struct dwc3_gadget_ep_cmd_params params;
84 dep = dwc->eps[epnum];
85 if (dep->flags & DWC3_EP_BUSY) {
86 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
92 trb->bpl = lower_32_bits(buf_dma);
93 trb->bph = upper_32_bits(buf_dma);
97 trb->ctrl |= (DWC3_TRB_CTRL_HWO
100 | DWC3_TRB_CTRL_ISP_IMI);
102 memset(¶ms, 0, sizeof(params));
103 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
104 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
106 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
107 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
109 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
113 dep->flags |= DWC3_EP_BUSY;
114 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
117 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
122 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
123 struct dwc3_request *req)
125 struct dwc3 *dwc = dep->dwc;
128 req->request.actual = 0;
129 req->request.status = -EINPROGRESS;
130 req->epnum = dep->number;
132 list_add_tail(&req->list, &dep->request_list);
135 * Gadget driver might not be quick enough to queue a request
136 * before we get a Transfer Not Ready event on this endpoint.
138 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
139 * flag is set, it's telling us that as soon as Gadget queues the
140 * required request, we should kick the transfer here because the
141 * IRQ we were waiting for is long gone.
143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
146 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
148 if (dwc->ep0state != EP0_DATA_PHASE) {
149 dev_WARN(dwc->dev, "Unexpected pending request\n");
153 ret = dwc3_ep0_start_trans(dwc, direction,
154 req->request.dma, req->request.length,
155 DWC3_TRBCTL_CONTROL_DATA);
156 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
158 } else if (dwc->delayed_status) {
159 dwc->delayed_status = false;
161 if (dwc->ep0state == EP0_STATUS_PHASE)
162 dwc3_ep0_do_control_status(dwc, 1);
164 dev_dbg(dwc->dev, "too early for delayed status\n");
170 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
173 struct dwc3_request *req = to_dwc3_request(request);
174 struct dwc3_ep *dep = to_dwc3_ep(ep);
175 struct dwc3 *dwc = dep->dwc;
181 spin_lock_irqsave(&dwc->lock, flags);
182 if (!dep->endpoint.desc) {
183 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
189 /* we share one TRB for ep0/1 */
190 if (!list_empty(&dep->request_list)) {
195 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
196 request, dep->name, request->length,
197 dwc3_ep0_state_string(dwc->ep0state));
199 ret = __dwc3_gadget_ep0_queue(dep, req);
202 spin_unlock_irqrestore(&dwc->lock, flags);
207 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
209 struct dwc3_ep *dep = dwc->eps[0];
211 /* stall is always issued on EP0 */
212 __dwc3_gadget_ep_set_halt(dep, 1);
213 dep->flags = DWC3_EP_ENABLED;
214 dwc->delayed_status = false;
216 if (!list_empty(&dep->request_list)) {
217 struct dwc3_request *req;
219 req = next_request(&dep->request_list);
220 dwc3_gadget_giveback(dep, req, -ECONNRESET);
223 dwc->ep0state = EP0_SETUP_PHASE;
224 dwc3_ep0_out_start(dwc);
227 void dwc3_ep0_out_start(struct dwc3 *dwc)
231 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
232 DWC3_TRBCTL_CONTROL_SETUP);
236 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
239 u32 windex = le16_to_cpu(wIndex_le);
242 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
243 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
246 dep = dwc->eps[epnum];
247 if (dep->flags & DWC3_EP_ENABLED)
253 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
259 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
260 struct usb_ctrlrequest *ctrl)
266 __le16 *response_pkt;
268 recip = ctrl->bRequestType & USB_RECIP_MASK;
270 case USB_RECIP_DEVICE:
272 * LTM will be set once we know how to set this in HW.
274 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
276 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
277 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
278 if (reg & DWC3_DCTL_INITU1ENA)
279 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
280 if (reg & DWC3_DCTL_INITU2ENA)
281 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
286 case USB_RECIP_INTERFACE:
288 * Function Remote Wake Capable D0
289 * Function Remote Wakeup D1
293 case USB_RECIP_ENDPOINT:
294 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
298 if (dep->flags & DWC3_EP_STALL)
299 usb_status = 1 << USB_ENDPOINT_HALT;
305 response_pkt = (__le16 *) dwc->setup_buf;
306 *response_pkt = cpu_to_le16(usb_status);
309 dwc->ep0_usb_req.dep = dep;
310 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
311 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
312 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
314 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
317 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
318 struct usb_ctrlrequest *ctrl, int set)
327 wValue = le16_to_cpu(ctrl->wValue);
328 wIndex = le16_to_cpu(ctrl->wIndex);
329 recip = ctrl->bRequestType & USB_RECIP_MASK;
331 case USB_RECIP_DEVICE:
334 case USB_DEVICE_REMOTE_WAKEUP:
337 * 9.4.1 says only only for SS, in AddressState only for
338 * default control pipe
340 case USB_DEVICE_U1_ENABLE:
341 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
343 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
346 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
348 reg |= DWC3_DCTL_INITU1ENA;
350 reg &= ~DWC3_DCTL_INITU1ENA;
351 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
354 case USB_DEVICE_U2_ENABLE:
355 if (dwc->dev_state != DWC3_CONFIGURED_STATE)
357 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
362 reg |= DWC3_DCTL_INITU2ENA;
364 reg &= ~DWC3_DCTL_INITU2ENA;
365 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
368 case USB_DEVICE_LTM_ENABLE:
372 case USB_DEVICE_TEST_MODE:
373 if ((wIndex & 0xff) != 0)
378 dwc->test_mode_nr = wIndex >> 8;
379 dwc->test_mode = true;
386 case USB_RECIP_INTERFACE:
388 case USB_INTRF_FUNC_SUSPEND:
389 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
390 /* XXX enable Low power suspend */
392 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
393 /* XXX enable remote wakeup */
401 case USB_RECIP_ENDPOINT:
403 case USB_ENDPOINT_HALT:
404 dep = dwc3_wIndex_to_dep(dwc, wIndex);
407 ret = __dwc3_gadget_ep_set_halt(dep, set);
423 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
428 addr = le16_to_cpu(ctrl->wValue);
430 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
434 if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
435 dev_dbg(dwc->dev, "trying to set address when configured\n");
439 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
440 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
441 reg |= DWC3_DCFG_DEVADDR(addr);
442 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
445 dwc->dev_state = DWC3_ADDRESS_STATE;
447 dwc->dev_state = DWC3_DEFAULT_STATE;
452 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
456 spin_unlock(&dwc->lock);
457 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
458 spin_lock(&dwc->lock);
462 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
467 dwc->start_config_issued = false;
468 cfg = le16_to_cpu(ctrl->wValue);
470 switch (dwc->dev_state) {
471 case DWC3_DEFAULT_STATE:
475 case DWC3_ADDRESS_STATE:
476 ret = dwc3_ep0_delegate_req(dwc, ctrl);
477 /* if the cfg matches and the cfg is non zero */
478 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
479 dwc->dev_state = DWC3_CONFIGURED_STATE;
480 dwc->resize_fifos = true;
481 dev_dbg(dwc->dev, "resize fifos flag SET\n");
485 case DWC3_CONFIGURED_STATE:
486 ret = dwc3_ep0_delegate_req(dwc, ctrl);
488 dwc->dev_state = DWC3_ADDRESS_STATE;
496 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
498 struct dwc3_ep *dep = to_dwc3_ep(ep);
499 struct dwc3 *dwc = dep->dwc;
513 memcpy(&timing, req->buf, sizeof(timing));
515 dwc->u1sel = timing.u1sel;
516 dwc->u1pel = timing.u1pel;
517 dwc->u2sel = timing.u2sel;
518 dwc->u2pel = timing.u2pel;
520 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
521 if (reg & DWC3_DCTL_INITU2ENA)
523 if (reg & DWC3_DCTL_INITU1ENA)
527 * According to Synopsys Databook, if parameter is
528 * greater than 125, a value of zero should be
529 * programmed in the register.
534 /* now that we have the time, issue DGCMD Set Sel */
535 ret = dwc3_send_gadget_generic_command(dwc,
536 DWC3_DGCMD_SET_PERIODIC_PAR, param);
540 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
546 if (dwc->dev_state == DWC3_DEFAULT_STATE)
549 wValue = le16_to_cpu(ctrl->wValue);
550 wLength = le16_to_cpu(ctrl->wLength);
553 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
559 * To handle Set SEL we need to receive 6 bytes from Host. So let's
560 * queue a usb_request for 6 bytes.
562 * Remember, though, this controller can't handle non-wMaxPacketSize
563 * aligned transfers on the OUT direction, so we queue a request for
564 * wMaxPacketSize instead.
567 dwc->ep0_usb_req.dep = dep;
568 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
569 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
570 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
572 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
575 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
581 wValue = le16_to_cpu(ctrl->wValue);
582 wLength = le16_to_cpu(ctrl->wLength);
583 wIndex = le16_to_cpu(ctrl->wIndex);
585 if (wIndex || wLength)
589 * REVISIT It's unclear from Databook what to do with this
590 * value. For now, just cache it.
592 dwc->isoch_delay = wValue;
597 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
601 switch (ctrl->bRequest) {
602 case USB_REQ_GET_STATUS:
603 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
604 ret = dwc3_ep0_handle_status(dwc, ctrl);
606 case USB_REQ_CLEAR_FEATURE:
607 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
608 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
610 case USB_REQ_SET_FEATURE:
611 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
612 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
614 case USB_REQ_SET_ADDRESS:
615 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
616 ret = dwc3_ep0_set_address(dwc, ctrl);
618 case USB_REQ_SET_CONFIGURATION:
619 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
620 ret = dwc3_ep0_set_config(dwc, ctrl);
622 case USB_REQ_SET_SEL:
623 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
624 ret = dwc3_ep0_set_sel(dwc, ctrl);
626 case USB_REQ_SET_ISOCH_DELAY:
627 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
628 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
631 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
632 ret = dwc3_ep0_delegate_req(dwc, ctrl);
639 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
640 const struct dwc3_event_depevt *event)
642 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
646 if (!dwc->gadget_driver)
649 len = le16_to_cpu(ctrl->wLength);
651 dwc->three_stage_setup = false;
652 dwc->ep0_expect_in = false;
653 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
655 dwc->three_stage_setup = true;
656 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
657 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
660 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
661 ret = dwc3_ep0_std_request(dwc, ctrl);
663 ret = dwc3_ep0_delegate_req(dwc, ctrl);
665 if (ret == USB_GADGET_DELAYED_STATUS)
666 dwc->delayed_status = true;
672 dwc3_ep0_stall_and_restart(dwc);
675 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
676 const struct dwc3_event_depevt *event)
678 struct dwc3_request *r = NULL;
679 struct usb_request *ur;
680 struct dwc3_trb *trb;
686 epnum = event->endpoint_number;
689 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
691 r = next_request(&ep0->request_list);
695 length = trb->size & DWC3_TRB_SIZE_MASK;
697 if (dwc->ep0_bounced) {
698 unsigned transfer_size = ur->length;
699 unsigned maxp = ep0->endpoint.maxpacket;
701 transfer_size += (maxp - (transfer_size % maxp));
702 transferred = min_t(u32, ur->length,
703 transfer_size - length);
704 memcpy(ur->buf, dwc->ep0_bounce, transferred);
705 dwc->ep0_bounced = false;
707 transferred = ur->length - length;
710 ur->actual += transferred;
712 if ((epnum & 1) && ur->actual < ur->length) {
713 /* for some reason we did not get everything out */
715 dwc3_ep0_stall_and_restart(dwc);
718 * handle the case where we have to send a zero packet. This
719 * seems to be case when req.length > maxpacket. Could it be?
722 dwc3_gadget_giveback(ep0, r, 0);
726 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
727 const struct dwc3_event_depevt *event)
729 struct dwc3_request *r;
734 if (!list_empty(&dep->request_list)) {
735 r = next_request(&dep->request_list);
737 dwc3_gadget_giveback(dep, r, 0);
740 if (dwc->test_mode) {
743 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
745 dev_dbg(dwc->dev, "Invalid Test #%d\n",
747 dwc3_ep0_stall_and_restart(dwc);
751 dwc->ep0state = EP0_SETUP_PHASE;
752 dwc3_ep0_out_start(dwc);
755 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
756 const struct dwc3_event_depevt *event)
758 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
760 dep->flags &= ~DWC3_EP_BUSY;
761 dep->res_trans_idx = 0;
762 dwc->setup_packet_pending = false;
764 switch (dwc->ep0state) {
765 case EP0_SETUP_PHASE:
766 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
767 dwc3_ep0_inspect_setup(dwc, event);
771 dev_vdbg(dwc->dev, "Data Phase\n");
772 dwc3_ep0_complete_data(dwc, event);
775 case EP0_STATUS_PHASE:
776 dev_vdbg(dwc->dev, "Status Phase\n");
777 dwc3_ep0_complete_req(dwc, event);
780 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
784 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
785 const struct dwc3_event_depevt *event)
787 dwc3_ep0_out_start(dwc);
790 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
791 const struct dwc3_event_depevt *event)
794 struct dwc3_request *req;
799 if (list_empty(&dep->request_list)) {
800 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
801 dep->flags |= DWC3_EP_PENDING_REQUEST;
803 if (event->endpoint_number)
804 dep->flags |= DWC3_EP0_DIR_IN;
808 req = next_request(&dep->request_list);
809 req->direction = !!event->endpoint_number;
811 if (req->request.length == 0) {
812 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
813 dwc->ctrl_req_addr, 0,
814 DWC3_TRBCTL_CONTROL_DATA);
815 } else if ((req->request.length % dep->endpoint.maxpacket)
816 && (event->endpoint_number == 0)) {
817 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
818 event->endpoint_number);
820 dev_dbg(dwc->dev, "failed to map request\n");
824 WARN_ON(req->request.length > dep->endpoint.maxpacket);
826 dwc->ep0_bounced = true;
829 * REVISIT in case request length is bigger than EP0
830 * wMaxPacketSize, we will need two chained TRBs to handle
833 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
834 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
835 DWC3_TRBCTL_CONTROL_DATA);
837 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
838 event->endpoint_number);
840 dev_dbg(dwc->dev, "failed to map request\n");
844 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
845 req->request.dma, req->request.length,
846 DWC3_TRBCTL_CONTROL_DATA);
852 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
854 struct dwc3 *dwc = dep->dwc;
857 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
858 : DWC3_TRBCTL_CONTROL_STATUS2;
860 return dwc3_ep0_start_trans(dwc, dep->number,
861 dwc->ctrl_req_addr, 0, type);
864 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
866 struct dwc3_ep *dep = dwc->eps[epnum];
868 if (dwc->resize_fifos) {
869 dev_dbg(dwc->dev, "starting to resize fifos\n");
870 dwc3_gadget_resize_tx_fifos(dwc);
871 dwc->resize_fifos = 0;
874 WARN_ON(dwc3_ep0_start_control_status(dep));
877 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
878 const struct dwc3_event_depevt *event)
880 dwc->setup_packet_pending = true;
883 * This part is very tricky: If we has just handled
884 * XferNotReady(Setup) and we're now expecting a
885 * XferComplete but, instead, we receive another
886 * XferNotReady(Setup), we should STALL and restart
889 * In all other cases, we just continue waiting
890 * for the XferComplete event.
892 * We are a little bit unsafe here because we're
893 * not trying to ensure that last event was, indeed,
894 * XferNotReady(Setup).
896 * Still, we don't expect any condition where that
897 * should happen and, even if it does, it would be
898 * another error condition.
900 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
901 switch (event->status) {
902 case DEPEVT_STATUS_CONTROL_SETUP:
903 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
904 dwc3_ep0_stall_and_restart(dwc);
906 case DEPEVT_STATUS_CONTROL_DATA:
908 case DEPEVT_STATUS_CONTROL_STATUS:
911 dev_vdbg(dwc->dev, "waiting for XferComplete\n");
917 switch (event->status) {
918 case DEPEVT_STATUS_CONTROL_SETUP:
919 dev_vdbg(dwc->dev, "Control Setup\n");
921 dwc->ep0state = EP0_SETUP_PHASE;
923 dwc3_ep0_do_control_setup(dwc, event);
926 case DEPEVT_STATUS_CONTROL_DATA:
927 dev_vdbg(dwc->dev, "Control Data\n");
929 dwc->ep0state = EP0_DATA_PHASE;
931 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
932 dev_vdbg(dwc->dev, "Expected %d got %d\n",
936 dwc3_ep0_stall_and_restart(dwc);
941 * One of the possible error cases is when Host _does_
942 * request for Data Phase, but it does so on the wrong
945 * Here, we already know ep0_next_event is DATA (see above),
946 * so we only need to check for direction.
948 if (dwc->ep0_expect_in != event->endpoint_number) {
949 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
950 dwc3_ep0_stall_and_restart(dwc);
954 dwc3_ep0_do_control_data(dwc, event);
957 case DEPEVT_STATUS_CONTROL_STATUS:
958 dev_vdbg(dwc->dev, "Control Status\n");
960 dwc->ep0state = EP0_STATUS_PHASE;
962 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
963 dev_vdbg(dwc->dev, "Expected %d got %d\n",
965 DWC3_EP0_NRDY_STATUS);
967 dwc3_ep0_stall_and_restart(dwc);
971 if (dwc->delayed_status) {
972 WARN_ON_ONCE(event->endpoint_number != 1);
973 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
977 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
981 void dwc3_ep0_interrupt(struct dwc3 *dwc,
982 const struct dwc3_event_depevt *event)
984 u8 epnum = event->endpoint_number;
986 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
987 dwc3_ep_event_string(event->endpoint_event),
988 epnum >> 1, (epnum & 1) ? "in" : "out",
989 dwc3_ep0_state_string(dwc->ep0state));
991 switch (event->endpoint_event) {
992 case DWC3_DEPEVT_XFERCOMPLETE:
993 dwc3_ep0_xfer_complete(dwc, event);
996 case DWC3_DEPEVT_XFERNOTREADY:
997 dwc3_ep0_xfernotready(dwc, event);
1000 case DWC3_DEPEVT_XFERINPROGRESS:
1001 case DWC3_DEPEVT_RXTXFIFOEVT:
1002 case DWC3_DEPEVT_STREAMEVT:
1003 case DWC3_DEPEVT_EPCMDCMPLT: