Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51
  52 #include "core.h"
  53 #include "gadget.h"
  54 #include "io.h"
  55
  56 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  57                 const struct dwc3_event_depevt *event);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb_hw              *trb_hw;
  80         struct dwc3_trb                 trb;
  81         struct dwc3_ep                  *dep;
  82
  83         int                             ret;
  84
  85         dep = dwc->eps[epnum];
  86         if (dep->flags & DWC3_EP_BUSY) {
  87                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  88                 return 0;
  89         }
  90
  91         trb_hw = dwc->ep0_trb;
  92         memset(&trb, 0, sizeof(trb));
  93
  94         trb.trbctl = type;
  95         trb.bplh = buf_dma;
  96         trb.length = len;
  97
  98         trb.hwo = 1;
  99         trb.lst = 1;
 100         trb.ioc = 1;
 101         trb.isp_imi = 1;
 102
 103         dwc3_trb_to_hw(&trb, trb_hw);
 104
 105         memset(&params, 0, sizeof(params));
 106         params.param0.depstrtxfer.transfer_desc_addr_high =
 107                 upper_32_bits(dwc->ep0_trb_addr);
 108         params.param1.depstrtxfer.transfer_desc_addr_low =
 109                 lower_32_bits(dwc->ep0_trb_addr);
 110
 111         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 112                         DWC3_DEPCMD_STARTTRANSFER, &params);
 113         if (ret < 0) {
 114                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 115                 return ret;
 116         }
 117
 118         dep->flags |= DWC3_EP_BUSY;
 119         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 120                         dep->number);
 121
 122         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 123
 124         return 0;
 125 }
 126
 127 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 128                 struct dwc3_request *req)
 129 {
 130         int                     ret = 0;
 131
 132         req->request.actual     = 0;
 133         req->request.status     = -EINPROGRESS;
 134         req->epnum              = dep->number;
 135
 136         list_add_tail(&req->list, &dep->request_list);
 137
 138         /*
 139          * Gadget driver might not be quick enough to queue a request
 140          * before we get a Transfer Not Ready event on this endpoint.
 141          *
 142          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 143          * flag is set, it's telling us that as soon as Gadget queues the
 144          * required request, we should kick the transfer here because the
 145          * IRQ we were waiting for is long gone.
 146          */
 147         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 148                 struct dwc3     *dwc = dep->dwc;
 149                 unsigned        direction;
 150                 u32             type;
 151
 152                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 153
 154                 if (dwc->ep0state == EP0_STATUS_PHASE) {
 155                         type = dwc->three_stage_setup
 156                                 ? DWC3_TRBCTL_CONTROL_STATUS3
 157                                 : DWC3_TRBCTL_CONTROL_STATUS2;
 158                 } else if (dwc->ep0state == EP0_DATA_PHASE) {
 159                         type = DWC3_TRBCTL_CONTROL_DATA;
 160                 } else {
 161                         /* should never happen */
 162                         WARN_ON(1);
 163                         return 0;
 164                 }
 165
 166                 ret = dwc3_ep0_start_trans(dwc, direction,
 167                                 req->request.dma, req->request.length, type);
 168                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 169                                 DWC3_EP0_DIR_IN);
 170         }
 171
 172         return ret;
 173 }
 174
 175 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 176                 gfp_t gfp_flags)
 177 {
 178         struct dwc3_request             *req = to_dwc3_request(request);
 179         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 180         struct dwc3                     *dwc = dep->dwc;
 181
 182         unsigned long                   flags;
 183
 184         int                             ret;
 185
 186         spin_lock_irqsave(&dwc->lock, flags);
 187         if (!dep->desc) {
 188                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 189                                 request, dep->name);
 190                 ret = -ESHUTDOWN;
 191                 goto out;
 192         }
 193
 194         /* we share one TRB for ep0/1 */
 195         if (!list_empty(&dwc->eps[0]->request_list) ||
 196                         !list_empty(&dwc->eps[1]->request_list) ||
 197                         dwc->ep0_status_pending) {
 198                 ret = -EBUSY;
 199                 goto out;
 200         }
 201
 202         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 203                         request, dep->name, request->length,
 204                         dwc3_ep0_state_string(dwc->ep0state));
 205
 206         ret = __dwc3_gadget_ep0_queue(dep, req);
 207
 208 out:
 209         spin_unlock_irqrestore(&dwc->lock, flags);
 210
 211         return ret;
 212 }
 213
 214 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 215 {
 216         struct dwc3_ep          *dep = dwc->eps[0];
 217
 218         /* stall is always issued on EP0 */
 219         __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
 220         dwc->eps[0]->flags = DWC3_EP_ENABLED;
 221
 222         if (!list_empty(&dep->request_list)) {
 223                 struct dwc3_request     *req;
 224
 225                 req = next_request(&dep->request_list);
 226                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 227         }
 228
 229         dwc->ep0state = EP0_SETUP_PHASE;
 230         dwc3_ep0_out_start(dwc);
 231 }
 232
 233 void dwc3_ep0_out_start(struct dwc3 *dwc)
 234 {
 235         int                             ret;
 236
 237         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 238                         DWC3_TRBCTL_CONTROL_SETUP);
 239         WARN_ON(ret < 0);
 240 }
 241
 242 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 243 {
 244         struct dwc3_ep          *dep;
 245         u32                     windex = le16_to_cpu(wIndex_le);
 246         u32                     epnum;
 247
 248         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 249         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 250                 epnum |= 1;
 251
 252         dep = dwc->eps[epnum];
 253         if (dep->flags & DWC3_EP_ENABLED)
 254                 return dep;
 255
 256         return NULL;
 257 }
 258
 259 static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
 260 {
 261         dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
 262                         dwc->ep0_usb_req.length,
 263                         DWC3_TRBCTL_CONTROL_DATA);
 264 }
 265
 266 /*
 267  * ch 9.4.5
 268  */
 269 static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 270 {
 271         struct dwc3_ep          *dep;
 272         u32                     recip;
 273         u16                     usb_status = 0;
 274         __le16                  *response_pkt;
 275
 276         recip = ctrl->bRequestType & USB_RECIP_MASK;
 277         switch (recip) {
 278         case USB_RECIP_DEVICE:
 279                 /*
 280                  * We are self-powered. U1/U2/LTM will be set later
 281                  * once we handle this states. RemoteWakeup is 0 on SS
 282                  */
 283                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 284                 break;
 285
 286         case USB_RECIP_INTERFACE:
 287                 /*
 288                  * Function Remote Wake Capable D0
 289                  * Function Remote Wakeup       D1
 290                  */
 291                 break;
 292
 293         case USB_RECIP_ENDPOINT:
 294                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 295                 if (!dep)
 296                        return -EINVAL;
 297
 298                 if (dep->flags & DWC3_EP_STALL)
 299                         usb_status = 1 << USB_ENDPOINT_HALT;
 300                 break;
 301         default:
 302                 return -EINVAL;
 303         };
 304
 305         response_pkt = (__le16 *) dwc->setup_buf;
 306         *response_pkt = cpu_to_le16(usb_status);
 307         dwc->ep0_usb_req.length = sizeof(*response_pkt);
 308         dwc->ep0_status_pending = 1;
 309
 310         return 0;
 311 }
 312
 313 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 314                 struct usb_ctrlrequest *ctrl, int set)
 315 {
 316         struct dwc3_ep          *dep;
 317         u32                     recip;
 318         u32                     wValue;
 319         u32                     wIndex;
 320         u32                     reg;
 321         int                     ret;
 322         u32                     mode;
 323
 324         wValue = le16_to_cpu(ctrl->wValue);
 325         wIndex = le16_to_cpu(ctrl->wIndex);
 326         recip = ctrl->bRequestType & USB_RECIP_MASK;
 327         switch (recip) {
 328         case USB_RECIP_DEVICE:
 329
 330                 /*
 331                  * 9.4.1 says only only for SS, in AddressState only for
 332                  * default control pipe
 333                  */
 334                 switch (wValue) {
 335                 case USB_DEVICE_U1_ENABLE:
 336                 case USB_DEVICE_U2_ENABLE:
 337                 case USB_DEVICE_LTM_ENABLE:
 338                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 339                                 return -EINVAL;
 340                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 341                                 return -EINVAL;
 342                 }
 343
 344                 /* XXX add U[12] & LTM */
 345                 switch (wValue) {
 346                 case USB_DEVICE_REMOTE_WAKEUP:
 347                         break;
 348                 case USB_DEVICE_U1_ENABLE:
 349                         break;
 350                 case USB_DEVICE_U2_ENABLE:
 351                         break;
 352                 case USB_DEVICE_LTM_ENABLE:
 353                         break;
 354
 355                 case USB_DEVICE_TEST_MODE:
 356                         if ((wIndex & 0xff) != 0)
 357                                 return -EINVAL;
 358                         if (!set)
 359                                 return -EINVAL;
 360
 361                         mode = wIndex >> 8;
 362                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 363                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 364
 365                         switch (mode) {
 366                         case TEST_J:
 367                         case TEST_K:
 368                         case TEST_SE0_NAK:
 369                         case TEST_PACKET:
 370                         case TEST_FORCE_EN:
 371                                 reg |= mode << 1;
 372                                 break;
 373                         default:
 374                                 return -EINVAL;
 375                         }
 376                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 377                         break;
 378                 default:
 379                         return -EINVAL;
 380                 }
 381                 break;
 382
 383         case USB_RECIP_INTERFACE:
 384                 switch (wValue) {
 385                 case USB_INTRF_FUNC_SUSPEND:
 386                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 387                                 /* XXX enable Low power suspend */
 388                                 ;
 389                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 390                                 /* XXX enable remote wakeup */
 391                                 ;
 392                         break;
 393                 default:
 394                         return -EINVAL;
 395                 }
 396                 break;
 397
 398         case USB_RECIP_ENDPOINT:
 399                 switch (wValue) {
 400                 case USB_ENDPOINT_HALT:
 401
 402                         dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 403                         if (!dep)
 404                                 return -EINVAL;
 405                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 406                         if (ret)
 407                                 return -EINVAL;
 408                         break;
 409                 default:
 410                         return -EINVAL;
 411                 }
 412                 break;
 413
 414         default:
 415                 return -EINVAL;
 416         };
 417
 418         return 0;
 419 }
 420
 421 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 422 {
 423         u32 addr;
 424         u32 reg;
 425
 426         addr = le16_to_cpu(ctrl->wValue);
 427         if (addr > 127)
 428                 return -EINVAL;
 429
 430         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 431         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 432         reg |= DWC3_DCFG_DEVADDR(addr);
 433         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 434
 435         if (addr)
 436                 dwc->dev_state = DWC3_ADDRESS_STATE;
 437         else
 438                 dwc->dev_state = DWC3_DEFAULT_STATE;
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 444 {
 445         int ret;
 446
 447         spin_unlock(&dwc->lock);
 448         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 449         spin_lock(&dwc->lock);
 450         return ret;
 451 }
 452
 453 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 454 {
 455         u32 cfg;
 456         int ret;
 457
 458         cfg = le16_to_cpu(ctrl->wValue);
 459
 460         switch (dwc->dev_state) {
 461         case DWC3_DEFAULT_STATE:
 462                 return -EINVAL;
 463                 break;
 464
 465         case DWC3_ADDRESS_STATE:
 466                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 467                 /* if the cfg matches and the cfg is non zero */
 468                 if (!ret && cfg)
 469                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 470                 break;
 471
 472         case DWC3_CONFIGURED_STATE:
 473                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 474                 if (!cfg)
 475                         dwc->dev_state = DWC3_ADDRESS_STATE;
 476                 break;
 477         }
 478         return 0;
 479 }
 480
 481 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 482 {
 483         int ret;
 484
 485         switch (ctrl->bRequest) {
 486         case USB_REQ_GET_STATUS:
 487                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 488                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 489                 break;
 490         case USB_REQ_CLEAR_FEATURE:
 491                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 492                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 493                 break;
 494         case USB_REQ_SET_FEATURE:
 495                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 496                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 497                 break;
 498         case USB_REQ_SET_ADDRESS:
 499                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 500                 ret = dwc3_ep0_set_address(dwc, ctrl);
 501                 break;
 502         case USB_REQ_SET_CONFIGURATION:
 503                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 504                 ret = dwc3_ep0_set_config(dwc, ctrl);
 505                 break;
 506         default:
 507                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 508                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 509                 break;
 510         };
 511
 512         return ret;
 513 }
 514
 515 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 516                 const struct dwc3_event_depevt *event)
 517 {
 518         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 519         int ret;
 520         u32 len;
 521
 522         if (!dwc->gadget_driver)
 523                 goto err;
 524
 525         len = le16_to_cpu(ctrl->wLength);
 526         if (!len) {
 527                 dwc->three_stage_setup = false;
 528                 dwc->ep0_expect_in = false;
 529                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 530         } else {
 531                 dwc->three_stage_setup = true;
 532                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 533                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 534         }
 535
 536         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 537                 ret = dwc3_ep0_std_request(dwc, ctrl);
 538         else
 539                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 540
 541         if (ret >= 0)
 542                 return;
 543
 544 err:
 545         dwc3_ep0_stall_and_restart(dwc);
 546 }
 547
 548 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 549                 const struct dwc3_event_depevt *event)
 550 {
 551         struct dwc3_request     *r = NULL;
 552         struct usb_request      *ur;
 553         struct dwc3_trb         trb;
 554         struct dwc3_ep          *dep;
 555         u32                     transferred;
 556         u8                      epnum;
 557
 558         epnum = event->endpoint_number;
 559         dep = dwc->eps[epnum];
 560
 561         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 562
 563         if (!dwc->ep0_status_pending) {
 564                 r = next_request(&dwc->eps[0]->request_list);
 565                 ur = &r->request;
 566         } else {
 567                 ur = &dwc->ep0_usb_req;
 568                 dwc->ep0_status_pending = 0;
 569         }
 570
 571         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 572
 573         if (dwc->ep0_bounced) {
 574                 struct dwc3_ep  *ep0 = dwc->eps[0];
 575
 576                 transferred = min_t(u32, ur->length,
 577                                 ep0->endpoint.maxpacket - trb.length);
 578                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 579                 dwc->ep0_bounced = false;
 580         } else {
 581                 transferred = ur->length - trb.length;
 582                 ur->actual += transferred;
 583         }
 584
 585         if ((epnum & 1) && ur->actual < ur->length) {
 586                 /* for some reason we did not get everything out */
 587
 588                 dwc3_ep0_stall_and_restart(dwc);
 589         } else {
 590                 /*
 591                  * handle the case where we have to send a zero packet. This
 592                  * seems to be case when req.length > maxpacket. Could it be?
 593                  */
 594                 if (r)
 595                         dwc3_gadget_giveback(dep, r, 0);
 596         }
 597 }
 598
 599 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 600                 const struct dwc3_event_depevt *event)
 601 {
 602         struct dwc3_request     *r;
 603         struct dwc3_ep          *dep;
 604
 605         dep = dwc->eps[0];
 606
 607         if (!list_empty(&dep->request_list)) {
 608                 r = next_request(&dep->request_list);
 609
 610                 dwc3_gadget_giveback(dep, r, 0);
 611         }
 612
 613         dwc->ep0state = EP0_SETUP_PHASE;
 614         dwc3_ep0_out_start(dwc);
 615 }
 616
 617 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 618                         const struct dwc3_event_depevt *event)
 619 {
 620         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 621
 622         dep->flags &= ~DWC3_EP_BUSY;
 623
 624         switch (dwc->ep0state) {
 625         case EP0_SETUP_PHASE:
 626                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 627                 dwc3_ep0_inspect_setup(dwc, event);
 628                 break;
 629
 630         case EP0_DATA_PHASE:
 631                 dev_vdbg(dwc->dev, "Data Phase\n");
 632                 dwc3_ep0_complete_data(dwc, event);
 633                 break;
 634
 635         case EP0_STATUS_PHASE:
 636                 dev_vdbg(dwc->dev, "Status Phase\n");
 637                 dwc3_ep0_complete_req(dwc, event);
 638                 break;
 639         default:
 640                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 641         }
 642 }
 643
 644 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 645                 const struct dwc3_event_depevt *event)
 646 {
 647         dwc->ep0state = EP0_SETUP_PHASE;
 648         dwc3_ep0_out_start(dwc);
 649 }
 650
 651 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 652                 const struct dwc3_event_depevt *event)
 653 {
 654         struct dwc3_ep          *dep;
 655         struct dwc3_request     *req;
 656         int                     ret;
 657
 658         dep = dwc->eps[0];
 659         dwc->ep0state = EP0_DATA_PHASE;
 660
 661         if (dwc->ep0_status_pending) {
 662                 dwc3_ep0_send_status_response(dwc);
 663                 return;
 664         }
 665
 666         if (list_empty(&dep->request_list)) {
 667                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 668                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 669
 670                 if (event->endpoint_number)
 671                         dep->flags |= DWC3_EP0_DIR_IN;
 672                 return;
 673         }
 674
 675         req = next_request(&dep->request_list);
 676         req->direction = !!event->endpoint_number;
 677
 678         dwc->ep0state = EP0_DATA_PHASE;
 679         if (req->request.length == 0) {
 680                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 681                                 dwc->ctrl_req_addr, 0,
 682                                 DWC3_TRBCTL_CONTROL_DATA);
 683         } else if ((req->request.length % dep->endpoint.maxpacket)
 684                         && (event->endpoint_number == 0)) {
 685                 dwc3_map_buffer_to_dma(req);
 686
 687                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 688
 689                 dwc->ep0_bounced = true;
 690
 691                 /*
 692                  * REVISIT in case request length is bigger than EP0
 693                  * wMaxPacketSize, we will need two chained TRBs to handle
 694                  * the transfer.
 695                  */
 696                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 697                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 698                                 DWC3_TRBCTL_CONTROL_DATA);
 699         } else {
 700                 dwc3_map_buffer_to_dma(req);
 701
 702                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 703                                 req->request.dma, req->request.length,
 704                                 DWC3_TRBCTL_CONTROL_DATA);
 705         }
 706
 707         WARN_ON(ret < 0);
 708 }
 709
 710 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 711                 const struct dwc3_event_depevt *event)
 712 {
 713         u32                     type;
 714         int                     ret;
 715
 716         dwc->ep0state = EP0_STATUS_PHASE;
 717
 718         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 719                 : DWC3_TRBCTL_CONTROL_STATUS2;
 720
 721         ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 722                         dwc->ctrl_req_addr, 0, type);
 723
 724         WARN_ON(ret < 0);
 725 }
 726
 727 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 728                 const struct dwc3_event_depevt *event)
 729 {
 730         switch (event->status) {
 731         case DEPEVT_STATUS_CONTROL_SETUP:
 732                 dev_vdbg(dwc->dev, "Control Setup\n");
 733                 dwc3_ep0_do_control_setup(dwc, event);
 734                 break;
 735
 736         case DEPEVT_STATUS_CONTROL_DATA:
 737                 dev_vdbg(dwc->dev, "Control Data\n");
 738
 739                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 740                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 741                                         dwc->ep0_next_event,
 742                                         DWC3_EP0_NRDY_DATA);
 743
 744                         dwc3_ep0_stall_and_restart(dwc);
 745                         return;
 746                 }
 747
 748                 /*
 749                  * One of the possible error cases is when Host _does_
 750                  * request for Data Phase, but it does so on the wrong
 751                  * direction.
 752                  *
 753                  * Here, we already know ep0_next_event is DATA (see above),
 754                  * so we only need to check for direction.
 755                  */
 756                 if (dwc->ep0_expect_in != event->endpoint_number) {
 757                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 758                         dwc3_ep0_stall_and_restart(dwc);
 759                         return;
 760                 }
 761
 762                 dwc3_ep0_do_control_data(dwc, event);
 763                 break;
 764
 765         case DEPEVT_STATUS_CONTROL_STATUS:
 766                 dev_vdbg(dwc->dev, "Control Status\n");
 767
 768                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 769                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 770                                         dwc->ep0_next_event,
 771                                         DWC3_EP0_NRDY_STATUS);
 772
 773                         dwc3_ep0_stall_and_restart(dwc);
 774                         return;
 775                 }
 776                 dwc3_ep0_do_control_status(dwc, event);
 777         }
 778 }
 779
 780 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 781                 const const struct dwc3_event_depevt *event)
 782 {
 783         u8                      epnum = event->endpoint_number;
 784
 785         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 786                         dwc3_ep_event_string(event->endpoint_event),
 787                         epnum >> 1, (epnum & 1) ? "in" : "out",
 788                         dwc3_ep0_state_string(dwc->ep0state));
 789
 790         switch (event->endpoint_event) {
 791         case DWC3_DEPEVT_XFERCOMPLETE:
 792                 dwc3_ep0_xfer_complete(dwc, event);
 793                 break;
 794
 795         case DWC3_DEPEVT_XFERNOTREADY:
 796                 dwc3_ep0_xfernotready(dwc, event);
 797                 break;
 798
 799         case DWC3_DEPEVT_XFERINPROGRESS:
 800         case DWC3_DEPEVT_RXTXFIFOEVT:
 801         case DWC3_DEPEVT_STREAMEVT:
 802         case DWC3_DEPEVT_EPCMDCMPLT:
 803                 break;
 804         }
 805 }