Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  * All rights reserved.
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions, and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. The names of the above-listed copyright holders may not be used
  20  *    to endorse or promote products derived from this software without
  21  *    specific prior written permission.
  22  *
  23  * ALTERNATIVELY, this software may be distributed under the terms of the
  24  * GNU General Public License ("GPL") version 2, as published by the Free
  25  * Software Foundation.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  28  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  29  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  30  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  31  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  32  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  33  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  34  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  35  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  36  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  37  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
  58                 const struct dwc3_event_depevt *event);
  59
  60 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  61 {
  62         switch (state) {
  63         case EP0_UNCONNECTED:
  64                 return "Unconnected";
  65         case EP0_SETUP_PHASE:
  66                 return "Setup Phase";
  67         case EP0_DATA_PHASE:
  68                 return "Data Phase";
  69         case EP0_STATUS_PHASE:
  70                 return "Status Phase";
  71         default:
  72                 return "UNKNOWN";
  73         }
  74 }
  75
  76 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  77                 u32 len, u32 type)
  78 {
  79         struct dwc3_gadget_ep_cmd_params params;
  80         struct dwc3_trb_hw              *trb_hw;
  81         struct dwc3_trb                 trb;
  82         struct dwc3_ep                  *dep;
  83
  84         int                             ret;
  85
  86         dep = dwc->eps[epnum];
  87         if (dep->flags & DWC3_EP_BUSY) {
  88                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  89                 return 0;
  90         }
  91
  92         trb_hw = dwc->ep0_trb;
  93         memset(&trb, 0, sizeof(trb));
  94
  95         trb.trbctl = type;
  96         trb.bplh = buf_dma;
  97         trb.length = len;
  98
  99         trb.hwo = 1;
 100         trb.lst = 1;
 101         trb.ioc = 1;
 102         trb.isp_imi = 1;
 103
 104         dwc3_trb_to_hw(&trb, trb_hw);
 105
 106         memset(&params, 0, sizeof(params));
 107         params.param0.depstrtxfer.transfer_desc_addr_high =
 108                 upper_32_bits(dwc->ep0_trb_addr);
 109         params.param1.depstrtxfer.transfer_desc_addr_low =
 110                 lower_32_bits(dwc->ep0_trb_addr);
 111
 112         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 113                         DWC3_DEPCMD_STARTTRANSFER, &params);
 114         if (ret < 0) {
 115                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 116                 return ret;
 117         }
 118
 119         dep->flags |= DWC3_EP_BUSY;
 120         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 121                         dep->number);
 122
 123         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 124
 125         return 0;
 126 }
 127
 128 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 129                 struct dwc3_request *req)
 130 {
 131         int                     ret = 0;
 132
 133         req->request.actual     = 0;
 134         req->request.status     = -EINPROGRESS;
 135         req->epnum              = dep->number;
 136
 137         list_add_tail(&req->list, &dep->request_list);
 138
 139         /*
 140          * Gadget driver might not be quick enough to queue a request
 141          * before we get a Transfer Not Ready event on this endpoint.
 142          *
 143          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 144          * flag is set, it's telling us that as soon as Gadget queues the
 145          * required request, we should kick the transfer here because the
 146          * IRQ we were waiting for is long gone.
 147          */
 148         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 149                 struct dwc3     *dwc = dep->dwc;
 150                 unsigned        direction;
 151                 u32             type;
 152
 153                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 154
 155                 if (dwc->ep0state == EP0_STATUS_PHASE) {
 156                         type = dwc->three_stage_setup
 157                                 ? DWC3_TRBCTL_CONTROL_STATUS3
 158                                 : DWC3_TRBCTL_CONTROL_STATUS2;
 159                 } else if (dwc->ep0state == EP0_DATA_PHASE) {
 160                         type = DWC3_TRBCTL_CONTROL_DATA;
 161                 } else {
 162                         /* should never happen */
 163                         WARN_ON(1);
 164                         return 0;
 165                 }
 166
 167                 ret = dwc3_ep0_start_trans(dwc, direction,
 168                                 req->request.dma, req->request.length, type);
 169                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 170                                 DWC3_EP0_DIR_IN);
 171         }
 172
 173         return ret;
 174 }
 175
 176 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 177                 gfp_t gfp_flags)
 178 {
 179         struct dwc3_request             *req = to_dwc3_request(request);
 180         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 181         struct dwc3                     *dwc = dep->dwc;
 182
 183         unsigned long                   flags;
 184
 185         int                             ret;
 186
 187         spin_lock_irqsave(&dwc->lock, flags);
 188         if (!dep->desc) {
 189                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 190                                 request, dep->name);
 191                 ret = -ESHUTDOWN;
 192                 goto out;
 193         }
 194
 195         /* we share one TRB for ep0/1 */
 196         if (!list_empty(&dwc->eps[0]->request_list) ||
 197                         !list_empty(&dwc->eps[1]->request_list) ||
 198                         dwc->ep0_status_pending) {
 199                 ret = -EBUSY;
 200                 goto out;
 201         }
 202
 203         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 204                         request, dep->name, request->length,
 205                         dwc3_ep0_state_string(dwc->ep0state));
 206
 207         ret = __dwc3_gadget_ep0_queue(dep, req);
 208
 209 out:
 210         spin_unlock_irqrestore(&dwc->lock, flags);
 211
 212         return ret;
 213 }
 214
 215 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 216 {
 217         struct dwc3_ep          *dep = dwc->eps[0];
 218
 219         /* stall is always issued on EP0 */
 220         __dwc3_gadget_ep_set_halt(dwc->eps[0], 1);
 221         dwc->eps[0]->flags = DWC3_EP_ENABLED;
 222
 223         if (!list_empty(&dep->request_list)) {
 224                 struct dwc3_request     *req;
 225
 226                 req = next_request(&dep->request_list);
 227                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 228         }
 229
 230         dwc->ep0state = EP0_SETUP_PHASE;
 231         dwc3_ep0_out_start(dwc);
 232 }
 233
 234 void dwc3_ep0_out_start(struct dwc3 *dwc)
 235 {
 236         int                             ret;
 237
 238         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 239                         DWC3_TRBCTL_CONTROL_SETUP);
 240         WARN_ON(ret < 0);
 241 }
 242
 243 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 244 {
 245         struct dwc3_ep          *dep;
 246         u32                     windex = le16_to_cpu(wIndex_le);
 247         u32                     epnum;
 248
 249         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 250         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 251                 epnum |= 1;
 252
 253         dep = dwc->eps[epnum];
 254         if (dep->flags & DWC3_EP_ENABLED)
 255                 return dep;
 256
 257         return NULL;
 258 }
 259
 260 static void dwc3_ep0_send_status_response(struct dwc3 *dwc)
 261 {
 262         dwc3_ep0_start_trans(dwc, 1, dwc->setup_buf_addr,
 263                         dwc->ep0_usb_req.length,
 264                         DWC3_TRBCTL_CONTROL_DATA);
 265 }
 266
 267 /*
 268  * ch 9.4.5
 269  */
 270 static int dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 271 {
 272         struct dwc3_ep          *dep;
 273         u32                     recip;
 274         u16                     usb_status = 0;
 275         __le16                  *response_pkt;
 276
 277         recip = ctrl->bRequestType & USB_RECIP_MASK;
 278         switch (recip) {
 279         case USB_RECIP_DEVICE:
 280                 /*
 281                  * We are self-powered. U1/U2/LTM will be set later
 282                  * once we handle this states. RemoteWakeup is 0 on SS
 283                  */
 284                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 285                 break;
 286
 287         case USB_RECIP_INTERFACE:
 288                 /*
 289                  * Function Remote Wake Capable D0
 290                  * Function Remote Wakeup       D1
 291                  */
 292                 break;
 293
 294         case USB_RECIP_ENDPOINT:
 295                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 296                 if (!dep)
 297                        return -EINVAL;
 298
 299                 if (dep->flags & DWC3_EP_STALL)
 300                         usb_status = 1 << USB_ENDPOINT_HALT;
 301                 break;
 302         default:
 303                 return -EINVAL;
 304         };
 305
 306         response_pkt = (__le16 *) dwc->setup_buf;
 307         *response_pkt = cpu_to_le16(usb_status);
 308         dwc->ep0_usb_req.length = sizeof(*response_pkt);
 309         dwc->ep0_status_pending = 1;
 310
 311         return 0;
 312 }
 313
 314 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 315                 struct usb_ctrlrequest *ctrl, int set)
 316 {
 317         struct dwc3_ep          *dep;
 318         u32                     recip;
 319         u32                     wValue;
 320         u32                     wIndex;
 321         u32                     reg;
 322         int                     ret;
 323         u32                     mode;
 324
 325         wValue = le16_to_cpu(ctrl->wValue);
 326         wIndex = le16_to_cpu(ctrl->wIndex);
 327         recip = ctrl->bRequestType & USB_RECIP_MASK;
 328         switch (recip) {
 329         case USB_RECIP_DEVICE:
 330
 331                 /*
 332                  * 9.4.1 says only only for SS, in AddressState only for
 333                  * default control pipe
 334                  */
 335                 switch (wValue) {
 336                 case USB_DEVICE_U1_ENABLE:
 337                 case USB_DEVICE_U2_ENABLE:
 338                 case USB_DEVICE_LTM_ENABLE:
 339                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 340                                 return -EINVAL;
 341                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 342                                 return -EINVAL;
 343                 }
 344
 345                 /* XXX add U[12] & LTM */
 346                 switch (wValue) {
 347                 case USB_DEVICE_REMOTE_WAKEUP:
 348                         break;
 349                 case USB_DEVICE_U1_ENABLE:
 350                         break;
 351                 case USB_DEVICE_U2_ENABLE:
 352                         break;
 353                 case USB_DEVICE_LTM_ENABLE:
 354                         break;
 355
 356                 case USB_DEVICE_TEST_MODE:
 357                         if ((wIndex & 0xff) != 0)
 358                                 return -EINVAL;
 359                         if (!set)
 360                                 return -EINVAL;
 361
 362                         mode = wIndex >> 8;
 363                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 364                         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
 365
 366                         switch (mode) {
 367                         case TEST_J:
 368                         case TEST_K:
 369                         case TEST_SE0_NAK:
 370                         case TEST_PACKET:
 371                         case TEST_FORCE_EN:
 372                                 reg |= mode << 1;
 373                                 break;
 374                         default:
 375                                 return -EINVAL;
 376                         }
 377                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 378                         break;
 379                 default:
 380                         return -EINVAL;
 381                 }
 382                 break;
 383
 384         case USB_RECIP_INTERFACE:
 385                 switch (wValue) {
 386                 case USB_INTRF_FUNC_SUSPEND:
 387                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 388                                 /* XXX enable Low power suspend */
 389                                 ;
 390                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 391                                 /* XXX enable remote wakeup */
 392                                 ;
 393                         break;
 394                 default:
 395                         return -EINVAL;
 396                 }
 397                 break;
 398
 399         case USB_RECIP_ENDPOINT:
 400                 switch (wValue) {
 401                 case USB_ENDPOINT_HALT:
 402
 403                         dep =  dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 404                         if (!dep)
 405                                 return -EINVAL;
 406                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 407                         if (ret)
 408                                 return -EINVAL;
 409                         break;
 410                 default:
 411                         return -EINVAL;
 412                 }
 413                 break;
 414
 415         default:
 416                 return -EINVAL;
 417         };
 418
 419         return 0;
 420 }
 421
 422 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 423 {
 424         int ret = 0;
 425         u32 addr;
 426         u32 reg;
 427
 428         addr = le16_to_cpu(ctrl->wValue);
 429         if (addr > 127)
 430                 return -EINVAL;
 431
 432         switch (dwc->dev_state) {
 433         case DWC3_DEFAULT_STATE:
 434         case DWC3_ADDRESS_STATE:
 435                 /*
 436                  * Not sure if we should program DevAddr now or later
 437                  */
 438                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 439                 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 440                 reg |= DWC3_DCFG_DEVADDR(addr);
 441                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 442
 443                 if (addr)
 444                         dwc->dev_state = DWC3_ADDRESS_STATE;
 445                 else
 446                         dwc->dev_state = DWC3_DEFAULT_STATE;
 447                 break;
 448
 449         case DWC3_CONFIGURED_STATE:
 450                 ret = -EINVAL;
 451                 break;
 452         }
 453
 454         return ret;
 455 }
 456
 457 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 458 {
 459         int ret;
 460
 461         spin_unlock(&dwc->lock);
 462         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 463         spin_lock(&dwc->lock);
 464         return ret;
 465 }
 466
 467 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 468 {
 469         u32 cfg;
 470         int ret;
 471
 472         cfg = le16_to_cpu(ctrl->wValue);
 473
 474         switch (dwc->dev_state) {
 475         case DWC3_DEFAULT_STATE:
 476                 return -EINVAL;
 477                 break;
 478
 479         case DWC3_ADDRESS_STATE:
 480                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 481                 /* if the cfg matches and the cfg is non zero */
 482                 if (!ret && cfg)
 483                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 484                 break;
 485
 486         case DWC3_CONFIGURED_STATE:
 487                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 488                 if (!cfg)
 489                         dwc->dev_state = DWC3_ADDRESS_STATE;
 490                 break;
 491         }
 492         return 0;
 493 }
 494
 495 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 496 {
 497         int ret;
 498
 499         switch (ctrl->bRequest) {
 500         case USB_REQ_GET_STATUS:
 501                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 502                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 503                 break;
 504         case USB_REQ_CLEAR_FEATURE:
 505                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 506                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 507                 break;
 508         case USB_REQ_SET_FEATURE:
 509                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 510                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 511                 break;
 512         case USB_REQ_SET_ADDRESS:
 513                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 514                 ret = dwc3_ep0_set_address(dwc, ctrl);
 515                 break;
 516         case USB_REQ_SET_CONFIGURATION:
 517                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 518                 ret = dwc3_ep0_set_config(dwc, ctrl);
 519                 break;
 520         default:
 521                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 522                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 523                 break;
 524         };
 525
 526         return ret;
 527 }
 528
 529 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 530                 const struct dwc3_event_depevt *event)
 531 {
 532         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 533         int ret;
 534         u32 len;
 535
 536         if (!dwc->gadget_driver)
 537                 goto err;
 538
 539         len = le16_to_cpu(ctrl->wLength);
 540         if (!len) {
 541                 dwc->three_stage_setup = 0;
 542                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 543         } else {
 544                 dwc->three_stage_setup = 1;
 545                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 546         }
 547
 548         dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 549
 550         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 551                 ret = dwc3_ep0_std_request(dwc, ctrl);
 552         else
 553                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 554
 555         if (ret >= 0)
 556                 return;
 557
 558 err:
 559         dwc3_ep0_stall_and_restart(dwc);
 560 }
 561
 562 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 563                 const struct dwc3_event_depevt *event)
 564 {
 565         struct dwc3_request     *r = NULL;
 566         struct usb_request      *ur;
 567         struct dwc3_trb         trb;
 568         struct dwc3_ep          *dep;
 569         u32                     transferred;
 570         u8                      epnum;
 571
 572         epnum = event->endpoint_number;
 573         dep = dwc->eps[epnum];
 574
 575         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 576
 577         if (!dwc->ep0_status_pending) {
 578                 r = next_request(&dwc->eps[0]->request_list);
 579                 ur = &r->request;
 580         } else {
 581                 ur = &dwc->ep0_usb_req;
 582                 dwc->ep0_status_pending = 0;
 583         }
 584
 585         dwc3_trb_to_nat(dwc->ep0_trb, &trb);
 586
 587         if (dwc->ep0_bounced) {
 588                 struct dwc3_ep  *ep0 = dwc->eps[0];
 589
 590                 transferred = min_t(u32, ur->length,
 591                                 ep0->endpoint.maxpacket - trb.length);
 592                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 593                 dwc->ep0_bounced = false;
 594         } else {
 595                 transferred = ur->length - trb.length;
 596                 ur->actual += transferred;
 597         }
 598
 599         if ((epnum & 1) && ur->actual < ur->length) {
 600                 /* for some reason we did not get everything out */
 601
 602                 dwc3_ep0_stall_and_restart(dwc);
 603                 dwc3_gadget_giveback(dep, r, -ECONNRESET);
 604         } else {
 605                 /*
 606                  * handle the case where we have to send a zero packet. This
 607                  * seems to be case when req.length > maxpacket. Could it be?
 608                  */
 609                 if (r)
 610                         dwc3_gadget_giveback(dep, r, 0);
 611         }
 612 }
 613
 614 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 615                 const struct dwc3_event_depevt *event)
 616 {
 617         struct dwc3_request     *r;
 618         struct dwc3_ep          *dep;
 619
 620         dep = dwc->eps[0];
 621
 622         if (!list_empty(&dep->request_list)) {
 623                 r = next_request(&dep->request_list);
 624
 625                 dwc3_gadget_giveback(dep, r, 0);
 626         }
 627
 628         dwc->ep0state = EP0_SETUP_PHASE;
 629         dwc3_ep0_out_start(dwc);
 630 }
 631
 632 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 633                         const struct dwc3_event_depevt *event)
 634 {
 635         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 636
 637         dep->flags &= ~DWC3_EP_BUSY;
 638
 639         switch (dwc->ep0state) {
 640         case EP0_SETUP_PHASE:
 641                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 642                 dwc3_ep0_inspect_setup(dwc, event);
 643                 break;
 644
 645         case EP0_DATA_PHASE:
 646                 dev_vdbg(dwc->dev, "Data Phase\n");
 647                 dwc3_ep0_complete_data(dwc, event);
 648                 break;
 649
 650         case EP0_STATUS_PHASE:
 651                 dev_vdbg(dwc->dev, "Status Phase\n");
 652                 dwc3_ep0_complete_req(dwc, event);
 653                 break;
 654         default:
 655                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 656         }
 657 }
 658
 659 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 660                 const struct dwc3_event_depevt *event)
 661 {
 662         dwc->ep0state = EP0_SETUP_PHASE;
 663         dwc3_ep0_out_start(dwc);
 664 }
 665
 666 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 667                 const struct dwc3_event_depevt *event)
 668 {
 669         struct dwc3_ep          *dep;
 670         struct dwc3_request     *req;
 671         int                     ret;
 672
 673         dep = dwc->eps[0];
 674         dwc->ep0state = EP0_DATA_PHASE;
 675
 676         if (dwc->ep0_status_pending) {
 677                 dwc3_ep0_send_status_response(dwc);
 678                 return;
 679         }
 680
 681         if (list_empty(&dep->request_list)) {
 682                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 683                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 684
 685                 if (event->endpoint_number)
 686                         dep->flags |= DWC3_EP0_DIR_IN;
 687                 return;
 688         }
 689
 690         req = next_request(&dep->request_list);
 691         req->direction = !!event->endpoint_number;
 692
 693         dwc->ep0state = EP0_DATA_PHASE;
 694         if (req->request.length == 0) {
 695                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 696                                 dwc->ctrl_req_addr, 0,
 697                                 DWC3_TRBCTL_CONTROL_DATA);
 698         } else if ((req->request.length % dep->endpoint.maxpacket)
 699                         && (event->endpoint_number == 0)) {
 700                 dwc3_map_buffer_to_dma(req);
 701
 702                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 703
 704                 dwc->ep0_bounced = true;
 705
 706                 /*
 707                  * REVISIT in case request length is bigger than EP0
 708                  * wMaxPacketSize, we will need two chained TRBs to handle
 709                  * the transfer.
 710                  */
 711                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 712                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 713                                 DWC3_TRBCTL_CONTROL_DATA);
 714         } else {
 715                 dwc3_map_buffer_to_dma(req);
 716
 717                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 718                                 req->request.dma, req->request.length,
 719                                 DWC3_TRBCTL_CONTROL_DATA);
 720         }
 721
 722         WARN_ON(ret < 0);
 723 }
 724
 725 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 726                 const struct dwc3_event_depevt *event)
 727 {
 728         u32                     type;
 729         int                     ret;
 730
 731         dwc->ep0state = EP0_STATUS_PHASE;
 732
 733         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 734                 : DWC3_TRBCTL_CONTROL_STATUS2;
 735
 736         ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 737                         dwc->ctrl_req_addr, 0, type);
 738
 739         WARN_ON(ret < 0);
 740 }
 741
 742 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 743                 const struct dwc3_event_depevt *event)
 744 {
 745         switch (event->status) {
 746         case DEPEVT_STATUS_CONTROL_SETUP:
 747                 dev_vdbg(dwc->dev, "Control Setup\n");
 748                 dwc3_ep0_do_control_setup(dwc, event);
 749                 break;
 750
 751         case DEPEVT_STATUS_CONTROL_DATA:
 752                 dev_vdbg(dwc->dev, "Control Data\n");
 753
 754                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 755                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 756                                         DEPEVT_STATUS_CONTROL_DATA,
 757                                         event->status);
 758
 759                         dwc3_ep0_stall_and_restart(dwc);
 760                         return;
 761                 }
 762
 763                 /*
 764                  * One of the possible error cases is when Host _does_
 765                  * request for Data Phase, but it does so on the wrong
 766                  * direction.
 767                  *
 768                  * Here, we already know ep0_next_event is DATA (see above),
 769                  * so we only need to check for direction.
 770                  */
 771                 if (dwc->ep0_expect_in != event->endpoint_number) {
 772                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 773                         dwc3_ep0_stall_and_restart(dwc);
 774                         return;
 775                 }
 776
 777                 dwc3_ep0_do_control_data(dwc, event);
 778                 break;
 779
 780         case DEPEVT_STATUS_CONTROL_STATUS:
 781                 dev_vdbg(dwc->dev, "Control Status\n");
 782
 783                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 784                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 785                                         DEPEVT_STATUS_CONTROL_STATUS,
 786                                         event->status);
 787
 788                         dwc3_ep0_stall_and_restart(dwc);
 789                         return;
 790                 }
 791                 dwc3_ep0_do_control_status(dwc, event);
 792         }
 793 }
 794
 795 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 796                 const const struct dwc3_event_depevt *event)
 797 {
 798         u8                      epnum = event->endpoint_number;
 799
 800         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 801                         dwc3_ep_event_string(event->endpoint_event),
 802                         epnum, (epnum & 1) ? "in" : "out",
 803                         dwc3_ep0_state_string(dwc->ep0state));
 804
 805         switch (event->endpoint_event) {
 806         case DWC3_DEPEVT_XFERCOMPLETE:
 807                 dwc3_ep0_xfer_complete(dwc, event);
 808                 break;
 809
 810         case DWC3_DEPEVT_XFERNOTREADY:
 811                 dwc3_ep0_xfernotready(dwc, event);
 812                 break;
 813
 814         case DWC3_DEPEVT_XFERINPROGRESS:
 815         case DWC3_DEPEVT_RXTXFIFOEVT:
 816         case DWC3_DEPEVT_STREAMEVT:
 817         case DWC3_DEPEVT_EPCMDCMPLT:
 818                 break;
 819         }
 820 }