Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  58 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  59                 struct dwc3_ep *dep, struct dwc3_request *req);
  60
  61 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  62 {
  63         switch (state) {
  64         case EP0_UNCONNECTED:
  65                 return "Unconnected";
  66         case EP0_SETUP_PHASE:
  67                 return "Setup Phase";
  68         case EP0_DATA_PHASE:
  69                 return "Data Phase";
  70         case EP0_STATUS_PHASE:
  71                 return "Status Phase";
  72         default:
  73                 return "UNKNOWN";
  74         }
  75 }
  76
  77 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  78                 u32 len, u32 type)
  79 {
  80         struct dwc3_gadget_ep_cmd_params params;
  81         struct dwc3_trb                 *trb;
  82         struct dwc3_ep                  *dep;
  83
  84         int                             ret;
  85
  86         dep = dwc->eps[epnum];
  87         if (dep->flags & DWC3_EP_BUSY) {
  88                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  89                 return 0;
  90         }
  91
  92         trb = dwc->ep0_trb;
  93
  94         trb->bpl = lower_32_bits(buf_dma);
  95         trb->bph = upper_32_bits(buf_dma);
  96         trb->size = len;
  97         trb->ctrl = type;
  98
  99         trb->ctrl |= (DWC3_TRB_CTRL_HWO
 100                         | DWC3_TRB_CTRL_LST
 101                         | DWC3_TRB_CTRL_IOC
 102                         | DWC3_TRB_CTRL_ISP_IMI);
 103
 104         memset(&params, 0, sizeof(params));
 105         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 106         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 107
 108         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 109                         DWC3_DEPCMD_STARTTRANSFER, &params);
 110         if (ret < 0) {
 111                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 112                 return ret;
 113         }
 114
 115         dep->flags |= DWC3_EP_BUSY;
 116         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 117                         dep->number);
 118
 119         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 120
 121         return 0;
 122 }
 123
 124 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 125                 struct dwc3_request *req)
 126 {
 127         struct dwc3             *dwc = dep->dwc;
 128         int                     ret = 0;
 129
 130         req->request.actual     = 0;
 131         req->request.status     = -EINPROGRESS;
 132         req->epnum              = dep->number;
 133
 134         list_add_tail(&req->list, &dep->request_list);
 135
 136         /*
 137          * Gadget driver might not be quick enough to queue a request
 138          * before we get a Transfer Not Ready event on this endpoint.
 139          *
 140          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 141          * flag is set, it's telling us that as soon as Gadget queues the
 142          * required request, we should kick the transfer here because the
 143          * IRQ we were waiting for is long gone.
 144          */
 145         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 146                 unsigned        direction;
 147
 148                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 149
 150                 if (dwc->ep0state != EP0_DATA_PHASE) {
 151                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 152                         return 0;
 153                 }
 154
 155                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 156
 157                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 158                                 DWC3_EP0_DIR_IN);
 159         } else if (dwc->delayed_status) {
 160                 dwc->delayed_status = false;
 161
 162                 if (dwc->ep0state == EP0_STATUS_PHASE)
 163                         __dwc3_ep0_do_control_status(dwc, dwc->eps[1]);
 164                 else
 165                         dev_dbg(dwc->dev, "too early for delayed status\n");
 166         }
 167
 168         return ret;
 169 }
 170
 171 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 172                 gfp_t gfp_flags)
 173 {
 174         struct dwc3_request             *req = to_dwc3_request(request);
 175         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 176         struct dwc3                     *dwc = dep->dwc;
 177
 178         unsigned long                   flags;
 179
 180         int                             ret;
 181
 182         spin_lock_irqsave(&dwc->lock, flags);
 183         if (!dep->endpoint.desc) {
 184                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 185                                 request, dep->name);
 186                 ret = -ESHUTDOWN;
 187                 goto out;
 188         }
 189
 190         /* we share one TRB for ep0/1 */
 191         if (!list_empty(&dep->request_list)) {
 192                 ret = -EBUSY;
 193                 goto out;
 194         }
 195
 196         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 197                         request, dep->name, request->length,
 198                         dwc3_ep0_state_string(dwc->ep0state));
 199
 200         ret = __dwc3_gadget_ep0_queue(dep, req);
 201
 202 out:
 203         spin_unlock_irqrestore(&dwc->lock, flags);
 204
 205         return ret;
 206 }
 207
 208 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 209 {
 210         struct dwc3_ep          *dep = dwc->eps[0];
 211
 212         /* stall is always issued on EP0 */
 213         __dwc3_gadget_ep_set_halt(dep, 1);
 214         dep->flags = DWC3_EP_ENABLED;
 215         dwc->delayed_status = false;
 216
 217         if (!list_empty(&dep->request_list)) {
 218                 struct dwc3_request     *req;
 219
 220                 req = next_request(&dep->request_list);
 221                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 222         }
 223
 224         dwc->ep0state = EP0_SETUP_PHASE;
 225         dwc3_ep0_out_start(dwc);
 226 }
 227
 228 void dwc3_ep0_out_start(struct dwc3 *dwc)
 229 {
 230         int                             ret;
 231
 232         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 233                         DWC3_TRBCTL_CONTROL_SETUP);
 234         WARN_ON(ret < 0);
 235 }
 236
 237 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 238 {
 239         struct dwc3_ep          *dep;
 240         u32                     windex = le16_to_cpu(wIndex_le);
 241         u32                     epnum;
 242
 243         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 244         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 245                 epnum |= 1;
 246
 247         dep = dwc->eps[epnum];
 248         if (dep->flags & DWC3_EP_ENABLED)
 249                 return dep;
 250
 251         return NULL;
 252 }
 253
 254 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 255 {
 256 }
 257 /*
 258  * ch 9.4.5
 259  */
 260 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 261                 struct usb_ctrlrequest *ctrl)
 262 {
 263         struct dwc3_ep          *dep;
 264         u32                     recip;
 265         u32                     reg;
 266         u16                     usb_status = 0;
 267         __le16                  *response_pkt;
 268
 269         recip = ctrl->bRequestType & USB_RECIP_MASK;
 270         switch (recip) {
 271         case USB_RECIP_DEVICE:
 272                 /*
 273                  * LTM will be set once we know how to set this in HW.
 274                  */
 275                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 276
 277                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 278                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 279                         if (reg & DWC3_DCTL_INITU1ENA)
 280                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 281                         if (reg & DWC3_DCTL_INITU2ENA)
 282                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 283                 }
 284
 285                 break;
 286
 287         case USB_RECIP_INTERFACE:
 288                 /*
 289                  * Function Remote Wake Capable D0
 290                  * Function Remote Wakeup       D1
 291                  */
 292                 break;
 293
 294         case USB_RECIP_ENDPOINT:
 295                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 296                 if (!dep)
 297                         return -EINVAL;
 298
 299                 if (dep->flags & DWC3_EP_STALL)
 300                         usb_status = 1 << USB_ENDPOINT_HALT;
 301                 break;
 302         default:
 303                 return -EINVAL;
 304         };
 305
 306         response_pkt = (__le16 *) dwc->setup_buf;
 307         *response_pkt = cpu_to_le16(usb_status);
 308
 309         dep = dwc->eps[0];
 310         dwc->ep0_usb_req.dep = dep;
 311         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 312         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 313         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 314
 315         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 316 }
 317
 318 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 319                 struct usb_ctrlrequest *ctrl, int set)
 320 {
 321         struct dwc3_ep          *dep;
 322         u32                     recip;
 323         u32                     wValue;
 324         u32                     wIndex;
 325         u32                     reg;
 326         int                     ret;
 327
 328         wValue = le16_to_cpu(ctrl->wValue);
 329         wIndex = le16_to_cpu(ctrl->wIndex);
 330         recip = ctrl->bRequestType & USB_RECIP_MASK;
 331         switch (recip) {
 332         case USB_RECIP_DEVICE:
 333
 334                 switch (wValue) {
 335                 case USB_DEVICE_REMOTE_WAKEUP:
 336                         break;
 337                 /*
 338                  * 9.4.1 says only only for SS, in AddressState only for
 339                  * default control pipe
 340                  */
 341                 case USB_DEVICE_U1_ENABLE:
 342                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 343                                 return -EINVAL;
 344                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 345                                 return -EINVAL;
 346
 347                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 348                         if (set)
 349                                 reg |= DWC3_DCTL_INITU1ENA;
 350                         else
 351                                 reg &= ~DWC3_DCTL_INITU1ENA;
 352                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 353                         break;
 354
 355                 case USB_DEVICE_U2_ENABLE:
 356                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 357                                 return -EINVAL;
 358                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 359                                 return -EINVAL;
 360
 361                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 362                         if (set)
 363                                 reg |= DWC3_DCTL_INITU2ENA;
 364                         else
 365                                 reg &= ~DWC3_DCTL_INITU2ENA;
 366                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 367                         break;
 368
 369                 case USB_DEVICE_LTM_ENABLE:
 370                         return -EINVAL;
 371                         break;
 372
 373                 case USB_DEVICE_TEST_MODE:
 374                         if ((wIndex & 0xff) != 0)
 375                                 return -EINVAL;
 376                         if (!set)
 377                                 return -EINVAL;
 378
 379                         dwc->test_mode_nr = wIndex >> 8;
 380                         dwc->test_mode = true;
 381                         break;
 382                 default:
 383                         return -EINVAL;
 384                 }
 385                 break;
 386
 387         case USB_RECIP_INTERFACE:
 388                 switch (wValue) {
 389                 case USB_INTRF_FUNC_SUSPEND:
 390                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 391                                 /* XXX enable Low power suspend */
 392                                 ;
 393                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 394                                 /* XXX enable remote wakeup */
 395                                 ;
 396                         break;
 397                 default:
 398                         return -EINVAL;
 399                 }
 400                 break;
 401
 402         case USB_RECIP_ENDPOINT:
 403                 switch (wValue) {
 404                 case USB_ENDPOINT_HALT:
 405                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 406                         if (!dep)
 407                                 return -EINVAL;
 408                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 409                         if (ret)
 410                                 return -EINVAL;
 411                         break;
 412                 default:
 413                         return -EINVAL;
 414                 }
 415                 break;
 416
 417         default:
 418                 return -EINVAL;
 419         };
 420
 421         return 0;
 422 }
 423
 424 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 425 {
 426         u32 addr;
 427         u32 reg;
 428
 429         addr = le16_to_cpu(ctrl->wValue);
 430         if (addr > 127) {
 431                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 432                 return -EINVAL;
 433         }
 434
 435         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 436                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 437                 return -EINVAL;
 438         }
 439
 440         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 441         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 442         reg |= DWC3_DCFG_DEVADDR(addr);
 443         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 444
 445         if (addr)
 446                 dwc->dev_state = DWC3_ADDRESS_STATE;
 447         else
 448                 dwc->dev_state = DWC3_DEFAULT_STATE;
 449
 450         return 0;
 451 }
 452
 453 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 454 {
 455         int ret;
 456
 457         spin_unlock(&dwc->lock);
 458         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 459         spin_lock(&dwc->lock);
 460         return ret;
 461 }
 462
 463 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 464 {
 465         u32 cfg;
 466         int ret;
 467
 468         dwc->start_config_issued = false;
 469         cfg = le16_to_cpu(ctrl->wValue);
 470
 471         switch (dwc->dev_state) {
 472         case DWC3_DEFAULT_STATE:
 473                 return -EINVAL;
 474                 break;
 475
 476         case DWC3_ADDRESS_STATE:
 477                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 478                 /* if the cfg matches and the cfg is non zero */
 479                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 480                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 481                         dwc->resize_fifos = true;
 482                         dev_dbg(dwc->dev, "resize fifos flag SET\n");
 483                 }
 484                 break;
 485
 486         case DWC3_CONFIGURED_STATE:
 487                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 488                 if (!cfg)
 489                         dwc->dev_state = DWC3_ADDRESS_STATE;
 490                 break;
 491         default:
 492                 ret = -EINVAL;
 493         }
 494         return ret;
 495 }
 496
 497 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 498 {
 499         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 500         struct dwc3     *dwc = dep->dwc;
 501
 502         u32             param = 0;
 503         u32             reg;
 504
 505         struct timing {
 506                 u8      u1sel;
 507                 u8      u1pel;
 508                 u16     u2sel;
 509                 u16     u2pel;
 510         } __packed timing;
 511
 512         int             ret;
 513
 514         memcpy(&timing, req->buf, sizeof(timing));
 515
 516         dwc->u1sel = timing.u1sel;
 517         dwc->u1pel = timing.u1pel;
 518         dwc->u2sel = le16_to_cpu(timing.u2sel);
 519         dwc->u2pel = le16_to_cpu(timing.u2pel);
 520
 521         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 522         if (reg & DWC3_DCTL_INITU2ENA)
 523                 param = dwc->u2pel;
 524         if (reg & DWC3_DCTL_INITU1ENA)
 525                 param = dwc->u1pel;
 526
 527         /*
 528          * According to Synopsys Databook, if parameter is
 529          * greater than 125, a value of zero should be
 530          * programmed in the register.
 531          */
 532         if (param > 125)
 533                 param = 0;
 534
 535         /* now that we have the time, issue DGCMD Set Sel */
 536         ret = dwc3_send_gadget_generic_command(dwc,
 537                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 538         WARN_ON(ret < 0);
 539 }
 540
 541 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 542 {
 543         struct dwc3_ep  *dep;
 544         u16             wLength;
 545         u16             wValue;
 546
 547         if (dwc->dev_state == DWC3_DEFAULT_STATE)
 548                 return -EINVAL;
 549
 550         wValue = le16_to_cpu(ctrl->wValue);
 551         wLength = le16_to_cpu(ctrl->wLength);
 552
 553         if (wLength != 6) {
 554                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 555                                 wLength);
 556                 return -EINVAL;
 557         }
 558
 559         /*
 560          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 561          * queue a usb_request for 6 bytes.
 562          *
 563          * Remember, though, this controller can't handle non-wMaxPacketSize
 564          * aligned transfers on the OUT direction, so we queue a request for
 565          * wMaxPacketSize instead.
 566          */
 567         dep = dwc->eps[0];
 568         dwc->ep0_usb_req.dep = dep;
 569         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 570         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 571         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 572
 573         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 574 }
 575
 576 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 577 {
 578         u16             wLength;
 579         u16             wValue;
 580         u16             wIndex;
 581
 582         wValue = le16_to_cpu(ctrl->wValue);
 583         wLength = le16_to_cpu(ctrl->wLength);
 584         wIndex = le16_to_cpu(ctrl->wIndex);
 585
 586         if (wIndex || wLength)
 587                 return -EINVAL;
 588
 589         /*
 590          * REVISIT It's unclear from Databook what to do with this
 591          * value. For now, just cache it.
 592          */
 593         dwc->isoch_delay = wValue;
 594
 595         return 0;
 596 }
 597
 598 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 599 {
 600         int ret;
 601
 602         switch (ctrl->bRequest) {
 603         case USB_REQ_GET_STATUS:
 604                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 605                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 606                 break;
 607         case USB_REQ_CLEAR_FEATURE:
 608                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 609                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 610                 break;
 611         case USB_REQ_SET_FEATURE:
 612                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 613                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 614                 break;
 615         case USB_REQ_SET_ADDRESS:
 616                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 617                 ret = dwc3_ep0_set_address(dwc, ctrl);
 618                 break;
 619         case USB_REQ_SET_CONFIGURATION:
 620                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 621                 ret = dwc3_ep0_set_config(dwc, ctrl);
 622                 break;
 623         case USB_REQ_SET_SEL:
 624                 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
 625                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 626                 break;
 627         case USB_REQ_SET_ISOCH_DELAY:
 628                 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
 629                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 630                 break;
 631         default:
 632                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 633                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 634                 break;
 635         };
 636
 637         return ret;
 638 }
 639
 640 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 641                 const struct dwc3_event_depevt *event)
 642 {
 643         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 644         int ret = -EINVAL;
 645         u32 len;
 646
 647         if (!dwc->gadget_driver)
 648                 goto out;
 649
 650         len = le16_to_cpu(ctrl->wLength);
 651         if (!len) {
 652                 dwc->three_stage_setup = false;
 653                 dwc->ep0_expect_in = false;
 654                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 655         } else {
 656                 dwc->three_stage_setup = true;
 657                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 658                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 659         }
 660
 661         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 662                 ret = dwc3_ep0_std_request(dwc, ctrl);
 663         else
 664                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 665
 666         if (ret == USB_GADGET_DELAYED_STATUS)
 667                 dwc->delayed_status = true;
 668
 669 out:
 670         if (ret < 0)
 671                 dwc3_ep0_stall_and_restart(dwc);
 672 }
 673
 674 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 675                 const struct dwc3_event_depevt *event)
 676 {
 677         struct dwc3_request     *r = NULL;
 678         struct usb_request      *ur;
 679         struct dwc3_trb         *trb;
 680         struct dwc3_ep          *ep0;
 681         u32                     transferred;
 682         u32                     length;
 683         u8                      epnum;
 684
 685         epnum = event->endpoint_number;
 686         ep0 = dwc->eps[0];
 687
 688         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 689
 690         r = next_request(&ep0->request_list);
 691         ur = &r->request;
 692
 693         trb = dwc->ep0_trb;
 694         length = trb->size & DWC3_TRB_SIZE_MASK;
 695
 696         if (dwc->ep0_bounced) {
 697                 unsigned transfer_size = ur->length;
 698                 unsigned maxp = ep0->endpoint.maxpacket;
 699
 700                 transfer_size += (maxp - (transfer_size % maxp));
 701                 transferred = min_t(u32, ur->length,
 702                                 transfer_size - length);
 703                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 704                 dwc->ep0_bounced = false;
 705         } else {
 706                 transferred = ur->length - length;
 707         }
 708
 709         ur->actual += transferred;
 710
 711         if ((epnum & 1) && ur->actual < ur->length) {
 712                 /* for some reason we did not get everything out */
 713
 714                 dwc3_ep0_stall_and_restart(dwc);
 715         } else {
 716                 /*
 717                  * handle the case where we have to send a zero packet. This
 718                  * seems to be case when req.length > maxpacket. Could it be?
 719                  */
 720                 if (r)
 721                         dwc3_gadget_giveback(ep0, r, 0);
 722         }
 723 }
 724
 725 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 726                 const struct dwc3_event_depevt *event)
 727 {
 728         struct dwc3_request     *r;
 729         struct dwc3_ep          *dep;
 730
 731         dep = dwc->eps[0];
 732
 733         if (!list_empty(&dep->request_list)) {
 734                 r = next_request(&dep->request_list);
 735
 736                 dwc3_gadget_giveback(dep, r, 0);
 737         }
 738
 739         if (dwc->test_mode) {
 740                 int ret;
 741
 742                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 743                 if (ret < 0) {
 744                         dev_dbg(dwc->dev, "Invalid Test #%d\n",
 745                                         dwc->test_mode_nr);
 746                         dwc3_ep0_stall_and_restart(dwc);
 747                 }
 748         }
 749
 750         dwc->ep0state = EP0_SETUP_PHASE;
 751         dwc3_ep0_out_start(dwc);
 752 }
 753
 754 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 755                         const struct dwc3_event_depevt *event)
 756 {
 757         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 758
 759         dep->flags &= ~DWC3_EP_BUSY;
 760         dep->resource_index = 0;
 761         dwc->setup_packet_pending = false;
 762
 763         switch (dwc->ep0state) {
 764         case EP0_SETUP_PHASE:
 765                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 766                 dwc3_ep0_inspect_setup(dwc, event);
 767                 break;
 768
 769         case EP0_DATA_PHASE:
 770                 dev_vdbg(dwc->dev, "Data Phase\n");
 771                 dwc3_ep0_complete_data(dwc, event);
 772                 break;
 773
 774         case EP0_STATUS_PHASE:
 775                 dev_vdbg(dwc->dev, "Status Phase\n");
 776                 dwc3_ep0_complete_status(dwc, event);
 777                 break;
 778         default:
 779                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 780         }
 781 }
 782
 783 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 784                 const struct dwc3_event_depevt *event)
 785 {
 786         dwc3_ep0_out_start(dwc);
 787 }
 788
 789 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 790                 struct dwc3_ep *dep, struct dwc3_request *req)
 791 {
 792         int                     ret;
 793
 794         req->direction = !!dep->number;
 795
 796         if (req->request.length == 0) {
 797                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 798                                 dwc->ctrl_req_addr, 0,
 799                                 DWC3_TRBCTL_CONTROL_DATA);
 800         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 801                         && (dep->number == 0)) {
 802                 u32             transfer_size;
 803
 804                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 805                                 dep->number);
 806                 if (ret) {
 807                         dev_dbg(dwc->dev, "failed to map request\n");
 808                         return;
 809                 }
 810
 811                 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
 812
 813                 transfer_size = roundup(req->request.length,
 814                                 (u32) dep->endpoint.maxpacket);
 815
 816                 dwc->ep0_bounced = true;
 817
 818                 /*
 819                  * REVISIT in case request length is bigger than
 820                  * DWC3_EP0_BOUNCE_SIZE we will need two chained
 821                  * TRBs to handle the transfer.
 822                  */
 823                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 824                                 dwc->ep0_bounce_addr, transfer_size,
 825                                 DWC3_TRBCTL_CONTROL_DATA);
 826         } else {
 827                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 828                                 dep->number);
 829                 if (ret) {
 830                         dev_dbg(dwc->dev, "failed to map request\n");
 831                         return;
 832                 }
 833
 834                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
 835                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
 836         }
 837
 838         WARN_ON(ret < 0);
 839 }
 840
 841 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 842                 const struct dwc3_event_depevt *event)
 843 {
 844         struct dwc3_ep          *dep;
 845         struct dwc3_request     *req;
 846
 847         dep = dwc->eps[0];
 848
 849         if (list_empty(&dep->request_list)) {
 850                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 851                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 852
 853                 if (event->endpoint_number)
 854                         dep->flags |= DWC3_EP0_DIR_IN;
 855                 return;
 856         }
 857
 858         req = next_request(&dep->request_list);
 859         dep = dwc->eps[event->endpoint_number];
 860
 861         __dwc3_ep0_do_control_data(dwc, dep, req);
 862 }
 863
 864 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 865 {
 866         struct dwc3             *dwc = dep->dwc;
 867         u32                     type;
 868
 869         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 870                 : DWC3_TRBCTL_CONTROL_STATUS2;
 871
 872         return dwc3_ep0_start_trans(dwc, dep->number,
 873                         dwc->ctrl_req_addr, 0, type);
 874 }
 875
 876 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
 877 {
 878         if (dwc->resize_fifos) {
 879                 dev_dbg(dwc->dev, "starting to resize fifos\n");
 880                 dwc3_gadget_resize_tx_fifos(dwc);
 881                 dwc->resize_fifos = 0;
 882         }
 883
 884         WARN_ON(dwc3_ep0_start_control_status(dep));
 885 }
 886
 887 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
 888                 const struct dwc3_event_depevt *event)
 889 {
 890         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 891
 892         __dwc3_ep0_do_control_status(dwc, dep);
 893 }
 894
 895 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 896                 const struct dwc3_event_depevt *event)
 897 {
 898         dwc->setup_packet_pending = true;
 899
 900         /*
 901          * This part is very tricky: If we have just handled
 902          * XferNotReady(Setup) and we're now expecting a
 903          * XferComplete but, instead, we receive another
 904          * XferNotReady(Setup), we should STALL and restart
 905          * the state machine.
 906          *
 907          * In all other cases, we just continue waiting
 908          * for the XferComplete event.
 909          *
 910          * We are a little bit unsafe here because we're
 911          * not trying to ensure that last event was, indeed,
 912          * XferNotReady(Setup).
 913          *
 914          * Still, we don't expect any condition where that
 915          * should happen and, even if it does, it would be
 916          * another error condition.
 917          */
 918         if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
 919                 switch (event->status) {
 920                 case DEPEVT_STATUS_CONTROL_SETUP:
 921                         dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
 922                         dwc3_ep0_stall_and_restart(dwc);
 923                         break;
 924                 case DEPEVT_STATUS_CONTROL_DATA:
 925                         /* FALLTHROUGH */
 926                 case DEPEVT_STATUS_CONTROL_STATUS:
 927                         /* FALLTHROUGH */
 928                 default:
 929                         dev_vdbg(dwc->dev, "waiting for XferComplete\n");
 930                 }
 931
 932                 return;
 933         }
 934
 935         switch (event->status) {
 936         case DEPEVT_STATUS_CONTROL_SETUP:
 937                 dev_vdbg(dwc->dev, "Control Setup\n");
 938
 939                 dwc->ep0state = EP0_SETUP_PHASE;
 940
 941                 dwc3_ep0_do_control_setup(dwc, event);
 942                 break;
 943
 944         case DEPEVT_STATUS_CONTROL_DATA:
 945                 dev_vdbg(dwc->dev, "Control Data\n");
 946
 947                 dwc->ep0state = EP0_DATA_PHASE;
 948
 949                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 950                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 951                                         dwc->ep0_next_event,
 952                                         DWC3_EP0_NRDY_DATA);
 953
 954                         dwc3_ep0_stall_and_restart(dwc);
 955                         return;
 956                 }
 957
 958                 /*
 959                  * One of the possible error cases is when Host _does_
 960                  * request for Data Phase, but it does so on the wrong
 961                  * direction.
 962                  *
 963                  * Here, we already know ep0_next_event is DATA (see above),
 964                  * so we only need to check for direction.
 965                  */
 966                 if (dwc->ep0_expect_in != event->endpoint_number) {
 967                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 968                         dwc3_ep0_stall_and_restart(dwc);
 969                         return;
 970                 }
 971
 972                 dwc3_ep0_do_control_data(dwc, event);
 973                 break;
 974
 975         case DEPEVT_STATUS_CONTROL_STATUS:
 976                 dev_vdbg(dwc->dev, "Control Status\n");
 977
 978                 dwc->ep0state = EP0_STATUS_PHASE;
 979
 980                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 981                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 982                                         dwc->ep0_next_event,
 983                                         DWC3_EP0_NRDY_STATUS);
 984
 985                         dwc3_ep0_stall_and_restart(dwc);
 986                         return;
 987                 }
 988
 989                 if (dwc->delayed_status) {
 990                         WARN_ON_ONCE(event->endpoint_number != 1);
 991                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
 992                         return;
 993                 }
 994
 995                 dwc3_ep0_do_control_status(dwc, event);
 996         }
 997 }
 998
 999 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1000                 const struct dwc3_event_depevt *event)
1001 {
1002         u8                      epnum = event->endpoint_number;
1003
1004         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1005                         dwc3_ep_event_string(event->endpoint_event),
1006                         epnum >> 1, (epnum & 1) ? "in" : "out",
1007                         dwc3_ep0_state_string(dwc->ep0state));
1008
1009         switch (event->endpoint_event) {
1010         case DWC3_DEPEVT_XFERCOMPLETE:
1011                 dwc3_ep0_xfer_complete(dwc, event);
1012                 break;
1013
1014         case DWC3_DEPEVT_XFERNOTREADY:
1015                 dwc3_ep0_xfernotready(dwc, event);
1016                 break;
1017
1018         case DWC3_DEPEVT_XFERINPROGRESS:
1019         case DWC3_DEPEVT_RXTXFIFOEVT:
1020         case DWC3_DEPEVT_STREAMEVT:
1021         case DWC3_DEPEVT_EPCMDCMPLT:
1022                 break;
1023         }
1024 }