Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/io.h>
  46 #include <linux/list.h>
  47 #include <linux/dma-mapping.h>
  48
  49 #include <linux/usb/ch9.h>
  50 #include <linux/usb/gadget.h>
  51 #include <linux/usb/composite.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum);
  58
  59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  60 {
  61         switch (state) {
  62         case EP0_UNCONNECTED:
  63                 return "Unconnected";
  64         case EP0_SETUP_PHASE:
  65                 return "Setup Phase";
  66         case EP0_DATA_PHASE:
  67                 return "Data Phase";
  68         case EP0_STATUS_PHASE:
  69                 return "Status Phase";
  70         default:
  71                 return "UNKNOWN";
  72         }
  73 }
  74
  75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  76                 u32 len, u32 type)
  77 {
  78         struct dwc3_gadget_ep_cmd_params params;
  79         struct dwc3_trb                 *trb;
  80         struct dwc3_ep                  *dep;
  81
  82         int                             ret;
  83
  84         dep = dwc->eps[epnum];
  85         if (dep->flags & DWC3_EP_BUSY) {
  86                 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
  87                 return 0;
  88         }
  89
  90         trb = dwc->ep0_trb;
  91
  92         trb->bpl = lower_32_bits(buf_dma);
  93         trb->bph = upper_32_bits(buf_dma);
  94         trb->size = len;
  95         trb->ctrl = type;
  96
  97         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  98                         | DWC3_TRB_CTRL_LST
  99                         | DWC3_TRB_CTRL_IOC
 100                         | DWC3_TRB_CTRL_ISP_IMI);
 101
 102         memset(&params, 0, sizeof(params));
 103         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 104         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 105
 106         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 107                         DWC3_DEPCMD_STARTTRANSFER, &params);
 108         if (ret < 0) {
 109                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 110                 return ret;
 111         }
 112
 113         dep->flags |= DWC3_EP_BUSY;
 114         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 115                         dep->number);
 116
 117         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 118
 119         return 0;
 120 }
 121
 122 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 123                 struct dwc3_request *req)
 124 {
 125         struct dwc3             *dwc = dep->dwc;
 126         int                     ret = 0;
 127
 128         req->request.actual     = 0;
 129         req->request.status     = -EINPROGRESS;
 130         req->epnum              = dep->number;
 131
 132         list_add_tail(&req->list, &dep->request_list);
 133
 134         /*
 135          * Gadget driver might not be quick enough to queue a request
 136          * before we get a Transfer Not Ready event on this endpoint.
 137          *
 138          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 139          * flag is set, it's telling us that as soon as Gadget queues the
 140          * required request, we should kick the transfer here because the
 141          * IRQ we were waiting for is long gone.
 142          */
 143         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 144                 unsigned        direction;
 145
 146                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 147
 148                 if (dwc->ep0state != EP0_DATA_PHASE) {
 149                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 150                         return 0;
 151                 }
 152
 153                 ret = dwc3_ep0_start_trans(dwc, direction,
 154                                 req->request.dma, req->request.length,
 155                                 DWC3_TRBCTL_CONTROL_DATA);
 156                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 157                                 DWC3_EP0_DIR_IN);
 158         } else if (dwc->delayed_status) {
 159                 dwc->delayed_status = false;
 160
 161                 if (dwc->ep0state == EP0_STATUS_PHASE)
 162                         dwc3_ep0_do_control_status(dwc, 1);
 163                 else
 164                         dev_dbg(dwc->dev, "too early for delayed status\n");
 165         }
 166
 167         return ret;
 168 }
 169
 170 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 171                 gfp_t gfp_flags)
 172 {
 173         struct dwc3_request             *req = to_dwc3_request(request);
 174         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 175         struct dwc3                     *dwc = dep->dwc;
 176
 177         unsigned long                   flags;
 178
 179         int                             ret;
 180
 181         spin_lock_irqsave(&dwc->lock, flags);
 182         if (!dep->desc) {
 183                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
 184                                 request, dep->name);
 185                 ret = -ESHUTDOWN;
 186                 goto out;
 187         }
 188
 189         /* we share one TRB for ep0/1 */
 190         if (!list_empty(&dep->request_list)) {
 191                 ret = -EBUSY;
 192                 goto out;
 193         }
 194
 195         dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
 196                         request, dep->name, request->length,
 197                         dwc3_ep0_state_string(dwc->ep0state));
 198
 199         ret = __dwc3_gadget_ep0_queue(dep, req);
 200
 201 out:
 202         spin_unlock_irqrestore(&dwc->lock, flags);
 203
 204         return ret;
 205 }
 206
 207 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 208 {
 209         struct dwc3_ep          *dep = dwc->eps[0];
 210
 211         /* stall is always issued on EP0 */
 212         __dwc3_gadget_ep_set_halt(dep, 1);
 213         dep->flags = DWC3_EP_ENABLED;
 214         dwc->delayed_status = false;
 215
 216         if (!list_empty(&dep->request_list)) {
 217                 struct dwc3_request     *req;
 218
 219                 req = next_request(&dep->request_list);
 220                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 221         }
 222
 223         dwc->ep0state = EP0_SETUP_PHASE;
 224         dwc3_ep0_out_start(dwc);
 225 }
 226
 227 void dwc3_ep0_out_start(struct dwc3 *dwc)
 228 {
 229         int                             ret;
 230
 231         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 232                         DWC3_TRBCTL_CONTROL_SETUP);
 233         WARN_ON(ret < 0);
 234 }
 235
 236 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 237 {
 238         struct dwc3_ep          *dep;
 239         u32                     windex = le16_to_cpu(wIndex_le);
 240         u32                     epnum;
 241
 242         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 243         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 244                 epnum |= 1;
 245
 246         dep = dwc->eps[epnum];
 247         if (dep->flags & DWC3_EP_ENABLED)
 248                 return dep;
 249
 250         return NULL;
 251 }
 252
 253 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 254 {
 255 }
 256 /*
 257  * ch 9.4.5
 258  */
 259 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 260                 struct usb_ctrlrequest *ctrl)
 261 {
 262         struct dwc3_ep          *dep;
 263         u32                     recip;
 264         u16                     usb_status = 0;
 265         __le16                  *response_pkt;
 266
 267         recip = ctrl->bRequestType & USB_RECIP_MASK;
 268         switch (recip) {
 269         case USB_RECIP_DEVICE:
 270                 /*
 271                  * We are self-powered. U1/U2/LTM will be set later
 272                  * once we handle this states. RemoteWakeup is 0 on SS
 273                  */
 274                 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
 275                 break;
 276
 277         case USB_RECIP_INTERFACE:
 278                 /*
 279                  * Function Remote Wake Capable D0
 280                  * Function Remote Wakeup       D1
 281                  */
 282                 break;
 283
 284         case USB_RECIP_ENDPOINT:
 285                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 286                 if (!dep)
 287                         return -EINVAL;
 288
 289                 if (dep->flags & DWC3_EP_STALL)
 290                         usb_status = 1 << USB_ENDPOINT_HALT;
 291                 break;
 292         default:
 293                 return -EINVAL;
 294         };
 295
 296         response_pkt = (__le16 *) dwc->setup_buf;
 297         *response_pkt = cpu_to_le16(usb_status);
 298
 299         dep = dwc->eps[0];
 300         dwc->ep0_usb_req.dep = dep;
 301         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 302         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 303         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 304
 305         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 306 }
 307
 308 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 309                 struct usb_ctrlrequest *ctrl, int set)
 310 {
 311         struct dwc3_ep          *dep;
 312         u32                     recip;
 313         u32                     wValue;
 314         u32                     wIndex;
 315         int                     ret;
 316
 317         wValue = le16_to_cpu(ctrl->wValue);
 318         wIndex = le16_to_cpu(ctrl->wIndex);
 319         recip = ctrl->bRequestType & USB_RECIP_MASK;
 320         switch (recip) {
 321         case USB_RECIP_DEVICE:
 322
 323                 /*
 324                  * 9.4.1 says only only for SS, in AddressState only for
 325                  * default control pipe
 326                  */
 327                 switch (wValue) {
 328                 case USB_DEVICE_U1_ENABLE:
 329                 case USB_DEVICE_U2_ENABLE:
 330                 case USB_DEVICE_LTM_ENABLE:
 331                         if (dwc->dev_state != DWC3_CONFIGURED_STATE)
 332                                 return -EINVAL;
 333                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 334                                 return -EINVAL;
 335                 }
 336
 337                 /* XXX add U[12] & LTM */
 338                 switch (wValue) {
 339                 case USB_DEVICE_REMOTE_WAKEUP:
 340                         break;
 341                 case USB_DEVICE_U1_ENABLE:
 342                         break;
 343                 case USB_DEVICE_U2_ENABLE:
 344                         break;
 345                 case USB_DEVICE_LTM_ENABLE:
 346                         break;
 347
 348                 case USB_DEVICE_TEST_MODE:
 349                         if ((wIndex & 0xff) != 0)
 350                                 return -EINVAL;
 351                         if (!set)
 352                                 return -EINVAL;
 353
 354                         dwc->test_mode_nr = wIndex >> 8;
 355                         dwc->test_mode = true;
 356                 }
 357                 break;
 358
 359         case USB_RECIP_INTERFACE:
 360                 switch (wValue) {
 361                 case USB_INTRF_FUNC_SUSPEND:
 362                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 363                                 /* XXX enable Low power suspend */
 364                                 ;
 365                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 366                                 /* XXX enable remote wakeup */
 367                                 ;
 368                         break;
 369                 default:
 370                         return -EINVAL;
 371                 }
 372                 break;
 373
 374         case USB_RECIP_ENDPOINT:
 375                 switch (wValue) {
 376                 case USB_ENDPOINT_HALT:
 377                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 378                         if (!dep)
 379                                 return -EINVAL;
 380                         ret = __dwc3_gadget_ep_set_halt(dep, set);
 381                         if (ret)
 382                                 return -EINVAL;
 383                         break;
 384                 default:
 385                         return -EINVAL;
 386                 }
 387                 break;
 388
 389         default:
 390                 return -EINVAL;
 391         };
 392
 393         return 0;
 394 }
 395
 396 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 397 {
 398         u32 addr;
 399         u32 reg;
 400
 401         addr = le16_to_cpu(ctrl->wValue);
 402         if (addr > 127) {
 403                 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
 404                 return -EINVAL;
 405         }
 406
 407         if (dwc->dev_state == DWC3_CONFIGURED_STATE) {
 408                 dev_dbg(dwc->dev, "trying to set address when configured\n");
 409                 return -EINVAL;
 410         }
 411
 412         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 413         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 414         reg |= DWC3_DCFG_DEVADDR(addr);
 415         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 416
 417         if (addr)
 418                 dwc->dev_state = DWC3_ADDRESS_STATE;
 419         else
 420                 dwc->dev_state = DWC3_DEFAULT_STATE;
 421
 422         return 0;
 423 }
 424
 425 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 426 {
 427         int ret;
 428
 429         spin_unlock(&dwc->lock);
 430         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 431         spin_lock(&dwc->lock);
 432         return ret;
 433 }
 434
 435 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 436 {
 437         u32 cfg;
 438         int ret;
 439
 440         dwc->start_config_issued = false;
 441         cfg = le16_to_cpu(ctrl->wValue);
 442
 443         switch (dwc->dev_state) {
 444         case DWC3_DEFAULT_STATE:
 445                 return -EINVAL;
 446                 break;
 447
 448         case DWC3_ADDRESS_STATE:
 449                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 450                 /* if the cfg matches and the cfg is non zero */
 451                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 452                         dwc->dev_state = DWC3_CONFIGURED_STATE;
 453                         dwc->resize_fifos = true;
 454                         dev_dbg(dwc->dev, "resize fifos flag SET\n");
 455                 }
 456                 break;
 457
 458         case DWC3_CONFIGURED_STATE:
 459                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 460                 if (!cfg)
 461                         dwc->dev_state = DWC3_ADDRESS_STATE;
 462                 break;
 463         default:
 464                 ret = -EINVAL;
 465         }
 466         return ret;
 467 }
 468
 469 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 470 {
 471         int ret;
 472
 473         switch (ctrl->bRequest) {
 474         case USB_REQ_GET_STATUS:
 475                 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
 476                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 477                 break;
 478         case USB_REQ_CLEAR_FEATURE:
 479                 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
 480                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 481                 break;
 482         case USB_REQ_SET_FEATURE:
 483                 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
 484                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 485                 break;
 486         case USB_REQ_SET_ADDRESS:
 487                 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
 488                 ret = dwc3_ep0_set_address(dwc, ctrl);
 489                 break;
 490         case USB_REQ_SET_CONFIGURATION:
 491                 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
 492                 ret = dwc3_ep0_set_config(dwc, ctrl);
 493                 break;
 494         default:
 495                 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
 496                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 497                 break;
 498         };
 499
 500         return ret;
 501 }
 502
 503 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 504                 const struct dwc3_event_depevt *event)
 505 {
 506         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 507         int ret;
 508         u32 len;
 509
 510         if (!dwc->gadget_driver)
 511                 goto err;
 512
 513         len = le16_to_cpu(ctrl->wLength);
 514         if (!len) {
 515                 dwc->three_stage_setup = false;
 516                 dwc->ep0_expect_in = false;
 517                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 518         } else {
 519                 dwc->three_stage_setup = true;
 520                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 521                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 522         }
 523
 524         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 525                 ret = dwc3_ep0_std_request(dwc, ctrl);
 526         else
 527                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 528
 529         if (ret == USB_GADGET_DELAYED_STATUS)
 530                 dwc->delayed_status = true;
 531
 532         if (ret >= 0)
 533                 return;
 534
 535 err:
 536         dwc3_ep0_stall_and_restart(dwc);
 537 }
 538
 539 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 540                 const struct dwc3_event_depevt *event)
 541 {
 542         struct dwc3_request     *r = NULL;
 543         struct usb_request      *ur;
 544         struct dwc3_trb         *trb;
 545         struct dwc3_ep          *ep0;
 546         u32                     transferred;
 547         u32                     length;
 548         u8                      epnum;
 549
 550         epnum = event->endpoint_number;
 551         ep0 = dwc->eps[0];
 552
 553         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 554
 555         r = next_request(&ep0->request_list);
 556         ur = &r->request;
 557
 558         trb = dwc->ep0_trb;
 559         length = trb->size & DWC3_TRB_SIZE_MASK;
 560
 561         if (dwc->ep0_bounced) {
 562                 transferred = min_t(u32, ur->length,
 563                                 ep0->endpoint.maxpacket - length);
 564                 memcpy(ur->buf, dwc->ep0_bounce, transferred);
 565                 dwc->ep0_bounced = false;
 566         } else {
 567                 transferred = ur->length - length;
 568                 ur->actual += transferred;
 569         }
 570
 571         if ((epnum & 1) && ur->actual < ur->length) {
 572                 /* for some reason we did not get everything out */
 573
 574                 dwc3_ep0_stall_and_restart(dwc);
 575         } else {
 576                 /*
 577                  * handle the case where we have to send a zero packet. This
 578                  * seems to be case when req.length > maxpacket. Could it be?
 579                  */
 580                 if (r)
 581                         dwc3_gadget_giveback(ep0, r, 0);
 582         }
 583 }
 584
 585 static void dwc3_ep0_complete_req(struct dwc3 *dwc,
 586                 const struct dwc3_event_depevt *event)
 587 {
 588         struct dwc3_request     *r;
 589         struct dwc3_ep          *dep;
 590
 591         dep = dwc->eps[0];
 592
 593         if (!list_empty(&dep->request_list)) {
 594                 r = next_request(&dep->request_list);
 595
 596                 dwc3_gadget_giveback(dep, r, 0);
 597         }
 598
 599         if (dwc->test_mode) {
 600                 int ret;
 601
 602                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 603                 if (ret < 0) {
 604                         dev_dbg(dwc->dev, "Invalid Test #%d\n",
 605                                         dwc->test_mode_nr);
 606                         dwc3_ep0_stall_and_restart(dwc);
 607                 }
 608         }
 609
 610         dwc->ep0state = EP0_SETUP_PHASE;
 611         dwc3_ep0_out_start(dwc);
 612 }
 613
 614 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 615                         const struct dwc3_event_depevt *event)
 616 {
 617         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 618
 619         dep->flags &= ~DWC3_EP_BUSY;
 620         dep->res_trans_idx = 0;
 621         dwc->setup_packet_pending = false;
 622
 623         switch (dwc->ep0state) {
 624         case EP0_SETUP_PHASE:
 625                 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
 626                 dwc3_ep0_inspect_setup(dwc, event);
 627                 break;
 628
 629         case EP0_DATA_PHASE:
 630                 dev_vdbg(dwc->dev, "Data Phase\n");
 631                 dwc3_ep0_complete_data(dwc, event);
 632                 break;
 633
 634         case EP0_STATUS_PHASE:
 635                 dev_vdbg(dwc->dev, "Status Phase\n");
 636                 dwc3_ep0_complete_req(dwc, event);
 637                 break;
 638         default:
 639                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 640         }
 641 }
 642
 643 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc,
 644                 const struct dwc3_event_depevt *event)
 645 {
 646         dwc3_ep0_out_start(dwc);
 647 }
 648
 649 static void dwc3_ep0_do_control_data(struct dwc3 *dwc,
 650                 const struct dwc3_event_depevt *event)
 651 {
 652         struct dwc3_ep          *dep;
 653         struct dwc3_request     *req;
 654         int                     ret;
 655
 656         dep = dwc->eps[0];
 657
 658         if (list_empty(&dep->request_list)) {
 659                 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n");
 660                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 661
 662                 if (event->endpoint_number)
 663                         dep->flags |= DWC3_EP0_DIR_IN;
 664                 return;
 665         }
 666
 667         req = next_request(&dep->request_list);
 668         req->direction = !!event->endpoint_number;
 669
 670         if (req->request.length == 0) {
 671                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 672                                 dwc->ctrl_req_addr, 0,
 673                                 DWC3_TRBCTL_CONTROL_DATA);
 674         } else if ((req->request.length % dep->endpoint.maxpacket)
 675                         && (event->endpoint_number == 0)) {
 676                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 677                                 event->endpoint_number);
 678                 if (ret) {
 679                         dev_dbg(dwc->dev, "failed to map request\n");
 680                         return;
 681                 }
 682
 683                 WARN_ON(req->request.length > dep->endpoint.maxpacket);
 684
 685                 dwc->ep0_bounced = true;
 686
 687                 /*
 688                  * REVISIT in case request length is bigger than EP0
 689                  * wMaxPacketSize, we will need two chained TRBs to handle
 690                  * the transfer.
 691                  */
 692                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 693                                 dwc->ep0_bounce_addr, dep->endpoint.maxpacket,
 694                                 DWC3_TRBCTL_CONTROL_DATA);
 695         } else {
 696                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 697                                 event->endpoint_number);
 698                 if (ret) {
 699                         dev_dbg(dwc->dev, "failed to map request\n");
 700                         return;
 701                 }
 702
 703                 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number,
 704                                 req->request.dma, req->request.length,
 705                                 DWC3_TRBCTL_CONTROL_DATA);
 706         }
 707
 708         WARN_ON(ret < 0);
 709 }
 710
 711 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
 712 {
 713         struct dwc3             *dwc = dep->dwc;
 714         u32                     type;
 715
 716         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
 717                 : DWC3_TRBCTL_CONTROL_STATUS2;
 718
 719         return dwc3_ep0_start_trans(dwc, dep->number,
 720                         dwc->ctrl_req_addr, 0, type);
 721 }
 722
 723 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum)
 724 {
 725         struct dwc3_ep          *dep = dwc->eps[epnum];
 726
 727         if (dwc->resize_fifos) {
 728                 dev_dbg(dwc->dev, "starting to resize fifos\n");
 729                 dwc3_gadget_resize_tx_fifos(dwc);
 730                 dwc->resize_fifos = 0;
 731         }
 732
 733         WARN_ON(dwc3_ep0_start_control_status(dep));
 734 }
 735
 736 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
 737                 const struct dwc3_event_depevt *event)
 738 {
 739         dwc->setup_packet_pending = true;
 740
 741         /*
 742          * This part is very tricky: If we has just handled
 743          * XferNotReady(Setup) and we're now expecting a
 744          * XferComplete but, instead, we receive another
 745          * XferNotReady(Setup), we should STALL and restart
 746          * the state machine.
 747          *
 748          * In all other cases, we just continue waiting
 749          * for the XferComplete event.
 750          *
 751          * We are a little bit unsafe here because we're
 752          * not trying to ensure that last event was, indeed,
 753          * XferNotReady(Setup).
 754          *
 755          * Still, we don't expect any condition where that
 756          * should happen and, even if it does, it would be
 757          * another error condition.
 758          */
 759         if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) {
 760                 switch (event->status) {
 761                 case DEPEVT_STATUS_CONTROL_SETUP:
 762                         dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n");
 763                         dwc3_ep0_stall_and_restart(dwc);
 764                         break;
 765                 case DEPEVT_STATUS_CONTROL_DATA:
 766                         /* FALLTHROUGH */
 767                 case DEPEVT_STATUS_CONTROL_STATUS:
 768                         /* FALLTHROUGH */
 769                 default:
 770                         dev_vdbg(dwc->dev, "waiting for XferComplete\n");
 771                 }
 772
 773                 return;
 774         }
 775
 776         switch (event->status) {
 777         case DEPEVT_STATUS_CONTROL_SETUP:
 778                 dev_vdbg(dwc->dev, "Control Setup\n");
 779
 780                 dwc->ep0state = EP0_SETUP_PHASE;
 781
 782                 dwc3_ep0_do_control_setup(dwc, event);
 783                 break;
 784
 785         case DEPEVT_STATUS_CONTROL_DATA:
 786                 dev_vdbg(dwc->dev, "Control Data\n");
 787
 788                 dwc->ep0state = EP0_DATA_PHASE;
 789
 790                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) {
 791                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 792                                         dwc->ep0_next_event,
 793                                         DWC3_EP0_NRDY_DATA);
 794
 795                         dwc3_ep0_stall_and_restart(dwc);
 796                         return;
 797                 }
 798
 799                 /*
 800                  * One of the possible error cases is when Host _does_
 801                  * request for Data Phase, but it does so on the wrong
 802                  * direction.
 803                  *
 804                  * Here, we already know ep0_next_event is DATA (see above),
 805                  * so we only need to check for direction.
 806                  */
 807                 if (dwc->ep0_expect_in != event->endpoint_number) {
 808                         dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
 809                         dwc3_ep0_stall_and_restart(dwc);
 810                         return;
 811                 }
 812
 813                 dwc3_ep0_do_control_data(dwc, event);
 814                 break;
 815
 816         case DEPEVT_STATUS_CONTROL_STATUS:
 817                 dev_vdbg(dwc->dev, "Control Status\n");
 818
 819                 dwc->ep0state = EP0_STATUS_PHASE;
 820
 821                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) {
 822                         dev_vdbg(dwc->dev, "Expected %d got %d\n",
 823                                         dwc->ep0_next_event,
 824                                         DWC3_EP0_NRDY_STATUS);
 825
 826                         dwc3_ep0_stall_and_restart(dwc);
 827                         return;
 828                 }
 829
 830                 if (dwc->delayed_status) {
 831                         WARN_ON_ONCE(event->endpoint_number != 1);
 832                         dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
 833                         return;
 834                 }
 835
 836                 dwc3_ep0_do_control_status(dwc, event->endpoint_number);
 837         }
 838 }
 839
 840 void dwc3_ep0_interrupt(struct dwc3 *dwc,
 841                 const struct dwc3_event_depevt *event)
 842 {
 843         u8                      epnum = event->endpoint_number;
 844
 845         dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
 846                         dwc3_ep_event_string(event->endpoint_event),
 847                         epnum >> 1, (epnum & 1) ? "in" : "out",
 848                         dwc3_ep0_state_string(dwc->ep0state));
 849
 850         switch (event->endpoint_event) {
 851         case DWC3_DEPEVT_XFERCOMPLETE:
 852                 dwc3_ep0_xfer_complete(dwc, event);
 853                 break;
 854
 855         case DWC3_DEPEVT_XFERNOTREADY:
 856                 dwc3_ep0_xfernotready(dwc, event);
 857                 break;
 858
 859         case DWC3_DEPEVT_XFERINPROGRESS:
 860         case DWC3_DEPEVT_RXTXFIFOEVT:
 861         case DWC3_DEPEVT_STREAMEVT:
 862         case DWC3_DEPEVT_EPCMDCMPLT:
 863                 break;
 864         }
 865 }