Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/dwc3-omap.c

   1 /**
   2  * dwc3-omap.c - OMAP Specific Glue layer
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/platform_data/dwc3-omap.h>
  46 #include <linux/pm_runtime.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/ioport.h>
  49 #include <linux/io.h>
  50 #include <linux/of.h>
  51 #include <linux/of_platform.h>
  52 #include <linux/extcon.h>
  53 #include <linux/extcon/of_extcon.h>
  54 #include <linux/regulator/consumer.h>
  55
  56 #include <linux/usb/otg.h>
  57
  58 /*
  59  * All these registers belong to OMAP's Wrapper around the
  60  * DesignWare USB3 Core.
  61  */
  62
  63 #define USBOTGSS_REVISION                       0x0000
  64 #define USBOTGSS_SYSCONFIG                      0x0010
  65 #define USBOTGSS_IRQ_EOI                        0x0020
  66 #define USBOTGSS_EOI_OFFSET                     0x0008
  67 #define USBOTGSS_IRQSTATUS_RAW_0                0x0024
  68 #define USBOTGSS_IRQSTATUS_0                    0x0028
  69 #define USBOTGSS_IRQENABLE_SET_0                0x002c
  70 #define USBOTGSS_IRQENABLE_CLR_0                0x0030
  71 #define USBOTGSS_IRQ0_OFFSET                    0x0004
  72 #define USBOTGSS_IRQSTATUS_RAW_1                0x0030
  73 #define USBOTGSS_IRQSTATUS_1                    0x0034
  74 #define USBOTGSS_IRQENABLE_SET_1                0x0038
  75 #define USBOTGSS_IRQENABLE_CLR_1                0x003c
  76 #define USBOTGSS_IRQSTATUS_RAW_2                0x0040
  77 #define USBOTGSS_IRQSTATUS_2                    0x0044
  78 #define USBOTGSS_IRQENABLE_SET_2                0x0048
  79 #define USBOTGSS_IRQENABLE_CLR_2                0x004c
  80 #define USBOTGSS_IRQSTATUS_RAW_3                0x0050
  81 #define USBOTGSS_IRQSTATUS_3                    0x0054
  82 #define USBOTGSS_IRQENABLE_SET_3                0x0058
  83 #define USBOTGSS_IRQENABLE_CLR_3                0x005c
  84 #define USBOTGSS_IRQSTATUS_EOI_MISC             0x0030
  85 #define USBOTGSS_IRQSTATUS_RAW_MISC             0x0034
  86 #define USBOTGSS_IRQSTATUS_MISC                 0x0038
  87 #define USBOTGSS_IRQENABLE_SET_MISC             0x003c
  88 #define USBOTGSS_IRQENABLE_CLR_MISC             0x0040
  89 #define USBOTGSS_IRQMISC_OFFSET                 0x03fc
  90 #define USBOTGSS_UTMI_OTG_CTRL                  0x0080
  91 #define USBOTGSS_UTMI_OTG_STATUS                0x0084
  92 #define USBOTGSS_UTMI_OTG_OFFSET                0x0480
  93 #define USBOTGSS_TXFIFO_DEPTH                   0x0508
  94 #define USBOTGSS_RXFIFO_DEPTH                   0x050c
  95 #define USBOTGSS_MMRAM_OFFSET                   0x0100
  96 #define USBOTGSS_FLADJ                          0x0104
  97 #define USBOTGSS_DEBUG_CFG                      0x0108
  98 #define USBOTGSS_DEBUG_DATA                     0x010c
  99 #define USBOTGSS_DEV_EBC_EN                     0x0110
 100 #define USBOTGSS_DEBUG_OFFSET                   0x0600
 101
 102 /* REVISION REGISTER */
 103 #define USBOTGSS_REVISION_XMAJOR(reg)           ((reg >> 8) & 0x7)
 104 #define USBOTGSS_REVISION_XMAJOR1               1
 105 #define USBOTGSS_REVISION_XMAJOR2               2
 106 /* SYSCONFIG REGISTER */
 107 #define USBOTGSS_SYSCONFIG_DMADISABLE           (1 << 16)
 108
 109 /* IRQ_EOI REGISTER */
 110 #define USBOTGSS_IRQ_EOI_LINE_NUMBER            (1 << 0)
 111
 112 /* IRQS0 BITS */
 113 #define USBOTGSS_IRQO_COREIRQ_ST                (1 << 0)
 114
 115 /* IRQMISC BITS */
 116 #define USBOTGSS_IRQMISC_DMADISABLECLR          (1 << 17)
 117 #define USBOTGSS_IRQMISC_OEVT                   (1 << 16)
 118 #define USBOTGSS_IRQMISC_DRVVBUS_RISE           (1 << 13)
 119 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE          (1 << 12)
 120 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE       (1 << 11)
 121 #define USBOTGSS_IRQMISC_IDPULLUP_RISE          (1 << 8)
 122 #define USBOTGSS_IRQMISC_DRVVBUS_FALL           (1 << 5)
 123 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL          (1 << 4)
 124 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL               (1 << 3)
 125 #define USBOTGSS_IRQMISC_IDPULLUP_FALL          (1 << 0)
 126
 127 /* UTMI_OTG_CTRL REGISTER */
 128 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS          (1 << 5)
 129 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS         (1 << 4)
 130 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS      (1 << 3)
 131 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP         (1 << 0)
 132
 133 /* UTMI_OTG_STATUS REGISTER */
 134 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE        (1 << 31)
 135 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT   (1 << 9)
 136 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
 137 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG          (1 << 4)
 138 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND        (1 << 3)
 139 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID      (1 << 2)
 140 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID      (1 << 1)
 141
 142 struct dwc3_omap {
 143         /* device lock */
 144         spinlock_t              lock;
 145
 146         struct device           *dev;
 147
 148         int                     irq;
 149         void __iomem            *base;
 150
 151         u32                     utmi_otg_status;
 152         u32                     utmi_otg_offset;
 153         u32                     irqmisc_offset;
 154         u32                     irq_eoi_offset;
 155         u32                     debug_offset;
 156         u32                     irq0_offset;
 157         u32                     revision;
 158
 159         u32                     dma_status:1;
 160
 161         struct extcon_specific_cable_nb extcon_vbus_dev;
 162         struct extcon_specific_cable_nb extcon_id_dev;
 163         struct notifier_block   vbus_nb;
 164         struct notifier_block   id_nb;
 165
 166         struct regulator        *vbus_reg;
 167 };
 168
 169 enum omap_dwc3_vbus_id_status {
 170         OMAP_DWC3_ID_FLOAT,
 171         OMAP_DWC3_ID_GROUND,
 172         OMAP_DWC3_VBUS_OFF,
 173         OMAP_DWC3_VBUS_VALID,
 174 };
 175
 176 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
 177 {
 178         return readl(base + offset);
 179 }
 180
 181 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
 182 {
 183         writel(value, base + offset);
 184 }
 185
 186 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
 187 {
 188         return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 189                                                         omap->utmi_otg_offset);
 190 }
 191
 192 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
 193 {
 194         dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
 195                                         omap->utmi_otg_offset, value);
 196
 197 }
 198
 199 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
 200 {
 201         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
 202                                                 omap->irq0_offset);
 203 }
 204
 205 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
 206 {
 207         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
 208                                                 omap->irq0_offset, value);
 209
 210 }
 211
 212 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
 213 {
 214         return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
 215                                                 omap->irqmisc_offset);
 216 }
 217
 218 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
 219 {
 220         dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
 221                                         omap->irqmisc_offset, value);
 222
 223 }
 224
 225 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
 226 {
 227         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
 228                                                 omap->irqmisc_offset, value);
 229
 230 }
 231
 232 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
 233 {
 234         dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
 235                                                 omap->irq0_offset, value);
 236 }
 237
 238 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
 239         enum omap_dwc3_vbus_id_status status)
 240 {
 241         int     ret;
 242         u32     val;
 243
 244         switch (status) {
 245         case OMAP_DWC3_ID_GROUND:
 246                 dev_dbg(omap->dev, "ID GND\n");
 247
 248                 if (omap->vbus_reg) {
 249                         ret = regulator_enable(omap->vbus_reg);
 250                         if (ret) {
 251                                 dev_dbg(omap->dev, "regulator enable failed\n");
 252                                 return;
 253                         }
 254                 }
 255
 256                 val = dwc3_omap_read_utmi_status(omap);
 257                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
 258                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 259                                 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
 260                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 261                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 262                 dwc3_omap_write_utmi_status(omap, val);
 263                 break;
 264
 265         case OMAP_DWC3_VBUS_VALID:
 266                 dev_dbg(omap->dev, "VBUS Connect\n");
 267
 268                 val = dwc3_omap_read_utmi_status(omap);
 269                 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
 270                 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
 271                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 272                                 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 273                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
 274                 dwc3_omap_write_utmi_status(omap, val);
 275                 break;
 276
 277         case OMAP_DWC3_ID_FLOAT:
 278                 if (omap->vbus_reg)
 279                         regulator_disable(omap->vbus_reg);
 280
 281         case OMAP_DWC3_VBUS_OFF:
 282                 dev_dbg(omap->dev, "VBUS Disconnect\n");
 283
 284                 val = dwc3_omap_read_utmi_status(omap);
 285                 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
 286                                 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
 287                                 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
 288                 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
 289                                 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
 290                 dwc3_omap_write_utmi_status(omap, val);
 291                 break;
 292
 293         default:
 294                 dev_dbg(omap->dev, "invalid state\n");
 295         }
 296 }
 297
 298 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 299 {
 300         struct dwc3_omap        *omap = _omap;
 301         u32                     reg;
 302
 303         spin_lock(&omap->lock);
 304
 305         reg = dwc3_omap_read_irqmisc_status(omap);
 306
 307         if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
 308                 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
 309                 omap->dma_status = false;
 310         }
 311
 312         if (reg & USBOTGSS_IRQMISC_OEVT)
 313                 dev_dbg(omap->dev, "OTG Event\n");
 314
 315         if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
 316                 dev_dbg(omap->dev, "DRVVBUS Rise\n");
 317
 318         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
 319                 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
 320
 321         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
 322                 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
 323
 324         if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
 325                 dev_dbg(omap->dev, "IDPULLUP Rise\n");
 326
 327         if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
 328                 dev_dbg(omap->dev, "DRVVBUS Fall\n");
 329
 330         if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
 331                 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
 332
 333         if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
 334                 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
 335
 336         if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
 337                 dev_dbg(omap->dev, "IDPULLUP Fall\n");
 338
 339         dwc3_omap_write_irqmisc_status(omap, reg);
 340
 341         reg = dwc3_omap_read_irq0_status(omap);
 342
 343         dwc3_omap_write_irq0_status(omap, reg);
 344
 345         spin_unlock(&omap->lock);
 346
 347         return IRQ_HANDLED;
 348 }
 349
 350 static int dwc3_omap_remove_core(struct device *dev, void *c)
 351 {
 352         struct platform_device *pdev = to_platform_device(dev);
 353
 354         platform_device_unregister(pdev);
 355
 356         return 0;
 357 }
 358
 359 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 360 {
 361         u32                     reg;
 362
 363         /* enable all IRQs */
 364         reg = USBOTGSS_IRQO_COREIRQ_ST;
 365         dwc3_omap_write_irq0_set(omap, reg);
 366
 367         reg = (USBOTGSS_IRQMISC_OEVT |
 368                         USBOTGSS_IRQMISC_DRVVBUS_RISE |
 369                         USBOTGSS_IRQMISC_CHRGVBUS_RISE |
 370                         USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
 371                         USBOTGSS_IRQMISC_IDPULLUP_RISE |
 372                         USBOTGSS_IRQMISC_DRVVBUS_FALL |
 373                         USBOTGSS_IRQMISC_CHRGVBUS_FALL |
 374                         USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
 375                         USBOTGSS_IRQMISC_IDPULLUP_FALL);
 376
 377         dwc3_omap_write_irqmisc_set(omap, reg);
 378 }
 379
 380 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 381 {
 382         /* disable all IRQs */
 383         dwc3_omap_write_irqmisc_set(omap, 0x00);
 384         dwc3_omap_write_irq0_set(omap, 0x00);
 385 }
 386
 387 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
 388
 389 static int dwc3_omap_id_notifier(struct notifier_block *nb,
 390         unsigned long event, void *ptr)
 391 {
 392         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
 393
 394         if (event)
 395                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 396         else
 397                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
 398
 399         return NOTIFY_DONE;
 400 }
 401
 402 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
 403         unsigned long event, void *ptr)
 404 {
 405         struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
 406
 407         if (event)
 408                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 409         else
 410                 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
 411
 412         return NOTIFY_DONE;
 413 }
 414
 415 static int dwc3_omap_probe(struct platform_device *pdev)
 416 {
 417         struct device_node      *node = pdev->dev.of_node;
 418
 419         struct dwc3_omap        *omap;
 420         struct resource         *res;
 421         struct device           *dev = &pdev->dev;
 422         struct extcon_dev       *edev;
 423         struct regulator        *vbus_reg = NULL;
 424
 425         int                     ret = -ENOMEM;
 426         int                     irq;
 427
 428         int                     utmi_mode = 0;
 429         int                     x_major;
 430
 431         u32                     reg;
 432
 433         void __iomem            *base;
 434
 435         if (!node) {
 436                 dev_err(dev, "device node not found\n");
 437                 return -EINVAL;
 438         }
 439
 440         omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
 441         if (!omap) {
 442                 dev_err(dev, "not enough memory\n");
 443                 return -ENOMEM;
 444         }
 445
 446         platform_set_drvdata(pdev, omap);
 447
 448         irq = platform_get_irq(pdev, 0);
 449         if (irq < 0) {
 450                 dev_err(dev, "missing IRQ resource\n");
 451                 return -EINVAL;
 452         }
 453
 454         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 455         if (!res) {
 456                 dev_err(dev, "missing memory base resource\n");
 457                 return -EINVAL;
 458         }
 459
 460         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 461         if (!base) {
 462                 dev_err(dev, "ioremap failed\n");
 463                 return -ENOMEM;
 464         }
 465
 466         if (of_property_read_bool(node, "vbus-supply")) {
 467                 vbus_reg = devm_regulator_get(dev, "vbus");
 468                 if (IS_ERR(vbus_reg)) {
 469                         dev_err(dev, "vbus init failed\n");
 470                         return PTR_ERR(vbus_reg);
 471                 }
 472         }
 473
 474         spin_lock_init(&omap->lock);
 475
 476         omap->dev       = dev;
 477         omap->irq       = irq;
 478         omap->base      = base;
 479         omap->vbus_reg  = vbus_reg;
 480         dev->dma_mask   = &dwc3_omap_dma_mask;
 481
 482         pm_runtime_enable(dev);
 483         ret = pm_runtime_get_sync(dev);
 484         if (ret < 0) {
 485                 dev_err(dev, "get_sync failed with err %d\n", ret);
 486                 goto err0;
 487         }
 488
 489         reg = dwc3_omap_readl(omap->base, USBOTGSS_REVISION);
 490         omap->revision = reg;
 491         x_major = USBOTGSS_REVISION_XMAJOR(reg);
 492
 493         /* Differentiate between OMAP5 and AM437x */
 494         switch (x_major) {
 495         case USBOTGSS_REVISION_XMAJOR1:
 496         case USBOTGSS_REVISION_XMAJOR2:
 497                 omap->irq_eoi_offset = 0;
 498                 omap->irq0_offset = 0;
 499                 omap->irqmisc_offset = 0;
 500                 omap->utmi_otg_offset = 0;
 501                 omap->debug_offset = 0;
 502                 break;
 503         default:
 504                 /* Default to the latest revision */
 505                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 506                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 507                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 508                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 509                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 510                 break;
 511         }
 512
 513         /* For OMAP5(ES2.0) and AM437x x_major is 2 even though there are
 514          * changes in wrapper registers, Using dt compatible for aegis
 515          */
 516
 517         if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
 518                 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
 519                 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
 520                 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
 521                 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
 522                 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
 523         }
 524
 525         reg = dwc3_omap_read_utmi_status(omap);
 526
 527         of_property_read_u32(node, "utmi-mode", &utmi_mode);
 528
 529         switch (utmi_mode) {
 530         case DWC3_OMAP_UTMI_MODE_SW:
 531                 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 532                 break;
 533         case DWC3_OMAP_UTMI_MODE_HW:
 534                 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
 535                 break;
 536         default:
 537                 dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
 538         }
 539
 540         dwc3_omap_write_utmi_status(omap, reg);
 541
 542         /* check the DMA Status */
 543         reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
 544         omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
 545
 546         ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
 547                         "dwc3-omap", omap);
 548         if (ret) {
 549                 dev_err(dev, "failed to request IRQ #%d --> %d\n",
 550                                 omap->irq, ret);
 551                 goto err1;
 552         }
 553
 554         dwc3_omap_enable_irqs(omap);
 555
 556         if (of_property_read_bool(node, "extcon")) {
 557                 edev = of_extcon_get_extcon_dev(dev, 0);
 558                 if (IS_ERR(edev)) {
 559                         dev_vdbg(dev, "couldn't get extcon device\n");
 560                         ret = PTR_ERR(edev);
 561                         goto err2;
 562                 }
 563
 564                 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
 565                 ret = extcon_register_interest(&omap->extcon_vbus_dev,
 566                         edev->name, "USB", &omap->vbus_nb);
 567                 if (ret < 0)
 568                         dev_vdbg(dev, "failed to register notifier for USB\n");
 569                 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
 570                 ret = extcon_register_interest(&omap->extcon_id_dev, edev->name,
 571                                          "USB-HOST", &omap->id_nb);
 572                 if (ret < 0)
 573                         dev_vdbg(dev,
 574                                 "failed to register notifier for USB-HOST\n");
 575
 576                 if (extcon_get_cable_state(edev, "USB") == true)
 577                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
 578                 if (extcon_get_cable_state(edev, "USB-HOST") == true)
 579                         dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
 580         }
 581
 582         ret = of_platform_populate(node, NULL, NULL, dev);
 583         if (ret) {
 584                 dev_err(&pdev->dev, "failed to create dwc3 core\n");
 585                 goto err3;
 586         }
 587
 588         return 0;
 589
 590 err3:
 591         if (omap->extcon_vbus_dev.edev)
 592                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 593         if (omap->extcon_id_dev.edev)
 594                 extcon_unregister_interest(&omap->extcon_id_dev);
 595
 596 err2:
 597         dwc3_omap_disable_irqs(omap);
 598
 599 err1:
 600         pm_runtime_put_sync(dev);
 601
 602 err0:
 603         pm_runtime_disable(dev);
 604
 605         return ret;
 606 }
 607
 608 static int dwc3_omap_remove(struct platform_device *pdev)
 609 {
 610         struct dwc3_omap        *omap = platform_get_drvdata(pdev);
 611
 612         if (omap->extcon_vbus_dev.edev)
 613                 extcon_unregister_interest(&omap->extcon_vbus_dev);
 614         if (omap->extcon_id_dev.edev)
 615                 extcon_unregister_interest(&omap->extcon_id_dev);
 616         dwc3_omap_disable_irqs(omap);
 617         pm_runtime_put_sync(&pdev->dev);
 618         pm_runtime_disable(&pdev->dev);
 619         device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
 620
 621         return 0;
 622 }
 623
 624 static const struct of_device_id of_dwc3_match[] = {
 625         {
 626                 .compatible =   "ti,dwc3"
 627         },
 628         {
 629                 .compatible =   "ti,am437x-dwc3"
 630         },
 631         { },
 632 };
 633 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 634
 635 #ifdef CONFIG_PM_SLEEP
 636 static int dwc3_omap_prepare(struct device *dev)
 637 {
 638         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 639
 640         dwc3_omap_disable_irqs(omap);
 641
 642         return 0;
 643 }
 644
 645 static void dwc3_omap_complete(struct device *dev)
 646 {
 647         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 648
 649         dwc3_omap_enable_irqs(omap);
 650 }
 651
 652 static int dwc3_omap_suspend(struct device *dev)
 653 {
 654         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 655
 656         omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
 657
 658         return 0;
 659 }
 660
 661 static int dwc3_omap_resume(struct device *dev)
 662 {
 663         struct dwc3_omap        *omap = dev_get_drvdata(dev);
 664
 665         dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
 666
 667         pm_runtime_disable(dev);
 668         pm_runtime_set_active(dev);
 669         pm_runtime_enable(dev);
 670
 671         return 0;
 672 }
 673
 674 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
 675         .prepare        = dwc3_omap_prepare,
 676         .complete       = dwc3_omap_complete,
 677
 678         SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
 679 };
 680
 681 #define DEV_PM_OPS      (&dwc3_omap_dev_pm_ops)
 682 #else
 683 #define DEV_PM_OPS      NULL
 684 #endif /* CONFIG_PM_SLEEP */
 685
 686 static struct platform_driver dwc3_omap_driver = {
 687         .probe          = dwc3_omap_probe,
 688         .remove         = dwc3_omap_remove,
 689         .driver         = {
 690                 .name   = "omap-dwc3",
 691                 .of_match_table = of_dwc3_match,
 692                 .pm     = DEV_PM_OPS,
 693         },
 694 };
 695
 696 module_platform_driver(dwc3_omap_driver);
 697
 698 MODULE_ALIAS("platform:omap-dwc3");
 699 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 700 MODULE_LICENSE("Dual BSD/GPL");
 701 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");