Pileus Git - ~andy/linux/blob - drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/module.h>
  40 #include <linux/kernel.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/ioport.h>
  47 #include <linux/io.h>
  48 #include <linux/list.h>
  49 #include <linux/delay.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/of.h>
  52
  53 #include <linux/usb/otg.h>
  54 #include <linux/usb/ch9.h>
  55 #include <linux/usb/gadget.h>
  56
  57 #include "core.h"
  58 #include "gadget.h"
  59 #include "io.h"
  60
  61 #include "debug.h"
  62
  63 static char *maximum_speed = "super";
  64 module_param(maximum_speed, charp, 0);
  65 MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
  66
  67 /* -------------------------------------------------------------------------- */
  68
  69 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  70 {
  71         u32 reg;
  72
  73         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  74         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  75         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  76         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  77 }
  78
  79 /**
  80  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  81  * @dwc: pointer to our context structure
  82  */
  83 static void dwc3_core_soft_reset(struct dwc3 *dwc)
  84 {
  85         u32             reg;
  86
  87         /* Before Resetting PHY, put Core in Reset */
  88         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  89         reg |= DWC3_GCTL_CORESOFTRESET;
  90         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  91
  92         /* Assert USB3 PHY reset */
  93         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  94         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  95         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  96
  97         /* Assert USB2 PHY reset */
  98         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  99         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
 100         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 101
 102         usb_phy_init(dwc->usb2_phy);
 103         usb_phy_init(dwc->usb3_phy);
 104         mdelay(100);
 105
 106         /* Clear USB3 PHY reset */
 107         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 108         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 109         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 110
 111         /* Clear USB2 PHY reset */
 112         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 113         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 114         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 115
 116         mdelay(100);
 117
 118         /* After PHYs are stable we can take Core out of reset state */
 119         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 120         reg &= ~DWC3_GCTL_CORESOFTRESET;
 121         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 122 }
 123
 124 /**
 125  * dwc3_free_one_event_buffer - Frees one event buffer
 126  * @dwc: Pointer to our controller context structure
 127  * @evt: Pointer to event buffer to be freed
 128  */
 129 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 130                 struct dwc3_event_buffer *evt)
 131 {
 132         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 133 }
 134
 135 /**
 136  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 137  * @dwc: Pointer to our controller context structure
 138  * @length: size of the event buffer
 139  *
 140  * Returns a pointer to the allocated event buffer structure on success
 141  * otherwise ERR_PTR(errno).
 142  */
 143 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 144                 unsigned length)
 145 {
 146         struct dwc3_event_buffer        *evt;
 147
 148         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 149         if (!evt)
 150                 return ERR_PTR(-ENOMEM);
 151
 152         evt->dwc        = dwc;
 153         evt->length     = length;
 154         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 155                         &evt->dma, GFP_KERNEL);
 156         if (!evt->buf)
 157                 return ERR_PTR(-ENOMEM);
 158
 159         return evt;
 160 }
 161
 162 /**
 163  * dwc3_free_event_buffers - frees all allocated event buffers
 164  * @dwc: Pointer to our controller context structure
 165  */
 166 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 167 {
 168         struct dwc3_event_buffer        *evt;
 169         int i;
 170
 171         for (i = 0; i < dwc->num_event_buffers; i++) {
 172                 evt = dwc->ev_buffs[i];
 173                 if (evt)
 174                         dwc3_free_one_event_buffer(dwc, evt);
 175         }
 176 }
 177
 178 /**
 179  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 180  * @dwc: pointer to our controller context structure
 181  * @length: size of event buffer
 182  *
 183  * Returns 0 on success otherwise negative errno. In the error case, dwc
 184  * may contain some buffers allocated but not all which were requested.
 185  */
 186 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 187 {
 188         int                     num;
 189         int                     i;
 190
 191         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 192         dwc->num_event_buffers = num;
 193
 194         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 195                         GFP_KERNEL);
 196         if (!dwc->ev_buffs) {
 197                 dev_err(dwc->dev, "can't allocate event buffers array\n");
 198                 return -ENOMEM;
 199         }
 200
 201         for (i = 0; i < num; i++) {
 202                 struct dwc3_event_buffer        *evt;
 203
 204                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 205                 if (IS_ERR(evt)) {
 206                         dev_err(dwc->dev, "can't allocate event buffer\n");
 207                         return PTR_ERR(evt);
 208                 }
 209                 dwc->ev_buffs[i] = evt;
 210         }
 211
 212         return 0;
 213 }
 214
 215 /**
 216  * dwc3_event_buffers_setup - setup our allocated event buffers
 217  * @dwc: pointer to our controller context structure
 218  *
 219  * Returns 0 on success otherwise negative errno.
 220  */
 221 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 222 {
 223         struct dwc3_event_buffer        *evt;
 224         int                             n;
 225
 226         for (n = 0; n < dwc->num_event_buffers; n++) {
 227                 evt = dwc->ev_buffs[n];
 228                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 229                                 evt->buf, (unsigned long long) evt->dma,
 230                                 evt->length);
 231
 232                 evt->lpos = 0;
 233
 234                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 235                                 lower_32_bits(evt->dma));
 236                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 237                                 upper_32_bits(evt->dma));
 238                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 239                                 evt->length & 0xffff);
 240                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 247 {
 248         struct dwc3_event_buffer        *evt;
 249         int                             n;
 250
 251         for (n = 0; n < dwc->num_event_buffers; n++) {
 252                 evt = dwc->ev_buffs[n];
 253
 254                 evt->lpos = 0;
 255
 256                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 257                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 258                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
 259                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 260         }
 261 }
 262
 263 static void dwc3_core_num_eps(struct dwc3 *dwc)
 264 {
 265         struct dwc3_hwparams    *parms = &dwc->hwparams;
 266
 267         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 268         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 269
 270         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 271                         dwc->num_in_eps, dwc->num_out_eps);
 272 }
 273
 274 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 275 {
 276         struct dwc3_hwparams    *parms = &dwc->hwparams;
 277
 278         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 279         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 280         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 281         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 282         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 283         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 284         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 285         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 286         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 287 }
 288
 289 /**
 290  * dwc3_core_init - Low-level initialization of DWC3 Core
 291  * @dwc: Pointer to our controller context structure
 292  *
 293  * Returns 0 on success otherwise negative errno.
 294  */
 295 static int dwc3_core_init(struct dwc3 *dwc)
 296 {
 297         unsigned long           timeout;
 298         u32                     reg;
 299         int                     ret;
 300
 301         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 302         /* This should read as U3 followed by revision number */
 303         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 304                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 305                 ret = -ENODEV;
 306                 goto err0;
 307         }
 308         dwc->revision = reg;
 309
 310         /* issue device SoftReset too */
 311         timeout = jiffies + msecs_to_jiffies(500);
 312         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 313         do {
 314                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 315                 if (!(reg & DWC3_DCTL_CSFTRST))
 316                         break;
 317
 318                 if (time_after(jiffies, timeout)) {
 319                         dev_err(dwc->dev, "Reset Timed Out\n");
 320                         ret = -ETIMEDOUT;
 321                         goto err0;
 322                 }
 323
 324                 cpu_relax();
 325         } while (true);
 326
 327         dwc3_core_soft_reset(dwc);
 328
 329         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 330         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 331         reg &= ~DWC3_GCTL_DISSCRAMBLE;
 332
 333         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 334         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 335                 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 336                 break;
 337         default:
 338                 dev_dbg(dwc->dev, "No power optimization available\n");
 339         }
 340
 341         /*
 342          * WORKAROUND: DWC3 revisions <1.90a have a bug
 343          * where the device can fail to connect at SuperSpeed
 344          * and falls back to high-speed mode which causes
 345          * the device to enter a Connect/Disconnect loop
 346          */
 347         if (dwc->revision < DWC3_REVISION_190A)
 348                 reg |= DWC3_GCTL_U2RSTECN;
 349
 350         dwc3_core_num_eps(dwc);
 351
 352         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 353
 354         return 0;
 355
 356 err0:
 357         return ret;
 358 }
 359
 360 static void dwc3_core_exit(struct dwc3 *dwc)
 361 {
 362         usb_phy_shutdown(dwc->usb2_phy);
 363         usb_phy_shutdown(dwc->usb3_phy);
 364 }
 365
 366 #define DWC3_ALIGN_MASK         (16 - 1)
 367
 368 static int dwc3_probe(struct platform_device *pdev)
 369 {
 370         struct device_node      *node = pdev->dev.of_node;
 371         struct resource         *res;
 372         struct dwc3             *dwc;
 373         struct device           *dev = &pdev->dev;
 374
 375         int                     ret = -ENOMEM;
 376
 377         void __iomem            *regs;
 378         void                    *mem;
 379
 380         u8                      mode;
 381
 382         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 383         if (!mem) {
 384                 dev_err(dev, "not enough memory\n");
 385                 return -ENOMEM;
 386         }
 387         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 388         dwc->mem = mem;
 389
 390         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 391         if (!res) {
 392                 dev_err(dev, "missing IRQ\n");
 393                 return -ENODEV;
 394         }
 395         dwc->xhci_resources[1].start = res->start;
 396         dwc->xhci_resources[1].end = res->end;
 397         dwc->xhci_resources[1].flags = res->flags;
 398         dwc->xhci_resources[1].name = res->name;
 399
 400         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 401         if (!res) {
 402                 dev_err(dev, "missing memory resource\n");
 403                 return -ENODEV;
 404         }
 405         dwc->xhci_resources[0].start = res->start;
 406         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 407                                         DWC3_XHCI_REGS_END;
 408         dwc->xhci_resources[0].flags = res->flags;
 409         dwc->xhci_resources[0].name = res->name;
 410
 411          /*
 412           * Request memory region but exclude xHCI regs,
 413           * since it will be requested by the xhci-plat driver.
 414           */
 415         res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
 416                         resource_size(res) - DWC3_GLOBALS_REGS_START,
 417                         dev_name(dev));
 418         if (!res) {
 419                 dev_err(dev, "can't request mem region\n");
 420                 return -ENOMEM;
 421         }
 422
 423         regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 424         if (!regs) {
 425                 dev_err(dev, "ioremap failed\n");
 426                 return -ENOMEM;
 427         }
 428
 429         if (node) {
 430                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 431                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 432         } else {
 433                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 434                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 435         }
 436
 437         if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
 438                 dev_err(dev, "no usb2 phy configured\n");
 439                 return -EPROBE_DEFER;
 440         }
 441
 442         if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
 443                 dev_err(dev, "no usb3 phy configured\n");
 444                 return -EPROBE_DEFER;
 445         }
 446
 447         usb_phy_set_suspend(dwc->usb2_phy, 0);
 448         usb_phy_set_suspend(dwc->usb3_phy, 0);
 449
 450         spin_lock_init(&dwc->lock);
 451         platform_set_drvdata(pdev, dwc);
 452
 453         dwc->regs       = regs;
 454         dwc->regs_size  = resource_size(res);
 455         dwc->dev        = dev;
 456
 457         dev->dma_mask   = dev->parent->dma_mask;
 458         dev->dma_parms  = dev->parent->dma_parms;
 459         dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 460
 461         if (!strncmp("super", maximum_speed, 5))
 462                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 463         else if (!strncmp("high", maximum_speed, 4))
 464                 dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
 465         else if (!strncmp("full", maximum_speed, 4))
 466                 dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
 467         else if (!strncmp("low", maximum_speed, 3))
 468                 dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
 469         else
 470                 dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
 471
 472         dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
 473
 474         pm_runtime_enable(dev);
 475         pm_runtime_get_sync(dev);
 476         pm_runtime_forbid(dev);
 477
 478         dwc3_cache_hwparams(dwc);
 479
 480         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 481         if (ret) {
 482                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 483                 ret = -ENOMEM;
 484                 goto err0;
 485         }
 486
 487         ret = dwc3_core_init(dwc);
 488         if (ret) {
 489                 dev_err(dev, "failed to initialize core\n");
 490                 goto err0;
 491         }
 492
 493         ret = dwc3_event_buffers_setup(dwc);
 494         if (ret) {
 495                 dev_err(dwc->dev, "failed to setup event buffers\n");
 496                 goto err1;
 497         }
 498
 499         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 500                 mode = DWC3_MODE_HOST;
 501         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 502                 mode = DWC3_MODE_DEVICE;
 503         else
 504                 mode = DWC3_MODE_DRD;
 505
 506         switch (mode) {
 507         case DWC3_MODE_DEVICE:
 508                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 509                 ret = dwc3_gadget_init(dwc);
 510                 if (ret) {
 511                         dev_err(dev, "failed to initialize gadget\n");
 512                         goto err2;
 513                 }
 514                 break;
 515         case DWC3_MODE_HOST:
 516                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 517                 ret = dwc3_host_init(dwc);
 518                 if (ret) {
 519                         dev_err(dev, "failed to initialize host\n");
 520                         goto err2;
 521                 }
 522                 break;
 523         case DWC3_MODE_DRD:
 524                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 525                 ret = dwc3_host_init(dwc);
 526                 if (ret) {
 527                         dev_err(dev, "failed to initialize host\n");
 528                         goto err2;
 529                 }
 530
 531                 ret = dwc3_gadget_init(dwc);
 532                 if (ret) {
 533                         dev_err(dev, "failed to initialize gadget\n");
 534                         goto err2;
 535                 }
 536                 break;
 537         default:
 538                 dev_err(dev, "Unsupported mode of operation %d\n", mode);
 539                 goto err2;
 540         }
 541         dwc->mode = mode;
 542
 543         ret = dwc3_debugfs_init(dwc);
 544         if (ret) {
 545                 dev_err(dev, "failed to initialize debugfs\n");
 546                 goto err3;
 547         }
 548
 549         pm_runtime_allow(dev);
 550
 551         return 0;
 552
 553 err3:
 554         switch (mode) {
 555         case DWC3_MODE_DEVICE:
 556                 dwc3_gadget_exit(dwc);
 557                 break;
 558         case DWC3_MODE_HOST:
 559                 dwc3_host_exit(dwc);
 560                 break;
 561         case DWC3_MODE_DRD:
 562                 dwc3_host_exit(dwc);
 563                 dwc3_gadget_exit(dwc);
 564                 break;
 565         default:
 566                 /* do nothing */
 567                 break;
 568         }
 569
 570 err2:
 571         dwc3_event_buffers_cleanup(dwc);
 572
 573 err1:
 574         dwc3_core_exit(dwc);
 575
 576 err0:
 577         dwc3_free_event_buffers(dwc);
 578
 579         return ret;
 580 }
 581
 582 static int dwc3_remove(struct platform_device *pdev)
 583 {
 584         struct dwc3     *dwc = platform_get_drvdata(pdev);
 585
 586         usb_phy_set_suspend(dwc->usb2_phy, 1);
 587         usb_phy_set_suspend(dwc->usb3_phy, 1);
 588
 589         pm_runtime_put(&pdev->dev);
 590         pm_runtime_disable(&pdev->dev);
 591
 592         dwc3_debugfs_exit(dwc);
 593
 594         switch (dwc->mode) {
 595         case DWC3_MODE_DEVICE:
 596                 dwc3_gadget_exit(dwc);
 597                 break;
 598         case DWC3_MODE_HOST:
 599                 dwc3_host_exit(dwc);
 600                 break;
 601         case DWC3_MODE_DRD:
 602                 dwc3_host_exit(dwc);
 603                 dwc3_gadget_exit(dwc);
 604                 break;
 605         default:
 606                 /* do nothing */
 607                 break;
 608         }
 609
 610         dwc3_event_buffers_cleanup(dwc);
 611         dwc3_free_event_buffers(dwc);
 612         dwc3_core_exit(dwc);
 613
 614         return 0;
 615 }
 616
 617 #ifdef CONFIG_PM
 618 static int dwc3_prepare(struct device *dev)
 619 {
 620         struct dwc3     *dwc = dev_get_drvdata(dev);
 621         unsigned long   flags;
 622
 623         spin_lock_irqsave(&dwc->lock, flags);
 624
 625         switch (dwc->mode) {
 626         case DWC3_MODE_DEVICE:
 627         case DWC3_MODE_DRD:
 628                 dwc3_gadget_prepare(dwc);
 629                 /* FALLTHROUGH */
 630         case DWC3_MODE_HOST:
 631         default:
 632                 dwc3_event_buffers_cleanup(dwc);
 633                 break;
 634         }
 635
 636         spin_unlock_irqrestore(&dwc->lock, flags);
 637
 638         return 0;
 639 }
 640
 641 static void dwc3_complete(struct device *dev)
 642 {
 643         struct dwc3     *dwc = dev_get_drvdata(dev);
 644         unsigned long   flags;
 645
 646         spin_lock_irqsave(&dwc->lock, flags);
 647
 648         switch (dwc->mode) {
 649         case DWC3_MODE_DEVICE:
 650         case DWC3_MODE_DRD:
 651                 dwc3_gadget_complete(dwc);
 652                 /* FALLTHROUGH */
 653         case DWC3_MODE_HOST:
 654         default:
 655                 dwc3_event_buffers_setup(dwc);
 656                 break;
 657         }
 658
 659         spin_unlock_irqrestore(&dwc->lock, flags);
 660 }
 661
 662 static int dwc3_suspend(struct device *dev)
 663 {
 664         struct dwc3     *dwc = dev_get_drvdata(dev);
 665         unsigned long   flags;
 666
 667         spin_lock_irqsave(&dwc->lock, flags);
 668
 669         switch (dwc->mode) {
 670         case DWC3_MODE_DEVICE:
 671         case DWC3_MODE_DRD:
 672                 dwc3_gadget_suspend(dwc);
 673                 /* FALLTHROUGH */
 674         case DWC3_MODE_HOST:
 675         default:
 676                 /* do nothing */
 677                 break;
 678         }
 679
 680         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 681         spin_unlock_irqrestore(&dwc->lock, flags);
 682
 683         usb_phy_shutdown(dwc->usb3_phy);
 684         usb_phy_shutdown(dwc->usb2_phy);
 685
 686         return 0;
 687 }
 688
 689 static int dwc3_resume(struct device *dev)
 690 {
 691         struct dwc3     *dwc = dev_get_drvdata(dev);
 692         unsigned long   flags;
 693
 694         usb_phy_init(dwc->usb3_phy);
 695         usb_phy_init(dwc->usb2_phy);
 696         msleep(100);
 697
 698         spin_lock_irqsave(&dwc->lock, flags);
 699
 700         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 701
 702         switch (dwc->mode) {
 703         case DWC3_MODE_DEVICE:
 704         case DWC3_MODE_DRD:
 705                 dwc3_gadget_resume(dwc);
 706                 /* FALLTHROUGH */
 707         case DWC3_MODE_HOST:
 708         default:
 709                 /* do nothing */
 710                 break;
 711         }
 712
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         pm_runtime_disable(dev);
 716         pm_runtime_set_active(dev);
 717         pm_runtime_enable(dev);
 718
 719         return 0;
 720 }
 721
 722 static const struct dev_pm_ops dwc3_dev_pm_ops = {
 723         .prepare        = dwc3_prepare,
 724         .complete       = dwc3_complete,
 725
 726         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
 727 };
 728
 729 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
 730 #else
 731 #define DWC3_PM_OPS     NULL
 732 #endif
 733
 734 #ifdef CONFIG_OF
 735 static const struct of_device_id of_dwc3_match[] = {
 736         {
 737                 .compatible = "synopsys,dwc3"
 738         },
 739         { },
 740 };
 741 MODULE_DEVICE_TABLE(of, of_dwc3_match);
 742 #endif
 743
 744 static struct platform_driver dwc3_driver = {
 745         .probe          = dwc3_probe,
 746         .remove         = dwc3_remove,
 747         .driver         = {
 748                 .name   = "dwc3",
 749                 .of_match_table = of_match_ptr(of_dwc3_match),
 750                 .pm     = DWC3_PM_OPS,
 751         },
 752 };
 753
 754 module_platform_driver(dwc3_driver);
 755
 756 MODULE_ALIAS("platform:dwc3");
 757 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 758 MODULE_LICENSE("Dual BSD/GPL");
 759 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");