2 * ci.h - common structures, functions, and macros of the ChipIdea driver
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
21 /******************************************************************************
23 *****************************************************************************/
24 #define TD_PAGE_COUNT 5
25 #define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
28 /******************************************************************************
30 *****************************************************************************/
31 /* register indices */
37 CAP_LAST = CAP_TESTMODE,
53 /* endptctrl1..15 follow */
54 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
57 /******************************************************************************
59 *****************************************************************************/
61 * struct ci_hw_ep - endpoint representation
62 * @ep: endpoint structure for gadget drivers
63 * @dir: endpoint direction (TX/RX)
64 * @num: endpoint number
65 * @type: endpoint type
66 * @name: string description of the endpoint
67 * @qh: queue head for this endpoint
68 * @wedge: is the endpoint wedged
69 * @ci: pointer to the controller
70 * @lock: pointer to controller's spinlock
71 * @td_pool: pointer to controller's TD pool
80 struct list_head queue;
86 /* global resources */
89 struct dma_pool *td_pool;
90 struct td_node *pending_td;
100 * struct ci_role_driver - host/gadget role driver
101 * start: start this role
102 * stop: stop this role
103 * irq: irq handler for this role
104 * name: role name string (host/gadget)
106 struct ci_role_driver {
107 int (*start)(struct ci_hdrc *);
108 void (*stop)(struct ci_hdrc *);
109 irqreturn_t (*irq)(struct ci_hdrc *);
114 * struct hw_bank - hardware register mapping representation
115 * @lpm: set if the device is LPM capable
116 * @phys: physical address of the controller's registers
117 * @abs: absolute address of the beginning of register window
118 * @cap: capability registers
119 * @op: operational registers
120 * @size: size of the register window
121 * @regmap: register lookup table
125 resource_size_t phys;
130 void __iomem *regmap[OP_LAST + 1];
134 * struct ci_hdrc - chipidea device representation
135 * @dev: pointer to parent device
136 * @lock: access synchronization
137 * @hw_bank: hardware register mapping
139 * @roles: array of supported roles for this controller
140 * @role: current role
141 * @is_otg: if the device is otg-capable
142 * @work: work for role changing
143 * @wq: workqueue thread
144 * @qh_pool: allocation pool for queue heads
145 * @td_pool: allocation pool for transfer descriptors
146 * @gadget: device side representation for peripheral controller
147 * @driver: gadget driver
148 * @hw_ep_max: total number of endpoints supported by hardware
149 * @ci_hw_ep: array of endpoints
150 * @ep0_dir: ep0 direction
151 * @ep0out: pointer to ep0 OUT endpoint
152 * @ep0in: pointer to ep0 IN endpoint
153 * @status: ep0 status request
154 * @setaddr: if we should set the address on status completion
155 * @address: usb address received from the host
156 * @remote_wakeup: host-enabled remote wakeup
157 * @suspended: suspended by host
158 * @test_mode: the selected test mode
159 * @platdata: platform specific information supplied by parent device
160 * @vbus_active: is VBUS active
161 * @transceiver: pointer to USB PHY, if any
162 * @hcd: pointer to usb_hcd for ehci host driver
163 * @debugfs: root dentry for this controller in debugfs
164 * @id_event: indicates there is an id event, and handled at ci_otg_work
165 * @b_sess_valid_event: indicates there is a vbus event, and handled
167 * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
172 struct hw_bank hw_bank;
174 struct ci_role_driver *roles[CI_ROLE_END];
177 struct work_struct work;
178 struct workqueue_struct *wq;
180 struct dma_pool *qh_pool;
181 struct dma_pool *td_pool;
183 struct usb_gadget gadget;
184 struct usb_gadget_driver *driver;
186 struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
188 struct ci_hw_ep *ep0out, *ep0in;
190 struct usb_request *status;
197 struct ci_hdrc_platform_data *platdata;
199 /* FIXME: some day, we'll not use global phy */
201 struct usb_phy *transceiver;
203 struct dentry *debugfs;
205 bool b_sess_valid_event;
206 bool imx28_write_fix;
209 static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
211 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
212 return ci->roles[ci->role];
215 static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
219 if (role >= CI_ROLE_END)
222 if (!ci->roles[role])
225 ret = ci->roles[role]->start(ci);
231 static inline void ci_role_stop(struct ci_hdrc *ci)
233 enum ci_role role = ci->role;
235 if (role == CI_ROLE_END)
238 ci->role = CI_ROLE_END;
240 ci->roles[role]->stop(ci);
244 * hw_read: reads from a hw register
245 * @reg: register index
246 * @mask: bitfield mask
248 * This function returns register contents
250 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
252 return ioread32(ci->hw_bank.regmap[reg]) & mask;
255 #ifdef CONFIG_SOC_IMX28
256 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
258 __asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr));
261 static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr)
266 static inline void __hw_write(struct ci_hdrc *ci, u32 val,
269 if (ci->imx28_write_fix)
270 imx28_ci_writel(val, addr);
272 iowrite32(val, addr);
276 * hw_write: writes to a hw register
277 * @reg: register index
278 * @mask: bitfield mask
281 static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
285 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
288 __hw_write(ci, data, ci->hw_bank.regmap[reg]);
292 * hw_test_and_clear: tests & clears a hw register
293 * @reg: register index
294 * @mask: bitfield mask
296 * This function returns register contents
298 static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
301 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
303 __hw_write(ci, val, ci->hw_bank.regmap[reg]);
308 * hw_test_and_write: tests & writes a hw register
309 * @reg: register index
310 * @mask: bitfield mask
313 * This function returns register contents
315 static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
318 u32 val = hw_read(ci, reg, ~0);
320 hw_write(ci, reg, mask, data);
321 return (val & mask) >> __ffs(mask);
324 int hw_device_reset(struct ci_hdrc *ci, u32 mode);
326 int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
328 u8 hw_port_test_get(struct ci_hdrc *ci);
330 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
331 u32 value, unsigned int timeout_ms);
333 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */