2 * Xilinx PS UART driver
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/clk.h>
26 #include <linux/irq.h>
29 #include <linux/module.h>
31 #define XUARTPS_TTY_NAME "ttyPS"
32 #define XUARTPS_NAME "xuartps"
33 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34 #define XUARTPS_MINOR 0 /* works best with devtmpfs */
35 #define XUARTPS_NR_PORTS 2
36 #define XUARTPS_FIFO_SIZE 16 /* FIFO size */
37 #define XUARTPS_REGISTER_SPACE 0xFFF
39 #define xuartps_readl(offset) ioread32(port->membase + offset)
40 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
42 /********************************Register Map********************************/
45 * Register offsets for the UART.
48 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
49 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
50 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
51 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
52 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
53 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
54 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
55 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
56 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
57 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
58 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
59 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
60 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
61 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
62 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
63 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
65 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
67 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
71 * The Control register (CR) controls the major functions of the device.
73 * Control Register Bit Definitions
75 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
76 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
77 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
78 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
79 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
80 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
81 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
82 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
83 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
87 * The mode register (MR) defines the mode of transfer as well as the data
88 * format. If this register is modified during transmission or reception,
89 * data validity cannot be guaranteed.
91 * Mode Register Bit Definitions
94 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
95 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
96 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
98 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
99 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
101 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
102 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
103 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
104 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
105 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
107 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
108 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
109 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
111 /** Interrupt Registers
113 * Interrupt control logic uses the interrupt enable register (IER) and the
114 * interrupt disable register (IDR) to set the value of the bits in the
115 * interrupt mask register (IMR). The IMR determines whether to pass an
116 * interrupt to the interrupt status register (ISR).
117 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
118 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
119 * Reading either IER or IDR returns 0x00.
121 * All four registers have the same bit definitions.
123 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
124 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
125 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
126 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
127 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
128 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
129 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
130 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
131 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
132 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
133 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
135 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
136 #define XUARTPS_IXR_BRK 0x80000000
138 /** Channel Status Register
140 * The channel status register (CSR) is provided to enable the control logic
141 * to monitor the status of bits in the channel interrupt status register,
142 * even if these are masked out by the interrupt mask register.
144 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
145 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
146 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
147 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
150 * struct xuartps - device data
151 * @refclk Reference clock
160 * xuartps_isr - Interrupt handler
162 * @dev_id: Id of the port
166 static irqreturn_t xuartps_isr(int irq, void *dev_id)
168 struct uart_port *port = (struct uart_port *)dev_id;
170 unsigned int isrstatus, numbytes;
172 char status = TTY_NORMAL;
174 spin_lock_irqsave(&port->lock, flags);
176 /* Read the interrupt status register to determine which
177 * interrupt(s) is/are active.
179 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
182 * There is no hardware break detection, so we interpret framing
183 * error with all-zeros data as a break sequence. Most of the time,
184 * there's another non-zero byte at the end of the sequence.
187 if (isrstatus & XUARTPS_IXR_FRAMING) {
188 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
189 XUARTPS_SR_RXEMPTY)) {
190 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
191 port->read_status_mask |= XUARTPS_IXR_BRK;
192 isrstatus &= ~XUARTPS_IXR_FRAMING;
195 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
198 /* drop byte with parity error if IGNPAR specified */
199 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
200 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
202 isrstatus &= port->read_status_mask;
203 isrstatus &= ~port->ignore_status_mask;
205 if ((isrstatus & XUARTPS_IXR_TOUT) ||
206 (isrstatus & XUARTPS_IXR_RXTRIG)) {
207 /* Receive Timeout Interrupt */
208 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
209 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
210 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
212 /* Non-NULL byte after BREAK is garbage (99%) */
213 if (data && (port->read_status_mask &
215 port->read_status_mask &= ~XUARTPS_IXR_BRK;
217 if (uart_handle_break(port))
222 * uart_handle_sysrq_char() doesn't work if
223 * spinlocked, for some reason
226 spin_unlock(&port->lock);
227 if (uart_handle_sysrq_char(port,
228 (unsigned char)data)) {
229 spin_lock(&port->lock);
232 spin_lock(&port->lock);
237 if (isrstatus & XUARTPS_IXR_PARITY) {
238 port->icount.parity++;
240 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
241 port->icount.frame++;
243 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
244 port->icount.overrun++;
246 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
249 spin_unlock(&port->lock);
250 tty_flip_buffer_push(&port->state->port);
251 spin_lock(&port->lock);
254 /* Dispatch an appropriate handler */
255 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
256 if (uart_circ_empty(&port->state->xmit)) {
257 xuartps_writel(XUARTPS_IXR_TXEMPTY,
260 numbytes = port->fifosize;
261 /* Break if no more data available in the UART buffer */
263 if (uart_circ_empty(&port->state->xmit))
265 /* Get the data from the UART circular buffer
266 * and write it to the xuartps's TX_FIFO
270 port->state->xmit.buf[port->state->xmit.
271 tail], XUARTPS_FIFO_OFFSET);
275 /* Adjust the tail of the UART buffer and wrap
276 * the buffer if it reaches limit.
278 port->state->xmit.tail =
279 (port->state->xmit.tail + 1) & \
280 (UART_XMIT_SIZE - 1);
283 if (uart_circ_chars_pending(
284 &port->state->xmit) < WAKEUP_CHARS)
285 uart_write_wakeup(port);
289 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
291 /* be sure to release the lock and tty before leaving */
292 spin_unlock_irqrestore(&port->lock, flags);
298 * xuartps_set_baud_rate - Calculate and set the baud rate
299 * @port: Handle to the uart port structure
300 * @baud: Baud rate to set
302 * Returns baud rate, requested baud when possible, or actual baud when there
305 static unsigned int xuartps_set_baud_rate(struct uart_port *port,
308 unsigned int sel_clk;
309 unsigned int calc_baud = 0;
310 unsigned int brgr_val, brdiv_val;
311 unsigned int bauderror;
313 /* Formula to obtain baud rate is
314 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
315 * input_clk = (Uart User Defined Clock or Apb Clock)
316 * depends on UCLKEN in MR Reg
317 * sel_clk = input_clk or input_clk/8;
318 * depends on CLKS in MR reg
319 * CD and BDIV depends on values in
320 * baud rate generate register
321 * baud rate clock divisor register
323 sel_clk = port->uartclk;
324 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
325 sel_clk = sel_clk / 8;
327 /* Find the best values for baud generation */
328 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
330 brgr_val = sel_clk / (baud * (brdiv_val + 1));
331 if (brgr_val < 2 || brgr_val > 65535)
334 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
336 if (baud > calc_baud)
337 bauderror = baud - calc_baud;
339 bauderror = calc_baud - baud;
341 /* use the values when percent error is acceptable */
342 if (((bauderror * 100) / baud) < 3) {
348 /* Set the values for the new baud rate */
349 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
350 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
355 /*----------------------Uart Operations---------------------------*/
358 * xuartps_start_tx - Start transmitting bytes
359 * @port: Handle to the uart port structure
362 static void xuartps_start_tx(struct uart_port *port)
364 unsigned int status, numbytes = port->fifosize;
366 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
369 status = xuartps_readl(XUARTPS_CR_OFFSET);
370 /* Set the TX enable bit and clear the TX disable bit to enable the
373 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
376 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
377 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
379 /* Break if no more data available in the UART buffer */
380 if (uart_circ_empty(&port->state->xmit))
383 /* Get the data from the UART circular buffer and
384 * write it to the xuartps's TX_FIFO register.
387 port->state->xmit.buf[port->state->xmit.tail],
388 XUARTPS_FIFO_OFFSET);
391 /* Adjust the tail of the UART buffer and wrap
392 * the buffer if it reaches limit.
394 port->state->xmit.tail = (port->state->xmit.tail + 1) &
395 (UART_XMIT_SIZE - 1);
398 /* Enable the TX Empty interrupt */
399 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
401 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
402 uart_write_wakeup(port);
406 * xuartps_stop_tx - Stop TX
407 * @port: Handle to the uart port structure
410 static void xuartps_stop_tx(struct uart_port *port)
414 regval = xuartps_readl(XUARTPS_CR_OFFSET);
415 regval |= XUARTPS_CR_TX_DIS;
416 /* Disable the transmitter */
417 xuartps_writel(regval, XUARTPS_CR_OFFSET);
421 * xuartps_stop_rx - Stop RX
422 * @port: Handle to the uart port structure
425 static void xuartps_stop_rx(struct uart_port *port)
429 regval = xuartps_readl(XUARTPS_CR_OFFSET);
430 regval |= XUARTPS_CR_RX_DIS;
431 /* Disable the receiver */
432 xuartps_writel(regval, XUARTPS_CR_OFFSET);
436 * xuartps_tx_empty - Check whether TX is empty
437 * @port: Handle to the uart port structure
439 * Returns TIOCSER_TEMT on success, 0 otherwise
441 static unsigned int xuartps_tx_empty(struct uart_port *port)
445 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
446 return status ? TIOCSER_TEMT : 0;
450 * xuartps_break_ctl - Based on the input ctl we have to start or stop
451 * transmitting char breaks
452 * @port: Handle to the uart port structure
453 * @ctl: Value based on which start or stop decision is taken
456 static void xuartps_break_ctl(struct uart_port *port, int ctl)
461 spin_lock_irqsave(&port->lock, flags);
463 status = xuartps_readl(XUARTPS_CR_OFFSET);
466 xuartps_writel(XUARTPS_CR_STARTBRK | status,
469 if ((status & XUARTPS_CR_STOPBRK) == 0)
470 xuartps_writel(XUARTPS_CR_STOPBRK | status,
473 spin_unlock_irqrestore(&port->lock, flags);
477 * xuartps_set_termios - termios operations, handling data length, parity,
478 * stop bits, flow control, baud rate
479 * @port: Handle to the uart port structure
480 * @termios: Handle to the input termios structure
481 * @old: Values of the previously saved termios structure
484 static void xuartps_set_termios(struct uart_port *port,
485 struct ktermios *termios, struct ktermios *old)
487 unsigned int cval = 0;
490 unsigned int ctrl_reg, mode_reg;
492 spin_lock_irqsave(&port->lock, flags);
494 /* Empty the receive FIFO 1st before making changes */
495 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
496 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
497 xuartps_readl(XUARTPS_FIFO_OFFSET);
500 /* Disable the TX and RX to set baud rate */
501 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
502 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
505 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
506 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
507 baud = xuartps_set_baud_rate(port, baud);
508 if (tty_termios_baud_rate(termios))
509 tty_termios_encode_baud_rate(termios, baud, baud);
512 * Update the per-port timeout.
514 uart_update_timeout(port, termios->c_cflag, baud);
516 /* Set TX/RX Reset */
517 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
518 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
521 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
523 /* Clear the RX disable and TX disable bits and then set the TX enable
524 * bit and RX enable bit to enable the transmitter and receiver.
527 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
528 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
531 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
533 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
534 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
535 port->ignore_status_mask = 0;
537 if (termios->c_iflag & INPCK)
538 port->read_status_mask |= XUARTPS_IXR_PARITY |
541 if (termios->c_iflag & IGNPAR)
542 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
543 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
545 /* ignore all characters if CREAD is not set */
546 if ((termios->c_cflag & CREAD) == 0)
547 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
548 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
549 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
551 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
553 /* Handling Data Size */
554 switch (termios->c_cflag & CSIZE) {
556 cval |= XUARTPS_MR_CHARLEN_6_BIT;
559 cval |= XUARTPS_MR_CHARLEN_7_BIT;
563 cval |= XUARTPS_MR_CHARLEN_8_BIT;
564 termios->c_cflag &= ~CSIZE;
565 termios->c_cflag |= CS8;
569 /* Handling Parity and Stop Bits length */
570 if (termios->c_cflag & CSTOPB)
571 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
573 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
575 if (termios->c_cflag & PARENB) {
576 /* Mark or Space parity */
577 if (termios->c_cflag & CMSPAR) {
578 if (termios->c_cflag & PARODD)
579 cval |= XUARTPS_MR_PARITY_MARK;
581 cval |= XUARTPS_MR_PARITY_SPACE;
582 } else if (termios->c_cflag & PARODD)
583 cval |= XUARTPS_MR_PARITY_ODD;
585 cval |= XUARTPS_MR_PARITY_EVEN;
587 cval |= XUARTPS_MR_PARITY_NONE;
588 xuartps_writel(cval , XUARTPS_MR_OFFSET);
590 spin_unlock_irqrestore(&port->lock, flags);
594 * xuartps_startup - Called when an application opens a xuartps port
595 * @port: Handle to the uart port structure
597 * Returns 0 on success, negative error otherwise
599 static int xuartps_startup(struct uart_port *port)
601 unsigned int retval = 0, status = 0;
603 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
608 /* Disable the TX and RX */
609 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
612 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
615 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
618 status = xuartps_readl(XUARTPS_CR_OFFSET);
620 /* Clear the RX disable and TX disable bits and then set the TX enable
621 * bit and RX enable bit to enable the transmitter and receiver.
623 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
624 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
625 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
627 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
630 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
631 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
634 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
635 xuartps_writel(14, XUARTPS_RXWM_OFFSET);
637 /* Receive Timeout register is enabled with value of 10 */
638 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
640 /* Clear out any pending interrupts before enabling them */
641 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
643 /* Set the Interrupt Registers with desired interrupts */
644 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
645 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
646 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
652 * xuartps_shutdown - Called when an application closes a xuartps port
653 * @port: Handle to the uart port structure
656 static void xuartps_shutdown(struct uart_port *port)
660 /* Disable interrupts */
661 status = xuartps_readl(XUARTPS_IMR_OFFSET);
662 xuartps_writel(status, XUARTPS_IDR_OFFSET);
664 /* Disable the TX and RX */
665 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
667 free_irq(port->irq, port);
671 * xuartps_type - Set UART type to xuartps port
672 * @port: Handle to the uart port structure
674 * Returns string on success, NULL otherwise
676 static const char *xuartps_type(struct uart_port *port)
678 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
682 * xuartps_verify_port - Verify the port params
683 * @port: Handle to the uart port structure
684 * @ser: Handle to the structure whose members are compared
686 * Returns 0 if success otherwise -EINVAL
688 static int xuartps_verify_port(struct uart_port *port,
689 struct serial_struct *ser)
691 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
693 if (port->irq != ser->irq)
695 if (ser->io_type != UPIO_MEM)
697 if (port->iobase != ser->port)
705 * xuartps_request_port - Claim the memory region attached to xuartps port,
706 * called when the driver adds a xuartps port via
707 * uart_add_one_port()
708 * @port: Handle to the uart port structure
710 * Returns 0, -ENOMEM if request fails
712 static int xuartps_request_port(struct uart_port *port)
714 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
719 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
720 if (!port->membase) {
721 dev_err(port->dev, "Unable to map registers\n");
722 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
729 * xuartps_release_port - Release the memory region attached to a xuartps
730 * port, called when the driver removes a xuartps
731 * port via uart_remove_one_port().
732 * @port: Handle to the uart port structure
735 static void xuartps_release_port(struct uart_port *port)
737 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
738 iounmap(port->membase);
739 port->membase = NULL;
743 * xuartps_config_port - Configure xuartps, called when the driver adds a
745 * @port: Handle to the uart port structure
749 static void xuartps_config_port(struct uart_port *port, int flags)
751 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
752 port->type = PORT_XUARTPS;
756 * xuartps_get_mctrl - Get the modem control state
758 * @port: Handle to the uart port structure
760 * Returns the modem control state
763 static unsigned int xuartps_get_mctrl(struct uart_port *port)
765 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
768 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
773 static void xuartps_enable_ms(struct uart_port *port)
778 #ifdef CONFIG_CONSOLE_POLL
779 static int xuartps_poll_get_char(struct uart_port *port)
784 /* Disable all interrupts */
785 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
786 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
788 /* Check if FIFO is empty */
789 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
791 else /* Read a character */
792 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
794 /* Enable interrupts */
795 xuartps_writel(imr, XUARTPS_IER_OFFSET);
800 static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
804 /* Disable all interrupts */
805 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
806 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
808 /* Wait until FIFO is empty */
809 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
812 /* Write a character */
813 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
815 /* Wait until FIFO is empty */
816 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
819 /* Enable interrupts */
820 xuartps_writel(imr, XUARTPS_IER_OFFSET);
826 /** The UART operations structure
828 static struct uart_ops xuartps_ops = {
829 .set_mctrl = xuartps_set_mctrl,
830 .get_mctrl = xuartps_get_mctrl,
831 .enable_ms = xuartps_enable_ms,
833 .start_tx = xuartps_start_tx, /* Start transmitting */
834 .stop_tx = xuartps_stop_tx, /* Stop transmission */
835 .stop_rx = xuartps_stop_rx, /* Stop reception */
836 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
837 .break_ctl = xuartps_break_ctl, /* Start/stop
840 .set_termios = xuartps_set_termios, /* Set termios */
841 .startup = xuartps_startup, /* App opens xuartps */
842 .shutdown = xuartps_shutdown, /* App closes xuartps */
843 .type = xuartps_type, /* Set UART type */
844 .verify_port = xuartps_verify_port, /* Verification of port
847 .request_port = xuartps_request_port, /* Claim resources
851 .release_port = xuartps_release_port, /* Release resources
855 .config_port = xuartps_config_port, /* Configure when driver
856 * adds a xuartps port
858 #ifdef CONFIG_CONSOLE_POLL
859 .poll_get_char = xuartps_poll_get_char,
860 .poll_put_char = xuartps_poll_put_char,
864 static struct uart_port xuartps_port[2];
867 * xuartps_get_port - Configure the port from the platform device resource
870 * Returns a pointer to a uart_port or NULL for failure
872 static struct uart_port *xuartps_get_port(void)
874 struct uart_port *port;
877 /* Find the next unused port */
878 for (id = 0; id < XUARTPS_NR_PORTS; id++)
879 if (xuartps_port[id].mapbase == 0)
882 if (id >= XUARTPS_NR_PORTS)
885 port = &xuartps_port[id];
887 /* At this point, we've got an empty uart_port struct, initialize it */
888 spin_lock_init(&port->lock);
889 port->membase = NULL;
890 port->iobase = 1; /* mark port in use */
892 port->type = PORT_UNKNOWN;
893 port->iotype = UPIO_MEM32;
894 port->flags = UPF_BOOT_AUTOCONF;
895 port->ops = &xuartps_ops;
896 port->fifosize = XUARTPS_FIFO_SIZE;
902 /*-----------------------Console driver operations--------------------------*/
904 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
906 * xuartps_console_wait_tx - Wait for the TX to be full
907 * @port: Handle to the uart port structure
910 static void xuartps_console_wait_tx(struct uart_port *port)
912 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
913 != XUARTPS_SR_TXEMPTY)
918 * xuartps_console_putchar - write the character to the FIFO buffer
919 * @port: Handle to the uart port structure
920 * @ch: Character to be written
923 static void xuartps_console_putchar(struct uart_port *port, int ch)
925 xuartps_console_wait_tx(port);
926 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
930 * xuartps_console_write - perform write operation
931 * @port: Handle to the uart port structure
932 * @s: Pointer to character array
933 * @count: No of characters
935 static void xuartps_console_write(struct console *co, const char *s,
938 struct uart_port *port = &xuartps_port[co->index];
943 if (oops_in_progress)
944 locked = spin_trylock_irqsave(&port->lock, flags);
946 spin_lock_irqsave(&port->lock, flags);
948 /* save and disable interrupt */
949 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
950 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
952 uart_console_write(port, s, count, xuartps_console_putchar);
953 xuartps_console_wait_tx(port);
955 /* restore interrupt state, it seems like there may be a h/w bug
956 * in that the interrupt enable register should not need to be
957 * written based on the data sheet
959 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
960 xuartps_writel(imr, XUARTPS_IER_OFFSET);
963 spin_unlock_irqrestore(&port->lock, flags);
967 * xuartps_console_setup - Initialize the uart to default config
968 * @co: Console handle
969 * @options: Initial settings of uart
971 * Returns 0, -ENODEV if no device
973 static int __init xuartps_console_setup(struct console *co, char *options)
975 struct uart_port *port = &xuartps_port[co->index];
981 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
984 if (!port->mapbase) {
985 pr_debug("console on ttyPS%i not present\n", co->index);
990 uart_parse_options(options, &baud, &parity, &bits, &flow);
992 return uart_set_options(port, co, baud, parity, bits, flow);
995 static struct uart_driver xuartps_uart_driver;
997 static struct console xuartps_console = {
998 .name = XUARTPS_TTY_NAME,
999 .write = xuartps_console_write,
1000 .device = uart_console_device,
1001 .setup = xuartps_console_setup,
1002 .flags = CON_PRINTBUFFER,
1003 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1004 .data = &xuartps_uart_driver,
1008 * xuartps_console_init - Initialization call
1010 * Returns 0 on success, negative error otherwise
1012 static int __init xuartps_console_init(void)
1014 register_console(&xuartps_console);
1018 console_initcall(xuartps_console_init);
1020 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1022 /** Structure Definitions
1024 static struct uart_driver xuartps_uart_driver = {
1025 .owner = THIS_MODULE, /* Owner */
1026 .driver_name = XUARTPS_NAME, /* Driver name */
1027 .dev_name = XUARTPS_TTY_NAME, /* Node name */
1028 .major = XUARTPS_MAJOR, /* Major number */
1029 .minor = XUARTPS_MINOR, /* Minor number */
1030 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1031 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1032 .cons = &xuartps_console, /* Console */
1036 /* ---------------------------------------------------------------------
1037 * Platform bus binding
1040 * xuartps_probe - Platform driver probe
1041 * @pdev: Pointer to the platform device structure
1043 * Returns 0 on success, negative error otherwise
1045 static int xuartps_probe(struct platform_device *pdev)
1048 struct uart_port *port;
1049 struct resource *res, *res2;
1050 struct xuartps *xuartps_data;
1052 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1057 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1058 if (IS_ERR(xuartps_data->aperclk)) {
1059 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1060 return PTR_ERR(xuartps_data->aperclk);
1062 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1063 if (IS_ERR(xuartps_data->refclk)) {
1064 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1065 return PTR_ERR(xuartps_data->refclk);
1068 rc = clk_prepare_enable(xuartps_data->aperclk);
1070 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1073 rc = clk_prepare_enable(xuartps_data->refclk);
1075 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1076 goto err_out_clk_dis_aper;
1079 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 goto err_out_clk_disable;
1085 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1088 goto err_out_clk_disable;
1091 /* Initialize the port structure */
1092 port = xuartps_get_port();
1095 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1097 goto err_out_clk_disable;
1099 /* Register the port.
1100 * This function also registers this device with the tty layer
1101 * and triggers invocation of the config_port() entry point.
1103 port->mapbase = res->start;
1104 port->irq = res2->start;
1105 port->dev = &pdev->dev;
1106 port->uartclk = clk_get_rate(xuartps_data->refclk);
1107 port->private_data = xuartps_data;
1108 platform_set_drvdata(pdev, port);
1109 rc = uart_add_one_port(&xuartps_uart_driver, port);
1112 "uart_add_one_port() failed; err=%i\n", rc);
1113 goto err_out_clk_disable;
1118 err_out_clk_disable:
1119 clk_disable_unprepare(xuartps_data->refclk);
1120 err_out_clk_dis_aper:
1121 clk_disable_unprepare(xuartps_data->aperclk);
1127 * xuartps_remove - called when the platform driver is unregistered
1128 * @pdev: Pointer to the platform device structure
1130 * Returns 0 on success, negative error otherwise
1132 static int xuartps_remove(struct platform_device *pdev)
1134 struct uart_port *port = platform_get_drvdata(pdev);
1135 struct xuartps *xuartps_data = port->private_data;
1138 /* Remove the xuartps port from the serial core */
1139 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1141 clk_disable_unprepare(xuartps_data->refclk);
1142 clk_disable_unprepare(xuartps_data->aperclk);
1146 /* Match table for of_platform binding */
1147 static struct of_device_id xuartps_of_match[] = {
1148 { .compatible = "xlnx,xuartps", },
1151 MODULE_DEVICE_TABLE(of, xuartps_of_match);
1153 static struct platform_driver xuartps_platform_driver = {
1154 .probe = xuartps_probe, /* Probe method */
1155 .remove = xuartps_remove, /* Detach method */
1157 .owner = THIS_MODULE,
1158 .name = XUARTPS_NAME, /* Driver name */
1159 .of_match_table = xuartps_of_match,
1163 /* ---------------------------------------------------------------------
1164 * Module Init and Exit
1167 * xuartps_init - Initial driver registration call
1169 * Returns whether the registration was successful or not
1171 static int __init xuartps_init(void)
1175 /* Register the xuartps driver with the serial core */
1176 retval = uart_register_driver(&xuartps_uart_driver);
1180 /* Register the platform driver */
1181 retval = platform_driver_register(&xuartps_platform_driver);
1183 uart_unregister_driver(&xuartps_uart_driver);
1189 * xuartps_exit - Driver unregistration call
1191 static void __exit xuartps_exit(void)
1193 /* The order of unregistration is important. Unregister the
1194 * UART driver before the platform driver crashes the system.
1197 /* Unregister the platform driver */
1198 platform_driver_unregister(&xuartps_platform_driver);
1200 /* Unregister the xuartps driver */
1201 uart_unregister_driver(&xuartps_uart_driver);
1204 module_init(xuartps_init);
1205 module_exit(xuartps_exit);
1207 MODULE_DESCRIPTION("Driver for PS UART");
1208 MODULE_AUTHOR("Xilinx Inc.");
1209 MODULE_LICENSE("GPL");