2 * Xilinx PS UART driver
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
14 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/console.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/clk.h>
26 #include <linux/irq.h>
29 #include <linux/module.h>
31 #define XUARTPS_TTY_NAME "ttyPS"
32 #define XUARTPS_NAME "xuartps"
33 #define XUARTPS_MAJOR 0 /* use dynamic node allocation */
34 #define XUARTPS_MINOR 0 /* works best with devtmpfs */
35 #define XUARTPS_NR_PORTS 2
36 #define XUARTPS_FIFO_SIZE 64 /* FIFO size */
37 #define XUARTPS_REGISTER_SPACE 0xFFF
39 #define xuartps_readl(offset) ioread32(port->membase + offset)
40 #define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
52 /********************************Register Map********************************/
55 * Register offsets for the UART.
58 #define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
59 #define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
60 #define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
61 #define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
62 #define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
63 #define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
64 #define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
65 #define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
66 #define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
67 #define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
68 #define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
69 #define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
70 #define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
71 #define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
72 #define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
73 #define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
75 #define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
77 #define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
81 * The Control register (CR) controls the major functions of the device.
83 * Control Register Bit Definitions
85 #define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
86 #define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
87 #define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
88 #define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
89 #define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
90 #define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
91 #define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
92 #define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
93 #define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
97 * The mode register (MR) defines the mode of transfer as well as the data
98 * format. If this register is modified during transmission or reception,
99 * data validity cannot be guaranteed.
101 * Mode Register Bit Definitions
104 #define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
105 #define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
106 #define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
108 #define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
109 #define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
111 #define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
112 #define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
113 #define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
114 #define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
115 #define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
117 #define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
118 #define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
119 #define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
121 /** Interrupt Registers
123 * Interrupt control logic uses the interrupt enable register (IER) and the
124 * interrupt disable register (IDR) to set the value of the bits in the
125 * interrupt mask register (IMR). The IMR determines whether to pass an
126 * interrupt to the interrupt status register (ISR).
127 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
128 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
129 * Reading either IER or IDR returns 0x00.
131 * All four registers have the same bit definitions.
133 #define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
134 #define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
135 #define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
136 #define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
137 #define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
138 #define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
139 #define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
140 #define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
141 #define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
142 #define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
143 #define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define XUARTPS_IXR_BRK 0x80000000
148 /** Channel Status Register
150 * The channel status register (CSR) is provided to enable the control logic
151 * to monitor the status of bits in the channel interrupt status register,
152 * even if these are masked out by the interrupt mask register.
154 #define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
155 #define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
156 #define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
157 #define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
160 * struct xuartps - device data
161 * @refclk Reference clock
170 * xuartps_isr - Interrupt handler
172 * @dev_id: Id of the port
176 static irqreturn_t xuartps_isr(int irq, void *dev_id)
178 struct uart_port *port = (struct uart_port *)dev_id;
180 unsigned int isrstatus, numbytes;
182 char status = TTY_NORMAL;
184 spin_lock_irqsave(&port->lock, flags);
186 /* Read the interrupt status register to determine which
187 * interrupt(s) is/are active.
189 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
192 * There is no hardware break detection, so we interpret framing
193 * error with all-zeros data as a break sequence. Most of the time,
194 * there's another non-zero byte at the end of the sequence.
197 if (isrstatus & XUARTPS_IXR_FRAMING) {
198 while (!(xuartps_readl(XUARTPS_SR_OFFSET) &
199 XUARTPS_SR_RXEMPTY)) {
200 if (!xuartps_readl(XUARTPS_FIFO_OFFSET)) {
201 port->read_status_mask |= XUARTPS_IXR_BRK;
202 isrstatus &= ~XUARTPS_IXR_FRAMING;
205 xuartps_writel(XUARTPS_IXR_FRAMING, XUARTPS_ISR_OFFSET);
208 /* drop byte with parity error if IGNPAR specified */
209 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
210 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
212 isrstatus &= port->read_status_mask;
213 isrstatus &= ~port->ignore_status_mask;
215 if ((isrstatus & XUARTPS_IXR_TOUT) ||
216 (isrstatus & XUARTPS_IXR_RXTRIG)) {
217 /* Receive Timeout Interrupt */
218 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
219 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
220 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
222 /* Non-NULL byte after BREAK is garbage (99%) */
223 if (data && (port->read_status_mask &
225 port->read_status_mask &= ~XUARTPS_IXR_BRK;
227 if (uart_handle_break(port))
232 * uart_handle_sysrq_char() doesn't work if
233 * spinlocked, for some reason
236 spin_unlock(&port->lock);
237 if (uart_handle_sysrq_char(port,
238 (unsigned char)data)) {
239 spin_lock(&port->lock);
242 spin_lock(&port->lock);
247 if (isrstatus & XUARTPS_IXR_PARITY) {
248 port->icount.parity++;
250 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
251 port->icount.frame++;
253 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
254 port->icount.overrun++;
256 uart_insert_char(port, isrstatus, XUARTPS_IXR_OVERRUN,
259 spin_unlock(&port->lock);
260 tty_flip_buffer_push(&port->state->port);
261 spin_lock(&port->lock);
264 /* Dispatch an appropriate handler */
265 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
266 if (uart_circ_empty(&port->state->xmit)) {
267 xuartps_writel(XUARTPS_IXR_TXEMPTY,
270 numbytes = port->fifosize;
271 /* Break if no more data available in the UART buffer */
273 if (uart_circ_empty(&port->state->xmit))
275 /* Get the data from the UART circular buffer
276 * and write it to the xuartps's TX_FIFO
280 port->state->xmit.buf[port->state->xmit.
281 tail], XUARTPS_FIFO_OFFSET);
285 /* Adjust the tail of the UART buffer and wrap
286 * the buffer if it reaches limit.
288 port->state->xmit.tail =
289 (port->state->xmit.tail + 1) & \
290 (UART_XMIT_SIZE - 1);
293 if (uart_circ_chars_pending(
294 &port->state->xmit) < WAKEUP_CHARS)
295 uart_write_wakeup(port);
299 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
301 /* be sure to release the lock and tty before leaving */
302 spin_unlock_irqrestore(&port->lock, flags);
308 * xuartps_set_baud_rate - Calculate and set the baud rate
309 * @port: Handle to the uart port structure
310 * @baud: Baud rate to set
312 * Returns baud rate, requested baud when possible, or actual baud when there
315 static unsigned int xuartps_set_baud_rate(struct uart_port *port,
318 unsigned int sel_clk;
319 unsigned int calc_baud = 0;
320 unsigned int brgr_val, brdiv_val;
321 unsigned int bauderror;
323 /* Formula to obtain baud rate is
324 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
325 * input_clk = (Uart User Defined Clock or Apb Clock)
326 * depends on UCLKEN in MR Reg
327 * sel_clk = input_clk or input_clk/8;
328 * depends on CLKS in MR reg
329 * CD and BDIV depends on values in
330 * baud rate generate register
331 * baud rate clock divisor register
333 sel_clk = port->uartclk;
334 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
335 sel_clk = sel_clk / 8;
337 /* Find the best values for baud generation */
338 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
340 brgr_val = sel_clk / (baud * (brdiv_val + 1));
341 if (brgr_val < 2 || brgr_val > 65535)
344 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
346 if (baud > calc_baud)
347 bauderror = baud - calc_baud;
349 bauderror = calc_baud - baud;
351 /* use the values when percent error is acceptable */
352 if (((bauderror * 100) / baud) < 3) {
358 /* Set the values for the new baud rate */
359 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
360 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
365 /*----------------------Uart Operations---------------------------*/
368 * xuartps_start_tx - Start transmitting bytes
369 * @port: Handle to the uart port structure
372 static void xuartps_start_tx(struct uart_port *port)
374 unsigned int status, numbytes = port->fifosize;
376 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
379 status = xuartps_readl(XUARTPS_CR_OFFSET);
380 /* Set the TX enable bit and clear the TX disable bit to enable the
383 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
386 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
387 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
389 /* Break if no more data available in the UART buffer */
390 if (uart_circ_empty(&port->state->xmit))
393 /* Get the data from the UART circular buffer and
394 * write it to the xuartps's TX_FIFO register.
397 port->state->xmit.buf[port->state->xmit.tail],
398 XUARTPS_FIFO_OFFSET);
401 /* Adjust the tail of the UART buffer and wrap
402 * the buffer if it reaches limit.
404 port->state->xmit.tail = (port->state->xmit.tail + 1) &
405 (UART_XMIT_SIZE - 1);
407 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_ISR_OFFSET);
408 /* Enable the TX Empty interrupt */
409 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
411 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
412 uart_write_wakeup(port);
416 * xuartps_stop_tx - Stop TX
417 * @port: Handle to the uart port structure
420 static void xuartps_stop_tx(struct uart_port *port)
424 regval = xuartps_readl(XUARTPS_CR_OFFSET);
425 regval |= XUARTPS_CR_TX_DIS;
426 /* Disable the transmitter */
427 xuartps_writel(regval, XUARTPS_CR_OFFSET);
431 * xuartps_stop_rx - Stop RX
432 * @port: Handle to the uart port structure
435 static void xuartps_stop_rx(struct uart_port *port)
439 regval = xuartps_readl(XUARTPS_CR_OFFSET);
440 regval |= XUARTPS_CR_RX_DIS;
441 /* Disable the receiver */
442 xuartps_writel(regval, XUARTPS_CR_OFFSET);
446 * xuartps_tx_empty - Check whether TX is empty
447 * @port: Handle to the uart port structure
449 * Returns TIOCSER_TEMT on success, 0 otherwise
451 static unsigned int xuartps_tx_empty(struct uart_port *port)
455 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
456 return status ? TIOCSER_TEMT : 0;
460 * xuartps_break_ctl - Based on the input ctl we have to start or stop
461 * transmitting char breaks
462 * @port: Handle to the uart port structure
463 * @ctl: Value based on which start or stop decision is taken
466 static void xuartps_break_ctl(struct uart_port *port, int ctl)
471 spin_lock_irqsave(&port->lock, flags);
473 status = xuartps_readl(XUARTPS_CR_OFFSET);
476 xuartps_writel(XUARTPS_CR_STARTBRK | status,
479 if ((status & XUARTPS_CR_STOPBRK) == 0)
480 xuartps_writel(XUARTPS_CR_STOPBRK | status,
483 spin_unlock_irqrestore(&port->lock, flags);
487 * xuartps_set_termios - termios operations, handling data length, parity,
488 * stop bits, flow control, baud rate
489 * @port: Handle to the uart port structure
490 * @termios: Handle to the input termios structure
491 * @old: Values of the previously saved termios structure
494 static void xuartps_set_termios(struct uart_port *port,
495 struct ktermios *termios, struct ktermios *old)
497 unsigned int cval = 0;
500 unsigned int ctrl_reg, mode_reg;
502 spin_lock_irqsave(&port->lock, flags);
504 /* Empty the receive FIFO 1st before making changes */
505 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
506 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
507 xuartps_readl(XUARTPS_FIFO_OFFSET);
510 /* Disable the TX and RX to set baud rate */
511 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
512 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
515 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
516 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
517 baud = xuartps_set_baud_rate(port, baud);
518 if (tty_termios_baud_rate(termios))
519 tty_termios_encode_baud_rate(termios, baud, baud);
522 * Update the per-port timeout.
524 uart_update_timeout(port, termios->c_cflag, baud);
526 /* Set TX/RX Reset */
527 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
528 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
531 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
533 /* Clear the RX disable and TX disable bits and then set the TX enable
534 * bit and RX enable bit to enable the transmitter and receiver.
537 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
538 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
541 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
543 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
544 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
545 port->ignore_status_mask = 0;
547 if (termios->c_iflag & INPCK)
548 port->read_status_mask |= XUARTPS_IXR_PARITY |
551 if (termios->c_iflag & IGNPAR)
552 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
553 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
555 /* ignore all characters if CREAD is not set */
556 if ((termios->c_cflag & CREAD) == 0)
557 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
558 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
559 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
561 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
563 /* Handling Data Size */
564 switch (termios->c_cflag & CSIZE) {
566 cval |= XUARTPS_MR_CHARLEN_6_BIT;
569 cval |= XUARTPS_MR_CHARLEN_7_BIT;
573 cval |= XUARTPS_MR_CHARLEN_8_BIT;
574 termios->c_cflag &= ~CSIZE;
575 termios->c_cflag |= CS8;
579 /* Handling Parity and Stop Bits length */
580 if (termios->c_cflag & CSTOPB)
581 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
583 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
585 if (termios->c_cflag & PARENB) {
586 /* Mark or Space parity */
587 if (termios->c_cflag & CMSPAR) {
588 if (termios->c_cflag & PARODD)
589 cval |= XUARTPS_MR_PARITY_MARK;
591 cval |= XUARTPS_MR_PARITY_SPACE;
592 } else if (termios->c_cflag & PARODD)
593 cval |= XUARTPS_MR_PARITY_ODD;
595 cval |= XUARTPS_MR_PARITY_EVEN;
597 cval |= XUARTPS_MR_PARITY_NONE;
598 xuartps_writel(cval , XUARTPS_MR_OFFSET);
600 spin_unlock_irqrestore(&port->lock, flags);
604 * xuartps_startup - Called when an application opens a xuartps port
605 * @port: Handle to the uart port structure
607 * Returns 0 on success, negative error otherwise
609 static int xuartps_startup(struct uart_port *port)
611 unsigned int retval = 0, status = 0;
613 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
618 /* Disable the TX and RX */
619 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
622 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
625 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
628 status = xuartps_readl(XUARTPS_CR_OFFSET);
630 /* Clear the RX disable and TX disable bits and then set the TX enable
631 * bit and RX enable bit to enable the transmitter and receiver.
633 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
634 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
635 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
637 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
640 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
641 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
645 * Set the RX FIFO Trigger level to use most of the FIFO, but it
646 * can be tuned with a module parameter
648 xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
651 * Receive Timeout register is enabled but it
652 * can be tuned with a module parameter
654 xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
656 /* Clear out any pending interrupts before enabling them */
657 xuartps_writel(xuartps_readl(XUARTPS_ISR_OFFSET), XUARTPS_ISR_OFFSET);
659 /* Set the Interrupt Registers with desired interrupts */
660 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
661 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
662 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
668 * xuartps_shutdown - Called when an application closes a xuartps port
669 * @port: Handle to the uart port structure
672 static void xuartps_shutdown(struct uart_port *port)
676 /* Disable interrupts */
677 status = xuartps_readl(XUARTPS_IMR_OFFSET);
678 xuartps_writel(status, XUARTPS_IDR_OFFSET);
680 /* Disable the TX and RX */
681 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
683 free_irq(port->irq, port);
687 * xuartps_type - Set UART type to xuartps port
688 * @port: Handle to the uart port structure
690 * Returns string on success, NULL otherwise
692 static const char *xuartps_type(struct uart_port *port)
694 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
698 * xuartps_verify_port - Verify the port params
699 * @port: Handle to the uart port structure
700 * @ser: Handle to the structure whose members are compared
702 * Returns 0 if success otherwise -EINVAL
704 static int xuartps_verify_port(struct uart_port *port,
705 struct serial_struct *ser)
707 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
709 if (port->irq != ser->irq)
711 if (ser->io_type != UPIO_MEM)
713 if (port->iobase != ser->port)
721 * xuartps_request_port - Claim the memory region attached to xuartps port,
722 * called when the driver adds a xuartps port via
723 * uart_add_one_port()
724 * @port: Handle to the uart port structure
726 * Returns 0, -ENOMEM if request fails
728 static int xuartps_request_port(struct uart_port *port)
730 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
735 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
736 if (!port->membase) {
737 dev_err(port->dev, "Unable to map registers\n");
738 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
745 * xuartps_release_port - Release the memory region attached to a xuartps
746 * port, called when the driver removes a xuartps
747 * port via uart_remove_one_port().
748 * @port: Handle to the uart port structure
751 static void xuartps_release_port(struct uart_port *port)
753 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
754 iounmap(port->membase);
755 port->membase = NULL;
759 * xuartps_config_port - Configure xuartps, called when the driver adds a
761 * @port: Handle to the uart port structure
765 static void xuartps_config_port(struct uart_port *port, int flags)
767 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
768 port->type = PORT_XUARTPS;
772 * xuartps_get_mctrl - Get the modem control state
774 * @port: Handle to the uart port structure
776 * Returns the modem control state
779 static unsigned int xuartps_get_mctrl(struct uart_port *port)
781 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
784 static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
789 static void xuartps_enable_ms(struct uart_port *port)
794 #ifdef CONFIG_CONSOLE_POLL
795 static int xuartps_poll_get_char(struct uart_port *port)
800 /* Disable all interrupts */
801 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
802 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
804 /* Check if FIFO is empty */
805 if (xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY)
807 else /* Read a character */
808 c = (unsigned char) xuartps_readl(XUARTPS_FIFO_OFFSET);
810 /* Enable interrupts */
811 xuartps_writel(imr, XUARTPS_IER_OFFSET);
816 static void xuartps_poll_put_char(struct uart_port *port, unsigned char c)
820 /* Disable all interrupts */
821 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
822 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
824 /* Wait until FIFO is empty */
825 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
828 /* Write a character */
829 xuartps_writel(c, XUARTPS_FIFO_OFFSET);
831 /* Wait until FIFO is empty */
832 while (!(xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY))
835 /* Enable interrupts */
836 xuartps_writel(imr, XUARTPS_IER_OFFSET);
842 /** The UART operations structure
844 static struct uart_ops xuartps_ops = {
845 .set_mctrl = xuartps_set_mctrl,
846 .get_mctrl = xuartps_get_mctrl,
847 .enable_ms = xuartps_enable_ms,
849 .start_tx = xuartps_start_tx, /* Start transmitting */
850 .stop_tx = xuartps_stop_tx, /* Stop transmission */
851 .stop_rx = xuartps_stop_rx, /* Stop reception */
852 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
853 .break_ctl = xuartps_break_ctl, /* Start/stop
856 .set_termios = xuartps_set_termios, /* Set termios */
857 .startup = xuartps_startup, /* App opens xuartps */
858 .shutdown = xuartps_shutdown, /* App closes xuartps */
859 .type = xuartps_type, /* Set UART type */
860 .verify_port = xuartps_verify_port, /* Verification of port
863 .request_port = xuartps_request_port, /* Claim resources
867 .release_port = xuartps_release_port, /* Release resources
871 .config_port = xuartps_config_port, /* Configure when driver
872 * adds a xuartps port
874 #ifdef CONFIG_CONSOLE_POLL
875 .poll_get_char = xuartps_poll_get_char,
876 .poll_put_char = xuartps_poll_put_char,
880 static struct uart_port xuartps_port[2];
883 * xuartps_get_port - Configure the port from the platform device resource
886 * Returns a pointer to a uart_port or NULL for failure
888 static struct uart_port *xuartps_get_port(void)
890 struct uart_port *port;
893 /* Find the next unused port */
894 for (id = 0; id < XUARTPS_NR_PORTS; id++)
895 if (xuartps_port[id].mapbase == 0)
898 if (id >= XUARTPS_NR_PORTS)
901 port = &xuartps_port[id];
903 /* At this point, we've got an empty uart_port struct, initialize it */
904 spin_lock_init(&port->lock);
905 port->membase = NULL;
906 port->iobase = 1; /* mark port in use */
908 port->type = PORT_UNKNOWN;
909 port->iotype = UPIO_MEM32;
910 port->flags = UPF_BOOT_AUTOCONF;
911 port->ops = &xuartps_ops;
912 port->fifosize = XUARTPS_FIFO_SIZE;
918 /*-----------------------Console driver operations--------------------------*/
920 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
922 * xuartps_console_wait_tx - Wait for the TX to be full
923 * @port: Handle to the uart port structure
926 static void xuartps_console_wait_tx(struct uart_port *port)
928 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
929 != XUARTPS_SR_TXEMPTY)
934 * xuartps_console_putchar - write the character to the FIFO buffer
935 * @port: Handle to the uart port structure
936 * @ch: Character to be written
939 static void xuartps_console_putchar(struct uart_port *port, int ch)
941 xuartps_console_wait_tx(port);
942 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
946 * xuartps_console_write - perform write operation
947 * @port: Handle to the uart port structure
948 * @s: Pointer to character array
949 * @count: No of characters
951 static void xuartps_console_write(struct console *co, const char *s,
954 struct uart_port *port = &xuartps_port[co->index];
956 unsigned int imr, ctrl;
959 if (oops_in_progress)
960 locked = spin_trylock_irqsave(&port->lock, flags);
962 spin_lock_irqsave(&port->lock, flags);
964 /* save and disable interrupt */
965 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
966 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
969 * Make sure that the tx part is enabled. Set the TX enable bit and
970 * clear the TX disable bit to enable the transmitter.
972 ctrl = xuartps_readl(XUARTPS_CR_OFFSET);
973 xuartps_writel((ctrl & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
976 uart_console_write(port, s, count, xuartps_console_putchar);
977 xuartps_console_wait_tx(port);
979 xuartps_writel(ctrl, XUARTPS_CR_OFFSET);
981 /* restore interrupt state, it seems like there may be a h/w bug
982 * in that the interrupt enable register should not need to be
983 * written based on the data sheet
985 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
986 xuartps_writel(imr, XUARTPS_IER_OFFSET);
989 spin_unlock_irqrestore(&port->lock, flags);
993 * xuartps_console_setup - Initialize the uart to default config
994 * @co: Console handle
995 * @options: Initial settings of uart
997 * Returns 0, -ENODEV if no device
999 static int __init xuartps_console_setup(struct console *co, char *options)
1001 struct uart_port *port = &xuartps_port[co->index];
1007 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
1010 if (!port->mapbase) {
1011 pr_debug("console on ttyPS%i not present\n", co->index);
1016 uart_parse_options(options, &baud, &parity, &bits, &flow);
1018 return uart_set_options(port, co, baud, parity, bits, flow);
1021 static struct uart_driver xuartps_uart_driver;
1023 static struct console xuartps_console = {
1024 .name = XUARTPS_TTY_NAME,
1025 .write = xuartps_console_write,
1026 .device = uart_console_device,
1027 .setup = xuartps_console_setup,
1028 .flags = CON_PRINTBUFFER,
1029 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1030 .data = &xuartps_uart_driver,
1034 * xuartps_console_init - Initialization call
1036 * Returns 0 on success, negative error otherwise
1038 static int __init xuartps_console_init(void)
1040 register_console(&xuartps_console);
1044 console_initcall(xuartps_console_init);
1046 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1048 /** Structure Definitions
1050 static struct uart_driver xuartps_uart_driver = {
1051 .owner = THIS_MODULE, /* Owner */
1052 .driver_name = XUARTPS_NAME, /* Driver name */
1053 .dev_name = XUARTPS_TTY_NAME, /* Node name */
1054 .major = XUARTPS_MAJOR, /* Major number */
1055 .minor = XUARTPS_MINOR, /* Minor number */
1056 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
1057 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1058 .cons = &xuartps_console, /* Console */
1062 /* ---------------------------------------------------------------------
1063 * Platform bus binding
1066 * xuartps_probe - Platform driver probe
1067 * @pdev: Pointer to the platform device structure
1069 * Returns 0 on success, negative error otherwise
1071 static int xuartps_probe(struct platform_device *pdev)
1074 struct uart_port *port;
1075 struct resource *res, *res2;
1076 struct xuartps *xuartps_data;
1078 xuartps_data = devm_kzalloc(&pdev->dev, sizeof(*xuartps_data),
1083 xuartps_data->aperclk = devm_clk_get(&pdev->dev, "aper_clk");
1084 if (IS_ERR(xuartps_data->aperclk)) {
1085 dev_err(&pdev->dev, "aper_clk clock not found.\n");
1086 return PTR_ERR(xuartps_data->aperclk);
1088 xuartps_data->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1089 if (IS_ERR(xuartps_data->refclk)) {
1090 dev_err(&pdev->dev, "ref_clk clock not found.\n");
1091 return PTR_ERR(xuartps_data->refclk);
1094 rc = clk_prepare_enable(xuartps_data->aperclk);
1096 dev_err(&pdev->dev, "Unable to enable APER clock.\n");
1099 rc = clk_prepare_enable(xuartps_data->refclk);
1101 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1102 goto err_out_clk_dis_aper;
1105 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1108 goto err_out_clk_disable;
1111 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1114 goto err_out_clk_disable;
1117 /* Initialize the port structure */
1118 port = xuartps_get_port();
1121 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1123 goto err_out_clk_disable;
1125 /* Register the port.
1126 * This function also registers this device with the tty layer
1127 * and triggers invocation of the config_port() entry point.
1129 port->mapbase = res->start;
1130 port->irq = res2->start;
1131 port->dev = &pdev->dev;
1132 port->uartclk = clk_get_rate(xuartps_data->refclk);
1133 port->private_data = xuartps_data;
1134 platform_set_drvdata(pdev, port);
1135 rc = uart_add_one_port(&xuartps_uart_driver, port);
1138 "uart_add_one_port() failed; err=%i\n", rc);
1139 goto err_out_clk_disable;
1144 err_out_clk_disable:
1145 clk_disable_unprepare(xuartps_data->refclk);
1146 err_out_clk_dis_aper:
1147 clk_disable_unprepare(xuartps_data->aperclk);
1153 * xuartps_remove - called when the platform driver is unregistered
1154 * @pdev: Pointer to the platform device structure
1156 * Returns 0 on success, negative error otherwise
1158 static int xuartps_remove(struct platform_device *pdev)
1160 struct uart_port *port = platform_get_drvdata(pdev);
1161 struct xuartps *xuartps_data = port->private_data;
1164 /* Remove the xuartps port from the serial core */
1165 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1167 clk_disable_unprepare(xuartps_data->refclk);
1168 clk_disable_unprepare(xuartps_data->aperclk);
1172 /* Match table for of_platform binding */
1173 static struct of_device_id xuartps_of_match[] = {
1174 { .compatible = "xlnx,xuartps", },
1177 MODULE_DEVICE_TABLE(of, xuartps_of_match);
1179 static struct platform_driver xuartps_platform_driver = {
1180 .probe = xuartps_probe, /* Probe method */
1181 .remove = xuartps_remove, /* Detach method */
1183 .owner = THIS_MODULE,
1184 .name = XUARTPS_NAME, /* Driver name */
1185 .of_match_table = xuartps_of_match,
1189 /* ---------------------------------------------------------------------
1190 * Module Init and Exit
1193 * xuartps_init - Initial driver registration call
1195 * Returns whether the registration was successful or not
1197 static int __init xuartps_init(void)
1201 /* Register the xuartps driver with the serial core */
1202 retval = uart_register_driver(&xuartps_uart_driver);
1206 /* Register the platform driver */
1207 retval = platform_driver_register(&xuartps_platform_driver);
1209 uart_unregister_driver(&xuartps_uart_driver);
1215 * xuartps_exit - Driver unregistration call
1217 static void __exit xuartps_exit(void)
1219 /* The order of unregistration is important. Unregister the
1220 * UART driver before the platform driver crashes the system.
1223 /* Unregister the platform driver */
1224 platform_driver_unregister(&xuartps_platform_driver);
1226 /* Unregister the xuartps driver */
1227 uart_unregister_driver(&xuartps_uart_driver);
1230 module_init(xuartps_init);
1231 module_exit(xuartps_exit);
1233 MODULE_DESCRIPTION("Driver for PS UART");
1234 MODULE_AUTHOR("Xilinx Inc.");
1235 MODULE_LICENSE("GPL");